HYMP112R728-C4 - SK Hynix - Datasheet.Directory

This document is a general product description and is subject t o change without notice. Hynix Semiconductor do es not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.0 / Apr. 2005 1

240pin Registered DDR2 SDRAM DIMMs based on 1Gb 1st ver.

This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb first version DDR2 SDRAMs in

Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1 Gb 1st ver. based Registered

DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard.

It is suitable for easy interchange and addition.

FEATURES

ORDERING INFORMATION

Part Name Density Organization # of

DRAMs # of

ranks Materials

HYMP112R728-E3/C4 1GB 128Mx72 9 1 Leaded

HYMP125R728-E3/C4 2GB 256Mx72 18 2 Leaded

HYMP125R724-E3/C4 2GB 256Mx72 18 1 Leaded

HYMP351R72M4-E3/C4 4GB 512Mx72 36 2 Leaded

HYMP112R72P8-E3/C4 1GB 128Mx72 9 1 Lead free

HYMP125R72P8-E3/C4 2GB 256Mx72 18 2 Lead fr ee

HYMP125R7P24-E3/C4 2GB 256Mx72 18 1 Lead free

HYMP351R72MP4-E3/C4 4GB 512Mx72 36 2 Lead fr ee

• JEDEC standard Double Data Rate2 Synchronous

DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power

Supply

• All inputs and outputs are compatible with SS TL_1.8

interface

•8 Bank architecture

•Posted CAS

• Programmable CAS Latency 3 , 4 , 5

• OCD (Off-Chip Driver Impedance Adjustment)

• ODT (On-Die Termination)

• Fully differential clock operations (CK & /CK)

• Programm able Burst Length 4 / 8 with both sequen-

tial and interleave mode

• Auto refresh and self refresh supported

• 8192 refresh cycles / 64ms

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 68ball FBGA

• 133.35 x 30.00 mm form factor

• Lead-free Products are RoHS compliant

Rev. 1.0 / Apr. 2005 2

1

240pin Registered DDR2 SDRAM DIMMs

SPEED GRADE & KEY PARAMETERS

ADDRESS TABLE

E3 (DDR2-400) C4 (DDR2-533) Unit

Speed@CL3 400 400 Mbps

Speed@CL4 400 533 Mbps

Speed@CL5 400 533 Mbps

CL-tRCD-tRP 3-3-3 4-4-4 tCK

Organization Ranks SDRAMs # of

DRAMs # of row/bank/column Address Refresh

Method

1GB 128M x 72 1 128Mb x 8 9 14(A0~A13)/2(BA0~BA2)/10(A0~A9) 8K / 64ms

2GB 256M x 72 2 128Mb x 8 18 14(A0~A13)/2(BA0~BA2)/10(A0~A9) 8K / 64ms

2GB 256M x 72 1 256Mb x 4 18 14(A0~A13)/2(BA0~BA2)/11(A0~A9,A11) 8K / 64ms

4GB 512M x 72 2 256Mb x 4 36 14(A0~A13)/2(BA0~BA2)/11(A0~A9,A11) 8K / 64ms

Rev. 1.0 / Apr. 2005 3

1

240pin Registered DDR2 SDRAM DIMMs

Input/Output Functional Description

Symbol Type Polarity Pin Description

CK0 IN Positive

Edge Positive line of the differential pair of system clock inputs th at drives input to the on-DIMM PLL.

CK0IN

Negative

Edge Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.

CKE[1:0] IN Active

High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deac-

tivating the clocks, CK E low initiate s the Power Down mode or the Self Refresh mode.

S[1:0] IN Active

Low

Enables the associated DDR2 SDRAM command decoder when low and disables the command

decoder when high.

When the command decoder is disabled, new commands are ignored but previous operations con-

tinue. Rank 0 is selected by S0; Rank 1 is selected by S1

ODT[1:0] IN Active

High On-Die Termination signals.

RAS, CAS,

WE IN Active

Low When sampled at the positive rising edge of the clock. RAS,CAS and WE

(ALONG WITH S) define the command being entered.

Vref Supply Reference voltage for SSTL18 inputs

VDDQ Supply Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all

current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins.

BA[2:0] IN - Selects which DDR2 SDRAM internal bank of Eight is activated.

A[9:0],

A10/AP

A[13:11] IN -

During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)

During a Read or Write command cycle, Address input defines the column address when sampled

at the cross point of the rising edge of CK and

falling edge of CK.

In addition to the column address, AP is used to invoke autoprecharge operation at the end of the

burst read or write cycle.

If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged.

If AP is low, autoprecharge is disabled.

During a Precharge command cycle., AP is used in conjunction with BA0-BAn to c ont rol which

bank(s) to precharge.

If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs.

If AP is low, then BA0-BAn are used to define which bank to precharge.

DQ[63:0],

CB[7:0] IN - Data and Check Bit Input/Output pins.

DM[8:0] IN Activ

High

DM is an input mask signal for write data. Input data is masked when DM is sampled High coinci-

dent with that input data during a write access. DM is sampled on both edges of DQS. Although DM

pins are input only, the DM loading matches the DQ and DQS loading.

VDD,VSS Supply Power and ground for the DDR2 SDRAM input buffers, and core logic.

VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules.

DQS[17:0] I/O Positive

Edge Positive line of the differential data strobe for input and output data

DQS[17:0] I/O Negative

Edge Negative line of the differential data strobe for input and output data

SA[2:0] IN - These signals are tied at the system planar to either VSS or VDDSPD to

configure the serial SPD EEPROM address range.

SDA I/O - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM.

A resister may be connected from the SDA bus line to VDDSPD on the

system planar to act as a pull up.

SCL IN - This signal is used to clock data into and out of the SPD EEPROM .

A resistor may be connected from SCL to VDDSPD to act as a pull up on the system board.

VDDSPD Supply Power supply for SPD EEPROM.

This supply is separate from the VDD/VDDQ power plane.

EEPROM supply is operable from 1.7V to 3.6V.

RESET IN

The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL.

When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s)

will be set to low level (the PLL will remain

synchronized with the input clock )

Par_In IN Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)

Err_Out OUT Parity error found in the Address and Control bus

TEST Used by memory bus analysis tools(unused on memory DIMMs)

Rev. 1.0 / Apr. 2005 4

1

240pin Registered DDR2 SDRAM DIMMs

PIN DESCRIPTION

PIN LOCATION

Pin Pin Description Pin Pin Description

CK0 Clock Input,posi tive line ODT[1:0] On Die Termination Inputs

CK0 Clock input,negative line VDDQ DQs Power Supply

CKE0~CKE1 Clock Enable Input DQ0~DQ63 Data Input/Output

RAS Row Address Strobe CB0~CB7 Data check bits Input/Output

CAS Column Address Strobe DQS(0~8) Data strobes

WE Write Enable DQS(0~8) Data strobes,negative line

S0,S1 Chip Select Input DM(0~8),DQS(9~17) Data Maskes/Data strobes

A0~A9,A11~A13 Address input DQS(9~17) Data strobes,negative line

A10/AP Address input/Autoprecharge RFU Reserved for Future Use

BA0, BA1, BA2 SDRAM Bank Address NC No Connect

SCL Serial Presence Detect(SPD)

Clock Input TEST Memory bus test tool

(Not Connected and Not Usable on

DIMMs)

SDA SPD Data Input/Output VDD Core Power

SA0~SA2 E2PROM Address Inputs VDDQ I/O Power

Par_In Parity bit for the Address and

Control bus VSS Ground

Err_Out Parity error found on the Addre VREF Input/Output Reference

RESET Reset Enable VDDSPD SPD Power

CB0~CB7 Data Check bit Inputs/Outputs

1 pin

Front Side

64 pin 65 pin 120 pin

121 pin

Back Side

184 pin 185 pin 240 pin

Rev. 1.0 / Apr. 2005 5

1

240pin Registered DDR2 SDRAM DIMMs

PIN ASSIGNMENT

NC= No Connect, RFU= Reserved for Future Use.

Note:

1. RESET(Pin 18) is connected to both OE of PLL and Reset of register.

2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity.

3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs)

Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name

1 VREF 41 VSS 81 DQ33 121 VSS 161 CB4 201 VSS

2 VSS 42 CB0 82 VSS 122 DQ4 162 CB5 202 DM4/DQS13

3DQ043CB183DQS

4 123 DQ5 163 VSS 203 DQS13

4 DQ1 44 VSS 84 DQS4 124 VSS 164 DM8,DQS17 204 VSS

5VSS45DQS

8 85 VSS 125 DM0/DQS9 165 DQS17 205 DQ38

6DQS

046DQS886 DQ34126DQS9 166 VSS 206 DQ39

7 DQS0 47 VSS 87 DQ35 127 VSS 167 CB6 207 VSS

8 VSS 48 CB2 88 VSS 128 DQ6 168 CB7 208 DQ44

9 DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45

10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS

11 VSS 51 VDDQ 91 VSS 131 DQ12 171 NC,CKE1 211 DM5/DQS14

12 DQ8 52 CKE0 92 DQS5 132 DQ13 172 VDD 212 DQS14

13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15,NC 213 VSS

14 VSS 54 BA2,NC 94 VSS 134 DM1/DQS10 174 A14,NC 214 DQ46

15 DQS155NC,Err_Out95 DQ42 135 DQS10 175 VDDQ 215 DQ47

16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS

17 VSS 57 A11 97 VSS 137 RFU 177 A9 217 DQ52

18 RESET 58 A7 98 DQ48 138 RFU 178 VDD 218 DQ53

19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS

20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 RFU

21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 RFU

22 DQ11 62 VDDQ 102 NC(TEST) 142 VSS 182 A3 222 VSS

23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6/DQS15

24 DQ16 64 VDD 104 DQS6 144 DQ21 184 VDD 224 NC,DQS15

25 DQ17 Key 105 DQS6 145 VSS Key 225 VSS

26 VSS 65 VSS 106 VSS 146 DM2/DQS11 185 CK0 226 DQ54

27 DQS2 66 VSS 107 DQ50 147 DQS11 186 CK0227DQ55

28 DQS2 67 VDD 108 DQ51 148 VSS 187 VDD 228 VSS

29 VSS 68 NC,Err_Out 109 VSS 149 DQ22 188 A0 229 DQ60

30 DQ18 69 VDD 110 DQ56 150 DQ23 189 VDD 230 DQ61

31 DQ19 70 A10/AP 111 DQ57 151 VSS 190 BA1 231 VSS

32 VSS 71 BA0 112 VSS 152 DQ28 191 VDDQ 232 DM7/DQS16

33 DQ24 72 VDDQ 113 DQS7 153 DQ29 192 RAS 233 NC,DQS16

34 DQ25 73 WE 114 DQS7 154 VSS 193 S0234VSS

35 VSS 74 CAS 115 VSS 155 DM3/DQS12 194 VDDQ 235 DQ62

36 DQS3 75 VDDQ 116 DQ58 156 DQS12 195 ODT0 236 DQ63

37 DQS3 76 NC, S1 117 DQ59 157 VSS 196 A13,NC 237 VSS

38 VSS 77 NC, ODT1 118 VSS 158 DQ30 197 VDD 238 VDDSPD

39 DQ26 78 VDDQ 119 SDA 159 DQ31 198 VSS 239 SA0

40 DQ27 79 VSS 120 SCL 160 VSS 199 DQ36 240 SA1

80 DQ32 200 DQ37

Rev. 1.0 / Apr. 2005 6

1

240pin Registered DDR2 SDRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

1GB(128Mbx72) : HYMP112R72[P]8

P

L

OE

PCK0 to PCK6, PCK8,PCK9 ==> CK: SDRAMs D0 toD8

/PCK0 to /PCK6, /PCK8, /PCK9 ==> /CK: SDRAMs D0 toD8

PCK7 ==> CK: Register

/PCK7 ==> /CK: Register

CK0

/CK0

/RESET

/RS0

D0

DQ0 I/O 0

DQ1 I/O 1

DQ2 I/O 2

DQ3 I/O 3

DQ4 I/O 4

DQ5 I/O 5

DQ6 I/O 6

I/O 7

DQ7

/DQS0

DM0,DQS9

DQS0

/CS D QS /DQ S

DM

RDQS NU

/RDQS

/DQS9

D1

DQ8 I/O 0

DQ9 I/O 1

DQ10 I/O 2

DQ11 I/O 3

DQ12 I/O 4

DQ13 I/O 5

DQ14 I/O 6

I/O 7

DQ15

/DQS1

DM1,DQS10

DQS1

/CS D QS /DQ S

DM

RDQS NU

/RDQS

/DQS10

D2

DQ16 I/O 0

DQ17 I/O 1

DQ18 I/O 2

DQ19 I/O 3

DQ20 I/O 4

DQ21 I/O 5

DQ22 I/O 6

I/O 7

DQ23

/DQS2

DM2,DQS11

DQS2

/CS D QS /DQ S

DM

RDQS NU

/RDQS

/DQS11

D3

DQ24 I/O 0

DQ25 I/O 1

DQ26 I/O 2

DQ27 I/O 3

DQ28 I/O 4

DQ29 I/O 5

DQ30 I/O 6

I/O 7

DQ31

/DQS3

DM3,DQS12

DQS3

/CS D QS /DQ S

DM

RDQS NU

/RDQS

/DQS12

D8

CB0 I/O 0

CB1 I/O 1

CB2 I/O 2

CB3 I/O 3

CB4 I/O 4

CB5 I/O 5

CB6 I/O 6

I/O 7

CB7

/DQS8

DM8DQS17

DQS8

/CS D QS /DQ S

DM

RDQS NU

/RDQS

/DQS17

D4

DQ32 I/O 0

DQ33 I/O 1

DQ34 I/O 2

DQ35 I/O 3

DQ36 I/O 4

DQ37 I/O 5

DQ38 I/O 6

I/O 7

DQ39

/DQS4

DM4,DQS13

DQS4

/CS D QS /D QS

DM

RDQS NU

/RDQS

/DQS13

D5

DQ40 I/O 0

DQ41 I/O 1

DQ42 I/O 2

DQ43 I/O 3

DQ44 I/O 4

DQ45 I/O 5

DQ46 I/O 6

I/O 7

DQ47

/DQS5

DM5,DQS14

DQS5

/CS D QS /D QS

DM

RDQS NU

/RDQS

/DQS14

D6

DQ48 I/O 0

DQ49 I/O 1

DQ50 I/O 2

DQ51 I/O 3

DQ52 I/O 4

DQ53 I/O 5

DQ54 I/O 6

I/O 7

DQ55

/DQS6

DM6,DQS15

DQS6

/CS D QS /D QS

DM

RDQS NU

/RDQS

/DQS15

D7

DQ56 I/O 0

DQ57 I/O 1

DQ58 I/O 2

DQ59 I/O 3

DQ60 I/O 4

DQ61 I/O 5

DQ62 I/O 6

I/O 7

DQ63

/DQS7

DM7,DQS16

DQS7

/CS D QS /D QS

DM

RDQS NU

/RDQS

/DQS16

VDD SPD

VDD /

VDDQ

VREF

VSS

Serial PD

DO-D8

SA0 SA1 SA2

W

P

SCL SDA

A0 A1 A2

Serial PD

SCL U0 SDA

* : /S0 connects to D/CS and VDD connects to /CSR on register.

ODT0

CKE0

/PCK7

/WE

R

E

G

I

S

T

E

R

PCK7

/RESET

/CAS

/RAS

BA0 to BA2

A0 to A1 3

/CS0*

RODT 0 ==> OD T0: S DRA Ms D 0 to D8

/RWE ==> /WE: SDRAM s D 0 to D8

RCKE0 ==> CKE : SDRAM s D0 to D8

/RCAS ==>/CAS: SDRAMs D 0 to D8

/RRAS ==>/RAS: SDRAMs D 0 to D8

/RA0 to RA13 ==> A0 to A13: SDRAMs D 0 to D8

RBA0 to RBA2 ==> BA0 to BA2: SDRAM s D0 to D8

/RS0 to /CS ==> /CS: SDRAMs D 0 to D8

/RST 1. Register values are 22 Ohms.

Notes :

Rev. 1.0 / Apr. 2005 7

1

240pin Registered DDR2 SDRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

2GB(256Mbx72) : HYMP125R72[P]8

z

/RS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

/RS1

/DQS1

/DQS10

DM1,DQS10

DQS1

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D1

DM

RDQS NU

/RDQS /CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/ O 7

D10

DM

RDQS NU

/RDQS/CS DQS /DQS

/DQS0

/DQS9

DM0,DQS9

DQS0

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D0

DM

RDQS NU

/RDQS /CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/ O 7

D9

DM

RDQS NU

/RDQS/CS DQS /DQS

/DQS2

/DQS11

DM2, DQS11

DQS2

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D2

DM

RDQS NU

/RDQS /CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/ O 7

D11

DM

RDQS NU

/RDQS/CS DQS /DQS

/DQS3

/DQS12

DM3, DQS12

DQS3

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D3

DM

RDQS NU

/RDQS /CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/ O 7

D12

DM

RDQS NU

/RDQS /CS DQS /DQS

/DQS8

/DQS17

DM8, DQS17

DQS8

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D8

DM

RDQS NU

/RDQS/CS DQS /DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/ O 7

D17

DM

RDQS NU

/RDQS /CS DQS /DQS

/DQS4

/DQS13

DM4, DQS13

DQS4

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D4

DM

RDQS NU

/RDQS /CS DQS /DQS

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D13

DM

RDQS NU

/RDQS/CS DQS /DQS

/DQS5

/DQS14

DM5, DQS14

DQS5

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D5

DM

RDQS NU

/RDQS /CS DQS /DQS

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D14

DM

RDQS NU

/RDQS/CS DQS /DQS

/DQS6

/DQS15

DM6, DQS15

DQS6

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D6

DM

RDQS NU

/RDQS /CS DQS /DQS

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D15

DM

RDQS NU

/RDQS/CS DQS /DQS

/DQS7

/DQS16

DM7, DQS16

DQS7

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D7

DM

RDQS NU

/RDQS /CS DQS /DQS

I/ O 0

I/ O 1

I/ O 2

I/ O 3

I/ O 4

I/ O 5

I/ O 6

I/ O 7

D16

DM

RDQS NU

/RDQS/CS DQS /DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

ODT0

CKE0

/PCK7

/WE

1:2

R

E

G

I

S

T

E

R

PCK7

/RESET

/CAS

/RAS

BA0 to BA2

A0 to A13

/S1

/RST

/S0

RODT1 => O DT 1 : SD RA Ms D9-D1 7

ODT1

CKE1

RODT0 => ODT0: SDRAMs D0-D8

RCKE1 => CKE1: SDRAMs D9-D17

RCKE0 => CKE0: SDRAMs D0-D8

/RA 0 to R A1 2 => A0 - A12 : SDRAMs D0 - D17

/RWE => /WE: SDRAMs D0-D17

/RCAS => /CAS: SDRAMs D0-D17

/RRAS => /R AS: SDRA Ms D0 - D1 7

/RBA0 to RBA2 => BA0 - BA2 : SDRAMs D0 - D17

/R S1 to / CS : SDRAMs D9 - D17

/RS0 to /C S : SD RAMs D0 - D 8

Notes:

1. Register values are 22 O hm s +/- 5%.

2. /RS0 and /RS 1 alternate between the back and front sides of the DIMM

P

L

OE

CK0

/CK0

/RESET

PCK0 to PCK6, PCK8,PCK9 => CK : SDRAMx D0-D17

/PCK0 to /PCK6, /PCK8,/PCK9 => /CK : SDRAMx D0-D17

PCK7 => CK: Register

/PCK7 => /CK: Register

SCL SDA

A0 A1

WP Serial PD

SCL

SA0 SA1 SA2

A1

VDD SPD

VREF

VDD/VDDQ

VSS

Serial

PD

DO-D17

Rev. 1.0 / Apr. 2005 8

1

240pin Registered DDR2 SDRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

2GB(256Mbx72): HYMP125R72[P]4

/RS0

VSS

D0

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

DQ0

DQ1

DQ2

DQ3

/DQS0

/DQS

DQS0

D1

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS1

/DQS

DQS1

D2

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

DQ16

DQ17

DQ18

DQ19

/DQS2

/DQS

DQS2

D3

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS3

/DQS

DQS3

D4

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS4

/DQS

DQS4

D5

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS5

/DQS

DQS5

D6

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS6

/DQS

DQS6

D7

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS7

/DQS

DQS7

D8

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

CB0

CB1

CB2

CB3

/DQS8

/DQS

DQS8

D9

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

DQ4

DQ5

DQ6

DQ7

/DQS9

/DQS

DQS9

D10

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS10

/DQS

DQS10

D11

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS11

/DQS

DQS11

D12

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS12

/DQS

DQS12

D13

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS13

/DQS

DQS13

D14

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS14

/DQS

DQS14

D15

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS15

/DQS

DQS15

D16

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

/DQS16

/DQS

DQS16

D17

DQS /CS DM

I/O0

I/O1

I/O2

I/O3

CB4

CB5

CB6

CB7

/DQS17

/DQS

DQS17

DQ60

DQ61

DQ62

DQ63

DQ52

DQ53

DQ54

DQ55

DQ44

DQ45

DQ46

DQ47

DQ36

DQ37

DQ38

DQ39

DQ28

DQ29

DQ30

DQ31

DQ20

DQ21

DQ22

DQ23

DQ12

DQ13

DQ14

DQ15

DQ8

DQ9

DQ10

DQ11

DQ24

DQ25

DQ26

DQ27

DQ32

DQ33

DQ34

DQ35

DQ40

DQ41

DQ42

DQ43

DQ48

DQ49

DQ50

DQ51

DQ56

DQ57

DQ58

DQ59

* /S0 connects to D/CS of Register1 and /CSR of Register2. /C SR of register and D/CS of register2 connects to VDD.

** /RESET,PCK7 connect to both Registers. Other signals connect to one of two R egisters. /S1,CKE1 and O DT1 are NC .

P

L

OE

CK0

/CK0

/RESET

PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMx D0-D17

/PCK0 to /PCK6, /PCK8,/PCK9 = > /CK : SDRAMx D0-D17

PCK7 = > CK: Register

/PCK7 = > /CK: Register

SA0 SA1 SA2

W

P

SCL SDA

A0 A1 A2

Serial PD

SCL U0 SDA

VDD SPD

VREF

VDD/VDDQ

VSS

Serial

PD

DO-D17

1. Resistor values are 22 Ohms +/- 5% .

Notes:

ODT0

CKE0

/PCK7

/WE

R

E

G

I

S

T

E

R

PCK7

/RESET

/CAS

/RAS

BA0 to BA2

A 0 to A13

/CS0*

RODT0 ==> ODT0: SDRAMs D0 to D17

/RWE ==> /W E: SDRA M s D 0 to D17

RCKE0 ==> CKE: SDRAMs D0 to D17

/RCAS ==>/CAS: SDRAMs D0 to D17

/RRAS ==>/RAS: SDRAMs D0 to D17

/R A0 to RA 1 3 ==> A0 to A1 3 : S DR AM s D0 to D17

R B A0 to RB A2 ==> BA0 to BA2 : S DR AMs D0 to D1 7

/R S 0 to /C S = => /CS : S DR AMs D0 to D17

/RST

Rev. 1.0 / Apr. 2005 9

1

240pin Registered DDR2 SDRAM DIMMs

FUNCTIONAL BLOCK DIAGRAM

4GB(512Mbx72) : HYMP351R72M[P]4

/RS0

VSS

/RS1

DQ0

DQ1

DQ2

DQ3

DQS0

/DQS0

D0,D18(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM /DQS

DQ8

DQ9

DQ10

DQ11

DQS1

/DQS1

D1,D19(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

/RS0

/RS1

DQ16

DQ17

DQ18

DQ19

DQS2

/DQS2

D2,D20(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM /DQS

DQ24

DQ25

DQ26

DQ27

DQS3

/DQS3

D3,D21(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

/RS0

/RS1

DQ48

DQ49

DQ50

DQ51

DQS6

/DQS6

D6,D24(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM /DQS

DQ56

DQ57

DQ58

DQ59

DQS7

/DQS7

D7,D25(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

/RS0

/RS1

DQ32

DQ33

DQ34

DQ35

DQS4

/DQS4

D4,D2(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM /DQS

DQ40

DQ41

DQ42

DQ43

DQS5

/DQS5

D5,D23(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

CB0

CB1

CB2

CB3

DQS8

/DQS8

D8,D26(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

DQ4

DQ5

DQ6

DQ7

DQS9

/DQS9

D9,D27(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM /DQS

DQ12

DQ13

DQ14

DQ15

DQS10

/DQS10

D10,D28(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

DQ20

DQ21

DQ22

DQ23

DQS11

/DQS11

D11,D29(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM /DQS

DQ28

DQ29

DQ30

DQ31

DQS12

/DQS12

D12,D30(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

DQ52

DQ53

DQ54

DQ55

DQS15

/DQS15

D15,D33(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM /DQS

DQ60

DQ61

DQ62

DQ63

DQS9

/DQS9

D9,D34(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

DQ36

DQ37

DQ38

DQ39

DQS13

/DQS13

D13,D31(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM /DQS

DQ44

DQ45

DQ46

DQ47

DQS14

/DQS14

D14,D32(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

CB4

CB5

CB6

CB7

DQS17

/DQS17

D17,D35(DDP)

DQS/CSDM

I/O0

I/O1

I/O2

I/O3

/DQS DQS/CSDM

ODT0

CKE0

/PCK7**

/WE

1:2

R

E

G

I

S

T

E

R

PCK7**

/RESET**

/CAS

/RAS

BA0 ? BA2

A0?A13

/S1*

/RST

/S0*

RODT1 = > ODT1: SDRAMs D18-D 35

ODT1

CKE1

RODT0 = > ODT0: SDRAMs D0-D17

RCKE 1 = > CK E1: SDRAM s D 18-D35

RCKE0 = > CKE0: SDRAMs D0-D17

/R A 0 ? RA12 = > A0 -A12 : SDRAMs D0-D35

/R WE = > /WE: SDR AMs D0 - D35

/RCAS = > /CAS: SDRAMs D0-D35

/RRAS = > /RAS: SDRAM s D0-D35

/RBA0 ? RBA2 = > BA0 -BA2 : SDRAM s D0-D35

/R S1 to /CS : SD R AM s D1 8 ? D35

/R S 0 to /C S : S DRAMs D0 ? D17

Notes:

1. Register values are 22 O hms +/- 5%.

2. /RS0 and /RS1 alternate between the back and front sides of the DIMM

* /S0 connects to D/CS0 and /S1 connects to D/CS1 on both Registers.

** /RESET,PCK7 and /PCK7 connect to both Registers. Other signals connect to two Registers.

SA0 SA1 SA2

W

P

SCL SDA

A0 A1 A2

Serial PD

SCL U0 SDA

VDD SPD

VREF

VDD/VDDQ

VSS

Serial

PD

D O to D3 5

P

L

OE

CK0

/CK0

/RESET

PCK0 to PCK6, PCK8,PCK9 = > CK : SDRAMx D0-D35

/PCK0 to /PCK6, /PCK8,/PCK9 = > /CK : SDRAMx D0-D35

PCK7 = > CK: Register

/PCK7 = > /CK: Register

Rev. 1.0 / Apr. 2005 10

1

240pin Registered DDR2 SDRAM DIMMs

ABSOLUTE MAXIMUM RATINGS

Note :

1. Stress greater than those listed may cause permanent dama ge to the device. This is a stress r ating only, and device

functional operation at or above the conditions indicated is not implied.

Expousure to absolute maximum rating conditions for extended periods may affect reliablility.

OPERATING CONDITIONS

Note :

1. Up to 9850 ft.

2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to

tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.

DC OPERATING CONDITIONS (SSTL_1.8)

Note :

1. VDDQ must be less than or equal to VDD.

2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)

3. VTT of transmitting device must track VREF of receiving device.

Parameter Symbol Value Unit Note

Voltage on VDD pin relative to Vss VDD - 1.0 V ~ 2.3 V V 1

Voltage on VDDL pin relative to Vss VDDL - 0.5 V ~ 2.3 V V 1

Voltage on VDDQ pin relative to Vss VDDQ - 0.5 V ~ 2.3 V V 1

Voltage on any pin relative to Vss VIN, VOUT - 0.5 V ~ 2.3 V V 1

Storage Temperature TSTG -50 ~ +100 oC1

Storage Humidity(without condensation) HSTG 5 to 95 %1

Parameter Symbol Rating Units Notes

DIMM Operating temperature(ambient) TOPR 0 ~ +55 oC

DIMM Barometric Pressure(operating & storage) PBAR 105 to 69 K Pascal 1

DRAM Component Case Temperature Range TCASE 0 ~+95 oC2

Parameter Symbol Min Max Unit Note

Power Supply Voltage

VDD 1.7 1.9 V

VDDL 1.7 1.9 V

VDDQ 1.7 1.9 V 1

Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V2

EEPROM Supply Voltage VDDSPD 1.7 3.6 V

Termination Voltage VTT VREF-0.04 VREF+0.04 V 3

Rev. 1.0 / Apr. 2005 11

1

240pin Registered DDR2 SDRAM DIMMs

INPUT DC LOGIC LEVEL

INPUT AC LOGIC LEVEL

AC INPUT TEST CONDITIONS

Note:

1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the devi ce

under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges

and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions

and VIH(ac) to VIL(ac) on the negative transitions.

Parameter Symbol Min Max Unit Note

Input High V oltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V

Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V

Parameter Symbol Min Max Unit Note

AC Input logic High VIH(AC) VREF + 0. 25 0 - V

AC Input logic Low VIL(AC) -V

REF - 0.250 V

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V1

VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

VDDQ

VIH(ac) min

VIH(dc) min

VREF

VIL(dc) max

VIL(ac) max

VSS

V

SWING(MAX)

delta TRdelta TF

VREF

-

VIL

(ac)

max

delta TF

Falling Slew = Rising Slew =

VIH

(ac)

min

- V

REF

delta TR

< Figure : AC Input Test Signal Waveform>

Rev. 1.0 / Apr. 2005 12

1

240pin Registered DDR2 SDRAM DIMMs

Differential Input AC logic Level

Note:

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQ S,

LDQS, UDQS and UDQS.

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input

(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS)

level. The minimum value is equal to VIH(DC) - VIL(DC).

Note:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal

(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).

The minimum value is equal to V IH(AC) - VIL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VIX(AC) is expected to

track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.

DIFFERENTIAL AC OUTPUT PARAMETERS

Note:

1. The typical v a lue of VOX(AC) is expected to be abou t 0.5 * V DDQ of the transmitting device and V OX(AC) is expected to

track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.

Symbol Parameter Min. Max. Units Note

VID (ac) ac differen tial input voltage 0.5 VDDQ + 0.6 V 1

VIX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

Symbol Parameter Min. Max. Units Note

VOX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1

VDDQ

Crossing point

VSSQ

VTR

VCP

VID VIX or VOX

< Differential signal levels >

Rev. 1.0 / Apr. 2005 13

1

240pin Registered DDR2 SDRAM DIMMs

OUTPUT BUFFER LEVELS

OUTPUT AC TEST CONDITIONS

Note:

1. The VDDQ of the device under test is referenced.

OUTPUT DC CURRENT DRIVE

Note:

1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and

VDDQ - 280 mV.

2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.

3. The dc value of VREF applied to the receiving device is set to VTT.

4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2.

They are used to test device drive current cap ability to ensure VIH min plus a no ise margin an d V IL max minus a noise

margin are delivered to an SSTL_18 receiver.

The actual current values are deriv ed by shifting the desir ed driv er operating poin t along a 21 ohm load line to define

a convenient driver current for measurement.

Symbol Parameter SSTL_18 Units Notes

VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1

Symbol Parameter SSTl_18 Units Notes

IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4

IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4

Rev. 1.0 / Apr. 2005 14

1

240pin Registered DDR2 SDRAM DIMMs

PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25oCf= 1MHz )

1GB : HYMP112R72[P]8

2GB : HYMP125R72[P]8

2GB : HYMP125R72[P]4

4GB : HYMP351R72M[P]4

Note :

1. Pins not under test are tied to GND.

2. These value are guaranteed by design and tested on a sample basis only.

Pin Symbol Min Max Unit

CK0, CK0 CCK 7 11 pF

CKE, ODT CI1 8 12 pF

CS CI2 8 12 pF

Address, RAS, CAS, WE CI3 8 12 pF

DQ, DM, DQS, DQS CIO 6 9 pF

Pin Symbol Min Max Unit

CK0, CK0 CCK 7 11 pF

CKE, ODT CI1 8 12 pF

CS CI2 10 15 pF

Address, RAS, CAS, WE CI3 8 12 pF

DQ, DM, DQS, DQS CIO 8 13 pF

Pin Symbol Min Max Unit

CK0, CK0 CCK 7 11 pF

CKE, ODT CI1 8 12 pF

CS CI2 10 15 pF

Address, RAS, CAS, WE CI3 8 12 pF

DQ, DM, DQS, DQS CIO 6 9 pF

Pin Symbol Min Max Unit

CK0, CK0 CCK 9.5 14 pF

CKE, ODT CI1 10.5 16 pF

CS CI2 10.5 16 pF

Address, RAS, CAS, WE CI3 10.5 16 pF

DQ, DM, DQS, DQS CIO 17 21 pF

Rev. 1.0 / Apr. 2005 15

1

240pin Registered DDR2 SDRAM DIMMs

IDD SPECIFICATIONS (TCASE : 0 to 95oC)

1GB, 128M x 72 Registered DIMM : HYMP112R72[P]8

2GB, 256M x 72 Registered DIMM : HYMP125R72[P]8

Note:

1. IDD6 current alues are guaranted up to Tcase of 85oC max.

Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Unit note

IDD0 1550 1640 mA

IDD1 1640 1730 mA

IDD2P 704 704 mA

IDD2Q 1010 1100 mA

IDD2N 1055 1145 mA

IDD3P(F) 875 920 mA

IDD3P(S) 713 722 mA

IDD3N 1190 1280 mA

IDD4R 1820 2180 mA

IDD4W 1910 2270 mA

IDD5B 3080 3080 mA 1

IDD6 522 522 mA

IDD7 2810 3350 mA

Symbol E3(DDR2 400@CL3) C4(DDR2 533@CL 4) Unit note

IDD0 2090 2270 mA

IDD1 2180 2360 mA

IDD2P 758 758 mA

IDD2Q 1370 1550 mA

IDD2N 1460 1640 mA

IDD3P(F) 1100 1190 mA

IDD3P(S) 776 794 mA

IDD3N 1730 1910 mA

IDD4R 2360 2810 mA

IDD4W 2450 2900 mA

IDD5B 3620 3710 mA

IDD6 594 594 mA 1

IDD7 3350 3980 mA

Rev. 1.0 / Apr. 2005 16

1

240pin Registered DDR2 SDRAM DIMMs

2GB, 256M x 72 Registered DIMM : HYMP125R72[P]4

4GB, 512M x 72 Registered DIMM : HYMP351R72M[P]4

Note :

1. IDD6 current alues are guaranted up to Tcase of 85oC max.

Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Unit note

IDD0 2450 2630 mA

IDD1 2630 2810 mA

IDD2P 758 758 mA

IDD2Q 1370 1550 mA

IDD2N 1460 1640 mA

IDD3P(F) 1100 1190 mA

IDD3P(S) 776 794 mA

IDD3N 1730 1910 mA

IDD4R 2990 3710 mA

IDD4W 3170 3890 mA

IDD5B 5510 5510 mA

IDD6 476 476 mA 1

IDD7 4970 6050 mA

Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Unit note

IDD0 3530 3890 mA

IDD1 3710 4070 mA

IDD2P 866 866 mA

IDD2Q 2090 2450 mA

IDD2N 2270 2630 mA

IDD3P(F) 1550 1730 mA

IDD3P(S) 902 938 mA

IDD3N 2810 3170 mA

IDD4R 4070 4970 mA

IDD4W 4250 5150 mA

IDD5B 6590 6770 mA

IDD6 738 738 mA 1

IDD7 6050 7310 mA

Rev. 1.0 / Apr. 2005 17

1

240pin Registered DDR2 SDRAM DIMMs

IDD Meauarement Conditions

Note:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS . IDD values must be met with all combinations

of EMRS bits 10 and 11.

5. Definiti ons for IDD

LOW is defined as Vin ≤ VILAC(max)

HIGH is defined as Vin ≥ VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and

control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)

for DQ signals not including masks or strobes.

Symbol Conditions Units

IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS-

min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are

SWITCHING;Data bus inputs are SWITCHING mA

IDD1 Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK =

tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH b etween vali d

commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA

IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is L OW ; Other control and address

bus inputs are STABLE; Data bus inputs are FLOATING mA

IDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control

and address bus inputs are STABLE; Data bus inp u ts are FLOATING mA

IDD2N Precharge standby current; All bank s idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Ot he r co ntrol and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW ;

Other control and addr ess bus inputs ar e STABLE; Data bus inputs are FLOAT-

ING

Fast PDN Exit MRS(12) = 0 mA

Slow PDN Exit MRS(12) = 1 mA

IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP=tRP(IDD); CKE is

HIGH, CS is HIGH between valid commands; Other control and address bus inputs a re SWITCHING; Data bus

inputs are SWITCHING mA

IDD4W Operating burst write current; All banks open, Continu ous burst w rites; BL = 4, CL = CL(IDD), AL = 0; tCK

= tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD4R Operating burst read current; All banks open, Contin uous bu rst re ads, IOUT = 0mA; BL = 4, CL = CL(IDD),

AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid com-

mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W mA

IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is

HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING mA

IDD6 Self refresh current; CK and CK at 0V ; CKE ≤ 0.2V ; Other contro l and address b us inputs are F LOATING; Data

bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85oC max. mA

IDD7

Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),

AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is

HIGH, CS is HIGH between valid commands; Address bus inputs are ST AB LE during DESELE CTs; Data pat tern i s

same as IDD4R; - Refer to the following page for detailed timing conditions

mA

Rev. 1.0 / Apr. 2005 18

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240pin Registered DDR2 SDRAM DIMMs

Electrical Characteristics & AC Timings

Speed Bins and CL,tRCD,tRP ,tRC and tRAS for Corresponding Bin

AC Timing Parameters by Speed Grade

Speed DDR2-533 (C4) DDR2-400 (E3) Unit

Bin(CL-tRCD-tRP) 4-4-4 3-3-3

Parameter min min

CAS Latency 4 3 tCK

tRCD 15 15 ns

tRP 15 15 ns

tRC 60 55 ns

tRAS 45 40 ns

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps

DQS-Out edge to Clock edge Skew tDQSCK -500 500 -450 450 ns

Clock High Level Widt h tCH 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK

Clock Half Period tHP min

(tCL,tCH) -min

(tCL,tCH) -ns

System Clock Cycle Time tCK 5000 8000 3750 8000 ps

DQ and DM input setup time tDS 150 - 100 - ps 1

DQ and DM input hold time tDH 275 - 225 - ps 1

DQ and DM input setup time(single-ended stro be) tDS1 25 - -25 - ps 1

DQ and DM input hold time(single-ended strobe) tDH1 25 - -25 - ps 1

Control & Address input Pulse Width

for each input tIPW 0.6 - 0.6 - tCK

DQ and DM input pu lse witdth for each input pulse

width for each input tDIPW 0.35 - 0.35 - tCK

Data-out high-impedance window from CK, /CK tHZ - tAC max - tAC max ps

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps

DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 -300ps

DQ hold skew factor tQHS - 450 -400ps

DQ/DQS output hold time from DQS tQH t H P - tQHS -tHP - tQHS -ps

First DQS latching transition to associated clock edge tDQSS 0.25 +0.25 0.25 +0.25 tCK

DQS input high pulse width tDQSH 0.35 -0.35 -tCK

DQS input low pulse width tDQSL 0.35 -0.35 -tCK

DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK

Mode register set command cycle time tMRD 2 - 2 - tCK

Write pos tamble tWPST 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.35 -0.35 -tCK

Rev. 1.0 / Apr. 2005 19

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240pin Registered DDR2 SDRAM DIMMs

- Continued -

Note :

1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS1G[4/8]31(L)F).

2. 0°C TCASE 85°C

3. 85°C TCASE 95°C

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

Address and control input setup time tIS 350 -250-ps

Address and control input hold time tIH 475 -375-ps

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Auto-Refresh to Active/Auto-Refresh command

period tRFC 127.5 -127.5 -ns

Row Active to Row Active Delay for 1KB page size tRRD 7.5 - 7.5 - ns

Row Active to Row Active Delay for 2KB page size tRRD 10 - 10 - ns

Four Activate Window for 1KB page size tFAW 37.5 - 37.5 - ns

Four Activate Window for 2KB page size tFAW 50 - 50 - ns

CAS to CAS command delay tCCD 2 2 tCK

Write recov ery time tWR 15 -15-ns

Auto Precharge Write Recovery + Precharge Time tDAL tWR+tRP - tWR+tRP - tCK

Write to Read Command Delay tWTR 10 - 7.5 -ns

Internal read to precharge command delay tRTP 7.5 7.5 ns

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refresh to a read com mand tXSRD 200 -200 -tCK

Exit precharge power down to any non-read

command tXP 2 - 2 - tCK

Exit active power down to read command tXARD 2 2 tCK

Exit active power down to read command

(Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK

CKE minimum pulse width

(high and low pulse width) tCKE 33tCK

ODT turn-on delay tAOND 2222tCK

ODT turn-on tAON tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns

ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+tAC

(max)+1 tAC(min)

+2 2tCK+tAC

(max)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max)+

0.6 tAC(min) tAC(max)+

0.6 ns

ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+tAC(

max)+1 tAC(min)+2 2.5tCK+tAC(

max)+1 ns

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after CKE

asynchronously drops LOW tDelay tIS+tCK

+tIH tIS+tCK

+tIH ns

Average periodic Refresh Interv al tREFI - 7.8 - 7.8 us 2

tREFI -3.9 -3.9 us 3

Rev. 1.0 / Apr. 2005 20

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240pin Registered DDR2 SDRAM DIMMs

PACKAGE OUTLINE

128Mx72 (1 rank) - HYMP112R72[P]8

Note) All dimensions are typical millimeter scale unless otherwise stated.

Front

30.0

4.0±0.1

133.35

63.0

5.175 5.175

55.0

5.0

Back

0.8

± 0.05

1.0

0.20

Detail of Contacts A

2.50 ± 0.20

Detail of Contacts B

2.50

1.50 ± 0.10

3.80

5.00

Detail-A Detail-B

3.0 3.0

10.0

17.80

PLL

R

E

G

I

S

T

E

R

Side

2. 7 max

(Front)

1. 27 ± 0.10

Rev. 1.0 / Apr. 2005 21

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240pin Registered DDR2 SDRAM DIMMs

PACKAGE OUTLINE

256Mx72 (2 ranks) - HYMP125R72[P]8

Note) All dimensions are typical millimeter scale unless otherwise stated.

Front

30.0

4.0±0.1

133.35

63.0

5.175 5.175

55.0

5.0

Back

0.8

± 0. 05

1.0

0.20

Detail of Contacts A

2.50 ± 0.20

Detail of Contacts B

2.50

1.50 ± 0. 10

3.80

5.00

Detail-A Detail-B

Side

4.0 max

1.27 ± 0.10

3.0 3.0

10.0

17.80

R

E

G

I

S

T

E

R

PLL

R

E

G

I

S

T

E

R

Rev. 1.0 / Apr. 2005 22

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240pin Registered DDR2 SDRAM DIMMs

PACKAGE OUTLINE

256Mx72 (1 rank) - HYMP125R72[P]4

Note) All dimensions are typical millimeter scale unless otherwise stated.

Front

30.0

4.0±0.1

133.35

63.0

5.175 5.175

55.0

5.0

Back

0.8

± 0.05

1.0

0.20

Detail of Contacts A

2.50 ± 0.20

Detail of Contacts B

2.50

1.50 ± 0.10

3.80

5.00

Detail-A Detail-B

Side

4.0 max

1.27 ± 0.10

3.0 3.0

10.0

17.80

R

E

G

I

S

T

E

R

PLL

R

E

G

I

S

T

E

R

Rev. 1.0 / Apr. 2005 23

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240pin Registered DDR2 SDRAM DIMMs

PACKAGE OUTLINE

512Mx72 (2 ranks) - HYMP351R72M[P]4

Note) All dimensions are typical millimeter scale unless otherwise stated.

Front

30.0

4.0±0.1

133.35

63.0

5.175 5.175

55.0

5.0

Back

0.8

± 0.05

1.0

0.20

Detail of Contacts A

2.50 ± 0.20

Detail of Contacts B

2.50

1.50 ± 0.10

3.80

5.00

Detail-A Detail-B

3.0 3.0

10.0

17.80

R

E

G

I

S

T

E

R

PLL

R

E

G

I

S

T

E

R

Side

4. 0 max

1. 27 ± 0.10

Rev. 1.0 / Apr. 2005 24

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240pin Registered DDR2 SDRAM DIMMs

REVISION HISTORY

Revision History Date Remark

1.0

First Version Release

Data sheet coverage changed from an individual module part to a component

based module family. Dec. 2004

Added VDDL spec, corrected tDS & tDH spec values. Apr. 2005