Product Brief
August 2000
ATM UTOPIA Master Core V2.0
Features
■UTOPIA Level 1/Level 2 Master with parity genera-
tion/checking. In Level 2, all multi-PHY modes are
supported:
— 1 RxClav/1 TxClav
— Direct status
— Multiplexed status polling
■Continuous round-robin polling of programmable
range of UTOPIA addresses
■8-/ 16-bit bus width
■Programmable cell length
■Programmable HEC generation
■25/33/50 MHz operation
■Flexible control inputs with options for the
following:
— Internal/ext ernal hardwiri ng
— Access via a parallel or serial microprocessor
interface
Standards Compliance
■ATM forum UTOPIA Level 1 versi on 2.1
■ATM forum UTOPIA Level 2 versi on 1.0
Benefits
■Faster development for improved time-to-market
with ATM functions
■Lower development cost through design reuse
■
VHDL
* source code for easy design integration
■
ORCA
®-specific optimization tailor-made for high
performance
■Ample design flexibility using control signals and
VHDL
generics
■Verified functionality and standards compliance
0389(F)
Figure 1. ATM UTOPIA Master Core Application
Description
The ATM UTOPIA Master Core from
Modelware
†
implements, in modular VHDL, the master functions
of the ATM forum's UTOPIA Le vel 1 and Level 2
specifications.
The core interfaces to the ATM layer via a generic
DMA-like interface, and to single or multiple physical
(MPHY) layer ports via a UTOPIA Level 1 or Level 2
interface (Figure 1). The core monitors, in a round-
robin fashion, a programmable range of PHY ports
and reports their cell available status to the ATM
layer. The ATM layer issues commands to the
UTOPIA master core to select a PHY port and initiate
a cell transfer.
The core synthesizes into an OR2C/2T08A. When
implemented using a –4 speed
ORCA
FPGA, the
core meets the 50 MHz UTOPIA Level 2 timing spec-
ifications.
*
VHDL
is a registered trademark of Gateway Design A utomation
Corporation.
†Modelware
is a registered trademark of Modelware, Inc.
UTOPIA
MASTER
CORE
ATM
LAYER
FUNCTION
ACCESS
INTERFACE
UTOPIA
PHY
PHY
PHY
Product Brief
August 2000
ATM UTOPIA Master Core V2.0
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
ORCA
is a registered trademark of Lucent Technologies Inc.
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
August 2000
PB00-089NCIP
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro, or for FPGA informat ion, http://www.lucent.com/orca
E-MAIL: docmaster@micro.lucent.com
N. AMERICA: Microelectronics Gro up, Lucent Technologies Inc., 555 Union Boul evard, Room 3 0L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610 -712-4106 ( In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Microelectronics Group, Lucent Techno logies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHIN A: Microelectr onics Gr oup, Luc en t Technologies ( C hina) Co., Ltd., A - F 2, 23/F, Zao Fon g Univ erse Buildin g, 1800 Zhong Shan Xi Ro ad, Sha ngh ai
200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652
JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inqui ries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 59 4 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Design Package
The ATM UTOPIA master core package contains the
following:
■
VHDL
source code
■
VHDL
testbench
■Scripts and data files for simulation
(
behavioral,
g
ate-level, and back-annotated
)
, s
y
nthesis, and
FPG A la
y
out
■Detailed documentation:
— Reference
g
uide: features, architecture, inter-
faces, and operation
— User's
g
uide: simulation, synthesis, and FPGA
layout step-by step procedures
Required Tools
■MTI modelsim for simulation
■
Exemplar LeonardoSpectrum
* for s
y
nthesis
■Lucent Technolo
g
ies
ORCA
Foundr
y
for FPGA la
y
-
out
*
Exemplar
and
LeonardoSpectrum
are trademarks of Exemplar
Logic, Inc.
Additional Resources
■ORCA
ATM Ph
y
sical La
y
er CSC Application Note
(
AP97-050FPGA available from Lucent Technolo-
g
ies
)
■ORCA
OR2CxxA and OR2TxxA Series Field Pro-
g
rammable Gate Arra
y
s
Data Sheet
(
DS96-
140FPGA
)
, Au
g
ust 1996
Ordering Inform ation
Modelware, Inc.
Tel: (732)936-1808
Fax: (732)936-1838
E-mail: sales@modelware.com
Internet: www.modelware.com
