Enpirion® Power Datasheet
EN6337QI 3A PowerSoC
Voltage Mode Synchronous
PWM Buck with Integrated Inductor
www.altera.com/enpirion
Description
The EN6337QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal circuits, compensation, and the
inductor in an advanced 4mm x 7mm x 1.85mm 38-
pin QFN package.
The EN6337QI is specifically designed to meet the
precise voltage and fast transient requirements of
present and future high-performance, low-power
processor, DSP, FPGA, memory boards and system
level applications in distributed power architecture.
The device’s advanced circuit techniques, ultra high
switching frequency, and proprietary integrated
inductor technology deliver high-quality, ultra
compact, non-isolat ed DC-DC conversion.
The Altera Enpirion power solution significantly helps
in system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, a reduction in the number
of vendors required for the complete power solution
helps to enable an overall system cost savings.
All Enpirion products are RoHS compliant and lead-
free manufacturing environment compatible.
Features
• Integrated Inductor, MOSFETs, Controller
• Up to 3A Continuous Operating Current
• High Eff ic ien c y ( Up to 95%)
• Frequency Synchronization to External Clock
• Input Voltage Range (2.5V to 6.6V)
• Programmable Light Load Mode
• Optimized Total Solution Size (75mm2)
• Output Enable Pin and Power OK
• Programmable Soft-Start
• Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltag e P rotectio n
• RoHS Compliant, MSL Level 3, 260°C Reflow
Applications
• Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
• Blade Servers, RAID Storage and LAN/SAN
Adapter Cards, Wireless Base Stations, Industrial
Automation, Test and Measurement, Embedded
Computing, and Printers
• High Efficiency 12V Intermediate Bus Architectures
• Beat Frequency/Noise Sensitive Applications
VOUT
VIN
47µF
1206
22µF
1206
VOUT
ENABLE
AGND
SS
PVIN
AVIN
PGND
C
A
PGND
RA
RB
VFB
EN6337QI
LLM/
SYNC
C
SS
Figure 1. Simplified Applications Circuit
Figure 2. Highest Efficiency in Smallest Solution Size
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 110
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficiency vs. Output Curre nt
VOUT = 2 .5V LL M
VOUT = 2 .5V PWM
CONDITIONS
V
IN
= 3.3V
LLM
PWM
Actual Solution Size
75mm
2
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EN6337QI
www.altera.com/enpirion, Page 2
Ordering Information
Part Number
Package Markings
TA (°C)
Package Description
EN6337QI
EN6337QI
-40 to +85
38-pin (4mm x 7mm x 1.85mm) QFN T&R
EVB-EN6337QI
EN6337QI
QFN Evaluation Board
Packing a nd Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
NC(SW)
NC
NC
VOUT
VOUT
1
VOUT
2
3
4
5
6
7
KEEP OUT
8
VOUT
VOUT
NC(SW)
9
10
11
12
13
14
15
16
17
18
19
NC
NC
NC
NC
PVIN
25
24
23
22
21
20
38
37
NC(SW)
AVIN
VFB
AGND
RLLM
SS
ENABLE
POK
LLM / SYNC
36
35
34
33
32
31
30
29
28
27
26
NC(SW)
VOUT
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
PVIN
PVIN
NC(SW)
NC(SW)
NC(SW)
KEEP OUT
39
PGND
NC(SW)
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connecte d to the PCB. Refer to Figure 11 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN
NAME
FUNCTION
1-2, 12,
34-38 NC(SW)
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground, or
voltage. Failure to follow this guideline may result in damage to the device.
3-4, 22-
25
NC
NO CONNECT – These pins may be internally connected. Do not connect to each other or to
any other electrical signal. Failure to follow this guideline may result in device damage.
5-11 VOUT
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 13-15.
13-18 PGND
Input/Output power ground. Connect these pins to the ground electrode of the input and output
filter capacitors. See VOUT and PVIN pin descriptions for more details.
19-21 PVIN
Input power supply. Connect to input power supply. Decouple with input capacitor to PGND
pins 16-18.
26 LLM/
SYNC
Dual function pin providing LLM Enable and External Clock Synchronization (see Application
Section). At static Logic HIGH, device will allow automatic engagement of light load mode. At
static logic LOW, the device is forced into PWM only. A clocked input to this pin will
synchronize the internal switching frequency to the external signal. If this pin is left floating, it
will pull to a static logic high, enabling LLM.
27 ENABLE
Input Enable. Applying logic high enables the output and initiates a soft-start. Applying logic
low disables the output.
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PIN
NAME
FUNCTION
28 POK
Power OK is an open drain transistor used for power system state indication. POK is logic high
when VOUT is within -10% of VOUT nominal.
29 RLLM
Programmable LLM engage resistor to AGND allows for adjustment of load current at which
Light-Load Mode engages. Can be left open for PWM only operation.
30 SS
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value
of this capacitor determines the startup time.
31 VFB
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The midpoint of the divider is connected to VFB. A
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.
32 AGND
Analog Ground. This is the controller ground return. Connect to a quiet ground.
33
AVIN
Input power supply for the controller. Connect to input voltage at a quiet point.
39 PGND
Device thermal pad to be connected to the system GND plane. See Layout Recommendations
section.
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Voltages on : PVIN, AVIN, VOUT -0.3 7.0 V
Voltages on: ENABLE, POK, LLM/SYNC -0.3 V
IN
+0.3 V
Voltages on: VFB, SS, RLLM -0.3 2.5 V
Storage Temperature Range TSTG -65 150 °C
Maximum Operating Junction Temperature T
J-ABS Max
150 °C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C
ESD Rating (based on Human Body Model) 2000 V
ESD Rating (based on CDM) 500 V
Recommended Operating Cond itions
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Voltage Range V
IN
2.5 6.6 V
Output Voltage Range (Note 1) V
OUT
0.75 V
IN
– V
DO
V
Output Current IOUT 3 A
Operating Ambient Temperature TA -40 +85 °C
Operating Junction Temperature T
J
-40 +125 °C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
Thermal Shutdown TSD 160 °C
Thermal Shutdown Hysteresis TSDH 35 °C
Thermal Resistance: Junction to Ambient (0 LFM) (Note 2) θJA 30 °C/W
Thermal Resistance: Junction to Case (0 LFM) θ
JC
3 °C/W
Note 1: VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table.
Note 2: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
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Electrical Characteristics
NOTE: V IN=6.6V, Minim um and Maximum values are over operating ambient te mperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDIT IONS
MIN
TYP
MAX
UNITS
Operating Input
Voltage VIN 2.5 6.6 V
Under Voltage Lock-
out – VIN Rising VUVLOR Voltage above which UVLO is not
asserted 2.3 V
Under Voltage Lock-
out – V
IN
Falling VUVLOF Voltage below which UVLO is
asserted 2.075 V
Shut-Down Supply
Current IS ENABLE=0V 100 µA
Operating Quiescent
Current IQ LLM/SYNC = High 650 µA
Feedback Pin Voltage
VFB
Feedback node voltage at:
VIN = 5V, ILOAD = 0, TA = 25°C
(Note 6) 0.7425 0.75 0.7575 V
VFB Pin Voltage (Load
and Temperature) VVFB 0A ≤ ILOAD ≤ 3A
Starting Date Code: X501 or higher 0.739 0.75 0.761 V
Feedback Pin Voltage
(Line, Load,
Temperature) VFB
Feedback node voltage at:
2.5V ≤ VIN ≤ 6.6V
0A ≤ ILOAD ≤ 3A 0.735 0.75 0.765 V
Feedback pin Input
Leakage Current
(Note 3) IFB VFB pin input leakage current -5 5 nA
VOUT Rise Time
(Note 3) tRISE
Measured from when VIN > VUVLOR
& ENABLE pin voltage crosses its
logic high threshold to when VOUT
reaches its final value. C
SS
= 15 nF
0.9 1.2 1.5 ms
Soft Start Capacitor
Range CSS_RANGE 10 68 nF
Output Drop Out
Voltage Resistance
(Note 3)
VDO
RDO VINMIN - VOUT at Full load
Input to Output Resistance
210
70
315
105
mV
mΩ
Continuous Output
Current IOUT P WM mode
LLM mode (Note 4) 0
0.002 3
3 A
Over Current Trip
Level IOCP VIN = 5V, VOUT = 1.2V 5 A
Disable Threshold VDISABLE ENABLE pin logic low. 0.0 0.6 V
ENABLE Threshold VENABLE ENABLE pin logic high
2.5V ≤ V
IN
≤ 6.6V 1.8 VIN V
ENABLE Lockout Time TENLOCKOUT 4.2 ms
ENABLE pin Input
Current (Note 3) IENABLE ENABLE pin h as ~180kΩ pull down 40 µA
Switching Frequency
(Free Running) FSW Free Running frequency of
oscillator 1.9 MHz
External SYNC Clock
Frequency Lock
Range FPLL_LOCK Range of SYNC clock frequency 1.5 2.3 MHz
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PARAMETER
SYMBOL
TEST CONDIT IONS
MIN
TYP
MAX
UNITS
SYNC Input Threshold
– Low (LLM/SYNC
PIN) VSYNC_LO SYNC Clock Logic Level 0.8 V
SYNC Input Threshold
– High (LLM/SYNC
PIN)
(Note 5)
VSYNC_HI SYNC Clock Logic Level 1.8 2.5 V
POK Lower Threshold POKLT Output voltage as a fraction of
expected out put vo lta ge 90 %
POK Output low
Voltage VPOKL With 4mA current sink into POK 0.4 V
POK Output Hi Volta ge V
POKH
2.5V ≤ V
IN
≤ 6.6V V
IN
V
POK pin VOH leakage
current (Note 3) IPOKL POK hig h 1 µA
LLM Engage
Headroom Minimum VIN-VOUT to ensure proper
LLM operatio n 800 mV
LLM Logic Low
(LLM/SYNC PIN) VLLM_LO LLM Static L ogic Le vel 0.3 V
LLM Logic High
(LLM/SYNC PIN) VLLM_HI LLM Static L ogic Level 1.5 V
LLM/SYNC Pin
Current LLM/SYNC Pin is <2.5V <100 nA
Note 3: Parameter not production tested but is guaranteed by design.
Note 4: LLM operation is only guaranteed above the minimum specified output current.
Note 5: For proper operation of the synchronization circuit, the high-level amplitude of the SYNC signal should not be
above 2.5V.
Note 6: The VFB pin is a sensitive node. Do not touch VFB while the device is in regulation.
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Typical Performance Curves
0
10
20
30
40
50
60
70
80
90
100
00.5 11.5 22.5 3
EFFI CIENCY (%)
OUT PUT CURRENT (A)
PWM Efficiency v s. IOUT (VIN = 3.3V)
VOUT = 2 .5V
VOUT = 1 .8V
VOUT = 1 .5V
VOUT = 1 .2V
VOUT = 1 .0V
CONDITIONS
V
IN
= 3.3V
CONDITIONS
V
IN
= 3.3V
0
10
20
30
40
50
60
70
80
90
100
00.5 11.5 22.5 3
EFFI CIENCY (%)
OUT PUT CURRENT (A)
PWM Efficiency v s. I
OUT
(V
IN
= 5.0V)
VOUT = 3 .3V
VOUT = 2 .5V
VOUT = 1 .8V
VOUT = 1 .5V
VOUT = 1 .2V
VOUT = 1 .0V
CONDITIONS
V
IN
= 5V
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 110
EFFI CIENCY (%)
OUT PUT CURRENT (A)
LLM Efficiency v s. IOUT (VIN = 3.3V)
VOUT = 2 .5V
VOUT = 1 .8V
VOUT = 1 .5V
VOUT = 1 .2V
VOUT = 1 .0V
CONDITIONS
V
IN
= 3.3V
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 110
EFFI CIENCY (%)
OUT PUT CURRENT (A)
LLM Efficiency v s. I
OUT
(V
IN
= 5.0V)
VOUT = 3 .3V
VOUT = 2 .5V
VOUT = 1 .8V
VOUT = 1 .5V
VOUT = 1 .2V
VOUT = 1 .0V
CONDITIONS
V
IN
= 5V
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
00.5 11.5 22.5 3
O UTPUT VOLTAG E ( V)
O UTPUT CURRENT ( A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
V
OUT
= 1. 0V
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
00.5 11.5 22.5 3
O UTPUT VOLTAG E ( V)
O UTPUT CURRENT ( A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
V
OUT
= 1. 2V
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Typical Performance Curves (Continued)
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
00.5 11.5 22.5 3
O UTPUT VOLTAG E ( V)
O UTPUT CURRENT ( A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
V
OUT
= 1. 5V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
00.5 11.5 22.5 3
O UTPUT VOLTAG E ( V)
O UTPUT CURRENT ( A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
V
OUT
= 1.8V
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
00.5 11.5 22.5 3
O UTPUT VOLTAG E ( V)
O UTPUT CURRENT ( A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
V
OUT
= 2. 5V
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
0 0.5 1 1.5 22.5 3
O UTPUT VOLTAG E ( V)
O UTPUT CURRENT ( A)
Output Voltage vs. Output Current
VIN = 5.0V
CONDITIONS
V
OUT
= 3. 3V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
O UTPUT VOLTAG E ( V)
INPUT VOL T AG E (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 0A
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
O UTPUT VOLTAG E ( V)
INPUT VOL T AG E (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 1A
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Typical Performance Curves (Continued)
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
O UTPUT VOLTAG E ( V)
INPUT VOL T AG E (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = A
CONDITIONS
Load = 2A
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
O UTPUT VOLTAG E ( V)
INPUT VOL T AG E (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = A
CONDITIONS
Load = 3A
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-40 -15 10 35 60 85
G UA RANTEED O UTPUT CURRENT (A)
AM BIENT TEM PERATURE( C)
No Thermal Derating
Conditions
VIN = 5.0V
VOUT = 3.3V
CONDITIONS
VIN = 5.0V
VOUT = 3.3V
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
30 300
LEVEL (dBµV/m)
FREQ UENCY (MHz)
EMI Perfor mance (H orizontal Scan)
CONDITIONS
V
IN
= 5.0V
V
OUT_NOM
= 1. 5V
LOAD = 0 .5 Ω
CISPR 22 Class B 3m
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
30 300
LEVEL (dBµV/m)
FREQ UENCY (MHz)
EMI Performance (Vertical Scan)
CONDITIONS
V
IN
= 5.0V
V
OUT_NOM
= 1. 5V
LOAD = 0 .5 Ω
CISPR 22 Class B 3m
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Typical Performance Characteristics
VOUT
(A C C ouple d)
Output Ripple at 2 0MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1V
IOUT = 3A
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
VOUT
(A C C ouple d)
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1V
IOUT = 3A
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
VOUT
(A C C ouple d)
Output Ripple at 2 0MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 1V
IOUT = 3A
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
VOUT
(A C C ouple d)
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 1V
IOUT = 3A
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
VOUT
(A C C ouple d)
LLM Output Ripple at 100mA
CONDITIONS
VIN = 3.3V
VOUT = 1V
IOUT = 100mA
CIN = 22µF (1206)
COUT = 2 x 47 µF ( 1206)
VOUT
(A C C ouple d)
LLM Output Ripple at 100mA
CONDITIONS
VIN = 5V
VOUT = 1V
IOUT = 100mA
CIN = 22µF (1206)
COUT = 2 x 47 µF ( 1206)
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Typical Performance Characteristics (Continued)
ENABLE
Enable Power Up/Down
CONDITIONS
VIN = 5.5V, VOUT = 3.3V
NO LOAD, Css = 15nF
CIN = 22µF (1206)
COUT = 47 µF (1206)
VOUT
POK
LOAD
ENABLE
Enable Power Up/Down
CONDITIONS
VIN = 5.5V, VOUT = 3.3V
LOAD=1.1Ω, Css = 15nF
CIN = 22µF (1206)
COUT = 47 µF (1206)
VOUT
POK
LOAD
VOUT
(A C C ouple d)
LLM Load Transient from 0.01 to 3A
CONDITIONS
LLM = ENABLED
VIN = 5V
VOUT = 1V
CIN = 2 x 22µF (1206)
CO U T = 2 x 47µF (1206)
LOAD
VOUT
(A C C ouple d)
LLM Load Transient from 0.01 to 3A
CONDITIONS
LLM = ENABLED
VIN = 5V
VOUT = 3V
CIN = 2 x 22µF (1206)
CO U T = 2 x 47µF (1206)
LOAD
VOUT
(A C C ouple d)
P WM Load Transient from 0 to 3A
CONDITIONS
LLM = DISA BLED
VIN = 5V
VOUT = 1V
CIN = 2 x 22µF (1206)
CO U T = 2 x 47µF (1206)
LOAD
VOUT
(A C C ouple d)
P WM Load Transient from 0 to 3A
CONDITIONS
LLM = DISA BLED
VIN = 5V
VOUT = 3V
CIN = 2 x 22µF (1206)
CO U T = 2 x 47µF (1206)
LOAD
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Functional Block Diagram
Soft Start
Power
Good
Logic
Regulated
Voltage
Voltage
Reference
Compensation
Network
Thermal Limit
UVLO
Current Limit
Mode
Logic
P-Drive
N-Drive
PLL/Sawtooth
Generator
LLM/SYNC
ENABLE
SS
AGND
POK
AVIN
VFB
PGND
VOUT
NC(SW)
PVINRLLM
Error
Amp
PWM
Comp
(+)
(-)
(-)
(+)
Figure 4: Functional Block Diagram
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Functional Description
Synchronous Buck Converter
The EN6337QI is a synchronous,
programmable power supply with integrated
power MOSFET switches and integrated
inductor. The nominal input voltage range is
2.5V to 6.6V. The output voltage is
programmed using an external resistor divider
network. The control loop is voltage-mode with
a type III compensation network. Much of the
compensation circuitry is internal to the device.
However, a phase lead capacitor is required
along with the output voltage feedback resistor
divider to complete the type III compensation
network. The device uses a low-noise PWM
topology and also integrates a unique light-load
mode (LLM) to improve efficiency at light
output load currents. LLM can be disabled with
a logic pin. Up to 3A of continuous output
current can be drawn from this converter. The
2 MHz switching frequency allows the use of
small size input / output capacitors, and
enables wide loop bandwidth within a small
foot print.
Protection Features:
The power supply has the following protection
features:
• Over-current protection (to protect the IC
from excessive load current)
• Thermal shutdown wit h hysteresis.
• Under-voltage lockout circuit to keep the
converter output off while the input voltage
is less than 2.3V.
Additional Features:
• The switching frequency can be phase-
locked to an external clock to eliminate or
move beat fr eq uency tones out of band.
• Soft-start circuit allowing controlled startup
when the converter is initially powered up.
The soft start time is programmable with an
appropriate choice of soft start capacitor.
• Power good circuit indicating the output
voltage is greater than 90% of programmed
value as long as feedback loop is closed.
• To maintain high efficiency at low output
current, the device incorporates automatic
light load mode operation.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device.
When the ENABLE pin is asserted (high) the
device will undergo a normal soft start. A logic
low on this pin will power the device down in a
controlled manner. From the moment ENABLE
goes low, there is a fixed lock out time before
the output will respond to the ENABLE pin re-
asserted (high). This lock out is activated for
even very short logic low pulses on the
ENABLE pin. The ENABLE signal must be
pulled high at a slew rate faster than 1V/5µs in
order to meet startup time specifications;
otherwise, the device may experience a delay
of ~4.2ms (lock-out time) before startup occurs.
See the Electrical Characteristics Table for
technical specifications for this pin.
LLM/SYNC Pin
This is a dual functio n pi n providing LLM
Enable and External Clock Synchronization. At
static Logic HI GH, device will allow automat ic
engagement of light load mode. At static logic
LOW, the device is forced into PWM only. A
clocked in put to t his pin will synchronize the
internal switching frequency – LLM mode is not
available if this input is clocked. If this pin is
left floating, it will pull to a static logic high ,
enabling LLM.
Frequency Synchronization
The switching frequency of the DC/DC
converter can be phase-locked to an external
clock source to move unwanted beat
frequencies out of band. To avail this feature,
the clock source should be connected to the
LLM/SYNC pin. An activity detector recognizes
the presence of an external clock signal and
automatically phase-locks the internal oscillator
to this external clock. Phase-lock will occur as
long as the clock frequency is in the range
specified in the Electrical Characteristics Table.
For proper operation of the synchronization
circuit, the high-level amplitude of the SYNC
05800 June 26, 2015 Rev E
EN6337QI
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signal should not be above 2.5V. Please note
LLM is not available when synchronizing to an
exter nal freq uency.
Spread Spectrum Mode
The external clock frequency may be swept
between the limits specified in the Electrical
Characteristics Table at repetition rates of up
to 10 kHz in order to reduce EMI frequency
components.
Soft-Start Operation
During Soft-start, the output voltage is ramped
up gradually upon start-up. The output rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin
(30) and the AGND pin (32).
Rise Time: TR ≈ (CSS* 80kΩ) ± 25%
During start-up of the converter, the reference
voltage to the error amplifier is linearly
increased to its final level by an internal current
source of approximately 10uA. Typical soft-
start rise time is ~1.2mS with SS capacitor
value of 15nF. The rise time is measured from
when VIN > VUVLOR and ENABLE pin voltage
crosses its logic high threshold to when VOUT
reaches its programmed value. Please note
LLM function is disabled during the soft-start
ramp-up time.
POK Operation
The POK signal is an open drain signal
(requires a pull up resistor to VIN or similar
voltage) from the converter indicating the
output voltage is within the specified range.
The POK signal will be logic high (VIN) when
the output voltage is above 90% of
programmed VOUT. If the output voltage goes
below this threshold, the POK signal will be
logic low.
Light Load Mode (LLM) Operation
The EN6337QI uses a proprietary light load
mode to provide high efficiency at low output
currents. W hen the LLM/SYNC pin is high, the
device is in automatic LLM “Detection” mode.
When the LLM/SYNC pin is low, the device is
forced into PWM mode. In automatic LLM
“Detection” mode, when a light load condition
is detected, the device will:
(1) Step VOUT up by approximately 1.0%
above the nominal operating output voltage
setting, VNOM and as low as -0.5% below
VNOM, and then
(2) Shut down unnecessary circuitry, and then
(3) Monitor VOUT.
When VOUT falls below VNOM, the device will
repeat (1), (2), and (3). The voltage step up, or
pre-positioning, improves transient droop when
a load transient causes a transition from LLM
mode to PWM mode. If a load transient
occurs, causing VOUT to fall below the
threshold VMIN, the device will exit LLM
operation and begin normal PWM operation.
Figure 5 demonstrates VOUT behavior during
transition into and out of LLM operation.
V
OUT
I
OUT
LLM
Ripple
PWM
Ripple
V
MAX
V
NOM
V
MIN
Load
Step
Figure 5: VOUT beha vior in LLM oper a tio n.
Many multi-mode DCDC converters suffer f rom
a condition that occurs when the load current
increases only slowly so that there is no load
transient driving VOUT below the VMIN
threshold. In this condition, the device would
never exit LLM operation. This could adversely
affect efficiency and cause unwanted ripple. To
prevent this from occurring, the EN6337QI
periodically exits LLM mode into PWM mode
and measures the load current. If the load
current is above the LLM threshold current, the
device will remain in PWM mode. If the load
current is below the LLM threshold, the device
will re-enter LLM operation. There may be a
small overshoot or undershoot in VOUT when
the device exits and re-enters LLM.
The load current at which the device will enter
LLM mode is a function of input and output
voltage, and the RLLM pin resistor. For PWM
05800 June 26, 2015 Rev E
EN6337QI
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only operation, the RLLM pin can be left open.
Figure 6. Typical LLM to PWM Current vs. RLLM
To ensure normal LLM operation, LLM mode
should be enabled and disabled with specific
sequencing. For applications with explicit LLM
pin control, enable LLM after VIN ramp up is
complete. For applications with only ENABLE
control, tie LLM to ENABLE; enable the device
after V IN ramp up is complete, and disable the
device before VIN ramp down begins. For
designs with ENABLE and LLM tied to VIN,
make sure the device soft-start time is longer
than the VIN ramp-up time. LLM will start
operating after the soft-start time i s completed.
NOTE: For proper LLM operation the
EN6337QI requires a minimum difference
between VIN and VOUT, and a minimum LLM
load requirement as specified in the Electrical
Character i st ic s Ta bl e.
Over-Cu rrent Prote ction
The current limit function is achieved by
sensing the current flowing through the Power
PFET. When the sensed current exceeds the
over current trip point, both power FETs are
turned off for the remainder of the switching
cycle. If the over-current condition is removed,
the over-current protection circuit will enable
normal PWM operation. If the over-current
condition persists, the soft start capacitor will
gradually discharge causing the output voltage
to fall. When the OCP fault is removed, the
output voltage will ramp back up to the desired
voltage. This circuit is designed to provide high
noise immunity.
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the Junction temperature
exceeds approximately 150ºC. After a thermal
shutdown event, when the junction
temperature drops by approximately 20ºC, the
converter will re-start with a normal soft-start.
Input Under-Voltage Lock-Out
Internal circuits ensure that the converter will
not start switching until the input voltage is
above the specified minimum voltage.
Hysteresis and input de-glitch circuits ensure
high noise immunity and prevent false UVLO
triggers.
Compensation
The EN6337QI uses a Type III voltage mode
control compensation network. As noted
earlier, a piece of the compensation network is
the phase lead capacitor CA in Figure 7. This
network is optimized for use with about 50-
100μF of output capacitance and will provide
wide loop bandwidth and excellent transient
performance for most applications. Voltage
mode operation provides high noise immunity
at light load.
In some applications, modifications to the
compensation may be required. Refer to the
Application Information section for more
details.
Application Information
The EN6337QI output voltage is programmed
using a simple resistor divider network. Since
VFB is a sensitive node, do not touch the VFB
node while the device is in operation as doing
so may introduce parasitic capacitance into the
control loop that causes the device to behave
abnormally and damage may occur. Figure 7
shows the resistor divider configuration.
0.000
0.200
0.400
0.600
0.800
1.000
1.200
1.400
1.600
1.800
2.000
010 20 30 40 50 60 70 80 90 100
LLM TO PWM CURRENT (A)
RLLM RESISTOR (kΩ)
LLM to PWM Current vs. RLLM
VIN = 5V, VOUT = 3.3V
VIN = 3.3V, VOUT = 2.5V
VIN = 5V, VOUT = 1V
VIN = 3.3V, VOUT = 1V
CONDITIONS
TA= 25°C
Typical Values
05800 June 26, 2015 Rev E
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VFB
V
OUT
R
A
CA = 15 pF
R
B
)75.0( *75.0
200
VVOUT RA
RB
kRA
−
=
Ω=
Figure 7: VOUT Resi st or Divider &
Compensation Capacitor
An additional compensation capacitor CA is
also required in parallel with the upper resistor.
Input Capacitor Selection
The EN6337QI requires about 20uF of input
capacitance. Low-cost, low-ESR ceramic
capacitors should be used as input capacitors
for this converter. The dielectric must be X5R
or X7R rated. Y5V or equivalent dielectric
formulations must not be used as these lose
too much capacitance with frequency,
temperature and bias voltage. In some
applications, lower value capacitors are
needed in parallel with the larger, capacitors in
order to provide high frequency decoupling.
Recommended Input Capacitors
Description
MFG
P/N
10 µF, 10V, 10%
X7R, 1206
(2 capacitors needed)
Murata
GRM31CR71A106KA01L
Taiyo Yuden
LMK316B7106KL-T
22 µF, 10V, 20%
X5R, 1206
(1 capacitor needed)
Murata
GRM31CR61A226ME19L
Taiyo Yuden
LMK316BJ226ML-T
Table 1 Rec om mended I nput C apac itors
Output Capacitor Selection
The EN6337QI has been nominally optimized
for use with approximately 50-100μF of output
capacitance. Low ESR ceramic capacitors are
required with X5R or X7R rated dielectric
formulation. Y5V or equivalent dielectric
formulations must not be used as these lose
too much capacitance with frequency,
temperature and bias voltage.
Output ripple voltage is determined by the
aggregate output capacitor impedance. Output
impedance, denoted as Z, is comprised of
effective series resistance, ESR, and effective
series inductance, ESL:
Z = ESR + ESL
Placing output capacitors in parallel reduces
the impedance and will hence result in lower
PWM ripple voltage. In addition, higher output
capacitance will improve overall regulation and
ripple in light-load mod e.
nTotal
ZZZZ 1
...
111
21
+++=
Typical PWM Ripple Voltages
Output Capacitor
Configuration
Typical Output Ripple (mVp-p)
(as measured on EN6337QI
Evaluation Board)*
1 x 47 µF 25
47 µF + 10 µF
14
Table 2 Typical PWM Ripple Voltages
* Note: 2 0 MHz BW limit
Recommended Output Capacitors
Description
MFG
P/N
47uF, 6.3V, 20%
X5R, 1206
(1 or 2 capacitors needed)
Murata
GRM31CR60J476ME19L
Taiyo Yuden
JMK316BJ476ML-T
10uF, 10V, 10%
X5R, 1206
(Optional 1 capacitor i n
parallel with 47uF above)
Murata
GRM31CR71A106KA01L
Taiyo Yuden LMK316BJ226ML-T
Table 3 Recommended Output Capacitors
For best LLM performance, we recommend
using just 2x47uF capacitors mentioned in the
above table, and no 10uF capacitor.
The VOUT sense point should be just after the
last output filter capacitor right next to the
device. Additional bulk output capacitance
beyond the above recommendations can be
used on the output node of the EN6337QI as
long as the bulk capacitors are far enough from
the VOUT sense point such that they do not
interfere with the control loop operation.
In some cases modifications to the
compensation or output filter capacitance may
be required to optimize device performance
such as transient response, ripple, or hold-up
time. The EN6337QI provides the capability to
modify the control loop response to allow for
customization for such applications. Note that
in Type III Voltage Mode Control, the double
pole of the output filter is around 1/
05800 June 26, 2015 Rev E
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2π�LO∙Cout, where Cout is the equivalent
capacitance of all the output capacitors
including the minimum required output
capacitors that Altera recommended and the
extra bulk capacitors customers added based
on their design requirement. While the
compensation network was designed based on
the capacitors that Altera recommended,
increasing the output capacitance will shift the
double pole to the direction of lower frequency,
which will lower the loop bandwidth and phase
margin. In most cases, this will not cause the
instability due to adequate phase margin
already in the design. In order to maintain a
higher bandwidth as well as adequate phase
margin, a slight modification of the external
compensation is necessary. This can be easily
implemented by increasing the leading
capacitor value, Ca. In addition the ESR of the
output capacitors also helps since the ESR and
output capacitance forms a zero which also
helps to boost the phase.
COUT Range (µF) Ca (pF) Minimum ESR (mΩ)
100
15
0
200
22
0
300
27
0
400
33
0
500
39
0
800
47
> 4
1000
56
> 4
Table 4 Bulk Capacitance Compensation
Power-Up
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. Tying all three pins
together meets these requirements.
The EN6337QI supports startup into a pre-
biased output of up to 1.5V. The output of the
EN6337QI can be pre-biased with a voltage up
to 1.5V when it is firs t ena bl ed.
05800 June 26, 2015 Rev E
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Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Enpirion
PowerSoC helps alleviate some of those concerns.
The Enpirion EN6337QI DC-DC converter is
packaged in a 4x7x3mm 38-pin QFN pack age. The
QFN package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
160°C.
The following example and calculations illustrate
the thermal performance of the EN6337QI.
Example:
VIN = 5V
VOUT = 3.3V
IOUT = 3A
First calculate the output power.
POUT = 3.3V x 3A = 9.9W
Next, determine the input power based on the
efficiency (η) shown in Figure 8.
Figure 8: Efficiency vs. Output Current
For VIN = 5V, VOUT = 3.3V at 3A, η ≈ 92.5%
η = POUT / PIN = 92.5% = 0.925
PIN = POUT / η
PIN ≈ 9.9W / 0.925 ≈ 10.7W
The power dissipation (P D) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 10.7W – 9.9W ≈ 0.8W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN6337QI has
a θJA value of 30 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 0.8W x 30°C/W = 24.08°C ≈ 24°C
The junction temperature (TJ) of the device is
approximately the ambient temperature (TA) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 24°C ≈ 49°C
The maximum operating junction temperature
(TJMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (TAMAX) allo wed can
be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 24°C ≈ 101°C
The maximum am bient temperature the device can
reach is 101°C given the input and output
conditions. Note that the efficiency will be slightly
lower at higher temperatures and this calculation is
an estimate.
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 110
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficiency vs. I
OUT
(V
OUT
= 3.3V)
VOUT = 3.3V LL M
VOUT = 3.3V PWM
CONDITIONS
V
IN
= 5V
LLM
PWM
05800 June 26, 2015 Rev E
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Layout Recommendation
Figure 10 shows critical components and layer
1 traces of a recommended minimum footprint
EN6337QI layout with ENABLE tied to VIN in
PW M mode. Alternate ENABLE conf igurations,
and other small signal pins need to be
connected and routed according to specific
customer application. Please see the Gerber
files on the Altera
website www.altera.com/enpirion for exact
dimensions and other layers. Please refer to
this Figure while reading the layout
recommendations in this section.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EN6337QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EN6337QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: Three PGND pins are
dedicated to the input circuit, and three to the
output circuit. The slit in Figure 10 separating
the input and output GND circuits helps
minimize noise coupling between the converter
input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
website www.altera.com/enpirion.
Recommendation 4: The large thermal pad
underneath the component must be connected
to the system ground plane through as many
vias as possible.
Figure 10: Top PCB Layer Cr i t i cal Components
and Copper for Minimum Footprint
The drill diameter of the vias should be
0.33mm, and the vias must have at least 1 oz.
copper plating on the inside wall, making the
finished hole size around 0.20-0.26mm. Do not
use thermal reliefs or spokes to connect the
vias to the ground plane. This connection
provides the path for heat dissipation from the
converter. Please see Figures: 7, 8, and 9.
Recommendation 5: Multiple small vias (the
same size as the thermal vias discussed in
recommendation 4 should be used to connect
ground terminal of the input capacitor and
output capacitors to the system ground plane.
It is preferred to put these vias under the
capacitors along the edge of the GND copper
closest to the +V copper. Please see Figure
10. These vias connect the input/output filter
capacitors to the GND plane, and help reduce
parasitic inductances in the input and output
current loops. If the vias cannot be placed
under C IN and C OUT, then put them just outside
the capacitors along the GND slit separating
the two components. Do not use therm al reliefs
or spokes to connect these vias to the ground
plane.
Recommendation 6: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 10 this connection is
made at the input capacitor close to the VIN
connection.
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Recommendation 7: The layer 1 metal under
the device must not be more than shown in
Figure 10. See the section regarding exposed
metal on bottom of package. As with any
switch-mode DC/DC converter, try not to run
sensitive signal or control lines underneath the
conver ter packag e on other layers.
Recommendation 8: The VOUT sense point
should be just after the last output filter
capacitor. Keep the sense trace as short as
possible in order to avoid noise coupling into
the control loop.
Recommendation 9: Keep RA, CA, and RB
close to the VFB pin (see Figures 6 and 7).
The VFB pin is a high-impedance, sensitive
node. Keep the trace to this pin as short as
possible. Whenever possible, connect RB
directly to the AGND pin instead of going
through the GND plane.
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Design Considerations for Lead-Frame Based M odules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead f rame construction requires that, f or mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 11.
Only the thermal pad an d the perim eter pads are to be mechanically or e lect rically connected to t he PC board.
The PCB top layer under the EN6337QI should be c lear of any metal (copper pours, traces, or vias) except for
the thermal pad. T he “ shaded-out” ar ea in Figure 11 represent s the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is cover ed by solderm ask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package.
Figure 11: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
05800 June 26, 2015 Rev E
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Package and Mechanical
Figure 13: EN6337QI Package Dimensions (Bottom View)
Packing a nd Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innov ati on Dr ive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2014 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countri es. All oth er words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warr ant s perf orm a nce of i ts semi co nd uc to r
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
05800 June 26, 2015 Rev E
