MICROCHIP PIC16C55X EPROM-Based 8-Bit CMOS Microcontrollers Devices included in this data sheet: Referred to collectively as PIC16C55X. * PIC16C554 * PIC16C558 High Performance RISC CPU: * Only 35 instructions to learn * All single-cycle instructions (200 ns), except for program branches which are two-cycle * Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle Device Program Data Memory Memory PIC16C554 512 80 PIC16C558 2K 128 * Interrupt capability * 16 special function hardware registers * 8-level deep hardware stack * Direct, Indirect and Relative addressing modes Peripheral Features: * 13 1/0 pins with individual direction control * High current sink/source for direct LED drive * TimerO: 8-bit timer/counter with 8-bit programmable prescaler Special Microcontroller Features: * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Pin Diagram PDIP, SOIC, Windowed CERDIP RAZ O11 5 18h ~~ RAt _P _= _P- RA4/TOCKI 224 5 Oo 16H ~a OSC1/CLKIN MCLR/Vpp 49 = 15] OSC2/CLKOUT Vss 5 o 14) ~ Voo RBO/INT ~<a } 6 180 ~- RB7 RB1 ee 7 on 12) + RBG RB2 me 8 OS 110 te RBS RBS a [9 100 ~e- RB4 SSOP RAZ <> C1 ~ 200 > BAl __ _P- RA4/TOCKI 35 3 a 13 H ~a OSC1/CLKIN MCLR/ Veep (4 St 171] * OSC2/CLKOUT Vss e 75 o 160 VoD Vsse 6 O 156 ~ VDD RBO/INT C7 @ 14 ~+ RB7 RB1 ae 8 52 130 ~ RB RB2 a 0 9 120 ~e+ RBS RBS ~q [10 11 <q RB4 Special Microcontroller Features (cont'd) * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options * Serial in-circuit programming (via two pins) Four user programmable ID locations CMOS Technology: Low-power, high-speed CMOS EPROM technology Fully static design Wide operating voltage range - 2.5V to 5.5V Commercial, industrial and extended tempera- ture range Low power consumption - <2.0mMA@ 5.0V, 4.0 MHz - 15 pA typical @ 3.0V, 32 kHz - < 1.0 yA typical standby current @ 3.0V 1998 Microchip Technology Inc. Preliminary DS40143C-page 1PIC16C55X Device Differences Voltage Process Device g Oscillator Technology Range : (Microns) PIC16C554 2.5 - 5.5 See Note 1 0.9 PIC16C558 2.5 - 5.5 See Note 1 0.9 Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. DS40143C-page 2 Preliminary 1998 Microchip Technology Inc.PIC16C55X Table of Contents 1.0 General DeSCription oo... cece i i rere ene rn ener tite cee ernie tne cece ete e see eeeietnnee site seeesieeseneeesieesneesieeessietsnessneessieeninesereees 5 2.0 PICIB6C55X Device Varieties oo... cccccccccccscnsnseeceeeccsseseseeececscseaaeaeeeceseeaeeeeeeeeeccssseeeeseecscseaeeeeesecsseaaesueeeeeeensaseeeeeeecssteaeeetess 7 CM ORV celal (-(ex(0] (=| @)7- 1611 (-\) re 9 4.0 Memory Organization.. 18 5.0 I/O Ports......... 23 6.0 TimerO Module .................... .. 29 7.0 Special Features of the CPU 8.0 Instruction Set Summary 9.0 Development Support..... 10.0 Electrical Specifications.. 11.0 Packaging Information..... Appendix A: | Enhancements Appendix B: Compatibility To Our Valued Customers Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at: http:/Avwww.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS3Q000A is version A of document DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi- sion of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http:/www.microchip.com + Your local Microchip sales office (see last page) + The Microchip Corporate Literature Center; U.S. FAX: (602) 786-/277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit- erature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: + Fill out and mail in the reader response form in the back of this data sheet. + E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. 1998 Microchip Technology Inc. Preliminary DS40143C-page 3PIC16C55X NOTES: DS40143C-page 4 Preliminary 1998 Microchip Technology Inc.PIC16C55X 1.0 GENERAL DESCRIPTION The PIC16C55X are 18 and 20-Pin EPROM-based members of the versatile PIC 16CXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers. All PICmicro microcontrollers employ an advanced RISC architecture. The PIC16C55X have enhanced core features, eight-level deep stack, and multiple inter- nal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16C55X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C554 has 80 bytes of RAM. The PIC16C558 has 128 bytes of RAM. Each device has 13 I/O pins and an 8-bit timer/counter with an 8-bit programmable pres- caler. PIC16C55X devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake up the chip from SLEEP through several external and internal interrupts and reset. A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock-up. A UV-erasable CERDIP-packaged version is ideal for code development while the cost-effective One-Time Programmable (OTP) version is suitable for production in any volume. Table 1-1 shows the features of the PIC16C55X mid-range microcontroller families. A simplified block diagram of the PIC16C55X is shown in Figure 3-1. The PIC16C55X series fit perfectly in applications ranging from motor control to low-power remote sen- sors. The EPROM technology makes customization of application programs (detection levels, pulse genera- tion, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high-performance, ease of use and I/O flexibility make the PIC16C55X very versatile. 1.1 Family and Upward Compatibility Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for PIC16C5X can be easily ported to PIC16C55X family of devices (Appendix B). The PIC16C55X family fills the niche for users wanting to migrate up from the PIC16C5X family and not need- ing various peripheral features of other members of the PIC16XX mid-range microcontroller family. 1.2 Development Support The PIC16C55X family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A C compiler and fuzzy logic support tools are also available. 1998 Microchip Technology Inc. Preiininary DS40143C-page 5PIC16C55X TABLE 1-1: PIC16C55X FAMILY OF DEVICES Maximum Frequency of Operation (MHz) 20 20 EPROM Program Memory (x14 words) 512 2K Data Memory (bytes) 80 128 Timer Module(s) TMRO TMRO Interrupt Sources 3 3 I/O Pins 13 13 Voltage Range (Volts) 2.5-5.5 2.5-5.5 Brown-out Reset _ _ Packages 18-pin DIP, 18-pin DIP, SOIC; SOIC; 20-pin SSOP 20-pin SSOP All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high \/O current capability. All PIC16C55X Family devices use serial programming with clock pin RB6 and data pin RB7. DS40143C-page 6 Prelininary 1998 Microchip Technology Inc.PIC16C55X 2.0 PIC16C55X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the PIC16C55X Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number. 2.1 UV Erasable Devices The UV erasable version, offered in CERDIP package is optimal for prototype development and _ pilot programs. This version can be erased and reprogrammed to any of the oscillator modes. Microchip's PICSTART and PROMATE programmers both support programming of the PIC16C55xX. 2.2 One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. In addition to the program memory, the configuration bits must also be programmed. 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code pat- terns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and config- uration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround-Production (SQTP*) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. 1998 Microchip Technology Inc. Preiininary DS40143C-page 7PIC16C55X NOTES: DS40143C-page 8 Prelininary 1998 Microchip Technology Inc.PIC16C55X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16C55X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C55X uses a Harvard architecture, in which, program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data words. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a sin- gle-cycle (200 ns @ 20 MHz) except for program branches. The table below lists the memory (EEPROM and ROM). Device Program Data Memory Memory PIC16C554 512 80 PIC16C558 2K 128 The PIC16C554 addresses 512 x 14 on-chip program memory. The PIC16C558 addresses 2K x 14 program memory. All program memory is internal. The PIC16C55X can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped into the data memory. The PIC16C55X have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of special optimal situations make program- ming with the PIC16C55X simple yet efficient. In addi- tion, the learning curve is reduced significantly. The PIC16C55X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. A simplified block diagram is shown in Figure 3-1, with a description of the device pins in Table 3-1. 1998 Microchip Technology Inc. Preiininary DS40143C-page 9PIC16C55X FIGURE 3-1: | BLOCK DIAGRAM . Program Data Memory Device Memory (RAM) PIC16C554 512x14 80x 8 PIC16C558 2K x 14 128x8 EPROM 13 Data Bus 8 PORTA </- Program Counter Program RAO Memory RAM RAY 512x 14 File > RAZ to 8 Level Stack Registers RAS 2Kx 14 (13-bit) 80 x8 to PX] RA4/TOCKI Program 14 Bus RAM Adar) Vy PORTB Instruction reg i 7 Indirect i] RBO/INT Direct Addr Addr LA] + ees RB7:RB1 7 3 Power-up V Timer Instruction Oscillator Decode & KG=>> | Start-up Timer tt Control Power-on Reset 8 Timing Watchdog KKS> Generation KK Timer OSC1/CLKIN OSC2/CLKOUT I J TimerO MCLR_ VbbD, Vss Note 1: Higher order bits are from the status register. meme meen DS40143C-page 10 Prelininary 1998 Microchip Technology Inc.PIC16C55X TABLE 3-1: PIC16C55X PINOUT DESCRIPTION DIP Name solic SSOP VoIP Buffer Description . Pin # Type Type Pin # OSC1/CLKIN 16 18 I ST/CMOS | Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 17 oO _ Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VpPP 4 4 VP ST Master clear (reset) input/programming voltage input. This pin is an active low reset to the device. RAO 17 19 fe) ST Bi-directional I/O port RA1 18 20 fe) ST Bi-directional I/O port RA2 1 1 fe) ST Bi-directional I/O port RA3 2 2 fe) ST Bi-directional I/O port RA4/TOCKI 3 3 fe) ST Bi-directional I/O port or external clock input for TMRO. Output is open drain type. RBO/AINT 6 7 vO TTL/sT) | Bi-directional I/O port can be software programmed for internal weak pull-up. RBO/INT can also be selected as an external interrupt pin. RB1 7 8 fe) TTL Bi-directional I/O port can be software programmed for internal weak pull-up. RB2 8 9 VO TTL Bi-directional I/O port can be software programmed for internal weak pull-up. RB3 9 10 VO TTL Bi-directional I/O port can be software programmed for internal weak pull-up. RB4 10 11 VO TTL Bi-directional I/O port can be software programmed for internal weak pull-up. Interrupt on change pin. RB5 11 12 VO TTL Bi-directional I/O port can be software programmed for internal weak pull-up. Interrupt on change pin. RB6 12 13 vO TTL/sT(2) | Bi-directional I/O port can be software programmed for internal weak pull-up. Interrupt on change pin. Serial pro- gramming clock. RB/ 13 14 vo TTL/sT2) | Bi-directional I/O port can be software programmed for internal weak pull-up. Interrupt on change pin. Serial pro- gramming data. Vss 5 5.6 P _ Ground reference for logic and I/O pins. VbpD 14 15,16 P _ Positive supply for logic and I/O pins. Legend: O = output I/O = input/output P = power = Not used | = Input ST = Schmitt Trigger input TTL =TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 1998 Microchip Technology Inc. Preliminary DS40143C-page 11PIC16C55X 3.1 Clocking Scheme/Instruction Cycle The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 3-2. 3.2 Instruction Flow/Pipelining An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-2: CLOCK/INSTRUCTION CYCLE 1 Qi | Q2 | Q3 [| Q4 1 Qi | G2 | QB | Q4 1 Qi | Q2 | QB | A | (<0 nn WO en WO fe en We | Qty FN y \ | Q2 | fv f [ \ f [N\ | Internal Q3 [* Bok Of} | | | PC PC kK PCs PC+e OSC2/CLKOUT | (RC mode) Po Fetch INST (PC I Execute INST (PC-1) Fetch INST (PO+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW 1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 Fetch 4 Flush Fetch SUB_1 |Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is flushed from the pipeline while the new instruction is being fetched and then executed. DS40143C-page 12 Prelhninary 1998 Microchip Technology Inc.PIC16C55X 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16C55X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 512 x 14 (0000h - 01FFh) for the PIC16C554 and 2K x 14 (0000h - 07FFh) for the PIC16C558 are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 512 x 14 space PIC16C554 or 2K x 14 space PIC16C558. The reset vector is at 0000h and the inter- rupt vector is at 0004h (Figure 4-1, Figure 4-2). FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16C554 PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 000h KK" Interrupt Vector 0004 0005 On-chip Program Memory O1FFh 0200h COCO | 1FEFh FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR THE PIC16C558 PC<12:0> CALL, RETURN RETFIE, RETLW Stack Level 1 Stack Level 2 2 Stack Level 8 Reset Vector 000h KK" Interrupt Vector 0004 0005 On-chip Program Memory O7FFh a 0800h | 1FEFh 4.2 Data Memory Organization The data memory (Figure 4-3 and Figure 4-4) is partitioned into two Banks which contain the general purpose registers and the special function registers. Bank 0 is selected when the RPO bit (STATUS <5>) is cleared. Bank 1 is selected when the RPO bit is set. The Special Function Registers are located in the first 32 locations of each Bank. Register locations 20-6Fh (BankO) on the PIC16C554 and 20-7Fh (BankO) and AO-BFh (Bank1) on the PIC16C558 are general pur- pose registers implemented as static RAM. Some spe- cial purpose registers are mapped in Bank 1. 4.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 80 x 8 in the PIC16C554 and 128 x 8 in the PIC16C558. Each can be accessed either directly or indirectly through the File Select Register, FSR (Section 4.4). 1998 Microchip Technology Inc. Preiininary DS40143C-page 13PIC16C55X FIGURE 4-3: DATA MEMORY MAP FOR THE PIC16C554 File File Address Address ooh} = INDFC) INDFO) 80h Oth TMRO OPTION 8th 02h PCL PCL 82h 03h STATUS STATUS 83h 04h FSR FSR 84h 05h PORTA TRISA 85h 06h PORTB TRISB 86h O7h 87h 08h 88h 09h 89h OAh PCLATH PCLATH 8Ah OBh INTCON INTCON 8Bh 0Ch 8Ch ODh 8Dh OEh PCON 8Eh OFh 8Fh 10h 90h 11h 91h 12h 92h 13h 93h 14h 94h 15h 95h 16h 96h 17h 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh 1Eh 9Eh 1Fh 9Fh 20h AOh General Purpose 6Eh Register 70h OO 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as '0. Note 1: Not a physical register. FIGURE 4-4: DATA MEMORY MAP FOR THE PIC16C558 File File Address Address ooh) INDFO INDFO) 80h Oth TMRO OPTION 8th 02h PCL PCL 82h 03h STATUS STATUS 83h 04h FSR FSR 84h 05h PORTA TRISA 85h 06h PORTB TRISB 86h O7h 87h 08h 88h 09h 89h OAh PCLATH PCLATH 8Ah OBh INTCON INTCON 8Bh 0Ch 8Ch ODh 8Dh OEh PCON 8Eh OFh 8Fh 10h 90h 11h 91h 12h 92h 13h 93h 14h 94h 15h 95h 16h 96h 17h 97h 18h 98h 19h 99h 1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh 1Eh 9Eh 1Fh 9Fh 20h AOh General General Purpose Purpose Register Register BFh Coh oo 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as '0. Note 1: Not a physical register. DS40143C-page 14 Prelhninary 1998 Microchip Technology Inc.PIC16C55X 4.2.2 SPECIAL FUNCTION REGISTERS The special function registers can be classified into two sets (core and peripheral). The special function regis- The Special Function Registers are registers used by ters associated with the core functions are described the CPU and peripheral functions for controlling the in this section. Those related to the operation of the desired operation of the device (Table 4-1). These peripheral features are described in the section of that registers are static RAM. peripheral feature. TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16C55X . . . . . . . : Value on Value on Address} Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit oO POR Reset all other resets(") Bank 0 00h INDE teolsten this location uses contents of FSR to address data memory (not a physical eeze axnx | EER BERR Oth TMRO TimerO Modules Register XXXX Xxxx | UUUU UUUU 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 | 0000 0000 03h STATUS IRPe) Rp42) | RPO | TO | PD | Zz DC C 0001 1xxx | 000q quuu 04h FSR Indirect data memory address pointer XXXX Xxxx | UUUU UUUU 05h PORTA RA4 RA3 RA2 RA1 RAO ---x xxxx | ---u uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBO xxx xxxx | uuuu uuuU 07h Unimplemented = = 08h Unimplemented = = 09h Unimplemented = = OAh PGLATH = = = Write buffer for upper 5 bits of program counter ---0 0000 | ---0 0000 OBh INTCON GIE @Q) TOIE INTE | RBIE | TOIF | INTF | RBIF | c000 o00x | 0000 o00u 0Ch Unimplemented = = ODh-1Eh | Unimplemented = = 1Fh Unimplemented = = Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical | xxxx xxxx | xxx xxxx register) 81h OPTION RBPU | INTEDG| Tocs | Tose | PsA | Ps2 | Psi | Pso | i111 1111] 1111 1111 82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 | 0000 0000 83h STATUS | | RPO | TO | PD | Z | DC | C 0001 1xxx | 000g quuu 84h FSR Indirect data memory address pointer XXXX Xxxx | UUUU UUUU 85h TRISA = = = TRISA4 | TRISA3 | TRISA2 | TRISA1 | TRISAO } ---1 1111 } ---1 1111 86h TRISB TRISB7 | TRISB6 | TRISBS | TRISB4 | TRISB3} TRISB2 | TRISB1 | TRISBO}] 1111 1111 1111 1111 87h Unimplemented = = 88h Unimplemented = = gh Unimplemented = = 8Ah PGLATH = = = Write buffer for upper 5 bits of program counter ---0 0000 | ---0 0000 8Bh INTCON GIE @) TOIE INTE | RBIE | TOIF | INTF | RBIF | 0000 000x | 0000 000u 8Ch Unimplemented = = 8Dh Unimplemented = = 8Eh PCON | |e - | = [| = | POR] | ---- --0- | ---- --u- 8Fh-9Eh | Unimplemented = = Fh Unimplemented = = Legend: = Unimplemented locations read as 0, u = unchanged, x = unknown, g = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR reset and Watchdog Timer reset during normal operation. Note 2: IRP & RP bits are reserved, always maintain these bits clear. Note 3: Bit 6 of INTCON register is reserved for future use. Always maintain this bit as clear. 1998 Microchip Technology Inc. Frail od eee Muhary DS40143C-page 15PIC16C55X 4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-5, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as the destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the status register as 000uuluu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOvWF instructions be used to alter the STA- TUS register because these instructions do not affect any status bits. For other instructions, not affecting any status bits, see the Instruction Set Summary. Note 1: [The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16C55X and should be programmed as 0'. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products. Note 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. FIGURE 4-5: STATUS REGISTER (ADDRESS 03H OR 83H) Reserved Reserved R/W-0 R-1 R-1 RIW-x RIW-x | inp | api | reo | To | Po | bit7 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) bit 4: TO: Time-out bit 0 = AWDT time-out occurred bit 3: PD: Power-down bit 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit the source register. 1 = After power-up or by the CLRWDT instruction | poe | c R_ = Readable bit bito |W = Writable bit -n = Value at POR reset -x = Unknown at POR reset bit 7: IRP: Register Bank Select bit (used for indirect addressing) The IRP bit is reserved on the PIC16C55X, always maintain this bit clear. bit 6-5: RP1:RPO0: Register Bank Select bits (used for direct addressing) Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C55X, always maintain this bit clear. 1 = After power-up, CLRWDT instruction, or SLEEP instruction 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWE, ADDLW, SUBLW, SUBWF instructions)(for borrow the polarity is reversed) 1 = Acarry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: : Carry/borrow bit (ADDWE, ADDLW, SUBLW, SUBWF instructions) 1 = Acarry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of DS40143C-page 16 Prelhninary 1998 Microchip Technology Inc.PIC16C55X 4.2.2.2 The OPTION register is a readable and writable register which contains various control bits to configure the TMRO/WDT prescaler, the external RBO/INT OPTION REGISTER Note: To achieve a 1:1 prescaler assignment for TMRO, assign the prescaler to the WDT (PSA = 1). interrupt, TMRO and the weak pull-ups on PORTB. FIGURE 4-6: OPTION REGISTER (ADDRESS 81H) bit 6: bit 5: bit 4: bit 3: bit 2-0: RW-1 -RAW-1 RAW RW-1 RAW RAW RW | RBPU |INTEDG| Tocs | Tose | PsA | ps2 | pst R_ = Readable bit bit7 W =Writable bit -n = Value at POR reset bit 7: RBPU: PORTB Pull-up Enable bit 1 =PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RBO/INT pin 0 = Interrupt on falling edge of RBO/INT pin TOCS: TMRO Clock Source Select bit 1 = Transition on RA4/TOCKI pin 0 = Internal instruction cycle clock (CLKOUT) TOSE: TMRO Source Edge Select bit 1 = Increment on high-to-low transition on RA4/TOCKI pin 0 = Increment on low-to-high transition on RA4/TOCKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the TimerO module PS2:PS0: Prescaler Rate Select bits Bit Value TMRO Rate WDT Rate 000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1:16 1:8 100 1:32 1:16 101 1:64 1:32 110 1:128 1:64 111 1: 256 1:128 1998 Microchip Technology Inc. Preliminary DS40143C-page 17PIC16C55X 4.2.2.3 The INTCON register is a readable and writable register which contains the various enable and flag bits for all interrupt sources. INTCON REGISTER Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INT CON<7s>). FIGURE 4-7: _INTCON REGISTER (ADDRESS OBH OR 8BH) bit 6: bit 5: bit 4: bit 3: bit 2: bit 1: bit 0: R/W-0 Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x | ge | | toe | inte | Ree | tore | intr | RBIF | |R = Readable bit bit7 bito |W = Writable bit -n = Value at POR reset - x = Unknown at POR reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts = Reserved for future use. Always maintain this bit clear. TOIE: TMRO Overflow Interrupt Enable bit 1 = Enables the TMRO interrupt 0 = Disables the TMRO interrupt INTE: RBO/INT External Interrupt Enable bit 1 = Enables the RBO/INT external interrupt 0 = Disables the RBO/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TOIF: TMRO Overflow Interrupt Flag bit 1 =TMRO register has overflowed (must be cleared in software) 0 = TMRO register did not overflow INTF: RBO/INT External Interrupt Flag bit 1 = The RBO/INT external interrupt occurred (must be cleared in software) 0 = The RBO/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state DS40143C-page 18 Prelininary 1998 Microchip Technology Inc.PIC16C55X 4.2.2.4 PCON REGISTER The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR reset or WDT reset. See Section 7.3 and Section 7.4 for detailed reset operation. FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 fe | et | - | - | | por R_ = Readable bit bit7 bito |W = Writable bit U = Unimplemented bit, read as 0 -n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: | POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = Power-on Reset occurred bit 0: Unimplemented: Read as '0' 1998 Microchip Technology Inc. Preiininary DS40143C-page 19PIC16C55X 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high bits (PC<12:8>) are not directly readable or writable and come from PCLATH. On any reset, the PC is cleared. Figure 4-9 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 4-9 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). FIGURE 4-9: LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 Instruction with PCL as 8 7 0 * Destination PCLATH<4:0> 8 5 ALU result PCLATH PC PCH PCL 12 11 10 2 PC | GOTO, CALL 8 7 0 PCLATH<4:3> 14 Opcode <10:0> PCLATH 4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note implementing a Table Read" (AN556). 4.3.2 STACK The PIC16C55X family has an 8 level deep x 13-bit wide hardware stack (Figure 4-1 and Figure 4-2). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of aRETURN, RETLWOr a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: [here are no STATUS bits to indicate stack overflow or stack underflow conditions. Note 2: There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or vectoring to an interrupt address. DS40143C-page 20 Prelhninary 1998 Microchip Technology Inc.PIC16C55X 4.4 Indirect Addressing. INDF and FSR Registers The INDF register is not a physical register. Addressing EXAMPLE 4-1: the INDF register will cause indirect addressing. 1 Indirect addressing is possible by using the INDF reg- a ister. Any instruction using the INDF register actually : . : NEXT clrf accesses data pointed to by the file select register j (FSR). Reading INDF itself indirectly will produce 00h. tnet Writing to the INDF register indirectly results in a btfss no-operation (although status bits may be affected). An goto effective 9-bit address is obtained by concatenating the CONTINUE: 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-10. However, IRP is not used in the A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-1. INDIRECT ADDRESSING 0x20 jinitialize pointer FSR 7;to RAM INDF ;clear INDF register FSR jinc pointer FSR, 4 ;all done? NEXT ;no clear next ;yes continue PIC16C55X. FIGURE 4-10: DIRECT/INDIRECT ADDRESSING PIC16C55xX Direct Addressing Indirect Addressing (MRP41 RPO 6 from opcode 0 IRP = =7 FSR register 0 X v v / bank select location select bank select location select \ > 00 01 10 11 + 00h 00h not ubed Data Memory 7Fh 7Fh Bank 0 Bank1 Bank2 Bank3 For memory map detail see Figure 4-3 and Figure 4-4. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear. 1998 Microchip Technology Inc. Preliminary DS40143C-page 21PIC16C55X NOTES: DS40143C-page 22 Prelininary 1998 Microchip Technology Inc.PIC16C55X 5.0 WVOPORTS FIGURE 5-2: BLOCK DIAGRAM OF RA4 PIN The PIC16C55X have two ports, PORTA and PORTB. Data 5.1 PORTA and TRISA Registers bus D = 6Q WR PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input PORTA and an open drain output. Port RA4 is multiplexed with the oKCG TOCKI clock input. All other RA port pins have Schmitt Data Latch Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can config- WR ure these pins as input or output. TRISA N V/O pin ey D Q Vss Vss Schmitt __1 _ Trigger \-4 input buffer cKLG A'1' in the TRISA register puts the corresponding output driver in a hi- impedance mode. A '0' in the TRISA register puts the contents of the output latch on the selected pin(s). TRISA Latch Reading the PORTA register reads the status of the pins, RD TRISA whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write <1 Q D to a port implies that the port pins are first read, then this value is modified and written to the port data latch. ENC | Note: On reset, the TRISA register is set to all inputs. _| RD PORTA ho | FIGURE 5-1: BLOCK DIAGRAM OF TMRO clock PORT PINS RA<3:0> clock input f Data bus D Q WR VpD PortA > CK Q OH 5 Data Latch D Q N VO pin WR TRISA cK @ vss | Schmitt | TRIS Latch Trigger \ 4 input d buffer EN RD PORTA > 1998 Microchip Technology Inc. Preliminary DS40143C-page 23PIC16C55X TABLE 5-1: PORTA FUNCTIONS Name Bit # Type Function RAO bitO ST Bi-directional I/O port. RA1 bit1 ST Bi-directional I/O port. RA2 bit2 ST Bi-directional I/O port. RA3 bit3 ST Bi-directional I/O port. RA4/TOCKI bit4 ST Bi-directional I/O port or external clock input for TMRO. Output is open drain type. Legend: ST = Schmitt Trigger input TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address | Name Bit7 | Bits | Bits | Bit4 | Bits | Bit2 | Bitt Bit 0 veeon All one Resets o5h | PORTA | = = = RA4 | RAS | RA2 | RAI RAO ==-K XXXX ==-u uuu 85h TRISA | _ | TRISA4|TRISA3| TRISA2|TRISA1|TRISAO} --1 1111 ---1 1111 Legend: = Unimplemented locations, read as 0 xX = unknown u = unchanged Note: Shaded bits are not used by PORTA. DS40143C-page 24 Prelininary 1998 Microchip Technology Inc.PIC16C55X 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A 1' in the TRISB register puts the corresponding output driver in a high impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s). Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. Each of the PORTB pins has a weak internal pull-up (=200 LA typical). A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on Power-on Reset. Four of PORTBs pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The mismatch outputs of RB7:RB4 are ORed together to generate the RBIF interrupt (flag FIGURE 5-3: BLOCK DIAGRAM OF RB7:RB4 PINS latched in INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression. (See AN552 in the Microchip Embedded Control Handbook.) Note: [fachange on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. RBPUM) Data Latch Data bus D o wos T eg [POH_L Fg /0 TRIS Latch N pin D Q oe Vss WRTRISB Sc OL Vss V W VbpD weak pull-up Vpb RD PortB TTL Yst Input } , Buffer Buffer RD TRISB Latch a" Q D Set RBIF ee a RB7:RB4 pins g Lot RB7:RB6 in serial programming mode EN 4 RD Port B (OPTION<7>). Note 1: TRISB = 1 enables weak pull-up if RBPU = '0' 1998 Microchip Technology Inc. Preliminary DS40143C-page 25PIC16C55X FIGURE 5-4: BLOCK DIAGRAM OF RB3:RBO PINS REPU) Vop P weak pull-up Data Latch voo Vop Data bus D a E Fos WR PortB SCKL 4 S TRIS Latch N pin io D a Vss WRTRISB ~ y bCKLG vss \J W Input ST npu ! Butier Buffer] RD TRISB Latch Q D RD PortB EN< RBO:INT AI A st RD Port B Buffer Note 1: TRISB = 1 enables weak pull-up if RBPU = '0' (OPTION<7>). TABLE 5-3: PORTB FUNCTIONS Name Bit # Buffer Type Function RBO/INT bitO TTL/stT Input/output or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bitS TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST@&) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock pin. RB7 bit7 TTL/ST@) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data pin. Legend: ST = Schmitt Trigger, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode. TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address|Name | Bit7 | Bite | Bits | Bits | Bits | Bit2 | Bit1 | Bito Value on Value on POR All Other Rests 06h PORTB | RB7 RB6 RB5 RB4 RB3 RB2 RB1 RBo XKKK XXKX uuuu uuuu 86h TRISB | TRISB7} TRISB6 | TRISBS | TRISB4 | TRISB3 | TRISB2 | TRISB1] TRISBO} 1111 1111 1111 1111 81h OPTION | RBPU | INTEDG| TOCS | TOSE | PSA PS2 PS1 PSO 1111 1111 1111 1111 Legend: x = unknown, u = unchanged Note: Shaded bits are not used by PORTB. DS40143C-page 26 Prelininary 1998 Microchip Technology Inc.PIC16C55X 5.3 1/O Programming Considerations 5.3.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a read followed by a write operation. The BcF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bits and PORTB is written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bitO is switched into output mode later on, the content of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read modify write instructions (ex. BCF, BSE, etc.) on a port the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-1 shows the effect of two sequential read-modify-write instructions (ex., BCF, BSF, etc.) on an I/O port A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (wired-or, wired-and). The resulting high output currents may damage the chip. FIGURE 5-5: SUCCESSIVE I/O OPERATION READ-MODIFY-WRITE INSTRUCTIONS ON AN 1/0 PORT ; Initial PORT settings: PORTB<7:4> Inputs EXAMPLE 5-1: r ; PORTB<3:0> Outputs ; PORTB<7:6> have external pull-up and are not ; connected to other circuitry ' ; PORT latch PORT pins BCF PORTB, 7 i Olpp pppp llpp pppp BCF PORTB, 6 i 10pp pppp illpp pppp BSF STATUS, RPO ; BCF TRISB, 7 i 10pp pppp illpp pppp BCF TRISB, 6 i 10pp pppp 10pp pppp ; Note that the user may ; values to be OO0pp pppp. ; RB7 to be latched as the pin value have expected the pin The 2nd BCF caused (High). 5.3.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-5). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with an NOP or another instruction not accessing this I/O port. ail gel aslas) ail a2! asta) ar} a2! asl a4} ail ae! asl as) Note: This example shows write to PORTB Tepe! <4 1 T ' . rey hoon pin 1 sampled here PC PC x PC +1 K PC +2 x PC +3 followed by a read from PORTB. Instruction ; MOVWF PORTB! MOVF PORTB,W: 1 NOP NOP | | Note that: fetched ; I I I I I , Write to Read PORTB 4 (0.25 Tey - Teo) | | | | ata setup time = (0.25 Tcy - TPD PORTB | \ \ | where TCY = instruction cycle and RB7:RBO Ne I I TPp = propagation delay of Q1 cycle 1 I to output valid. ; ; Therefore, at higher clock frequencies, I I I I Execute 1 Execute , 1 MOVWEF ! MOVF ! PORTB PORTB, W a write followed by a read may be problematic. Execute NOP 1998 Microchip Technology Inc. Preiininary DS40143C-page 27PIC16C55X NOTES: DS40143C-page 28 Prelininary 1998 Microchip Technology Inc.PIC16C55X 6.0 TIMERO MODULE The TimerO module timer/counter has the following features: * 8-bit timer/counter * Readable and writable * 8-bit software programmable prescaler * Internal or external clock select * Interrupt on overflow from FFh to 00h * Edge select for external clock Figure 6-1 is a simplified block diagram of the TimerO module. Timer mode is selected by clearing the TOCS bit (OPTION<5=>). In timer mode, the TMRO will increment every instruction cycle (without prescaler). If TimerO is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to TMRO. Counter mode is selected by setting the TOCS bit. In this mode Timer0 will increment either on every rising or falling edge of pin RA4/TOCKI. The incrementing edge is determined by the source edge (TOSE) control bit (OPTION<4>). Clearing the TOSE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the TimerO module and the WatchdogTimer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to TimerO. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. Section 6.3 details the operation of the prescaler. 6.1 TIMERO Interrupt TimerO interrupt is generated when the TMRO register timer/counter overflows from FFh to 00h. This overflow sets the TOIF bit. The interrupt can be masked by clearing the TOIE bit (INTCON<5>). The TOIF bit (INTCON<2>) must be cleared in software by the TimerO module interrupt service routine before re-enabling this interrupt. The TimerO interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. See Figure 6-4 for TimerO interrupt timing. FIGURE 6-1: TIMERO BLOCK DIAGRAM Data bus RA4/TOCKI Fosc/4 pin PSout 8 Sync with ) internal TMRO clocks Programmable PSout Prescaler TOSE f (2 Tey delay) Set Flag bit TOIF PS2:PSO on Overflow TOCS Note 1: Bits, TOSE, TOCS, PS2, PS1, PSO and PSA are located in the OPTION register. 2: The prescaler is shared with Watchdog Timer (Figure 6-6) FIGURE 6-2: TIMERO (TMRO) TIMING: INTERNAL CLOCK/NO PRESCALER PC ,ai]a2|a3] a4; at] a2]a3|a4iat|az|as3] a4 jat|a2]a3]a4,a1]a2|a3|a4 iat] a2] a3] a4) a1|a2z|a3]a4iai|az|a3|a4} (Program 1 1 ' 1 1 ' ' 1 ' Counter) PC-4 x PC X PC+1 Y Pox PC+3 X Pow Pore PC+6 ) struction ' MOVWFTMRO ! MOVF TMRO,W ! MOVF TMRO,W ! MOVE TMRO,W ' MOVF TMRO,W ! MOVE TMRO,W ! I I I I I I I I I I I I I I I I I I TMRO __10 To XY To X__NTo __NTO Y-,_ N16 Yo NTOnt YX NTO, I I I I I I I I I Instruction 1 1 1 4 1 4 1 4 1 4 1 4 1 4 ' Executed ' ' WriteTMRO ' ReadTMRO ' ReadTMRO ' ReadTMRO | ReadTMRO ' ReadTMRO ! executed reads NTO reads NTO reads NTO reads NTO +1 reads NTO + 2 1998 Microchip Technology Inc. Preiininary DS40143C-page 29PIC16C55X FIGURE 6-3: TIMERO TIMING: INTERNAL CLOCK/PRESCALE 1:2 PC ,Q1|a2/ a3] a4; a1] a2] a3] a4 ,a1] 2/3] a4 1Q1] a2] a3] a4; a1] Q2| a3] a4 1Q1| a2]Q3] a4, a1] Q2]a3]aQ4 a1] aQ2]a3] a4, (Program 1 1 1 1 1 1 ' 1 ' Counter) PC-1 PC X PC+T Y POL2 x PC+S X PCH PC+5 X PC+6 ) I I I I I I I I I Instruction ' MOVWETMRO ' MOVF TMRO,W ' MOVF TMRO,W ' MOVF TMRO,W 'MOVETMRO,W ' MOVF TMRO,W ! ' Fetch I I I I I I I I I I I I I I I I I I TMRO 10 x Tot arr F NTO F YON) I I I I I I I I I Instruction 1 1 1 | 1 1 1 1 1 ' Execute : : ' WriteTMRO | ReadTMRO ' ReadTMRO | ReadTMRO ! ReadTMRO ! ReadTMRO ! executed reads NTO reads NTO reads NTO reads NTO reads NTO +1 FIGURE 6-4: TIMERO INTERRUPT TIMING ; at | a2] a3] a4; ar] az] a3] at; at| a2| as] a4; at] a2] as] a4; ar] a2] a3| ae; OSC1 y 1 1 1 1 cleouT(3) | SCL COUF:t<CS OFC NO ft 1 1 1 1 1 1 1 TMRO timer + FEh X 1 FFh X 1 OOh XY OOTh YX 02h Xo 1 4 WA TOIF bit 1 y ' ' y T r r 1 (INTCON<2>) /#________+__/ ' ' ' ' 1 ' 1 1 1 1 1 1 ' 1 1 1 1 1 GIE bit I 1 1 ' ' ' (INTCON7>) 1 I I \ L ,; ' ' Interrupt Latency Time ' ' INSTRUCTION (FLOW , 1 1 ma ; PC PC W PC +1 x PC +1 x 0004h x 0005h ' | ion | 1 eohete | ; inst (PC) Inst(PC+1) Inst (0004h) Inst (0005h) astructon | ' Inst (PC-1) ' Inst (PC) ' Dummy cycle ' Dummy cycle ' Inst (0004h) ' Note 1: TOIF interrupt flag is sampled here (every Q1). 2: Interrupt latency = 4Tcy, where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. meme meen DS40143C-page 30 Prelininary 1998 Microchip Technology Inc.PIC16C55X 6.2 Using Timer0O with External Clock When an external clock input is used for Timer9, it must meet certain requirements. The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of TimerO after synchronization. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of TOCKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for TOCKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. FIGURE 6-5: When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for TOCKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on TOCKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 6.2.2 TIMERO INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the TMRO is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing. TIMERO TIMING WITH EXTERNAL CLOCK External Clock Input or Prescaler output 2) External Clock/Prescaler Output after sampling Increment TimerO0 (Q4) Qi] Q2] Q3] Q4 1 Q1] Q2] Q3] Q4 1Q1] Q2] Q3! Q4 1Q1] Q2l Q3] Q4 | ' Small pulse: | {-\_ misses samipling f to] - TimerO TO Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = +4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. TO +1 x T0+2 oa 1998 Microchip Technology Inc. Preiininary DS40143C-page 31PIC16C55X 6.3 Prescaler An 8-bit counter is available as a prescaler for the TimerO0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 6-6). For simplicity, this counter is being referred to as prescaler throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the TimerO module and the Watchdog Timer. Thus, a prescaler assignment for the TimerO module means that there is no prescaler for the Watchdog Timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMRO register (e.g., CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. FIGURE 6-6: _BLOCK DIAGRAM OF THE TIMERO/WDT PRESCALER CLKOUT (=Fosc/4) Data Bus y 8 1 y { TOCKI M SYNC pin ) OF x U > 2 TMRO reg | ' x Tey TOSE I A TOCS PSA Set flag bit TOIF on Overflow 0 _ . M > 8-bit Prescaler U Watchdog 1} Xx 8 Timer . | 8-to-1MUX t PSO - PS2 PSA . 0 1 WDT Enable bit MUX |}a PSA WDT Time-out Note: TOSE, TOCS, PSA, PSO-PS2 are bits in the OPTION register. DS40143C-page 32 Prelininary 1998 Microchip Technology Inc.PIC16C55X 6.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed on the fly during program execution). To avoid an unintended device To change prescaler from the WDT to the TMRO module use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled. . . . EXAMPLE 6-2: CHANGING PRESCALER RESET, the following instruction sequence . (WDT->TIMERO) (Example 6-1) must be executed when changing the prescaler assignment from TimerO to WDT. Lines 5-7 are required only if the desired postscaler rate is 1:1 CDRWDT iClear WDT and (PS<2:0> = 000) or 1:2 (PS<2:0> = 001). jPrescater BSF STATUS, RPO MOVLW b'xxxxOxxx' ;Select TMRO, new EXAMPLE 6-1: CHANGING PRESCALER ;prescale value and (TIMEROWDT) ;clock source MOVWE OPTION 1.BCF STATUS, RPO ;Skip if already in BCE STATUS, RPO ;, Bank 0 2.CLRWDT ;Clear WDT 3.CLRF TMRO ;Clear TMRO & Prescaler 4. BSF STATUS, RPO ;Bank 1 5.MOVLW '00101111b; ;These 3 lines (5, 6, 7) 6.MOVWF OPTION ; are required only if ; desired PS<2:0> are 7.CLRWDT ;, 000 or O01 8.MOVLW 'O00101xxxb ;Set Postscaler to 9.MOVWF OPTION ; desired WDT rate 10.BCF STATUS, RPO ;Return to Bank 0 TABLE 6-1: REGISTERS ASSOCIATED WITH TIMERO Address | Name Bit7 | Bits | Bits | Bit4 | Bits | Bit2 | Bit1 | Bito Value on Value on POR All Other Resets Oth TMRO TimerO modules register XXXX XXXX uuuu uuuU OBh/8Bh | INTCON GIE + TOIE INTE RBIE TOIF INTE RBIF 0000 000x 0000 000x 81h OPTION | RBPU | INTEDG | ToCs TOSE PSA PS2 PS1 PSO 1111 1111 1111 1111 85h TRISA _ _ _ TRISA4 | TRISAS | TRISA2 | TRISA1 | TRISAO ---1 1111 ---1 1111 Legend: = Unimplemented locations, read as 0. + = Reserved for future use. Note: Shaded bits are not used by TMRO module. 1998 Microchip Technology Inc. Preiininary DS40143C-page 33PIC16C55X NOTES: DS40143C-page 34 Prelininary 1998 Microchip Technology Inc.PIC16C55X 7.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16C55X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: 1. OSC selection 2. Reset Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-Up Timer (OST) Interrupts Watchdog Timer (WDT) SLEEP Code protection ID Locations In-circuit serial programming ON Oar Ww The PIC16C55X has a Watchdog Timer which is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two functions on-chip, most applications need no external reset circuitry. The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. 1998 Microchip Technology Inc. Preliminary DS40143C-page 35PIC16C55X 7.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. FIGURE 7-1: CONFIGURATION WORD The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming. | CP4 | cpot | CP4 | cpot | CP4 | cpot | = lReserved| CPt | cpo' [PWATE|woTE|Fosc1|Fosco| CONFIG Address bitt3 bit 13-8 CP<1:0>: Code protection bits) 5-4: 11 = Program Memory code protection off 10 =0400h - 07FFh code protected 01 = 0200h - 07FFh code protected 11 =0000h - 07FFh code protected bit 7: Unimplemented: Read as '1 bit 6: Reserved: Do not use bit 3: PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 =WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSCO: Oscillator Selection bits 11 =RC oscillator 10 = HS oscillator 01 = XT oscillator 00 =LP oscillator Note 1: All of the CP1:CPO pairs have to be given the same value to enable the code protection scheme listed. bio. =| REGISTER: 2007h DS40143C-page 36 Preliminary 1998 Microchip Technology Inc.PIC16C55X 7.2 Oscillator Configurations 7.2.1 OSCILLATOR TYPES The PIC16C55X can be operated in four different oscillator options. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * LP Low Power Crystal * XT Crystal/Resonator * HS High Speed Crystal/Resonator * RC Resistor/Capacitor 7.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 7-2). The PIC16C55X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin (Figure 7-3). FIGURE 7-2: CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION) \ Osc >o [4 ; : for 1 To internal logic [5 XTAL osce | * _ ce see Note SLEEP PIC16C55X See Table 7-1 and Table 7-2 for recommended values of C1 and C2. Note: A series resistor may be required for AT strip cut crystals. FIGURE 7-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Clock from > ext. system Ose) Open ~ 0SC2 PIC16C55X TABLE 7-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS (PRELIMINARY) Ranges Characterized: Mode Freq OSC1(C1) OSC2(C2) XT 455 kHz 22 - 100 pF 22 - 100 pF 2.0 MHz 15 - 68 pF 15 - 68 pF 4.0 MHz 15 - 68 pF 15 - 68 pF HS 8.0 MHz 10 - 68 pF 10 - 68 pF 16.0 MHz 10 - 22 pF 10 - 22 pF Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult with the resonator manufacturer for appropriate values of external compo- nents. TABLE 7-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR (PRELIMINARY) Mode Freq OSC1(C1) OSC2(C2) Lp 32 kHz 68-100pF | 68-100pF 200 kHz 15 - 30 pF 15 - 30 pF 100 kHz 68-150pF | 150-200 pF XT 2 MHz 15 - 30 pF 15 - 30 pF 4 MHz 15 - 30 pF 15 - 30 pF 8 MHz 15 - 30 pF 15 - 30 pF HS 10 MHz 15 - 30 pF 15 - 30 pF 20 MHz 15 - 30 pF 15 - 30 pF Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult with the crystal manufacturer for appropriate values of external compo- nents. 1998 Microchip Technology Inc. Preliminary DS40143C-page 37PIC16C55X 7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a pre-packaged oscillator can be used or a sim- ple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 7-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180 phase shift that a parallel oscillator requires. The 4.7 kQ resistor provides the negative feedback for stability. The 10kQ potentiometers bias the 74AS04 in the linear region. This could be used for external oscillator designs. FIGURE 7-4: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT +5V To other Too 4 eviceS BIC16C55X 47k 74AS04 AW 74AS04 | CLKIN Box , 4 XTAL K+ 2S + ose 10k 7.2.4 RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 7-6 shows how the R/C combination is connected to the PIC16C55xX. For Rext values below 2.2 kQ, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 MQ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 kQ and 100 kQ Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (Figure 3-2 for waveform). FIGURE 7-6: _RC OSCILLATOR MODE Figure 7-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180 phase shift in a series resonant oscillator circuit. The 330 Q resistors provide the negative feedback to bias the inverters in their linear region. FIGURE 7-5: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT To other Devi R20 2 S20 eves 1C16C55X 74AS04 74AS04 74AS04 CLKIN XTAL < oO oO PIC16C55X Rext osct | [LZ }_] Internal Clock Cext IKK Fosa/4 | OSC2/CLKOUT DS40143C-page 38 Preliminary 1998 Microchip Technology Inc.PIC16C55X 7.3 Reset The PIC16C55X differentiates between various kinds of reset: a) Power-on reset (POR) b) MCLR reset during normal operation c) MCLR reset during SLEEP d) WODT reset (normal operation) e) WDT wake-up (SLEEP) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a reset state on Power-on reset, on MCLR or WDT reset and on MCLR reset during SLEEP. They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different reset situations as indicated in Table 7-4. These bits are used in software to determine the nature of the reset. See Table 7-6 for a full descrip- tion of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 7-7. The MCLR reset path has a noise filter to detect and ignore small pulses. See Table 10-4 for pulse width specification. FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset Zz. MCLR/ Vpp Pin SLEEP WDT | WDT Module | time-out Reset VDD rise detect Vpp Power-on Reset Ss OST/PWRT OST Chip_Reset 10-bit Ripple-counter R Q- OSC1/ CLKIN Pin a PWRT ene > 10-bit Ripple-counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. See Table 7-3 for time-out situations. 1998 Microchip Technology Inc. Preliminary DS40143C-page 39PIC16C55X 7.4 Power-on Reset (POR), Power-up_ Timer (PWRT), Oscillator Start-up Timer (OST) 7.4.1 POWER-ON RESET (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.6 V- 1.8 V). To take advantage of the POR, just tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details. The POR circuit does not produce internal reset when VbD declines. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607 Power-up Trouble Shooting. 7.4.2 POWER-UP TIMER (PWRT) The Power-up Timer provides a fixed 72 ms (nominal) time-out on power-up only, from POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A configuration bit, PWRTE can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-Up Time delay will vary from chip to chip and due to VDD, temperature and process variation. See DC parameters for details. 7.4.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on power-on reset or wake-up from SLEEP. 7.4.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after POR has expired, then OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in RC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 7-8, Figure 7-9 and Figure 7-10 depict time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (see Figure 7-9). This is useful for testing purposes or to synchronize more than one PIC16C55X device oper- ating in parallel. Table 7-5 shows the reset conditions for some special registers, while Table 7-6 shows the reset conditions for all the registers. DS40143C-page 40 Preliminary 1998 Microchip Technology Inc.PIC16C55X 7.4.55 POWER CONTROL/STATUS REGISTER (PCON) Bit! is POR (Power-on-reset). It is a 0 on power-on-reset and unaffected otherwise. The user must write a 1 to this bit following a power-on-reset. Ona subsequent reset if POR is 0, it will indicate that a power-on-reset must have occurred (VDD may have gone too low). TABLE 7-3: TIME-OUT IN VARIOUS SITUATIONS Power-up 7 Oscillator Configuration vee eom PWRTE =0 PWRTE = 1 XT, HS, LP 72 ms + 1024 Tosc 1024 Tosc 1024 Tosc RC 72 ms TABLE 7-4: STATUS BITS AND THEIR SIGNIFICANCE POR T PD 0 1 1 Power-on-reset a) a) xX Illegal, TO is set on POR 0 x 0 legal, PD is set on POR 1 0 u WDT Reset 1 0 WDT Wake-up 1 u u MCLR reset during normal operation 1 MCLR reset during SLEEP 1998 Microchip Technology Inc. Preliminary DS40143C-page 41PIC16C55X TABLE 7-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program STATUS PCON Condition Counter Register Register Power-on Reset 000h 0001 1xxx ---- --0- MCLR reset during normal operation 000h 000u uuuu ---- --u- MCLR reset during SLEEP 000h 0001 Ouuu ---- --u- WDT reset 000h 0000 uuuu ---- -cu- WDT Wake-up PC +1 uuu0 Ouuu eatin ten Interrupt Wake-up from SLEEP PC + 1") uuul Ouuu soo --u- Legend: u=unchanged, x = unknown, = unimplemented bit, reads as 0. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1. TABLE 7-6: INITIALIZATION CONDITION FOR REGISTERS MCLR Reset during normal operation + Wake up from SLEEP + MCLR Reset during through interrupt SLEEP * Wake up from SLEEP Register Address Power-on Reset WDT Reset through WDT time-out WwW - XXXX KXXXX uuuu uuuu uuuu uuuu INDF 00h - - - TMRO Oth XXXX XXKX uuuu uuuU uuuu uuuU PCL 02h 0000 0000 0000 0000 pc + 1) STATUS 03h 0001 1lxxx 000q quuu!?? uuuq quuu') FSR 04h XXXX XXXX uuuu uuuUu uuuu uuuUu PORTA 05h ---X XXKX ---u uuuu ---u uuuu PORTB 06h XXXX XXXX uuuu uuuUu uuuu uuuUu PCLATH OAh ---0 0000 ---0 0000 ---u uuuu INTCON OBh 0000 000x 0000 000u uuuu uuu )? OPTION 81h 1111 1111 1111 1111 uuuu uuuUu TRISA 85h ---1 1111 ---1 1111 ---u uuuu TRISB 86h 1111 1111 1111 1111 uuuu uuuUu PCON 8Eh ---- --0- ---- HH eatin ten Legend: u = unchanged, x = unknown, = unimplemented bit, reads as 0,q = value depends on condition. Note 1: One or more bits in INTCON will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 7-5 for reset value for specific condition. DS40143C-page 42 Preliminary 1998 Microchip Technology Inc.PIC16C55X FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO Vpp): CASE 1 VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 4 TPWRT '-TOSt FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO Vpb): CASE 2 VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 4 TPWRT a < Tost FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO Vpp): CASE 3 VDD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 4 i+ TPWRFE* ! - Tost 1998 Microchip Technology Inc. Preliminary DS40143C-page 43PIC16C55X FIGURE 7-11: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW Vpp POWER-UP) VDD Note 1: VDD R1 MCLR PIC16C55X Cc -t External power-on reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capaci- tor quickly when VDD powers down. < 40 kQ is recommended to make sure that voltage drop across R does not vio- late the devices electrical specification. R1 = 100Q to 1 kQ will limit any current flowing into MCLR from external capaci- tor C in the event of MCLR/VPP pin break- down due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). DS40143C-page 44 Preliminary 1998 Microchip Technology Inc.PIC16C55X 7.5 Interrupts The PIC16C55X has 3 sources of interrupt: External interrupt RBO/INT * TMRO overflow interrupt * PortB change interrupts (pins RB7:RB4) The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. GIE is cleared on reset. The return from interrupt instruction, RETF IE, exits the interrupt routine as well as sets the GIE bit, which re-enables RBO/INT interrupts. The INT pin interrupt, the RB port change interrupt and the TMRO overflow interrupt flags are contained in the INTCON register. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in soft- ware before re-enabling interrupts to avoid RBO/INT recursive interrupts. FIGURE 7-12: INTERRUPT LOGIC For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 7-13). The latency is the same for one or two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again. TOIF + TOIE RBIF RBIE GIE Wake-up (If in SLEEP mode) | wet } > | ) Interrupt to CPU 1998 Microchip Technology Inc. Preliminary DS40143C-page 45PIC16C55X 7.5.4 RBO/INT INTERRUPT An external interrupt on RBO/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or fall- ing if INTEDG bit is clear. When a valid edge appears on the RBO/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. The RBO/INT interrupt can wake-up the processor from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 7.8 for details on SLEEP and Figure 7-16 for timing of wake-up from SLEEP through RBO/INT interrupt. FIGURE 7-13: INT PIN INTERRUPT TIMING 7.5.2 = TMRO INTERRUPT An overflow (FFh 00h) in the TMRO register will set the TOIF (INTCON<2>) bit. The interrupt can be enabled/disabled by _ setting/clearing TOIE (INTCON<5=) bit. For operation of the TimerO module, see Section 6.0. 7.5.3 PORTB INTERRUPT An input change on PORTB <7:4> sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/dis- abled by setting/clearing the RBIE (INTCON<4>) bit. For operation of PORTB (Section 5.2). Note: [f a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF inter- rupt flag may get set. Osc CLKOUT @) INT pin + Q1| Q2] Q3] a4: a1 | Q2] Q3] Q4: a1 | Q2] Q3| Q4: Q1| Q2| Q3] Q4: Q1| Q2| Q3] a4: . e W INTFflag 1 tS" Y76) GIE bit Interrupt Latency(2) (INTCON<7>) + (INTCON<1>) ' i INSTRUCTION FLOW PC < PC ~ rene PC+i Inst (PC) Inst (PC-+1) fetched sroouted 4 Inst (PC) executed Inst (PC-1) Note 1:INTF flag is sampled here (every Q1). 3: CLKOUT is available only in RC oscillator mode. >< 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. Dummy Cycle PC+i x 0004h <x 0005h > Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) DS40143C-page 46 Preliminary 1998 Microchip Technology Inc.PIC16C55X 7.6 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key reg- isters during an interrupt, e.g. W register and STATUS register. This will have to be implemented in software. Example 7-1 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x20 in Bank 0 and it must also be defined at OxA0 in Bank 1). The user register, STATUS_TEMP, must be defined in Bank 0. The Example 7-1: * Stores the W register * Stores the STATUS register in Bank 0 * Executes the ISR code * Restores the STATUS (and bank select bit register) Restores the W register EXAMPLE 7-1: SAVING THE STATUS AND W REGISTERS IN RAM ;copy W to temp register, ;could be in either bank MOVWE W_TEMP SWAPF STATUS, W ;Swap status to be saved into W BCF STATUS, RPO ;change to bank 0 regardless 7;of current bank ;save status to bank 0 ;register MOVWE STATUS TEMP (ISR) SWAPF STATUS TEMP,W ;swap STATUS TEMP register ;into W, sets bank to original j;state MOVWE STATUS ;move W into STATUS register SWAPF W_TEMP, F 7 swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W 77 Watchdog Timer (WDT) The watchdog timer is a free running on-chip RC oscil- lator which does not require any external components. This RC oscillator is separate from the RC oscillator of the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the con- figuration bit WDTE as clear (Section 7.1). 7.7.4 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with tempera- ture, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. 7.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler) it may take several seconds before a WDT time-out occurs. 1998 Microchip Technology Inc. Preliminary DS40143C-page 47PIC16C55X FIGURE 7-14: WATCHDOG TIMER BLOCK DIAGRAM From TMRO Clock Source (Figure 6-6) Watchdog Timer 1 , i WDT Enable Bit Postscaler q 8 - to -1 MUX Lg PS<2:0> o@p To TMRO (Figure 6-6) Oy ' 1 MUX Lug PSA WDT Time-out Note: TOSE, TOCS, PSA, PS0-PS2 are bits in the OPTION register. FIGURE 7-15: SUMMARY OF WATCHDOG TIMER REGISTERS Address | Name Bit7 | Bite | Bts|Bit4a| Bits | Bit2 | Bitt | Bito | Valueonpor| alueonall other Resets 2007h_ | Config. bits | + |Cpi |GPo |PWRTE| wore |FoOSsci | FOSCO 8th OPTION |RBPU |INTEDG|Tocs|ToseE|Psa |ps2 |Pst Pso. [44411414 41141114 Legend: Shaded cells are not used by the Watchdog Timer. = Unimplemented location, read as 0. + = Reserved for future use. DS40143C-page 48 Preliminary 1998 Microchip Technology Inc.PIC16C55X 7.8 Power-Down Mode (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit in the STATUS register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before SLEEP was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, all I/O pins should be either at VDD, or Vss, with no external circuitry drawing current from the I/O pin. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by float- ing inputs. The TOCKI input should also be at VDD or Vss for lowest current consumption. The contribution from on chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). Note: [tshouldbe noted thata RESE! generated by a WDT time-out does not drive MCLR pin low. 7.8.1 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. External reset input on MCLR pin 2. Watchdog Timer Wake-up (if WDT was enabled) 3. Interrupt from RBO/INT pin or RB Port change The first event will cause a device reset. The two latter events are considered a continuation of program exe- cution. The TO and PD bits in the STATUS register can be used to determine the cause of device reset. PD bit, which is set on power-up is cleared when SLEEP is invoked. TO bit is cleared if WDT Wake-up occurred. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the correspond- ing interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the inter- rupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction. Note: lf the global interrupts are disabled (GIE is cleared), but any interrupt source has both its interrupt enable bit and the correspond- ing interrupt flag bits set, the device will immediately wakeup from sleep. The sleep instruction is completely executed. The WDT is cleared when the device wakes-up from sleep, regardless of the source of wake-up. FIGURE 7-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT , a1] a2] a3] a4} ai] a2] a3] a4) ai] + at] a2} as] aa ai] a2] as]as} ai] a2] as] a4} at| a2| a3] a4} Note 1: XT, HS or LP oscillator mode assumed. _ i L lL eLKOUT() Lf F7e__ sf F____f Tos) / N / AN / AN / 1 1 1 1 ' I 1 1 1 1 INT pint ' ! ' ' ' ' 1 1 1 1 1 T I 1 1 1 1 INTF fl 1 1 1 ! (INTCONet >) fr 1 | Interrupt Latency , ; : 1 1 1 ' 1 1 (Note 2) 1 1 1 GIE bit 1 1 1 ' 1 1 1 1 1 I _T (INTCON<7>) ' Processor in , \ 1 1 1 SLEEP! 1 1 1 1 1 I I I ' I I I I I INSTRUCTION FLOW 1 1 ' 1 1 1 1 1 1 \ \ ' \ \ \ \ pc X PC x PC+1 X PC+2 x PC+2 x PC +2 x 0004h x 0005h 1 Instructi fetched {: Inst(PC) =SLEEP | Insit(PC +1)! ' Inst(PC +2)! ' Inst(0004h) ! ~Inst(0005h) astruction Inst(PC - 1) 1 SLEEP 1 1 Inst(PC + 1) 1 Dummy cycle 1 Dummy cycle 1 Inst(0004h) 2: TOST = 1024Tosc (drawing not to scale) This delay will not be there for RC osc mode. 3: GIE= '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 1998 Microchip Technology Inc. Preliminary DS40143C-page 49PIC16C55X 7.9 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip does not recommend code protecting windowed devices. 7.10 ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Only the least significant 4 bits of the ID locations are used. 7.11 In-Circuit Serial Programming The PIC16C55X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Specifications (Literature #DS30228). A typical in-circuit serial programming connection is shown in Figure 7-17. FIGURE 7-17: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION ' To Normal External ' Connections Connector | PIC16C55X Signals +5V 1 VDD ov ; \ Vss VPP ; e MCLR/VpPP CLK : T RBG Data I/O RB? ; Vop ' To Normal Connections DS40143C-page 50 Preliminary 1998 Microchip Technology Inc.PIC16C55X 8.0 INSTRUCTION SET SUMMARY Each PIC16C55xX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16C55X instruc- tion set summary in Table 8-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode field descriptions. For byte-oriented instructions, f' represents a file register designator and d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If d' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, b' represents a bit field designator which selects the number of the bit affected by the operation, while f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. TABLE 8-1: OPCODE FIELD DESCRIPTIONS Field Description f |Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label xo! Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d= 1: store result in file register f. Default is d = 1 label | Label name TOS |Top of Stack PC |Program Counter PCLATH| Program Counter High Latch GIE |Global Interrupt Enable bit WDT |Watchdog Timer/Counter TO | Time-out bit PD |Power-down bit dest |Destination either the W register or the specified register file location [ ] |Options ( ) |Contents |Assigned to <> |Register bit field |Inthe set of italics |User defined term (font is courier) The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is lus. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 us. Table 8-1 lists the instructions recognized by the MPASM assembler. Figure 8-1 shows the three general formats that the instructions can have. Note: [fo maintain upward compatibility with future PiCmicro products, do not use the OPTION and TRIS instructions. All examples use the following format to represent a hexadecimal number: Oxhh where h signifies a hexadecimal digit. FIGURE 8-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0 OPCODE | d | f (FILE #) | d= 0 for destination W d= 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE [b (BIT #)| f (FILE #) | it bit address it file register address b=3 f =7- b b Literal and control operations General 13 8 7 0 OPCODE | k (literal) | k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value 1998 Microchip Technology Inc. Preiininary DS40143C-page 51PIC16C55X TABLE 8-2: PIC16C55X INSTRUCTION SET Mnemonic, Description Cycles 14-Bit Opcode Status Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f,d | Add W and f 1 00 Q1l1l1 dfff ffff| C,DC,Z 1,2 ANDWF f,d | AND W with f 1 00 0101 dfff ffff|Z 1,2 CLRF f Clear f 1 00 0001 lfff ffff|Z 2 CLRW - Clear W 1 00 0001 0000 oo11/Z COMF f,d | Complement f 1 00 1001 dfff ffff)Z 1,2 DECF f,d_ | Decrement f 1 00 0011 dfff ffff]Z 1,2 DECFSZ f,d | Decrement f, Skip if 0 1(2) | 00 1011 dfff ffff 1,2,3 INCF f,d_ | Increment f 1 00 1010 dfff ffff]Z 1,2 INCFSZ f,d | Increment f, Skip if 0 1(2) | 00 1111 dfff ffff 1,2,3 IORWF f,d | Inclusive OR W with f 1 00 0100 dfff ffff|Z 1,2 MOVF f,d Move f 1 00 1000 dfff ffff|Z 1,2 MOVWF f Move W to f 1 00 ooo0o0 lfff ffft NOP : No Operation 1 00 0000 Oxx0 0000 RLF f,d | Rotate Left f through Carry 1 00 1101 dfff ffffl}c 1,2 RRF f,d | Rotate Right f through Carry 1 00 1100 dfff ffffl|c 1,2 SUBWF f,d_ | Subtract W from f 1 00 0010 dfff ffff}C,DC.Z 1,2 SWAPF f,d | Swap nibbles in f 1 00 1110 dfff ffff 1,2 XORWF f,d | Exclusive OR W with f 1 00 0110 dfff ffff|Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f,b Bit Clear f 1 O1 O0Obb bfff ffftf 1,2 BSF f,b Bit Set f 1 O1 Olbb bfff ffff 1,2 BTFSC f,b | Bit Test f, Skip if Clear 1(2) | 01 10bb bfff ffff 3 BTFSS f,b | Bit Test f, Skip if Set 1(2) | 01 llbb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal and W 1 11 1llx kkkk kkkk| C,DC,Z ANDLW k AND literal with W 1 11 1001 kkkk kkkk] Z CALL k Call subroutine 2 10 Okkk kkkk kkkk CLRWDT- - Clear Watchdog Timer 1 00 0000 0110 0100} TO.PD GOTO k Go to address 2 10 kkk kkkk kkkk IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk]| Z MOVLW k Move literal to W 1 11 OOxx kkkk kkkk RETFIE : Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal in W 2 11 Olxx kkkk kkkk RETURN : Return from Subroutine 2 00 0000 9000 1000 SLEEP - Go into standby mode 1 00 0000 0110 0011} TOPD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk} C,DC,Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk] Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0. 2: If this instruction is executed on the TMRO register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS40143C-page 52 Prelhninary 1998 Microchip Technology Inc.PIC16C55X 8.1 Instruction Descriptions ADDLW Add Literal and W ANDLW AND Literal with W Syntax: [ label] ADDLW_ k Syntax: [ label] ANDLW_ k Operands: 0<k<255 Operands: 0<k<255 Operation: (W) +k > (W) Operation: (W) .AND. (k) > (W) Status Affected: C,DC,Z Status Affected: Z Encoding: | 11 | 1lix | kkkk | kkkk | Encoding: | 11 | 1001 | kkkk | kkkk | Description: The contents of the W register are Description: The contents of W register are added to the eight bit literal 'k' and the ANDed with the eight bit literal 'k. The result is placed in the W register. result is placed in the W register. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example ADDLW 0x15 Example ANDLW Ox5F Before Instruction Before Instruction W = 0x10 W = O0xA3 After Instruction After Instruction W = 0x25 W = 0x03 ADDWF Add W and f ANDWF AND W with f Syntax: [ label] ADDWF _ fd Syntax: [ label] ANDWF _ fd Operands: O<f<127 Operands: O<f<127 de [0,1] de [0,1] Operation: (W) + (f) (dest) Operation: (W) .AND. (f) (dest) Status Affected: C, DC, Z Status Affected: Z Encoding: | 00 | 0111 | dfif | fff | Encoding: | 00 | 0101 | afft | ffff | Description: Add the contents of the W register Description: AND the W register with register 'f'. If with register 'f'. If 'd is 0 the result is 'd' is 0 the result is stored in the W stored in the W register. If 'dis 1 the register. If 'd is 1 the result is stored result is stored back in register 'f. back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example ADDWF FSR, 0 Example ANDWF FSR, 1 Before Instruction Before Instruction W = 0x17 W = 0x17 FSR= OxC2 FSR= OxC2 After Instruction After Instruction W = OxD9 W = 0x17 FSR= OxC2 FSR= 0x02 1998 Microchip Technology Inc. Preliminary DS40143C-page 53PIC16C55X Bit Test, Skip if Clear BCF Bit Clear f BTFSC Syntax: [label] BCF fb Syntax: Operands: O<f<127 Operands: O<b<7 Operation: 0 > (f<b>) Operation: Status Affected: None Status Affected: Encoding: | O1 | 00bb | bfff | ffff | Encoding: Description: Bit 'b' in register 'f' is cleared. Description: Words: 1 Cycles: 1 Example BCE FLAG REG, 7 Before Instruction After Instruction a Words: FLAG_REG = 0x47 Cycles: Example BSF Bit Set f Syntax: [label] BSF fb Operands: O<f<127 O<b<7 Operation: 1 > (f<b>) Status Affected: None Encoding: | O1 | Olbb | bfff | ffff | Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Example BSE FLAG REG, 7 Before Instruction FLAG_REG = Ox0A After Instruction FLAG_REG = Ox8A [label] BTFSC fb 0<f<127 O0<b<7 skip if (f<b>) = 0 None | o1 | 10bp | bfff | cree | If bit 'b' in register 'f' is '0' then the next instruction is skipped. If bit 'b' is '0 then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction. 1 1(2) HERE BTFSC FLAG,1 FALSE GOTO PROCESS CODE TRUE . Before Instruction PC = After Instruction if FLAG<1> =0, PC = address TRUE if FLAG<1>=1, PC = address FALSE address HERE DS40143C-page 54 Prelhninary 1998 Microchip Technology Inc.PIC16C55X BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ /abei] BTFSS f,b Syntax: [label] CLRF f Operands: O<f<127 Operands: O<f<127 O<b</ Operation: 00h > (f) Operation: skip if (f<b>) = 1 1>Z Status Affected: None Status Affected: Z Encoding: | 01 | 11bb | bfff | ffff | Encoding: | 00 | 0001 | 1fff | ffff | Description: If bit 'b' in register 'f is '1' then the next Description: The contents of register f' are cleared instruction is skipped. and the Z bit is set. If bit 'b' is '1', then the next instruction fetched during the current instruction Words: 1 execution, is discarded and a NOP is executed instead, making this a Cycles: 1 two-cycle instruction. Example CLRF FLAG REG Words: 1 ; Before Instruction Cycles: 1(2) FLAG_REG = Ox5A Example HERE BIFSS FLAG,1 After Instruction FALSE GOTO PROCESS CODE FLAG_LREG = = 0x00 TRUE . Z = 1 Before Instruction PC = address HERE After Instruction if FLAG<1> =0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE CALL Call Subroutine CLRW Clear W Syntax: [label] CALL k Syntax: [ label] CLRW Operands: 0<k< 2047 Operands: None Operation: (PC)+ 1 TOS, Operation: 00h > (W) k > PC<10:0>, 1>Z (PCLATH<4:3>) PC<12:11> Status Affected: Z Status Affected: None Encoding: | 00 | 0001 | 0000 | 0011 | Encoding: | 10 | Okkk | kkkk | kkkk | Description: W register is cleared. Zero bit (Z) is Description: Call Subroutine. First, return address set. (PC+1) is pushed onto the stack. The . eleven bit immediate address is loaded Words: 1 into PC bits <10:0>. The upper bits of Cvcles: 1 the PC are loaded from PCLATH. ycies. CALL is a two-cycle instruction. Example CLRW Words: 1 Before Instruction Cycles: 2 W = Ox5A After Instruction Example HERE CALL THERE W = 0x00 Before Instruction Z = 1 PC = Address HERE After Instruction PC = Address THERE TOS = Address HERE+1 1998 Microchip Technology Inc. Preiininary DS40143C-page 55PIC16C55X CLRWDT Clear Watchdog Timer DECF Decrement f Syntax: [ label] CLRWDT Syntax: [ label] DECF f,d Operands: None Operands: O<f<127 Operation: 00h > WDT de [0,1] 0 WDT prescaler, Operation: (f) - 1 (dest) 1> TO Status Affected: Z 1>PD Encoding: | 00 | 0011 | afft | ffff | Status Affected: TO, PD . Description: Decrement register f. If 'd is 0 the Encoding: | 00 | 0000 | 0110 | 0100 | result is stored in the W register. If d is 1 the result is stored back in register Description: CLRWDT instruction resets the i Watchdog Timer. It also resets the __ prescaler of the WDT. Status bits TO Words: 1 and PD are set. Cycles: 1 Words: 1 Example DECF CNT, 1 Cycles: 1 . y Before Instruction Example CLRWDT CNT = 0x01 Before Instruction Z ; = 0 WDT counter = ? After Instruction After Instruction CNT = 0x00 WDT counter = 0x00 Z = 1 WDT prescaler= 0 TO = 1 PD = 1 COMF Complement f DECFSZ Decrement f, Skip if 0 Syntax: [ label] COMF fd Syntax: [label] DECFSZ fd Operands: O<f<127 Operands: O<f<127 de [0,1] de [0,1] Operation: (f) > (dest) Operation: (f)- 1 (dest); skip if result = 0 Status Affected: Z Status Affected: None Encoding: | 00 | 1001 | afff | ffff | Encoding: | 00 | 1011 | dfff | ffff | Description: The contents of register f' are Description: The contents of register f' are complemented. If 'd' is 0 the result is decremented. If d' is 0 the result is stored in W. If 'd is 1 the result is placed in the W register. If d' is 1 the stored back in register 'f. result is placed back in register f'. If the result is 0, the next instruction, Words: 1 which is already fetched, is discarded. A . NOP is executed instead making it a Cycles: 1 two-cycle instruction. Example COME REG1,0 Words: 1 Before Instruction Cycles: 1(2) REG! = Oxt3 E | HERE DECFSZ CNT, 1 After Instruction xample Coto Looe REG1 = 0x13 CONTINUE W = OxEC : Before Instruction PC = address HERE After Instruction CNT = CNT-1 ifCNT= 0, PG = address CONTINUE ifCNT# 0, PC = address HERE+1 DS40143C-page 56 Prelininary 1998 Microchip Technology Inc.PIC16C55X GOTO Unconditional Branch INCFSZ Increment f, Skip if 0 Syntax: [label] GOTO k Syntax: [label] INCFSZ fd Operands: 0<k< 2047 Operands: O<f<127 Operation: k > PC<10:0> de [0,1] PCLATH<4:3> PC<12:11> Operation: (f) + 1 (dest), skip if result = 0 Status Affected: None Status Affected: None Encoding: | 10 | 1kkk | kkkk | kkkk Encoding: | 00 | 1111 | afft | ffff Description: GOTO is an unconditional branch. The Description: The contents of register 'f' are eleven bit immediate value is loaded incremented. If 'd' is 0 the result is into PC bits <10:0>. The upper bits of placed in the W register. If 'd is 1 the PC are loaded from PCLATH<4:3>. result is placed back in register 'f'. GOTO is a two-cycle instruction. If the result is 0, the next instruction, which is already fetched, is discarded. Words: 1 NOP is executed instead making it a two-cycle instruction. Cycles: 2 Words: 1 Example GOTO THERE ; Cycles: 1(2) After Instruction E 1 = xample HERE INCFSZ CNT, PC = Address THERE p coro Loop CONTINUE Before Instruction PG = address HERE After Instruction CNT = CNT+1 if CNT= 0, PC = address CONTINUE if CNT# 0, PG = address HERE +1 INCF Increment f IORLW Inclusive OR Literal with W Syntax: [/abe/] INCF f,d Syntax: [label] IORLW k Operands: O<f<127 Operands: 0<ks255 de [0,1] Operation: (W) .OR. k > (W) Operation: (f) + 1 (dest) Status Affected: Z Status Affected: Z Encoding: | 11 | 1000 | KkKK | kkkk | Encoding: | 08 | 1010 | afrt | feet | Description: The contents of the W register is Description: The contents of register f' are ORed with the eight bit literal 'k. The incremented. If 'd' is 0 the result is result is placed in the W register. placed in the W register. If 'd is 1 the . result is placed back in register 'f'. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Example IORLW 0x35 Example INCR CNT, 1 Before Instruction W = Ox9A Before Instruction After Instruction CNT = OxFF W <= OxBF Zz = 0 Z = 1 After Instruction CNT = 0x00 Z = 1 1998 Microchip Technology Inc. Preiininary DS40143C-page 57PIC16C55X IORWF Inclusive OR W with f Syntax: [label] IORWF fd Operands: O<f<127 de [0,1] Operation: (W) .OR. (f) (dest) Status Affected: Z Encoding: | 00 | 0100 | dfft | ffff | Description: Inclusive OR the W register with register 'f'. If 'd is 0 the result is placed in the W register. If 'd is 1 the result is placed back in register f. Words: 1 Cycles: 1 Example IORWE RESULT, 0 Before Instruction RESULT = 0x13 WwW = 0x91 After Instruction RESULT = 0x13 WwW = 0x93 Z = 1 MOVLW Move Literal to W Syntax: [ /abel] MOVLW k Operands: 0<k<255 Operation: k > (W) Status Affected: None Encoding: | 11 | 00xx | kkkk | kkkk | Description: The eight bit literal 'k' is loaded into W register. The dont cares will assemble as 0's. Words: 1 Cycles: 1 Example MOVLW Ox5A After Instruction W = OxbA MOVF Move f Syntax: [label] MOVF fd Operands: O<f<127 de [0,1] Operation: (f) (dest) Status Affected: Z Encoding: | 00 | 1000 | dfft | ffff Description: The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example MOVE FSR, 0 After Instruction W = value in FSR register Z =1 MOVWF Move W to f Syntax: [label] MOVWF f Operands: O<f<127 Operation: (W) > (f) Status Affected: None Encoding: | 00 | 0000 | 1fff | ffff | Description: Move data from W register to register f. Words: 1 Cycles: 1 Example MOVWE OPTION Before Instruction OPTION = OxFF Ww = Ox4F After Instruction OPTION = Ox4F Ww = Ox4F DS40143C-page 58 Prelhninary 1998 Microchip Technology Inc.PIC16C55X NOP No Operation RETFIE Return from Interrupt Syntax: [ label] NOP Syntax: [label] RETFIE Operands: None Operands: None Operation: No operation Operation: TOS > PC, Status Affected: | None 1 GIE Encoding: | 00 | 0000 | Oxx0 | 0000 | Status Affected: None Description: No operation. Encoding: | 00 | 0000 | 0000 | 1001 | Words: 1 Description: Return from Interrupt. Stack is POPed , and Top of Stack (TOS) is loaded in Cycles: 1 the PC. Interrupts are enabled by setting Global Interrupt Enable bit, NOP Example GIE (INTCON<75). This is a two-cycle instruction. Words: 1 Cycles: 2 Example RETFIE After Interrupt PC = TOS GIE= 1 OPTION Load Option Register RETLW Return with Literal in W Syntax: [label] OPTION Syntax: [label] RETLW k Operands: None Operands: 0<ks255 Operation: (W) OPTION Operation: is (W); Status Affected: None TOS > PC Encoding: | 00 |oo00 [ore jooto Status Affected: None Description: The contents of the W register are Encoding: | 11 | Olxx | kkkk | kkkk | loaded in the OPTION register. This a The W reqister is loaded with the eigh instruction is supported for code Description: ne register is oaded with t eelg t compatibility with PIC16C5X products. bit literal 'k. The program counter is Since OPTION is a readable/writable loaded from the top of the stack (the register, the user can directly return address). This is a two-cycle ddress it instruction. Words: 1 Words: 1 Cycles: { Cycles: 2 Example Example CALL TABLE ;W contains table ;offset value To maintain upward compatibility ;W now has table with future PiCmicro products, value do not use this instruction. TABLE ADDWF PC iW = offset RETLW k1 ;Begin table RETLW k2 ; RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W =. value of k8 1998 Microchip Technology Inc. Preiininary DS40143C-page 59PIC16C55X RETURN Return from Subroutine RRF Rotate Right f through Carry Syntax: [ /abe!] RETURN Syntax: [label] RRF fd Operands: None Operands: O<f<127 Operation: TOS > PC de [0,1] Status Affected: None Operation: See description below Encoding: | 00 | 0000 | 0000 | 1000 | Status Affected: C Description: Return from subroutine. The stack is Encoding: | 00 | 1100 | afte | frre | POPed and the top of the stack (TOS) Description: The contents of register 'f' are rotated is loaded into the program counter. one bit to the right through the Carry This is a two cycle instruction. Flag. If 'd' is 0 the result is placed in Words: 1 the W register. If a is 1 the result is placed back in register f. Cycles: 2 " Example RETURN Pe ee After Interrupt Words: 1 PO = TOS Cycles: 1 Example RRE REG1, 0 Before Instruction REGi1 = 1110 0110 Cc 0 After Instruction REGi1 = 1110 0110 Ww 0111 0011 Cc 0 RLF Rotate Left f through Carry SLEEP Syntax: [/abel] RLF td Syntax: [label] SLEEP Operands: O<f<127 Operands: None de [0,1 ; [0.1] oo Operation: 00h > WDT, Operation: See description below 0 WDT prescaler. Status Affected: C 1 > TO, Encoding: | 00 | 1101 | dfff | ffff | 0 PD Description: The contents of register f' are rotated Status Affected: TO, PD one bit to the left through the Carry Encoding: | 00 | 0000 | 0110 | oo11 | Flag. If 'd is 0 the result is placed in Description: The power-down status bit, PD is the W register. If 'd' is 1 the result is stored back in register 'f cleared. Time-out status bit, TO is set. Watchdog Timer and its Register f prescaler are cleared. The processor is put into SLEEP Words: 1 mode with the oscillator stopped. See Section 7.8 for more details. Cycles: 1 Words: 1 Example RLF REG1, 0 ; Cycles: 1 Before Instruction REG1 = 1110 0110 Example: SLEEP Cc = 0 After Instruction REG1 = 1110 0110 Ww = 1100 1100 Cc = 1 DS40143C-page 60 Prelininary 1998 Microchip Technology Inc.PIC16C55X SUBLW Subtract W from Literal Syntax: [label] SUBLW k Operands: 0<k<255 Operation: k - (W) > (W) Status C, DC, Z Affected: Encoding: | 11 | a10x | kkkk | kkkk | Description: The W register is subtracted (2's com- plement method) from the eight bit literal 'k. The result is placed in the W register. Words: 1 Cycles: 1 Example 1: SUBLW 0x02 Before Instruction W = 1 C = ? After Instruction W = 1 C = 1;result is posi- tive Example 2: Before Instruction W = 2 C = ? After Instruction W = 0 C = 1; result is zero Example 3: Before Instruction W = 3 C = ? After Instruction W =) OxFF C = O;result is nega- tive SUBWF Subtract W from f Syntax: [label] SUBWF fd Operands: O<f<127 de [0,1] Operation: (f) - (W) > (est) Status C, DC, Z Affected: Encoding: | oo | oo10 | aeee | feet | Description: Subtract (2's complement method) W register from register f. If 'd is 0 the result is stored in the W register. If 'd is 1 the result is stored back in register 'f. Words: 1 Cycles: 1 Example 1: SUBWE REG1,1 Before Instruction REG1 = 383 WwW = 2 Cc = ? After Instruction REG1 = 1 WwW = 2 Cc = 1; result is positive Example 2: Before Instruction REG1 = 2 WwW = 2 Cc = ? After Instruction REG1 = 0 WwW = 2 Cc 1; result is zero Example 3: Before Instruction REG1 = 1 WwW = 2 Cc = ? After Instruction REG1 = OxFF WwW = 2 Cc = O;result is negative 1998 Microchip Technology Inc. Preiininary DS40143C-page 61PIC16C55X SWAPF Swap Nibbles in f Syntax: [label] SWAPF fd Operands: O<f<127 de [0,1] Operation: (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) Status Affected: None Encoding: | 00 | 1110 | dafff | ffff | Description: The upper and lower nibbles of register 'f are exchanged. If 'd' is 0 the result is placed in W register. If 'd is 1 the result is placed in register f. Words: 1 Cycles: 1 Example SWAPF REG, 0 Before Instruction REG1 = OxA5 After Instruction REG1 = OxA5 WwW = Ox5A TRIS Load TRIS Register Syntax: [label] TRIS. f Operands: 5<fs7 Operation: (W) > TRIS register tf: Status Affected: None Encoding: | 00 | 0000 [0110 | Of FE Description: The instruction is supported for code compatibility with the PICT6C5xX products. Since TRIS registers are readable and writable, the user can directly address them. Words: 1 Cycles: { Example To maintain upward compatibility with future PiCmicro products, do not use this instruction. XORLW Exclusive OR Literal with W Syntax: [label] XORLW k Operands: 0<k<255 Operation: (W) .XOR. k > (W) Status Affected: Z Encoding: | 11 | 1010 | kkkk | keKk | Description: The contents of the W register are XORed with the eight bit literal 'k. The result is placed in the W register. Words: 1 Cycles: 1 Example: XORLW OxAF Before Instruction W = OxBd5 After Instruction W = OxIA XORWF Exclusive OR W with f Syntax: [label] XORWF fd Operands: O<f<127 de [0,1] Operation: (W) .XOR. (f) > (dest) Status Affected: Z Encoding: | 00 | 0110 | dfff | ffff | Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd is 1 the result is stored back in register f, Words: 1 Cycles: 1 Example XORWEF REG 1 Before Instruction REG = OxAF Ww = OxB5 After Instruction REG = OxtA Ww = OxB5 DS40143C-page 62 Prelhninary 1998 Microchip Technology Inc.PIC16C55X 9.0 DEVELOPMENT SUPPORT 9.1 Development Tools The PlCmicro microcontrollers are supported with a full range of hardware and software development tools: MPLAB-ICE Real-Time In-Circuit Emulator ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE II Universal Programmer * PICSTART Plus Entry-Level Prototype Programmer * SIMICE * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLAB SIM Software Simulator * MPLAB-C17 (C Compiler) + Fuzzy Logic Development System (fuzzyTECH-MP) * KEELOQ Evaluation Kits and Programmer 9.2 MPLAB-ICE: High Performance Universal In-Circuit Emulator with MPLAB IDE The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PiCmicro microcontrollers (MCUs). MPLAB-ICE is sup- plied with the MPLAB Integrated Development Environ- ment (IDE), which allows editing, make and download, and source debugging from a single envi- ronment. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different pro- cessors. The universal architecture of the MPLAB-ICE allows expansion to support all new Microchip micro- controllers. The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows 3.x or Windows 95 environment were chosen to best make these features available to you, the end user. MPLAB-ICE is available in two _ versions. MPLAB-ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor mod- ules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed reange of the PlCmicro MCU. 9.3 ICEPIC: Low-Cost PlCmicro In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 386 through Pentium based machines under Windows 3.x, Windows 95, or Win- dows NT environment. ICEPIC features real time, non-intrusive emulation. 9.4 PRO MATE Il: Universal Programmer The PRO MATE II Universal Programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE Il is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand- alone mode the PRO MATE II can read, verify or pro- gram PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode. 9.5 PICSTART Plus Entry Level Development System The PICSTART programmer is an _ easy-to-use, low-cost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC1GCXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be sup- ported with an adapter socket. PICSTART Plus is CE compliant. 1998 Microchip Technology Inc. Preiininary DS40143C-page 63PIC16C55X 9.6 SIMICE Entry-Level Hardware Simulator SIMICE is an entry-level hardware development sys- tem designed to operate in a PC-based environment with Microchips simulator MPLAB-SIM. Both SIM- ICE and MPLAB-SIM run under Microchip Technol- ogys MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchips PIC12C5XX, PIC12CE5XxX, and PIC16C5X families of PICmicro 8-bit microcontrol- lers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus files. SIMICE is a valuable debugging tool for entry-level system development. 9.7 PICDEM-1 Low-Cost PlCmicro Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchips microcontrol- lers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PICI6C58A), PIC16C61, PIC16C62x, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44, All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PROMATE Ill or PICSTART-Plus programmer, and easily test firm- ware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the firmware to the emulator for testing. Additional proto- type area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB. 9.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II pro- grammer or PICSTART-Plus, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a Serial EEPROM to demonstrate usage of the C bus and separate headers for connec- tion to an LCD module and a keypad. 9.9 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the neces- sary hardware and software is included to run the basic demonstration programs. The user can pro- gram the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II program- mer or PICSTART Plus with an adapter socket, and easily test firmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test firm- ware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an addi- tional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A sim- ple serial interface allows the user to construct a hard- ware demultiplexer for the LCD signals. DS40143C-page 64 Prelhninary 1998 Microchip Technology Inc.PIC16C55X 9.10 MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcon- troller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * Aproject manager * Customizable tool bar and key mapping * Astatus bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PlCmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file The ability to use MPLAB with Microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 9.11 Assembler (MPASM) The MPASM Universal Macro Assembler is a PC-hosted symbolic assembler. It supports all micro- controller series including the PIC12C5XX, PIC 14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, condi- tional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from MPLAB-ICE, Microchips Universal Emulator System. MPASM has the following features to assist in develop- ing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchips emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable. 9.12 Software Simulator (MPLAB-SIM) The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/output radix can be set by the user and the exe- cution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 9.13 MPLAB-C17 Compiler The MPLAB-C17 Code Development System is a complete ANSI C compiler and integrated develop- ment environment for Microchips PIC17CXXxX family of microcontrollers. The compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler pro- vides symbol information that is compatible with the MPLAB IDE memory display. 9.14 Fuzzy Logic Development System (fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is avail- able in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for imple- menting more complex systems. Both versions include Microchips fuzzy_LAB demon- stration board for hands-on experience with fuzzy logic systems implementation. 9.15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in trade-off analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system. 1998 Microchip Technology Inc. Preiininary DS40143C-page 65PIC16C55X 9.16 KEELo@ Evaluation and Programming Tools KEELOQG evaluation and programming tools support Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS40143C-page 66 Prelininary 1998 Microchip Technology Inc.Wy 49puodsuelL 007444 Wy UOReNjeag @00133y -WAddid -WaAddid b-IN3d9Id Vvl-WAddid PIC16C55X JSOINIS iy sisuBblseg @ IWAAAS sawuwesboid @0OTS4 sawuwesboid Jesaaaiun Il ga LVIN Od Wy Aaq [essai 1S09-MO] SNidoLYVLSOld JPpoW aeMYyos w20UPINPUY [e}OL Joo, "Aeq o16o7 Azzny uolpy/saiojdxy dW-gHOsLAzznj s9Idwo5 ZbLO wV1da yuswUOsJAUy juswidojaAcg po}e169}u| wi VIdW 4oje/NwWy YNI15D-u] 1SO9-MO7 widld3adl DEVELOPMENT TOOLS FROM MICROCHIP OOOPLDld | XXSO?b3ld XXZOLLOld] XPOLLOid | XX6D9LOIid| XBD9LDid | XXZO9LOIid} X9D9LDId |XXX99b3Id TABLE 9-1: d0l-wdVIida DS40143C-page 67 spieog owaqg ssoumues6o1d nary Fralim S|00] JeEMYOS Sel eee ye | 1998 Microchip Technology Inc.PIC16C55X NOTES: DS40143C-page 68 Prelininary 1998 Microchip Technology Inc.PIC16C55X 10.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings t Ambient Temperature Under DIAS 00.0... eee eeeeeeeenneeeeeee ee eaeeeeeeaeeeaeeeeeaaeeeeeaaeeeaeeeecaaeeeseaaeeeseeaeetseeeensaeeesnas 40 to +125C Storage TOMPeCrature....... ee eececeeenseceseeeeeenneeeeenaeecseeeeeesaeeeeeaaeecsneeeeesaeeeseaaeeecneeeeesaeeeeseaeeesneeeeeeaeeeeseaeeesnaeess 65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR)........cccccccscsssscscsesesscecseseseeecseseeess 0.6V to VDD +0.6V Voltage On VDD With respect tO VSS oo. eeceeee ee eenne ee teeeeee ee eeeeeae ee ceee setae ee eeeaeee sa aeeeeeaaeeeesaaeeegneeeesiaeeesenaeeesnes 0 to +7.5V Voltage on MCLR with respect to VSS (Note 2)......cccccscscsssscscscsesscscsesesececsesesesessescsesesaeacsusececacsesesesaesesesecaeaeenss 0 to +14V Total power Dissipation (Note 1)... ceeeeeeeeeeennee cece ee ernee ee ea nee eeeeae eee geeeeeaaeeeeeaaeecaaeeeeeaaeeeeeeaeessneeeeeaeeesenaeessneeeenieeeees 1.0W Maximum Current Out Of VSS DiI... eeecce cence eee ene eeeee eee teas ener ca ae sneer eae eeaaeeneee cae egeeee ae eeeaeseeeesaeeseeesnieesaesneeeeea 300 mA Maximum Current into VDD Pith... eee sees esneeeeeneeeeeeeeeeesaeeeeeaaeeeaeeeeesaeeeenaaeeeseeeeeeseeesnaaeeesneaeeesieeesnereesneneeeeneeeegs 250 mA Input Clamp Current, IIK (Vi<O OF Vi> VDD) oo. ec ceeceteesesescnseetensescssecessenssensenssesssssssssnanecsenssensenenenscatssnssanesssneenaeesees +20 mA Output Clamp Current, lOK (VO <0 Of VO>VDD) uo. eee cetetseseecsnecensesesenscssssnssstscssnecesssnssesensessscasssnsnanesienesensenseanees +20 mA Maximum Output Current SUNK by Any I/O Pin oo. eee eenne cess ee eeseeeeeenaeeeeeeeeeesaeeeeesaeeesnneeeesaeeeeeeaeeeenneeertnaeeseeateeenaas 25 mA Maximum Output Current sourced by any I/O Dit oo... eeeeeeeeeeeseeeeeenaeeeceeeeeeeeeeeesaeeeeneeeeesaeeesesaeeesnneeeetnaeeeseateeesags 25 mA Maximum Current sunk by PORTA and PORTS. ........cecceesseeeenneeeeeeee eens eeeeaaeeeaeeeeeaaeeeenaaeeesneeeessaeeeenaeeesnaaeereneeeegs 200 mA Maximum Current sourced by PORTA and PORTB..........ccccceeesseceeeeeeeeeneeeeeaeeesneeeeeseeeeneaeeesnneeeeseeesneaeeeseeneeeeneeess 200 mA Note 1: Power dissipation is calculated as follows: Pols = VDD x {IDD - IOH} + & {(VDD-VoH) x IOH} + X(VOl x IOL) 1 NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1998 Microchip Technology Inc. Preliminary DS40143C-page 69PIC16C55X TABLE 10-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) osc PIC16C55X-04 PIC16C55X-20 PIC16LC55X-04 PICT6C5SX JW Devices RG : Wop: 3ovre Von: 4.5V to 5.5V V0: 2.5V to 5.5V Vp: 3.0V to 5.5V Ipp: 3 3 mA IDD: 1.8 mA typ. IDD: 1.4 mA typ. IDD: 3.3 mA max. , max @55V @5.5V @3.0V @5.5V Ipp:20 A max IPD: 1.0 WA typ. IPD: 0.7 pA typ. IPD: 20 wA max. @ OV @45V @3.0V @4.0v Freq: 40 MHz Freq: 4.0 MHz Freq: 4.0 MHz Freq: 4.0 MHz max. max. max. max. XT . Von: 3.ov'e Vbb: 4.5V to 5.5V V0: 2.5V to 5.5V Vp: 3.0V to 5.5V Ipp:3 3 mA IDD: 1.8 mA typ. IDD: 1.4 mA typ. IDD: 3.3 mA max. . max @5.5V @5.5V @3.0V @5.5V Ipp:20 A max IPD: 1.0 WA typ. IPD: 0.7 pA typ. IPD: 20 pA max. @ OV @45V @3.0V @4.0V Freq: 4.0 MHz Freq: 4.0 MHz Freq: 4.0 MHz Freq: 4.0 MHz max. max. max. max. HS | Von: 4 5V to Vp: 4.5V to Vp: 4.5V to 5.5V. 5.5V 5.5V [bD: 9.0 mA typ. IDD: 20 mA IDD: 20 mA @B5V max. @5.5V . max.@5.5V IPD: 1.0 pA typ. IPD: 1.0 pA typ. Po pet use in Ip: 1.0 pA typ. @40V @4.5V @4.5V Freq: 4.0 MHz Freq: 20 MHz Freq: 20 MHz max. max. max. LP VoD: 3.0V to Vpp: 2.5V to Von: 2.5V to 5.5V 5.5V 5.5V IDD: 35 WA typ. IDD: 32 WA max. IDD: 32 WA max. @82 KHz, @32 kHz, @32 kHz, Bey Do not use in LP mode 3.0V 3.0V Pp: 1.0 WA typ. IPD: 9.0 pA IPD: 9.0 pA @40V max. @3.0V max. @3.0V Freq: 200 kHz Freq: 200 kHz Freq: 200 kHz maxi. max. max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. DS40143C-page 70 Preliminary 1998 Microchip Technology Inc.PIC16C55X 3: 4: 5: 10.1 DC CHARACTERISTICS: PIC16C55X-04 (Commercial, Industrial, Extended) PIC16C55X-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C <TA<+85C for industrial and O =< TA<+70C for commercial and 40C <TAS<+125C for extended Param Sym Characteristic Min | Typt | Max} Units Conditions No. DOO1 |VDD Supply Voltage 3.0 - 5.5 V_ |XT, RC and LP osc configuration DOO1A 4.5 - 5.5 V__| HS osc configuration DO02 =| VDR RAM Data Retention - 1.5% | - V_ | Device in SLEEP mode Voltage (Note 1) D003 =| VPOR VDD start voltage to - Vss | - V_ | See section on power-on reset for ensure Power-on Reset details DO04 | Svpp VDD rise rate to ensure 0.05*| - | V/ms | See section on power-on reset for Power-on Reset details DO10 | IDD Supply Current (Note 2) - 1.8 | 3.3] mA | XT and RC osc configuration Fosc = 4 MHz, VpbD = 5.5V, WDT disabled (Note 4) DO10A - 35 | 70 | wA |LP oscconfiguration, PIC 16C55X-04 only Fosc = 32 kHz, VDD = 4.0V, WDT disabled D013 - 9.0 | 20 | mA |HS osc configuration Fosc = 20 MHz, VbD = 5.5V, WDT disabled D020 =| IPD Power Down Current (Note 3) - 1.0 | 25] yA | VDD=4.0V, WDT disabled 15 | pA | (+85C to +125C) AIWDT WDT Current (Note 5) - 6.0 | 20 |} vA | VDD=4.0V (+85C to +125C) * These parameters are characterized but not tested. T Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to Vpp, MCLR = VDD; WDT enabled/disabled as specified. The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or Vss. For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kQ. The A current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 1998 Microchip Technology Inc. Preliminary DS40143C-page 71PIC16C55X 10.2 DC CHARACTERISTICS: PIC16LC55X-04 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C <TA<+85C for industrial and OC <TA<+70C for commercial and -40C <TA<+125C for extended Param Sym Characteristic Min | Typt | Max} Units Conditions No. DOO1 |VDD Supply Voltage 3.0 - 5.5 V_ | XT and RC osc configuration 2.5 5.5 LP ose configuration DO02 =| VDR RAM Data Retention - 1.5% | - V_ | Device in SLEEP mode Voltage (Note 1) D003 =| VPOR VDD start voltage to - Vss | - V_ | See section on Power-on Reset for ensure Power-on Reset details DO04 | Svpp VDD rise rate to ensure 0.05*| - | V/ms | See section on Power-on Reset for Power-on Reset details DO10 | IDD Supply Current (Note 2) - 1.4 | 2.5 | mA | XT and RC osc configuration Fosc = 2.0 MHz, VDD = 3.0V, WDT disabled (Note 4) DO10A - 26 | 53 | wA |LP ose configuration Fosc = 32 kHz, VDD = 3.0V, WDT disabled D020 =| IPD Power Down Current (Note 3) - 0.7 2 HA | VDD=3.0V, WDT disabled AIWDT WDT Current (Note 5) - 6.0 | 15 | wA | VDD=3.0V * These parameters are characterized but not tested. T Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all |IDD measurements in active operation mode are: OSC1=external square wave, from rail to rail; all /O pins configured as input, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power down current in SLEEP mode does not depend on the oscillator tyoe. Power down current is measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or Vss. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VpD/2Rext (mA) with Rext in kQ. 5: The Acurrent is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. DS40143C-page 72 Preliminary 1998 Microchip Technology Inc.PIC16C55X 10.3 DC CHARACTERISTICS: PIC16C55X (Commercial, Industrial, Extended) PIC16LC55X (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C <TA<+85C for industrial and OC <TA<+70C for commercial and -40C <TA<+125C for automotive Operating voltage VDD range as described in DC spec Table 10-1 Param, Sym Characteristic Min |Typt) Max {Unit Conditions No. VIL |Input Low Voltage I/O ports D030 with TTL buffer Vss - 0.8V V |VDD = 4.5V to 5.5V 0.15VDD otherwise D031 with Schmitt Trigger inout} Vss 0.2VDD | V D032 MCLR, RA4/TOCKI,OSC1 (in| Vss - 0.2VDD | V |Notet RC mode) D033 OSC1 (in XT* and HS) Vss - 0.3VDD | V OSC1 (in LP*) Vss - |0.6VDD-1.0) V ViH_ |Input High Voltage I/O ports - DO40 with TTL buffer 2.0V - VDD V |VDD = 4.5V to 5.5V D041 with Schmitt Trigger input |}0.25VDD VDD otherwise + 0.8V DO42 MCLR RA4/TOCKI O.8VDD] - VDD Vv D043 OSC1 (XT*, HS and LP) 0.7VDD}_ - VDD Vv DO043A OSC1 (in RC mode) 0.9VDD Note1 DO70 | IPURB|}PORTB weak pull-up current 50 200 400 HA | VDD = 5.0V, VPIN = VSS Input Leakage Current lit | (Notes 2, 3) I/O ports (Except PORTA) +1.0 HA |VSS < VPIN < VDD, pin at hi-impedance DO60 PORTA - - +0.5 HA |Vss < VPIN < VDD, pin at hi-impedance DO61 RA4/TOCKI - - +1.0 HA |Vss < VPIN < VDD DO63 OSC1, MCLR - - +5.0 HA |Vss < VPIN < VDD, XT, HS and LP ose configuration VoL |Output Low Voltage DO80 I/O ports - - 0.6 V |IlOL=8.5 mA, VDD=4.5V, -40 to +85C - - 0.6 V |IOL=7.0 mA, VoD=4.5V, +125C D083 OSC2/CLKOUT - - 0.6 V |IOL=1.6 mA, VDD=4.5V, -40 to +85C (RC only) - - 0.6 V |loL=1.2 mA, VoD=4.5V, +125C VOH | Output High Voltage (Note 3) DO90 I/O ports (Except RA4) VbbD-0.7] - - V |IOH=-3.0 mA, VDD=4.5V, -40 to +85C VDD-0.7|_ - - V |IOH=-2.5 mA, Vpb=4.5V, +125C Dog92 OSC2/CLKOUT VbbD-0.7] - - V |IOH=-1.3 mA, VDD=4.5V, -40 to +85C VDD-0.7|_ - - V |IOH=-1.0 mA, (RC only) Vopp=4.5V, +125C * Vop |Open-Drain High Voltage 10* V |RA4 pin * These parameters are characterized but not tested. T Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. 1998 Microchip Technology Inc. Preliminary DS40143C-page 73PIC16C55X 10.3 DC CHARACTERISTICS: PIC16C55X (Commercial, Industrial, Extended) PIC16LC55X (Commercial, Industrial, Extended) (Cont.) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C <TA<+85C for industrial and OC <TA<+70C for commercial and -40C <TA<+125C for automotive Operating voltage VDD range as described in DC spec Table 10-1 Param Sym Characteristic Min |Typt) Max {Unit Conditions No. Capacitive Loading Specs on Output Pins D100 |Cosc2]OSC2 pin 15 pF |In XT, HS and LP modes when external clock used to drive OSC1. D101 Cio |All I/O pins/OSC2 (in RC 50 pF mode) * These parameters are characterized but not tested. T Data in Typ column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. DS40143C-page 74 Preliminary 1998 Microchip Technology Inc.PIC16C55X 10.4 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. Tpps T F Frequency T Time Lowercase subscripts (pp) and their meanings: Pp ck CLKOUT os Osc io I/O port tO TOCKI mec MCLR Uppercase letters and their meanings: Ss F Fall P Period H High R Rise | Invalid (Hi-impedance) Vv Valid L Low Z Hi-lmpedance FIGURE 10-1: LOAD CONDITIONS Load condition 1 Load condition 2 Vop/2 RL Pin = ot Pin TT CL Vss Vss RL = 4640 CL = 50pF forall pins except OSC2 15pF for OSC2 output 1998 Microchip Technology Inc. Preliminary DS40143C-page 75PIC16C55X 10.5 Timing Diagrams and Specifications FIGURE 10-2: EXTERNAL CLOCK TIMING Osc Q4 Q1 Q2 Q1 akouT NY TABLE 10-2: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter} Sym | Characteristic Min Typt Max Units | Conditions No. Fos | External CLKIN Frequency DC _ 4 MHz | XT and RC osc mode, VoD=5.0V (Note 1) DC 20 MHz | HS osc mode DC _ 200 kHz | LP osc mode Oscillator Frequency DC _ 4 MHz | RC osc mode, VDD=5.0V (Note 1) 0.1 4 MHz | XT osc mode 1 _ 20 MHz | HS osc mode DC - 200 kHz | LP osc mode 1 Tosc | External CLKIN Period 250 _ _ ns_ | XT and RC osc mode (Note 1) 50 ns_ | HS osc mode 5 _ _ us |LP osc mode Oscillator Period 250 _ _ ns_ | RC osc mode (Note 1) 250 10,000 | ns_ | XT osc mode 50 1,000 ns_ |HS osc mode 5 _ _ us |LP osc mode 2 Tcy | Instruction Cycle Time (Note 1) 1.0 Fos/4 DC us | TCY=Fos/4 3* TosL, | External Clock in (OSC1) High or 100* _ _ ns_ | XT osc mode TosH | Low Time 9 us |LP osc mode 20* _ _ ns_ | HS osc mode 4* TosR, | External Clock in (OSC1) Rise or 25* _ _ ns_ | XT osc mode TosF | Fall Time 50* _ _ ns_ | LP osc mode 15* _ _ ns_ | HS osc mode * These parameters are characterized but not tested. T Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. DS40143C-page 76 Preliminary 1998 Microchip Technology Inc.PIC16C55X FIGURE 10-3: CLKOUT AND I/O TIMING Q4 1 Qt \ Q2 \ Q3 : Osct CLKOUT \ Be! ae : 1 = 1 I I 1 1 9. 1 | 1 6 1 /O Pin Yj (input) L/ S17 ae 1 =! ! /O Pin ' HVA ' ' ' (output) old value ; new value, ete 20, 21 Note: All tests must be do with specified capacitance loads (Figure 10-1) 50 pF on I/O pins and CLKOUT TABLE 10-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter # |Sym Characteristic Min Typt Max Units 10* TosH2ckL OSC1T to CLKOUTJ (Note1) _ 75 200 ns _ _ 400 ns 11 TosH2ckH OSC1T to CLKOUTT (Note1) _ 7 200 ns _ _ 400 ns 12 TekR CLKOUT rise time (Note1) _ 35 100 ns _ _ 200 ns 13 TekF CLKOUT fall time (Note1) _ 35 100 ns _ _ 200 ns 14* TckL2ioV CLKOUT J to Port out valid (Note1) _ _ 20 ns 15 TioV2ckH Port in valid before CLKOUT T (Note1) Tose +200ns | _ ns Tosc +400 ns _ _ ns 16* TekH2iol Port in hold after CLKOUT T (Note1) 0 _ _ ns 17* TosH2ioV OSC1T (Q1 cycle) to Port out valid _ 50 150 ns _ 300 ns 18* TosH2iol OSC1T (Q2 cycle) to Port input invalid (I/O in hold 100 _ _ ns time) 200 _ _ ns 19* TioV2osH Port input valid to OSC1T (I/O in setup time) 0 _ _ ns 20 TioR Port output rise time _ 10 40 ns _ _ 80 ns 21* TioF Port output fall time _ 10 40 ns _ _ 80 ns 22* Tinp RBO/INT pin high or low time 25 _ _ ns 40 _ _ ns 23 Trbp RB<7:4> change interrupt high or low time Tey _ _ ns These parameters are characterized but not tested + Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x Tosc 1998 Microchip Technology Inc. Preliminary DS40143C-page 77PIC16C55X FIGURE 10-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING : >? VbD ff ; td ' >? MCLR ff \; / I + 30> Internal 1 POR ' 7 ) u 33 _ 1 PWRT ? Timeout ' 32 , ; ; Ost ae Timeout Internal ' y RESET 1 Watchdog ' ' Timer ' ' : RESET 1 ' 1 I 7 . TABLE 10-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter Sym_ | Characteristic Min Typt Max | Units Conditions No. 30 TmcL |MCLR Pulse Width (low) 2000 _ _ ns_ | -40 to +85C 31 Twdt | Watchdog Timer Time-out Period T* 18 33* ms | VDD =5.0V, -40 to +85C (No Prescaler) 32 Tost | Oscillation Start-up Timer Period _ 1024 Tosc _ |Tosc = OSC1 period 33 Tpwrt | Power-up Timer Period 28" 72 132* ms | VDD =5.0V, -40 to +85C 34 Tioz | 1/O hi-impedance from MCLR low _ 2.0 us * These parameters are characterized but not tested. T Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40143C-page 78 Preliminary 1998 Microchip Technology Inc.PIC16C55X FIGURE 10-5: TIMERO CLOCK TIMING I I l RA4/T0C Sy en ee | | I TMRO XI | | | I TABLE 10-5: TIMERO CLOCK REQUIREMENTS Parameter | Sym | Characteristic Min Typt| Max] Units | Conditions No. 40 TtOH | TOCKI High Pulse Width No Prescaler 0.5 Tcy+20*}| _ ns With Prescaler 10* _ _ ns 41 TtOL | TOCKI Low Pulse Width No Prescaler 0.5 Tcy+20*}| _ ns With Prescaler 10* _ _ ns 42 TtOP | TOCKI Period Icy + 40* _ _ ns_ | N =prescale value N (1, 2, 4, ..., 256) These parameters are characterized but not tested. T Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 10-6: LOAD CONDITIONS Load condition 1 Load condition 2 Vop/2 RL Pin = Ol Pin > CL Vss Vss RL = 46402 CL = 50pF forall pins except OSC2 15pF for OSC2 output 1998 Microchip Technology Inc. Preliminary DS40143C-page 79PIC16C55X NOTES: DS40143C-page 80 Preliminary 1998 Microchip Technology Inc.PIC16C55X 11.0 PACKAGING INFORMATION 11.1 Package Marking Information 18-Lead PDIP Example XXKXXKXKXKXKXKXKXKXAXKKKKK PIC16C558 DO XXKXXKXKXKXKXKXKXKXAXKKKKK DO -041 / P456 AS AABBCDE AS 9823 CBA 18-Lead SOIC (.300") Example XXXKXXXXKXKXKKK PIC16C558 XXXKXXXXKXKXKKK -041 / S0218 XXXXXXXKXKXKKK O x AABBCDE O K 9818 CDK 18-Lead CERDIP Windowed Example . XXXXXKXKXK . 16C558 D XXXXXXXX D SS /JW AABBCDE 9801 CBA 20-Lead SSOP Example XXXXKXXXXKXKX PIC16C558 XXXXKXXXXKXKX -041/ 218 OS AABBCDE oS9851 CBP Legend: MM...M = Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week 01) Cc Facility code of the plant at which wafer is manufactured O = Outside Vendor C =5" Line S$ = 6 Line H = 8 Line D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: Inthe event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. 1998 Microchip Technology Inc. Preliminary DS40143C-page 81PIC16C55X Package Type: K04-010 18-Lead Ceramic Dual In-line with Window (JW) 300 mil a | Oo a Laan = so De a oh aes WI ~ai Eo. ' | Al fa Ny it. a _t B Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.300 7.62 Number of Pins n 18 18 Pitch p 0.098 0.100 0.102 2.49 2.54 2.59 Lower Lead Width B 0.016 0.019 0.021 0.44 0.47 0.53 Upper Lead Width Bi 0.050 0.055 0.060 1.27 1.40 1.52 Shoulder Radius R 0.010 0.013 0.015 0.25 0.32 0.38 Lead Thickness c 0.008 0.010 0.012 0.20 0.25 0.30 Top to Seating Plane A 0.175 0.183 0.190 4.45 4.64 4.83 Top of Lead to Seating Plane Al 0.091 0.111 0.131 2.31 2.82 3.33 Base to Seating Plane A2 0.015 0.023 0.030 0.00 0.57 0.76 Tip to Seating Plane L 0.125 0.138 0.150 3.18 3.49 3.81 Package Length D 0.880 0.900 0.920 22.35 22.86 23.37 Package Width E 0.285 0.298 0.310 7.24 7.56 7.87 Radius to Radius Width E1 0.255 0.270 0.285 6.48 6.86 7.24 Overall Row Spacing eB 0.345 0.385 0.425 8.76 9.78 10.80 Window Width W1 0.130 0.140 0.150 0.13 0.14 0.15 Window Length Ww2 0.190 0.200 0.210 0.19 0.2 0.21 * Controlling Parameter. JEDEC equivalent: MO-036 AE DS40143C-page 82 Prelininary 1998 Microchip Technology Inc.PIC16C55X Package Type: K04-007 18-Lead Plastic Dual In-line (P) 300 mil oI EF A a [pO a [rp 2 no Ollp1 y oj jr E{ tmm| oI A | L A R c L A2 B1 p a B p eB Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.300 7.62 Number of Pins n 18 18 Pitch p 0.100 2.54 Lower Lead Width B 0.013 0.018 0.023 0.33 0.46 0.58 Upper Lead Width Bit 0.055 0.060 0.065 1.40 1.52 1.65 Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.005 0.010 0.015 0.13 0.25 0.38 Top to Seating Plane A 0.110 0.155 0.155 2.79 3.94 3.94 Top of Lead to Seating Plane Al 0.075 0.095 0.115 1.91 2.41 2.92 Base to Seating Plane A2 0.000 0.020 0.020 0.00 0.51 0.51 Tip to Seating Plane L 0.125 0.130 0.135 3.18 3.30 3.43 Package Length Dt 0.890 0.895 0.900 22.61 22.73 22.86 Molded Package Width EF 0.245 0.255 0.265 6.22 6.48 6.73 Radius to Radius Width E1 0.230 0.250 0.270 5.84 6.35 6.86 Overall Row Spacing eB 0.310 0.349 0.387 7.87 8.85 9.83 Mold Draft Angle Top a 5 10 15 5 10 15 Mold Draft Angle Bottom B 5 10 15 5 10 15 * Controlling Parameter. T Dimension B1 does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension B1. + Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E. JEDEC equivalent: MS-001 AC 1998 Microchip Technology Inc. Preliminary DS40143C-page 83PIC16C55X Package Type: K04-051 18-Lead Plastic Small Outline (SO) Wide, 300 mil E1-_+ | p= tu = co | co | mo co [ D ! co | co | i [1 2 B n Co O xX 7 45 _ iN 2 | 1S, Fj {HESS . mB L1 A2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Pitch p 0.050 1.27 Number of Pins n 18 18 Overall Pack. Height A 0.093 0.099 0.104 2.36 2.50 2.64 Shoulder Height Al 0.048 0.058 0.068 1.22 1.47 1.73 Standoff A2 0.004 0.008 0.011 0.10 0.19 0.28 Molded Package Length Dt 0.450 0.456 0.462 11.43 11.58 11.73 Molded Package Width Et 0.292 0.296 0.299 7.42 7.51 7.59 Outside Dimension E1 0.394 0.407 0.419 10.01 10.33 10.64 Chamfer Distance xX 0.010 0.020 0.029 0.25 0.50 0.74 Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25 Gull Wing Radius R2 0.005 0.005 0.010 0.13 0.13 0.25 Foot Length L 0.011 0.016 0.021 0.28 0.41 0.53 Foot Angle o 0 4 8 0 4 8 Radius Centerline L1 0.010 0.015 0.020 0.25 0.38 0.51 Lead Thickness c 0.009 0.011 0.012 0.23 0.27 0.30 Lower Lead Width Br 0.014 0.017 0.019 0.36 0.42 0.48 Mold Draft Angle Top a 0 12 15 0 12 15 Mold Draft Angle Bottom B 0 12 15 0 12 15 . Controlling Parameter. T Dimension B does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension B. + Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E. JEDEC equivalent: MS-013 AB DS40143C-page 84 Prelininary 1998 Microchip Technology Inc.PIC16C55X Package Type: K04-072 20-Lead Plastic Shrink Small Outine (SS) 5.30 mm E1_+ pe | Ta 2 atte cee | A2 Btn Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Pitch p 0.026 0.65 Number of Pins n 20 20 Overall Pack. Height A 0.068 0.073 0.078 1.73 1.86 1.99 Shoulder Height Al 0.026 0.036 0.046 0.66 0.91 1.17 Standoff A2 0.002 0.005 0.008 0.05 0.13 0.21 Molded Package Length Dt 0.278 0.283 0.289 7.07 7.20 7.33 Molded Package Width Et 0.205 0.208 0.212 5.20 5.29 5.38 Outside Dimension E1 0.301 0.306 0.311 7.65 7.78 7.90 Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25 Gull Wing Radius R2 0.005 0.005 0.010 0.13 0.13 0.25 Foot Length L 0.015 0.020 0.025 0.38 0.51 0.64 Foot Angle o 0 4 8 0 4 8 Radius Centerline L1 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.005 0.007 0.009 0.13 0.18 0.22 Lower Lead Width Bt 0.010 0.012 0.015 0.25 0.32 0.38 Mold Draft Angle Top a 0 5 10 0 5 10 Mold Draft Angle Bottom B 0 5 10 0 5 10 . Controlling Parameter. T Dimension B does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension B. + Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E. JEDEC equivalent: MO-150 AE 1998 Microchip Technology Inc. Preliminary DS40143C-page 85PIC16C55X NOTES: DS40143C-page 86 Prelininary 1998 Microchip Technology Inc.PIC16C55X APPENDIX A: ENHANCEMENTS The following are the list of enhancements over the PIC16C5X microcontroller family: 1. 10. 11. 12. 13. 14. 15. 16. 17. 18. Instruction word length is increased to 14 bits. This allows larger page sizes both in program memory (4K now as opposed to 512 before) and register file (up to 128 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. PA2, PA1, PAO bits are removed from STATUS register. Data memory paging is slightly redefined. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and opTIoN are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revised. Three different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change feature. TimerO clock input, TOCKI pin is also a port pin (RA4/TOCKI) and has a TRIS bit. FSR is made a full 8-bit register. In-circuit programming is made possible. The user can program PIC16C55X devices using only five pins: VDD, Vss, VPP, RB6 (clock) and RB7 (data in/out). PCON status register is added with a Power-on-Reset (POR) status bit. Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. PORTA inputs are now Schmitt Trigger inputs. APPENDIX B: COMPATIBILITY To convert code written for PIC16C5X to PIC16C55xX, the user should take the following steps: 1. Remove any program memory page select operations (PA2, PA1, PAO bits) for cALL, corto. 2. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. 3. Eliminate any data memory page switching. Redefine data variables to reallocate them. 4. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. 5. Change reset vector to 0000h. 1998 Microchip Technology Inc. Preliminary DS40143C-page 87PIC16C55X NOTES: DS40143C-page 88 Prelininary 1998 Microchip Technology Inc.PIC16C55X INDEX A ADDLW Instruction .0........ ccc ccccccccncneeceeeceeseneaeeeeeeeenneaaea ADDWEF Instruction ........... ccc ccccccccccssteeseeececseneseeeeeeeeneeaaes ANDLW Instruction .0.0........cccccccccccccseneseeeceeneneaeeeeeeeenneaeea ANDWEF Instruction ....... Architectural Overview .. Assembler MPASM Assembler ...............ccccccccccccceceseseeeceeeessteeenees BCF Instruction ...........ccccccccccccccseseeeceeseescnseseeseeescsssteeeeeseeses Block Diagram TIMERO...........cccccceeeeeeteee TMRO/AWDT PRESCALER BSF IMStruction 0.0.0... ..cccccccccccccccseeeeceeceescnseaeeeeeeecsssteeeeeeeeses BTFSC INStruction............cccccccccseseecceecencseseeeeeesesssteeeteseees BTFSS INStruction 0.00.0... cccccccccesececceseencsseseeeeeesesssteeeeeeeees Cc CALL Instruction .............c cece Clocking Scheme/Instruction Cycle . CLF INStruction .........ccccccccccccccccscnseeeeeceescneseeseeseesstatanees CLRW Instruction ....... cc ccccccccccssnseeceececscsseseeeeeseesseteaness CLRWDT Instruction. Code Protection ........ COMP Instruction ............cccccccccccccccssnseeeeececseseseeeeeseesssaeanees Configuration BitS............cceccecceecececeeeeecereeieeteeseeenresiteneeats 36 D Data Memory Organization .....0.... ec ceeeeeerreneeenteeeees 13 DECE Instruction ...........ccccccccccssscecceeceseneseeeeeecsssteeeteeeeses 56 DECFSZ INStruction .......0 ccc cccccccecceccencnseseeeceenensseeeeeeeees 56 Development Support 0.0... eee eect eeeesesstetsneetnteceaes 63 F Fuzzy Logic Dev. System (fuzzyTECH-MP) ...........e 65 G General purpose Register File oo... eee ee eee 13 GOTO Instruction VO POmts ooo. cece cece reece einer enreceeeesneesineessneetntetiteeeees 23 /O Programming Considerations... eects 2/7 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 63 ID LOCAtIONS 00... eee cree ete ee tne eretetteetneetteeees INCF Instruction........ INCFSZ Instruction In-Circuit Serial Programming ...........0:cecee eee eeteeeee 50 Indirect Addressing, INDF and FSR Registers .................. 21 Instruction Flow/Pipelining ........0. ccc eee eee eee eet tees 12 Instruction Set Instruction Set SUMMATY ........ cee eeeeeeeeeeeeeneetnteeeees INT Interrupt .0...0 eee cece ce seesneenneenntesseeeneesnreenees 46 INTCON Register Interrupts ............ IORLW Instruction . . IORWE Instruction oo... ec cece ceeccnennennreceseeeneeenteenees 58 K KeeLoq Evaluation and Programming Tools ................. 66 M MOVE Instruction ............ccccccceececeeeeeeeeeeceeceeeceeeseeeeeeetieeeeee 58 MOVLW Instruction ............0:ccccecceeeeceeeceeceteceeeeeeceeeetsneteete 58 MOVWE Instruction .....0....ccccccecceeeeeceeeeeeeeteceeeeteeereetenereeee 58 MPLAB Integrated Development Environment Software.... 65 N NOP Instruction... cece cce ee eeeneesneetnteseeessneeneeeees 59 oO One-Time-Programmable (OTP) Devices ..............cee 7 OPTION Instruction oo... eee eee cee en eeeeeeneentetneeee 59 OPTION Register ............... Oscillator Configurations .... . Oscillator Start-up Timer (OST)... eee eee eeeeees 40 P Package Marking Information ..........0...::ceccecceeeeeeereeterenees Packaging Information .............:ccceeceeeeceeeecesteeseenteeneenteees PCL and PCLATH ........... PCON Register....... PICDEM-1 Low-Cost PICmicro Demo Board ... . PICDEM-2 Low-Cost PIC16CXX Demo Board.................. PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ PICSTART Plus Entry Level Development System . Pinout DeSCription ........ cee cee eeeeeeenneesnteceeerneeentenees Port RB Interrupt.......... eee ce eeeeeenetneesnteceeeeneenntenees PORTA ....eeeceecceeccecceeecesecereceecareceesnreaesnrtseesesaneesesnneeieenteeas Power Control/Status Register (PCON) .... . Power-Down Mode (SLEEP)............0.:::ccccsecesceteceeeeeeseeeees Power-On Reset (POR) .........cceccesscsceeeeeeneceeeeeneeenntenees Power-up Timer (PWRT) ..........::c:cccecececeesceeeceeetecneeetenenees 1998 Microchip Technology Inc. Preliminary DS40143C-page 89PIC16C55X PrOSC@IOD oe. eee cee ee ee reece entree seni rnetineseirenntesiteeeea 32 PRO MATE II Universal Programmet...............0::eeeee 63 Program Memory Organization ............. eee eneeneeees 13 Q Quick-Turnaround-Production (QTP) Devices ...............00 7 R RC Oscillator... ee cece reece enneeeetneerieeeed 38 RESO... eee cece ee eeei rene site senirietnnesenenneesirieeea 39 RETFIE Instruction... ccc ee ceeenneeneeeieeieeenteeeea 59 RETLW Instruction...... .. 59 RETURN Instruction... .... 60 RLF Instruction......... .... 60 RRP Instruction ooo... eee ene eeecesernetnneeeirerneeentieeea 60 Ss SEEVAL Evaluation and Programming System............... 65 Serialized Quick-Turnaround-Production (SQTP) Devices... 7 SLEEP Instruction .....0 eee eeeeeeeene eter eeeseeenneeenteseaes 60 Software Simulator (MPLAB-SIM).. . 65 Special Features of the CPU... ec ecceeceeseeeeereenreeteenes 35 Special Function Registers ........... cece ceeeeeneeeeneeeees 15 Status Register... ee cee eeeeeeeeeeneeeneeeeeeetneetnteseees 16 SUBLW Instruction... eee eee eeeeteeseeeentetnteeeaes 61 SUBWF Instruction... ee cece cere center teense tneetnteseees 61 SWAPF Instruction... eee cece ceee cent eeneeeeeeeetneeenteseees 62 T TimerO TIMERO 0.0... eececeecceeeeeeeereeeeereeaeceeeeneeeeesareseeenneeieeteas 29 TIMERO (TMRO) Interrupt... 1 29 TIMERO (TMRO) Module ...........0c:eececerseeterreeteeeeees 29 TMRO with External Clock... eeeeeeeeeeeeeees 31 Timer Switching Prescaler Assignment............00: eee 33 Timing Diagrams and Specifications ........0...0.:cecceeeeee 76 TMRO Interrupt... eee cece eee cereetenetenteeeeeetneeenteeees 46 TRIS INStruction oo... ee eee eee ceree rene ennteeeneerneeenteeees 62 Watchdog Timer (WDT) ....... ce cece cnet teetetnnetnteeeees 47 WWW, On-Line Support... eee eeeeeneeenteees 3 X XORLW Instruction 0.0.0... cccccesecssseeseeeceesesteaeeeeeeeeses 62 XORWE Instruction... ccc cccccesesssneeseeeceeseseaeeeeeeeeses 62 DS40143C-page 90 Preliminary 1998 Microchip Technology Inc.PIC16C55X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip InternetWeb Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: fip://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world. 981103 Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FlexROM, MPLAB and fuzzy- LAB are trademarks and SQTP is a service mark of Micro- chip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies. 1998 Microchip Technology Inc. DS40143C-page 91PIC16C55X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: ( ) - FAX: ( ) - Application (optional): Would you like a reply? Y N Device: PIC16C55X Literature Number: DS40143C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS40143C-page 92 1998 Microchip Technology Inc.p IC16C55X PIC16C55X Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. PART NO. -XX X /XX XXX Frequency 04 200kHz (LP osc) Range: 04 = 4 MHz (XT and RC osc) 20 = 20 MHz (HS osc) Device: PIC16C55X :VbD range 3.0V to 5.5V PIC16LC55X:VDD range 2.5V to 5.5V Ly Pattern: 3-Digit Pattern Code for QTP (blank otherwise) Package: P = PDIP SO = SOIC (Gull Wing, 300 mil body) SS = SSOP (209 mil) JW* = Windowed CERDIP Examples: ) Temperature - = 0Cto+70C Range: I = 40C to +85C E = 40C to +125C PIC16C55XT:VDD range 3.0V to 5.5V (Tape and Reel) PIC16LC55XT:VDD range 2.5V to 5.5V (Tape and Reel) PIC16C554 - 04/P 301 = Commercial temp., PDIP pack- age, 4 MHz, normal VDD limits, QTP pattern #301. PIC16LC558- 041/SO = Industrial temp., SOIC pack- age, 200kHz, extended VpD limits. * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one 1. Your local Microchip sales office (see below) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. of the following: 1998 Microchip Technology Inc. Preliminary DS40143C-page 93PIC16C55X NOTES: DS40143C-page 94 Preliminary 1998 Microchip Technology Inc.PIC16C55X NOTES: 1998 Microchip Technology Inc. Preliminary DS40143C-page 95MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http:/Avww.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Dayton Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 9/29/98 Microchip received ISO 9001 Quality DNV Cortincation, Inc. Th acy ds System certification for its worldwide ED Accredited by the RvA headquarters, design, and wafer o* > fabrication facilities in January, 1997. e % Our field-programmable PiCmicro < . 8-bit MCUs, KEELOG code hopping 3 fe DiI W devices, Serial EEPROMs, related @ ANSI-RAB , specialty memory products and e ist ISO 9001 development systems conform to the REGISTERED FIRM stringent quality standards of the International Standard Organization (ISO). All rights reserved. 1999 Microchip Technology Incorporated. Printed in the USA. 1/99 > Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assum ed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS40143C-page 96 1998 Microchip Technology Inc.