SN54/74LS375 4-BIT D LATCH The SN54 / 74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input /output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follow the input. When E goes LOW, the information present at the D input prior to its setup time will be retained at the Q outputs. 4-BIT D LATCH LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC D3 Q3 Q3 E2,3 Q2 Q2 D2 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 2 3 4 5 6 7 8 D0 Q0 Q0 E0,1 Q1 Q1 D1 GND J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 TRUTH TABLE (Each latch) tn tn+1 D H L Q H L 1 NOTES: tn = bit time before enable g g g transition. negative-going tn+1 = bit time after enable negative-going transition. PIN NAMES 16 1 LOADING (Note a) Data Inputs Enable Input Latches 0, 1 Enable Input Latches 2, 3 Latch Outputs (Note b) Complimentary Latch Outputs (Note b) ORDERING INFORMATION LOW HIGH D1 - D4 E0 - 1 E2 - 3 Q1 - Q4 Q1 - Q4 D SUFFIX SOIC CASE 751B-03 0.5 U.L. 2.0 U.L. 2.0 U.L. 10 U.L. 10 U.L. SN54LSXXXJ SN74LSXXXN SN74LSXXXD 0.25 U.L. 1.0 U.L. 1.0 U.L. 5 (2.5) U.L. 5 (2.5) U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. DATA LOGIC SYMBOL 1 7 9 15 D0 D1 D2 D3 4 E0,1 12 Q E2,3 Q0 Q 2 LOGIC DIAGRAM ENABLE TO OTHER LATCH Ceramic Plastic SOIC Q1 3 6 5 Q2 Q3 10 11 14 13 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-1 SN54/74LS375 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits S b l Symbol Min P Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Typ Max U i Unit 2.0 54 0.7 74 0.8 - 0.65 - 1.5 T Test C Conditions di i V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input p LOW Voltage g for All Inputs V VCC = MIN, IIN = - 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA D Input E Input 20 80 A VCC = MAX, VIN = 2.7 V D Input E Input 0.1 0.4 mA VCC = MAX, VIN = 7.0 V D Input E Input - 0.4 - 1.6 mA VCC = MAX, VIN = 0.4 V - 100 mA VCC = MAX 12 mA VCC = MAX Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current - 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits S b l Symbol Typ Max U i Unit Propagation Delay, Data to Q 15 9.0 27 17 ns Propagation Delay, Data to Q 12 7.0 20 15 ns tPLH tPHL Propagation Delay, Enable to Q 15 14 27 25 ns tPLH tPHL Propagation Delay, Enable to Q 16 7.0 30 15 ns tPLH tPHL tPLH tPHL P Parameter Min FAST AND LS TTL DATA 5-2 T Test C Conditions di i 50V VCC = 5.0 CL = 15 pF SN54/74LS375 LOGIC DIAGRAM DATA Q (SN54LS/74LS375 ONLY) Q ENABLE TO OTHER LATCH GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 - 55 0 25 25 125 70 C IOH Output Current -- High 54, 74 - 0.4 mA IOL Output Current -- Low 54 74 4.0 8.0 mA AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits S b l Symbol P Parameter Min Typ U i Unit Max tW Enable Pulse Width 20 ns ts Setup Time 20 ns th Hold Time 0 ns T C di i Test Conditions VCC = 5.0 50V AC WAVEFORMS D 1.3 V 1.3 V ts E th 1.3 V 1.3 V 1.3 V tPLH Q tPHL 1.3 V tPLH 1.3 V tPHL Q tPLH 1.3 V tPHL 1.3 V tPLH tPHL DEFINITION OF TERMS SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. HOLD TIME (th) -- is defined as the minimum time following FAST AND LS TTL DATA 5-3