MF1530-01 SCSI Interface Controller S1R72105 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. 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Configuration of product number DEVICES S1 R 72105 F 00A0 00 Packing specifications 00: Besides tape & reel 0A: TCP BL 2 directions 0B: Tape & reel Back 0C: TCP BR 2 directions 0D: TCP BT 2 directions 0E: TCP BD 2 directions 0F: Tape & reel FRONT 0G: TCP BT 4 directions 0H: TCP BD 4 directions 0J: TCP SL 2 directions 0K: TCP SR 2 directions 0L: Tape & reel LEFT 0M: TCP ST 2 directions 0N: TCP SD 2 directions 0P: TCP ST 4 directions 0Q: TCP SD 4 directions 0R: Tape & reel RIGHT 99: Specs not fixed Specifications Shape (F : QFP) Model number Model name (R : Exclusive use controller, Peripheral) Product classification (S1:Semiconductors) CONTENTS 1. DESCRIPTION..................................................................................................................................1 2. FEATURES .......................................................................................................................................1 3. BLOCK DIAGRAM ...........................................................................................................................2 4. PIN ASSIGNMENT ...........................................................................................................................3 5. PIN DESCRIPTION...........................................................................................................................4 6. FUNCTIONAL DESCRIPTION .........................................................................................................6 6.1 CPU Interface Circuit..................................................................................................................6 6.2 Internal Registers........................................................................................................................6 6.3 Port Interface Circuit...................................................................................................................6 6.4 DMA Control Circuit....................................................................................................................6 6.5 SCSI-2 (3) Interface Circuit ........................................................................................................6 6.6 USB Interface Circuit ..................................................................................................................7 6.7 PLL Circuit (Internal System Clock Generating Section) ...........................................................7 7. FUNCTION OF REGISTERS............................................................................................................9 7.1 List of Registers ..........................................................................................................................9 7.1.1 List of Register/Window Settings (USB) ......................................................................11 7.2 List of Registers/Bits.................................................................................................................13 7.2.1 List of Registers/Bits/List of Window Configuration (USB) List of Bits ........................15 7.3 Detailed Description of Each Register......................................................................................17 7.3.1 Main Interrupt Status (MainIntStat) R/W ...................................................................17 7.3.2 EPr Interrupt Status(EPrIntStat) R/W ........................................................................18 7.3.3 Interrupt Status Window 0(IntStatWindow_0) R/W ...................................................18 7.3.4 Interrupt Status Window 1(IntStatWindow_1) R/W ...................................................19 7.3.5 Main Interrupt Enable(MainIntEnb) R/W ...................................................................19 7.3.6 EPr Interrupt Enable(EPrIntEnb) R/W .......................................................................19 7.3.7 Interrupt Enable Window 0(IntEnbWindow_0) R/W ..................................................20 7.3.8 Interrupt Enable Window 1(IntEnbWindow_1) R/W ..................................................20 7.3.9 Interrupt Index(IntIndex) R/W ....................................................................................20 7.3.10 System Control(SystemCtrl) R/W...............................................................................21 7.3.11 USB Common(USBCommon) R/W ............................................................................21 7.3.12 Reset(Reset) R/W ......................................................................................................22 7.3.13 Port DMA Control(PortDMACtrl) R/W ........................................................................22 7.3.14 Port DMA Size High(PortDMASize_H) R/W ..............................................................23 7.3.15 Port DMA Size Middle(PortDMASize_M) R/W...........................................................23 7.3.16 Port DMA Size Low(PortDMASize_L) R/W................................................................23 7.3.17 Port Config 0 (PortConfig_0) R/W..............................................................................24 7.3.18 Port Config 1(PortConfig_1) R/W...............................................................................25 7.3.19 USB Index(USBIndex) R/W .......................................................................................26 7.3.20 USB Window 0(USBWindow_0) R/W ........................................................................26 7.3.21 USB Window 1(USBWindow_1) R/W ........................................................................26 7.3.22 USB Window 2(USBWindow_2) R/W ........................................................................27 7.3.23 USB Window 3(USBWindow_3) R/W ........................................................................27 7.3.24 USB Window 4(USBWindow_4) R/W ........................................................................27 7.3.25 USB Window 5(USBWindow_5) R/W ........................................................................28 Rev.1.0 EPSON i 7.3.26 USB Window 6(USBWindow_6) R/W ........................................................................28 7.3.27 USB Window 7(USBWindow_7) R/W ........................................................................28 7.3.28 Main Interrupt Status SCSI (MAININTS) R/W ...........................................................29 7.3.29 SCSI Interrupt Status 1 (SCSIINT1) R/W ..................................................................30 7.3.30 SCSI Interrupt Status 2 (SCSIINT2) R/W ..................................................................31 7.3.31 SCSI Mode Select0 (SCSIMODE0) R/W ...................................................................32 7.3.32 SCSI Mode Select1 (SCSIMODE1) R/W ...................................................................33 7.3.33 SCSI Control (SCSICTL) R/W....................................................................................34 7.3.34 SCSI Data (SCSIDATA) R/W .....................................................................................34 7.3.35 Synchronize Transfer Mode (SYNCMODE) R/W.......................................................35 7.3.36 SCSI Own ID (OWNID) R/W ......................................................................................35 7.3.37 Source/Destination ID (SDID) R/W ............................................................................36 7.3.38 Selection Timeout Counter (SLTIME) R/W ................................................................36 7.3.39 FIFO Control (FIFOCTL) R/W ....................................................................................37 7.3.40 FIFO Data(FIFODATA) R/W.......................................................................................37 7.3.41 Non DMA Transfer Size (NDMASIZ) R/W .................................................................37 7.3.42 SCSI Command (COMMAND) R/W...........................................................................38 7.3.43 Test(TEST) R..............................................................................................................38 7.3.44 Revision Reg. (REVISION) R.....................................................................................38 7.4 Detailed Description of Set Values of INTINDEX Register ......................................................39 7.4.1 Register Showing IntStatWindow_0,1 and IntEnbWindow_0,1 for Set Values of IntIndex Register.........................................................................................................39 7.4.2 EP{r}(r=0,a,b,c) Interrupt Status(EP{r}IntStat) R/W ..................................................39 7.4.3 EP{r}(r=0,a,b,c) Interrupt Enable(EP{r}IntEnb) R/W .................................................40 7.5 Detailed Description of Set Values of USBIndex Register .......................................................41 7.5.1 List of Registers Showing USBWindow Register (8 bytes) Corresponding to Set Values of USBIndex Register(17h) ......................................................................41 7.5.2 Description of Registers by Set Value of USBIndex ....................................................42 7.5.2.1 USB Address(USBAddress) R/W ................................................................42 7.5.2.2 EP0 Config 1(EP0Config_1) R/W................................................................42 7.5.2.3 EP0 In Transaction Control(EP0InControl) R/W .........................................43 7.5.2.4 EP0 OUT Transaction Control(EP0OutControl) R/W ..................................44 7.5.2.5 EP0 FIFO remain Counter(EP0FIFOremain) R ..........................................45 7.5.2.6 EP0 FIFO for CPU(EP0FIFOforCPU) R/W .................................................45 7.5.2.7 EP0 FIFO Control(EP0FIFOCtrl) R/W .........................................................46 7.5.2.8 EP{r}(r=a,b,c) Config 0(EPrConfig_0) R/W...............................................47 7.5.2.9 EP{r}(r=a,b,c) Config 1(EPrConfig_1) R/W...............................................47 7.5.2.10 EP{r}(r=a,b,c) Control(EPrControl) R/W ....................................................48 7.5.2.11 EP{r}(r=a,b,c) FIFO remain Counter(EPrFIFOremain) R ..........................49 7.5.2.12 EPr FIFO for CPU(EPrFIFOforCPU) R/W .................................................49 7.5.2.13 EPr FIFO Control(EPrFIFOCtrl) R/W ........................................................50 7.5.2.14 EP0 SETUP[n](n=0,1,2,3,4,5,6,7) (EP0SETUP[n]) R ...............................50 7.5.2.15 Frame Number H(FrameNumber_H) R.....................................................51 7.5.2.16 Frame NumberL(FrameNumber_L) R .......................................................51 7.6 SCSI Control Commands .........................................................................................................52 7.6.1 Control Commands and Command Codes ..................................................................52 7.6.2 Description of Each Control Command........................................................................52 7.6.3 Command Execution and Change of State..................................................................60 ii EPSON Rev.1.0 7.7 Others and Cautions in Operation............................................................................................60 8. ELECTRICAL CHARACTERISTICS..............................................................................................62 8.1 Absolute Maximum Ratings......................................................................................................62 8.2 Recommended Operating Conditions ......................................................................................62 8.3 DC Characteristics....................................................................................................................62 8.4 AC Characteristics....................................................................................................................65 8.4.1 CPU Interface...............................................................................................................66 8.4.1.1 Register Read Timing ..................................................................................66 8.4.1.2 Register Write Timing ..................................................................................67 8.4.2 SCSI Interface ..............................................................................................................68 8.4.2.1 Selection Timing ..........................................................................................68 8.4.2.2 Re-selection Timing .....................................................................................69 8.4.2.3 Timing of Being Selected ...........................................................................70 8.4.2.4 Timing of Being Selected.............................................................................71 8.4.2.5 XSATN Output Timing..................................................................................72 8.4.2.6 Initiator Asynchronous Data-out Timing (Data output) ................................73 8.4.2.7 Initiator Asynchronous Data-in Timing (Data input) ...................................74 8.4.2.8 Initiator Synchronous Data-out Timing (Data output) ................................75 8.4.2.9 Initiator Synchronous Data-in Timing (Data input) ....................................76 8.4.2.10 Target Asynchronous Data-in Timing (Data output) ...................................77 8.4.2.11 Target Asynchronous Data-out Timing (Data input) ...................................78 8.4.2.12 Target Synchronous Data-in Timing (Data output) .....................................79 8.4.2.13 Target Synchronous Data-out Timing (Data input) .....................................80 8.4.3 Port Interface ................................................................................................................81 8.4.3.1 DMA Read (PSLV=1: Slave mode) ............................................................81 8.4.3.2 DMA Write (PSLV=1: Slave mode) ............................................................82 8.4.3.3 DMA Write (PSLV=0: Master mode) ..........................................................83 8.4.3.4 DMA Read (PSLV=0: Master mode) ..........................................................84 8.4.4 Others...........................................................................................................................85 8.4.4.1 OSCIN Input Clock ( ex.40MHz)..................................................................85 8.4.4.2 EXCLK Input Clock (48MHz) .......................................................................86 8.4.4.3 XRESET Input Pulse Width .........................................................................87 8.4.4.4 USB Interface Access Timing......................................................................87 9. EXAMPLES OF CONNECTION .....................................................................................................88 10. EXTERNAL DIMENSIONS DRAWING ..........................................................................................90 Rev.1.0 EPSON iii S1R72105 Technical Manual 1. DESCRIPTION S1R72105 contains the SCSI-3 interface controller and the USB 1.1 controller that support SCAM and FAST20 transfer, which is capable of bridging general-purpose I/O port and IDE DMA port as well as SCSI and USB interfaces. 2. FEATURES CPU Interface It can be connected to a general-purpose CPU SCSI Interface Compatible with SCSI-2 (10Mbps (synchronous), 5Mbps (asynchronous)) Compatible with SCSI-3 FAST20 (20Mbps (synchronous)) transfer Compatible with SCAM Lv.1 (compatible with Lv.2 with firmware) Automatic processing of phase control Built-in single end driver Active negation I/O mounted USB Interface Compatible with full speed mode (12Mbps) transfer Compatible with control transfer by endpoint 0 and bulk and interrupt transfers by three individual endpoints Split of the built-in SRAM (256 bytes) is programmable by user definition In addition to two-way endpoint 0, a maximum of three endpoints can be set PORT Interface General-purpose 8/16 bit-selectable purpose interface It allows selection between master and slave Since it allows DMA connection to IDE(ATAPI), IDE (ATAPI) equipment can be easily turned into the SCSI and USB equipment Others Built-in oscillation circuit: 20MHz/40MHz Built-in PLL circuit (generates both USB and SCSI clocks from 20MHz oscillation) 100 pin QFP (0.5 mm pitch) Supply voltage: 5.0V10% and 3.3V0.3V No anti-radiation design Rev.1.0 EPSON 1 S1R72105 Technical Manual 3. BLOCK DIAGRAM Port interface section XPDREQ XPDACK Master mode control XPRD XPWR Slave mode control SCSI-3 interface section Command analysis and execution FIFO (16Byte) PD15-0 Bus control FIFO control DMA control section DMA control Start-up/stop control EXCLK Clock distribution OSCIN OSCOUT Parity GEN/CHK Asynchronous transfer control XSRST XSDP XSATN XSBSY XSIO XSCD XSMSG XSSEL XSD7-0 XSDP XSREQ XSACK SCAM control 40/48 MHz Generating PLL VC Phase control Synchronous transfer Clock control section CLKSEL Sequence control USB1.1 interface FIFO (256Byte) CPU interface section Internal register Data MPX ENDPOINTs control DM VBUS TEST XRESET X-NT XWR XCS XRD DB7-0 DP XUSBOE Interrupt control AD5-0 Serial Interface Engine XPUENB Timing control 2 Transfer control EPSON Rev.1.0 S1R72105 Technical Manual 4. PIN ASSIGNMENT (QFP15-100pin) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS XSRST XSMSG VSS XSSEL XSCD VSS XSREQ HVDD XSIO VSS VC CLKSEL EXCLK LVDD OSCOUT OSCIN VSS PD7(15) PD8(14) PD6(13) PD9(12) PD5(11) PD10 HVDD S1R72105F0A 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 EPSO EPSON S1R72105 INDEX TOP View 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS PD4(9) PD11(8) PD3(7) PD12(6) PD2(5) HVDD PD13(4) PD1(3) PD14(2) PD0(1) PD15(0) VSS PDREQ XPWR XPRD XPDACK HVDD XRESET XCS XINTU XINTS XRD XWR LVDD LVDD DM DP VSS XPUENB VBUS XUSBOE TESTMON TESTEN DB0 DB1 DB2 DB3 HVDD DB4 DB5 DB6 DB7 AD0 AD1 AD2 AD3 AD4 AD5 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LVDD HVDD XSACK VSS XSBSY XSATN HVDD XSDBP VSS XSDB7 HVDD XSDB6 VSS XSDB5 HVDD XSDB4 VSS XSDB3 HVDD XSDB2 VSS XSDB1 HVDD XSDB0 VSS Rev.1.0 EPSON 3 S1R72105 Technical Manual 5. PIN DESCRIPTION The control signal with "X" at the head of a pin name is LOW-active. Pin No. Symbol I/O Functional description SCSI interface-related matters (18) 99 XSDB0 Is/Otr SCSI data signal (SD0 to SD7) 97 XSDB1 95 XSDB2 93 XSDB3 91 XSDB4 89 XSDB5 87 XSDB6 85 XSDB7 83 XSDBP SCSI data parity signal 81 XSATN I/Ood SCSI ATN signal 80 XSBSY I/Ood SCSI BSY signal 78 XSACK Is/Otr SCSI ACK signal 74 XSRST I/Ood SCSI RST signal 73 XSMSG I/Ood SCSI MSG signal 71 XSSEL I/Ood SCSI SEL signal 70 XSCD I/Ood SCSI C/D signal 68 XSREQ Is/Otr SCSI REQ signal 66 XSIO I/Ood SCSI I/O signal USB interface-related matters (5) 2 DM I/O USB data port 3 DP I/O USB data port (Configure to pull up to 3.3V by a 1.5k resistor externally. The register can be controlled by "XPUENB.") 5 XPUENB Ood Control signal connecting a 1.5k pull-up resistor to "DP" pin Ood. VBUS = 5V and HIGH EnPullUp(USBCommon_b1) brings about LOW output. 6 VBUS Is USB bus power detection input (Pull down externally). 7 XUSBOE O LOW output while this IC outputs a signal to DP and DM pins. Port interface-related matters (20) 35 XPRD Is/O Port read signal 36 XPWR Is/O Port write signal 37 PDREQ Is/O Port DMA request signal (also operable in negative logic) 34 XPDACK Is/O Port DMA ACK signal 40 PD0 I/O Port DMA data bus signal (PD0 to 15) 42 PD1 45 PD2 47 PD3 49 PD4 53 PD5 55 PD6 57 PD7 56 PD8 54 PD9 52 PD10 48 PD11 46 PD12 43 PD13 41 PD14 39 PD15 4 EPSON Remarks Drive capability 48mA Drive capability 48mA Drive capability 48mA Drive capability 48mA Drive capability 48mA Drive capability 48mA Drive capability 48mA Drive capability 48mA Drive capability 48mA Drive capability 48mA Drive capability 48mA Drive capability 6mA Drive capability 3mA Drive capability 3mA Drive capability 3mA Drive capability 6mA Drive capability 3mA Drive capability 3mA Rev.1.0 S1R72105 Technical Manual Pin No. Symbol I/O Functional description CPU interface-related matters (19) 19 AD0 I Address input pin (AD0 to AD5) 20 AD1 21 AD2 22 AD3 23 AD4 24 AD5 10 DB0 I/O Data pin (DB0 to DB7) 11 DB1 12 DB2 13 DB3 15 DB4 16 DB5 17 DB6 18 DB7 31 XCS Is Chip select signal for accessing internal register 30 XINTU O USB interrupt request output signal 29 XINTS O SCSI interrupt request output signal 28 XRD Is Data read signal 27 XWR Is Data write signal Others (17) 59 OSCIN I Input to built-in oscillation circuit (40MHz or 20MHz) 60 OSCOUT O Output from built-in oscillation circuit 8 TESTMON O Monitor output for testing (open LOW output usually) 32 XRESET Ispu System reset input signal 9 TESTEN Ipd Pin for testing (connected to LOW (GND) usually) 63 CLKSEL I Input clock and PLL operation selection HIGH (LVDD): Generates clock (SCSI_40MHz,USB_48MHz) in internal PLL. 20MHz oscillation in OSCIN/OUT or input 20MHz(3.3V) to OSCIN EXCLK is connected to LOW (GND) or HIGH (LVDD). LOW (GND): PLL stop (power-down) , external clock in operation 40MHz oscillation in OSCIN/OUT or input 40MHz(3.3V) to OSCIN Input 48MHz(3.3V) to EXCLK 62 EXCLK I External clock input pin for 3.3V level USB (Connected to LOW (GND) or HIGH (LVDD) while it is not used). 64 VC O For instructions as to how to connect internal VCO control pins, refer to the description of PLL circuit. HVDD:5V (5) 14,33,44,51, HVDD P Power supply for 5V interface 67,77,82,86, 90,94,98 LVDD:3.3V (6) 1,26,61,76 LVDD P Power supply for internal operation VSS:0V (17) 4,25,38,50, VSS 58,65,69,72, 75,79,84,88, 92,96,100 (Note) Rev.1.0 I Is Ipu Ispu P Remarks Drive capability 3mA Drive capability 6mA Drive capability 6mA Drive capability 2mA GND : Input : Schmitt input : Pull-up input : Pull-up Schmitt input O Ood Otr Ipd : Output : Open-drain output : Try state output : Pull-down input EPSON 5 S1R72105 Technical Manual 6. FUNCTIONAL DESCRIPTION 6.1 CPU Interface Circuit This block can be interfaced to a general-purpose CPU. It generally controls the interface with the CPU. When the XCS signal from the CPU is LOW, the block can access the internal register. It decodes the address bus AD5 to AD0 to generate the address of the internal register. At this time, it generates the read/write strobe signal from the XRD/XWR signal, transferring data between the internal register. A wait signal to the CPU is not generated because of no-wait operation. 6.2 Internal Registers Refer to the section of Register Functions as for the addresses of the internal registers and description of each bit. The main functions of this block are as follows: (1) It generates control signals to each block according to the address, write-data and write-strobe signals generated by the CPU interface circuit. (2) It stores the status signals from each block, and outputs data according to the address and read-strobe signals sent from the CPU interface circuit. 6.3 Port Interface Circuit This is a block controlling the transfer to and from the external DMA port. It has the following functions: (1) It controls the linkage operation of each functional block according to the control signal and the stop-operation signal sent from the DMA control circuit. (2) It controls the transfer status of the external port according to PDREQ/XPDACK signals. (3) It reads/writes data of the data bus PD15-0 of the port from/to FIFO in the SCSI-2 block. When transfer is disabled in the full/empty state of SCSI_FIFO, transfer to and from the port is temporarily halted according to the timing specified by the PDREQ/XPDACK signals. (4) The port allows selection of bit width betweem 8 and 16. (5) The port interface allows selection between the master and slave function (toward PDREQ/XPDACK/XPRD/XPWR direction). 6.4 DMA Control Circuit This block controls the transfer between the DMA port and FIFO in the SCSI block and FIFO in the USB block. It has the following functions: (1) It controls the linkage operation of each functional block according to the control signal from the internal register and the information and stop-operation signals from each block. (2) It stores the status of each of functional blocks when their linkage operation ends, reporting it to the internal register at the specified timing. 6.5 SCSI-2 (3) Interface Circuit This block generally controls the interfaces conforming to the SCSI-2 standard. It has the following functions: (1) It automatically performs the SCSI protocol control on hardware. (2) It has 16-staged off-set counter to control the off-set and transfer rate during synchronous transfer. (3) In the command phase, it automatically distinguishes groups of commands received (in Target mode). (4) It controls the automatic status/message transfer function. It supports the messages 00h/0Ah/0Bh. (in Target mode). (5) It allows SCSI-3 FAST20(20Mbps) transfer. SCAM compatibility In addition to conventional SCSI, this LSI has SCAM (SCSI Configured Auto Magnify)-compatible functions as listed below: These functions enable the device to operate as a SCAM Lv.1 drive. (1) It monitors and recognizes the SCAM selection and causes an interruption. (2) It responds to the selection response delay of 4ms or more, which enables distinction between SCAM and ordinary selections. (3) It can operate SCSI bus's signal line directly because of its actual operation responding to the SCAM selection and sending/receiving data. 6 EPSON Rev.1.0 S1R72105 Technical Manual 6.6 USB Interface Circuit (1) It supports full speed device in conformity to the USB1.1 (It does not support low speed). It supports control transfer (endpoint 0), bulk transfer, and interrupt transfer (It does not support isochronous transfer). (2) Split of the built-in SRAM (256 bytes) is programmable by user definition. In addition to two-way endpoint 0, a maximum of three endpoints can be set. Three endpoints can be independently set to IN/OUT direction, any of four maximum packet lengths (8, 16, 32 or 64 bytes), any endpoint number, and buffer size (single or double). 6.7 PLL Circuit (Internal System Clock Generating Section) This IC has the function to generate 40MHz(SCSI) and 48MHz(USB) required for the internal circuit from the clock generated by the oscillation circuit by using the PLL circuit. The block diagram around the oscillation section is shown below: B(0) Y SCSI 40MHz A(1) S EXCLK Internal clock B(0) USB 48MHz Y PLL A(1) S VC OSCOUT OSCIN CLKSEL (20MHz/40MHz) 4.7k 1M 5pF GND * * * LVDD or GND 5pF GND 3pF 100pF GND GND The IC enables easy setup of an oscillation circuit by connecting a crystal vibrator and feedback resistor (For characteristics of the crystal vibrator, contact us separately). It allows oscillation of 20MHz by means of the oscillation circuit mentioned above. In this case, 40MHz and 48MHz required for each block of SCSI and USB are generated by using the internal PLL. So connect the EXCLK pin to LVDD or GND (CLKSEL = LVDD). The IC allows operation by inputting a 40MHz external clock of 3.3V level to the OSCIN pin or 40MHz oscillation and inputting a 48MHz external clock of 3.3V level to the EXCLK pin without using the internal PLL. In this case, connect the CLKSEL to the "GND" to stop operation of the PLL block. Rev.1.0 EPSON 7 S1R72105 Technical Manual Depending on the usage, set the control signal as shown below: - When an oscillator circuit (20MHz) is used - When a 20 MHz clock of 3.3V level is input from the OSCIN pin (PLL is used) - When an oscillator circuit (40MHz) is used - When a 40 MHz clock of 3.3V level is input from the OSCIN pin (PLL is not used) 20MHz 40MHz CLKSEL LVDD GND EXCLK LVDD or GND Input 48MHz(3.3V) Oscillation/input clock * PLL circuit specifications Ta=0 to 70C Item 8 LVDD=3.3V0.3V Specifications Lock-up time Within 1ms after oscillation was stabilized Jitter Within 1ns EPSON Rev.1.0 S1R72105 Technical Manual 7. FUNCTION OF REGISTERS 7.1 List of Registers Address Register name Abbreviated name 00h Main Interrupt Status MainIntStat 01h Epr Interrupt Status EPrIntStat 02h Interrupt Status Window_0 IntStatWindow_0 03h Interrupt Status Window_1 IntStatWindow_1 04h Main Interrupt Enable MainIntEnb 05h Epr Interrupt Enable EPrIntEnb 06h Interrupt Enable Window_0 IntEnbWindow_0 07h Interrupt Enable Window_1 IntEnbWindow_1 08h Interrupt Index IntIndex 09h System Control SystemCtrl 0Ah USB Common USBCommon 0Bh - Reserved - - 0Ch - Reserved - - 0Dh Reset 0Eh - Reserved - - 0Fh - Reserved - - 10h Port DMA Control PortDMACtrl 11h Port DMA Size_H PortDMASize_H 12h Port DMA Size_M PortDMASize_M 13h Port DMA Size_L PortDMASize_L 14h Port Configuration_0 PortConfig_0 15h Port Configuration_1 PortConfig_1 16h - Reserved - 17h USB Index 18h USB Window_0 USBWindow_0 19h USB Window_1 USBWindow_1 1Ah USB Window_2 USBWindow_2 1Bh USB Window_3 USBWindow_3 1Ch USB Window_4 USBWindow_4 1Dh USB Window_5 USBWindow_5 1Eh USB Window_6 USBWindow_6 1Fh USB Window_7 USBWindow_7 Rev.1.0 Reset USBIndex EPSON 9 S1R72105 Technical Manual Address 10 Register name Abbreviated name 20h Main Interrupt Status SCSI MAININTS 21h SCSI Interrupt status 1 SCSIINT1 22h SCSI Interrupt status 2 SCSIINT2 23h - Reserved - - 24h - Reserved - - 25h - Reserved - - 26h - Reserved - - 27h - Reserved - - 28h - Reserved - - 29h SCSI Mode 0 SCSIMODE0 2Ah SCSI Mode 1 SCSIMODE1 2Bh SCSI Control SCSICTL 2Ch SCSI Synchronous data transfer Mode 2Dh SCSI DATA 2Eh SCSI Own ID 2Fh SCSI Source/Destination ID 30h SCSI Selection Timeout Counter SELTIME 31h SCSI FIFO Control FIFOCTL 32h SCSI FIFO Data FIFODATA 33h SCSI Non-DMA Transfer Size NDMASIZE 34h SCSI Command COMMAND 35h - Reserved - - 36h - Reserved - - 37h - Reserved - - 38h - Reserved - - 39h - Reserved - - 3Ah - Reserved - - 3Bh - Reserved - - 3Ch - Reserved - - 3Dh - Reserved - - 3Eh Test 3Fh REVISION SCSIDATA SYNCMODE OWNID SDID TEST REVISION EPSON Rev.1.0 S1R72105 Technical Manual 7.1.1 List of Register/Window Settings (USB) * * * * Details appearing in IntStatWindow_0(02h) IntIndex(08h) 4 higher order bits (bit7,6,5,4) Function of IntStatWindow_0 register Description on display 0h EP0IntStat Endpoint 0 status display/clear 1h EPaIntStat Endpoint a status display/clear 2h EPbIntStat Endpoint b status display/clear 3h EPcIntStat Endpoint c status display/clear Details appearing in IntStatWindow_1(03h) IntIndex(08h) 4 lower order bits (BIT3,2,1,0) Function of IntStatWindow_1 register Description on display 0h EP0IntStat Endpoint 0 status display/clear 1h EPaIntStat Endpoint a status display/clear 2h EPbIntStat Endpoint b status display/clear 3h EPcIntStat Endpoint c status display/clear Details appearing in IntEnbWindow_0(06h) IntIndex(08h) higher order 4 bits (bit7,6,5,4) Function of IntEnbWindow_0 register Description on display 0h EP0IntEnb Endpoint 0 status interrupt enabled 1h EPaIntEnb Endpoint a status interrupt enabled 2h EPbIntEnb Endpoint b status interrupt enabled 3h EPcIntEnb Endpoint c status interrupt enabled Details appearing in IntEnbWindow_1(07h) IntIndex(08h) 4 lower order bits (bit3,2,1,0) Function of IntEnbWindow_1 register Description on display 0h EP0IntEnb Endpoint 0 status interrupt enabled 1h EPaIntEnb Endpoint a status interrupt enabled 2h EPbIntEnb Endpoint b status interrupt enabled 3h EPcIntEnb Endpoint c status interrupt enabled Rev.1.0 EPSON 11 S1R72105 Technical Manual * Details appearing in USBWindow_0(18h) to USBWindow_0(1Fh) USBIndex(17h) Register name 00h USBWindow_0(18h) USBAddress: USB address USBWindow_1(19h) EP0Config_1EP0 configuration USBWindow_2(1Ah) EP0InControl: EP0 IN Transaction control USBWindow_3(1Bh) EP0OutControl: EP0 OUT Transaction control USBWindow_4(1Ch) (Reserved) USBWindow_5(1Dh) EP0FIFOremain: EP0 FIFO counter USBWindow_6(1Eh) EP0FIFOforCPU: EP0 FIFO for CPU access USBWindow_7(1Fh) EP0FIFOCtrl: EP0 FIFO control USBWindow_0(18h) EPrConfig_0:EP{r}(r=a,b,c) configuration USBWindow_1(19h) EPrConfig_1:EP{r}(r=a,b,c) configuration USBWindow_2(1Ah) EPrControlEP {r} (r=a,b,c) Transaction control USBWindow_3(1Bh) (Reserved) USBWindow_4(1Ch) (Reserved) USBWindow_5(1Dh) EPrFIFOremainEP {r} (r=a,b,c) FIFO counter USBWindow_6(1Eh) EPrFIFOforCPUEP {r} (r=a,b,c) FIFO for CPU access USBWindow_7(1Fh) EPrFIFOCtrl EP {r} (r=a,b,c) FIFO control USBWindow_0(18h) EP0_SETUP_0 EP0 SETUP stage receive data USBWindow_1(19h) EP0_SETUP_1 EP0 SETUP stage receive data USBWindow_2(1Ah) EP0_SETUP_2 EP0 SETUP stage receive data USBWindow_3(1Bh) EP0_SETUP_3 EP0 SETUP stage receive data USBWindow_4(1Ch) EP0_SETUP_4 EP0 SETUP stage receive data USBWindow_5(1Dh) EP0_SETUP_5 EP0 SETUP stage receive data USBWindow_6(1Eh) EP0_SETUP_6 EP0 SETUP stage receive data USBWindow_7(1Fh) EP0_SETUP_7 EP0 SETUP stage receive data 01h to 03h 08h 09h USBWindow_0(18h) USBWindow_1(19h) 12 Description on display FrameNumber_H: Higher order 3 bits in the FrameNumber field of the SOF Packet received FrameNumber_L: Lower order 8 bits in the FrameNumber field of the SOF Packet received USBWindow_2(1Ah) (Reserved) USBWindow_3(1Bh) (Reserved) USBWindow_4(1Ch) (Reserved) USBWindow_5(1Dh) (Reserved) USBWindow_6(1Eh) (Reserved) USBWindow_7(1Fh) (Reserved) EPSON Rev.1.0 S1R72105 Technical Manual 7.2 List of Registers/Bits Address Type Register name Default value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 00h R/W MainIntStat 40/00h USB resume USB reset USB suspend Detect SOF Port DMACmp SCSI 01h R/W EPrIntStat 00h - - - - EPclnt Stat EPblnt Stat 02h R/W IntStatWindow_0 00h 03h R/W IntStatWindow_1 00h Bit1 Bit0 RcvEP0 SETUP EPalnt Stat EPrlnt Stat EP0lnt Stat EnRcv SETUP EnEPa lnt EnEPr IntStat EnEP0 lnt IntStatWindow_0 (swiching by IntIndex_0) IntStatWindow_1 (swiching by IntIndex_1) 04h R/W MainIntEnb 00h EnUSB resume EnUSB reset - EnUSB EnDetect EnPort EnSCSI DMACmp suspend SOF EnEPc EnEPb lnt lnt 05h R/W EPrIntEnb 00h - 06h R/W IntEnbWindow_0 00h IntEnWindow_0 (swiching by IntIndex_0) 07h R/W IntEnbWindow_1 00h IntEnWindow_1 (swiching by IntIndex_1) 08h R/W IntIndex 01h IntIndex_0 IntIndex_1 Go Send Suspend Wakeup IgnrTgl Mis xINT mode1 EnPull Up xINT mode0 Active USB - - - - - - - - PORT SCSI USB - - - - - - - - - - - - - S_FIFO DTGO DBC22 DBC21 DBC20 DBC19 DBC18 DBC17 DBC16 DBC15 DBC14 DBC13 DBC12 DBC11 DBC10 DBC9 DBC8 00h DBC7 DBC6 DBC5 DBC4 DBC3 DBC2 DBC1 DBC0 PortConfig_0 00h ACP BUSC PSLV - PRQLV SWAP ODS BUS8 R/W PortConfig_1 00h AP3 AP2 AP1 AP0 NP3 NP2 NP1 NP0 16h - - - - - - - - - - - 17h R/W USBIndex 00h USBIndex 18h R/W USBWindow_0 00h USBWindow_0 (swiching by USBIndex) 19h R/W USBWindow_1 00h USBWindow_1 (swiching by USBIndex) 1Ah R/W USBWindow_2 00h USBWindow_2 (swiching by USBIndex) 1Bh R/W USBWindow_3 00h USBWindow_3 (swiching by USBIndex) 1Ch R/W USBWindow_4 00h USBWindow_4 (swiching by USBIndex) 1Dh R/W USBWindow_5 00h USBWindow_5 (swiching by USBIndex) 1Eh R/W USBWindow_6 00h USBWindow_6 (swiching by USBIndex) 1Fh R/W USBWindow_7 00h USBWindow_7 (swiching by USBIndex) 09h R/W SystemCtrl 03h - - - 0Ah R/W USBCommon xxh VBUS - - - - 0Bh R/W - 00h - - - - 0Ch R/W - 00h - - - - 0Dh R/W Reset 00h 0Eh R/W - 00h - - - - 0Fh R/W - 00h - - - 10h R/W PortDMACtrl 00h MODE1 MODE0 11h R/W PortDMASize_H 00h DBC23 12h R/W PortDMASize_M 00h 13h R/W PortDMASize_L 14h R/W 15h Rev.1.0 EPSON - 13 S1R72105 Technical Manual Address Type Register name Default value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 20h R/W MAININTS 00h GOOD SABT EXEC SCSI1 SCSI2 - DTCMP ASCMP 21h R/W SCSIINT1 00h SPERR IDERR SELTO SATN BFREE ILPHS SCSEL WOATN 22h R/W SCSIINT2 00h - SRST OFERR UNDEF CMDER RESEL SEL LARBT 23h - - - - - - - - - - - 24h - - - - - - - - - - - 25h - - - - - - - - - - - 26h - - - - - - - - - - - 27h - - - - - - - - - - - 28h - - - - - - - - - - - 29h R/W SCSIMODE0 00h - - - ULTRA AUTO1 AUTO2 AN_C AN_D 2Ah R/W SCSIMODE1 00h STPPE ATNPE STATN AUTO RINH SINH DACS SPCEN 2Bh R/W SCSICTL 00h ACK ATN SEL BSY REQ MSG I/O C/D 2Ch R/W SCSIDATA 00h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 2Dh R/W SYNCMODE 00h RATE3 RATE2 RATE1 RATE0 OFF3 OFF2 OFF1 OFF0 2Eh R/W OWNID 00h - - - - - OID2 OID1 OID0 2Fh R/W SDID xxh - SID2 SID1 SID0 - DID2 DID1 DID0 30h R/W SELTIME 00h ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 31h R/W FIFOCTL 01h - - - - - FCLR FULL EMPTY 32h R/W FIFODATA xxh FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 33h R/W NDMASIZE FFh NSZ7 NSZ6 NSZ5 NSZ4 NSZ3 NSZ2 NSZ1 NSZ0 34h R/W COMMAND 00h CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 35h - - - - - - - - - - - 36h - - - - - - - - - - - 37h - - - - - - - - - - - 38h - - - - - - - - - - - 39h - - - - - - - - - - - 3Ah - - - - - - - - - - - 3Bh - - - - - - - - - - - 3Ch - - - - - - - - - - - 3Dh - - - - - - - - - - - 3Eh R TEST 00h TM2 TM1 TM0 USEL1 USEL0 OFST SCBC DMBC 3Fh R/W REVISION 00h REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 14 EPSON Rev.1.0 S1R72105 Technical Manual 7.2.1 List of Registers/Bits/List of Window Configuration(USB) List of Bits * Details appearing in IntStatWindow_0(02h) IntIndex(08h) Higher order IntStatWindow_0 Functions of 4 bits register (BIT7,6,5,4) * Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 EP0IntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 1h EPaIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 2h EPbIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 3h EPcIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv Details appearing in IntStatWindow_1(03h) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0h EP0IntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 1h EPaIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 2h EPbIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 3h EPcIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv Details appearing in IntEnbWindow_0(06h) IntIndex(08h) IntStatWindow_0 Higher order Functions of 4 bits register (bit7,6,5,4) * Bit6 0h IntIndex(08h) IntStatWindow_1 Lower order Functions of 4 bits register (bit3,2,1,0) * Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0h EP0IntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 1h EPaIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 2h EPbIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 3h EPcIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv Details appearing in IntEnbWindow_1(07h) IntIndex(08h) IntStatWindow_0 Lower order Functions of 4 bits register (bit3,2,1,0) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0h EP0IntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 1h EPaIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 2h EPbIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 3h EPcIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv Rev.1.0 EPSON 15 S1R72105 Technical Manual * Details appearing in USBWindow_0(18h) to USBWindow_0(1Fh) USBIndex(17h) Register name 00h 01h to 07h 08h 09h 16 USBWindow_0 (18h) USBWindow_1 (19h) USBWindow_2 (1Ah) USBWindow_3 (1Bh) USBWindow_4 (1Ch) USBWindow_5 (1Dh) USBWindow_6 (1Eh) USBWindow_7 (1Fh) USBWindow_0 (18h) USBWindow_1 (19h) USBWindow_2 (1Ah) USBWindow_3 (1Bh) USBWindow_4 (1Ch) USBWindow_5 (1Dh) USBWindow_6 (1Eh) USBWindow_7 (1Fh) USBWindow_0 (18h) USBWindow_1 (19h) USBWindow_2 (1Ah) USBWindow_3 (1Bh) USBWindow_4 (1Ch) USBWindow_5 (1Dh) USBWindow_6 (1Eh) USBWindow_7 (1Fh) USBWindow_0 (18h) USBWindow_1 (19h) Function of register Bit7 Bit6 USBAddress - (MSB) EP0Config_1 OUTxIN EP0InControl EP0OutControl (Reserved) EP0FIFOremain INForce NAK OutForce NAK - - Bit5 Bit4 (MSB) - - - FIFO Empty EPrConfig_0 - EPrConfig_ OUTxIN EPrControl (Reserved) (Reserved) INForce NAK OutForce NAK - FIFO Full (LSB) - - - - - InToggle InToggle InToggle Stat Clr Set OutToggle OutToggle OutToggle Stat Clr Set - - (LSB) EP0FIFOdata [7:0] (LSB) FIFO Ctr - - AutoForce EnFIFO NAK Owr USB Address [6:0] - - InForce InEnShort STALL Pkt OutForce STALL - Bit0 MaxPacketSize[3:0] - (MSB) - Bit1 EP0FIFOremainCounter [7:0] EP0FIFOforCPU (MSB) EP0FIFOCtrl Bit2 USB Address [6:0] InForce InEnShort STALL Pkt OutForce STALL - Bit3 - EnFIFO Ord (LSB) MaxPacketSize[3:0] - - - - - - InToggle InToggle InToggle Stat Clr Set OutToggle OutToggle OutToggle Stat Clr Set - - - EPrFIFOremain (MSB) EP0FIFOremainCounter [7:0] (LSB) EPrFIFOforCPU (MSB) EP0FIFOdata [7:0] (LSB) EPrFIFOCtrl FIFO Empty FIFO Full FIFO Ctr - - AutoForce EnFIFO NAK Owr EnFIFO Ord EP0_SETUP_0 (MSB) EP0_RcvSETUPdata_0 (LSB) EP0_SETUP_1 (MSB) EP0_RcvSETUPdata_1 (LSB) EP0_SETUP_2 (MSB) EP0_RcvSETUPdata_2 (LSB) EP0_SETUP_3 (MSB) EP0_RcvSETUPdata_3 (LSB) EP0_SETUP_4 (MSB) EP0_RcvSETUPdata_4 (LSB) EP0_SETUP_5 (MSB) EP0_RcvSETUPdata_5 (LSB) EP0_SETUP_6 (MSB) EP0_RcvSETUPdata_6 (LSB) EP0_SETUP_7 (MSB) EP0_RcvSETUPdata_7 (LSB) FrameNumber_H FrameNumber_L - - - - FrameNumber [10:0] EPSON - (MSB) (LSB) Rev.1.0 S1R72105 Technical Manual 7.3 Detailed Description of Each Register 7.3.1 Main Interrupt Status (MainIntStat) R/W When the IC interrupts the CPU, the CPU identifies the interrupt status register responsible for interruption by reading this register first. Following the reading of this register, the CPU identifies the bit as a source of interruption and clears it by writing the value read after appropriate interrupt processing. When the EPrIntStat is a source of interruption, the bit should be cleared by writing the value read to the interrupt status register corresponding to each bit of the interrupt status register. Address 00h Register Name MainIntStat Bit Symbol 7: USBresume 6: USBreset 5: USBsuspend 4: DetectSOF 3: PortDMACmp 2: SCSI 1: RcvEP0SETUP 0: EPrIntStat Description USB Resume USB Reset USB Suspend Detect SOF Token Port DMA Complete SCSI interrupt Receive EP0 SETUP Transaction Epr Interrupt Status BIT7 USB Resume When Resume is present while the GoSuspend bit of the SystemCtrl register (09h) is being set, this bit becomes HIGH. Clearing GoSuspend clears it. BIT6 USB Reset At USB reset, this bit becomes HIGH. At the same time, the USB address register shown in "7.5.2.1 USB Address (USBAddress)" is cleared. BIT5 USB Suspend At USB Suspend, this bit becomes HIGH. BIT4 Detect SOF Token When the SOF Token is detected, this bit becomes HIGH. BIT3 Port DMA Complete This bit becomes HIGH when a port DMA transfer activated by the PortDMACtrl register (10h) ends. It also becomes HIGH when the transfer is forced to terminate by writing "0" to the DTGO bit of the PortDMACtrl register. In conditions of mode1:0="00" of PortDMACtrl register, XINTU is set by this factor. In other modes, XINTU is not set by this factor. BIT2 SCSI Interrupt When SCSI-related interrupt occurs, this bit becomes HIGH Detailed factors appear in MAINTS/SCSIINT1/SCSIINT2 register. This does not change when accessing this register. BIT1 Receive EP0 SETUP Transaction This bit becomes HIGH when the endpoint 0 completes the SETUP Stage normally. The received data appears in the USBWindow_0 register (18h) - USBWindow_7 register (1Fh) following the setting of the USBIndex register (17h) to 08h. BIT0 EPr Interruput Status This bit becomes HIGH when the interrupt status corresponding to each of the EPrIntStat register(01h) is a factor. Rev.1.0 EPSON 17 S1R72105 Technical Manual 7.3.2 EPr Interrupt Status(EPrIntStat) R/W The factor responsible for endpoint interrupt status can be identified by reading this register. When all factors of endpoint-by-endpoint interruption (interrupt factors at the main source) shown by each bit are cleared, the relevant bit is cleared. Following the reading of this register, the bit (interrupt factor at the main source) is cleared by writing the value read in the interrupt status register (02h or 03h) corresponding to each bit of the appropriate interrupt status register. The appropriate interrupt status register is shown in the IntStatWindow_0 register (02h) or IntStatWindow_1 register (03h) by writing a value to the IntIndex register (08h). Address 01h Register Name EPrIntStat BIT3 Endpoint c Interrupt Status This bit becomes HIGH present. BIT2 Endpoint b Interrupt Status This bit becomes HIGH present. BIT1 Endpoint a Interrupt Status This bit becomes HIGH present. BIT0 Endpoint 0 Interrupt Status This bit becomes HIGH present. Bit Symbol Description 7: 6: 5: 4: 3: EPcIntStat 2: EPbIntStat 1: EPaIntStat 0: EP0IntSta t Reserved Reserved Reserved Reserved Endpoint c Interrupt Status Endpoint b Interrupt Status Endpoint a Interrupt Status Endpoint 0 Interrupt Status when an interrupt factor related to the USB interface shown in the EPcIntStat register is when an interrupt factor related to the USB interface shown in the EPbIntStat register is when an interrupt factor related to the USB interface shown in the EPaIntStat register is when an interrupt factor related to the USB interface shown in the EP0IntStat register is 7.3.3 Interrupt Status Window 0(IntStatWindow_0) R/W The endpoint interrupt status register appears. The interrupt status to be displayed changes according to the value set at IntIndex_0 of the IntIndex register (08h). For set value of the IntIndex register, refer to section "7.4 Detailed Description of Set Values of IntIndex Register." Address 02h 18 Register Name IntStatWindow_0 Bit Symbol 7: IntStatWindow_0[7] 6: IntStatWindow_0[6] 5: IntStatWindow_0[5] 4: IntStatWindow_0[4] 3: IntStatWindow_0[3] 2: IntStatWindow_0[2] 1: IntStatWindow_0[1] 0: IntStatWindow_0[0] Description Interrupt Status Window 0 EPSON Rev.1.0 S1R72105 Technical Manual 7.3.4 Interrupt Status Window 1(IntStatWindow_1) R/W The endpoint interrupt status register appears. The interrupt status to be displayed changes according to the value set at IntIndex_1 of the IntIndex register (08h). For set value of the IntIndex register, refer to section "7.4 Detailed Description of Set Values of IntIndex Register." Address 03h Register Name IntStatWindow_1 Bit Symbol 7: IntStatWindow_1[7] 6: IntStatWindow_1[6] 5: IntStatWindow_1[5] 4: IntStatWindow_1[4] 3: IntStatWindow_1[3] 2: IntStatWindow_1[2] 1: IntStatWindow_1[1] 0: IntStatWindow_1[0] Description Interrupt Status Window 1 7.3.5 Main Interrupt Enable (MainIntEnb) R/W This register enables/disables interrupt factors of the MinInstStat register. When the corresponding bit is set to HIGH an interruption to the CPU is enabled. Address 04h Register Name MainIntEnb Bit Symbol 7: EnUSBresume 6: EnUSBreset 5: EnUSBsuspend 4: EnDetectSOF 3: EnPortDMACmp 2: EnSCSI 1: EnRcvSETUP 0: EnEPrIntStat Description Enable USB Resume Enable USB Reset Enable USB Suspend Enable Detect SOF Enable Port DMA Complete Enable SCSI Interrupt Enable Received SETUP Enable EPr Interrupt Status BIT2 Enable SCSI Interrupt When this bit is set to HIGH all SCSI interruptions including ASCMP are enabled. SCSI, the BIT3 setting is valid instead of this bit. For DTCMP interruption by 7.3.6 EPr Interrupt Enable (EPrIntEnb) R/W This register enables/disables interrupt factors of the EprIntStat register. When the corresponding bit is set to HIGH an interruption to the CPU is enabled. Address 05h Rev.1.0 Register Name EPrIntEnb Bit Symbol 7: 6: 5: 4: 3: EnEPcInt 2: EnEPbInt 1: EnEPaInt 0: EnEP0Int EPSON Description Reserved Reserved Reserved Reserved Enable Endpoint c Interrupt Enable Endpoint b Interrupt Enable Endpoint a Interrupt Enable Endpoint 0 Interrupt 19 S1R72105 Technical Manual 7.3.7 Interrupt Enable Window 0 (IntEnbWindow_0) R/W The register enabling/disabling endpoint interruption appears. The interrupt status to be displayed changes according to the value set at IntIndex_0 of the IntIndex register (08h). For set value of the IntIndex register, refer to section "7.4 Detailed Description of Set Values of IntIndex Register." Address 06h Register Name IntEnbWindow_0 Bit Symbol 7: IntEnbWindow_0 [7] 6: IntEnbWindow_0 [6] 5: IntEnbWindow_0 [5] 4: IntEnbWindow_0 [4] 3: IntEnbWindow_0 [3] 2: IntEnbWindow_0 [2] 1: IntEnbWindow_0 [1] 0: IntEnbWindow_0 [0] Description Interrupt Enable Window 0 7.3.8 Interrupt Enable Window 1(IntEnbWindow_1) R/W The register enabling/disabling endpoint interruption appears. The interrupt status to be displayed changes according to the value set at IntIndex_1 of the IntIndex register (08h). For set value of the IntIndex register, refer to section "7.4 Detailed Description of Set Values of IntIndex Register." Address 07h Register Name IntEnbWindow_1 Bit Symbol 7: IntEnbWindow_1 [7] 6: IntEnbWindow_1 [6] 5: IntEnbWindow_1 [5] 4: IntEnbWindow_1 [4] 3: IntEnbWindow_1 [3] 2: IntEnbWindow_1 [2] 1: IntEnbWindow_1 [1] 0: IntEnbWindow_1 [0] Description Interrupt Enable Window 1 7.3.9 Interrupt Index(IntIndex) R/W Sets registers to be displayed in the IntStatWindow and IntEnbWindow registers. For set value of the IntIndex register, refer to section "7.4 Detailed Description of Set Values of IntIndex Register." Address 08h Register Name IntIndex Bit Symbol 7: IntIndex_0[3] 6: IntIndex_0[2] 5: IntIndex_0[1] 4: IntIndex_0[0] 3:IntIndex_1[3] 2: IntIndex_1[2] 1: IntIndex_1[1] 0: IntIndex_1[0] Description Interrupt Index 0 Interrupt Index 1 BIT7-4 Interrupt Index 0 Set registers to be displayed in IntStatWindow_0 and IntEnbWindow_0. BIT3-0 Interrupt Index 1 Set values to be displayed in IntStatWindow_1 and IntEnbWindow_1. 20 EPSON Rev.1.0 S1R72105 Technical Manual 7.3.10 System Control(SystemCtrl) R/W Sets the system operation. Address 09h Register Name SystemCtrl Bit Symbol Description 7: 0 6: 0 5: 0 4: GoSuspend 3: SendWakeup 2: 0 1: xINTmode 1 0: xINTmode 0 Reserved Reserved Reserved Go Suspend Send Wakeup Reserved xINT Mode 1 xINT Mode 0 BIT4 Go Suspend Setting this bit to HIGH places this IC in the Suspend mode. The clock supplying to internal circuits and external elements does not stop. This bit is used only for enabling USB Resume interrupt. BIT3 Send Wakeup Setting this bit to HIGH restores to the previous state from the Suspend state. BIT1 xINT Mode1 Determines the operation mode of the XINTU signal. 0: Outputs LOW when asserting interrupt and HIGH when negating it. 1: Outputs LOW when asserting interrupt and becomes "Hi-Z" condition when negating it. BIT0 xINT Mode0 Determines the operation mode of the XINTS signal. 0: Outputs LOW when asserting interrupt and HIGH when negating it. 1: Outputs LOW when asserting interrupt and becomes "Hi-Z" condition when negating it. 7.3.11 USB Common(USBCommon) R/W Sets operation of the USB interface. Address 0Ah Register Name USBCommont Bit Symbol 7: VBUS 6: 0 5: 0 4: 0 3: 0 2: IgnrTglMis 1: EnPullUp 0: ActiveUSB Description VBUS Reserved Reserved Reserved Reserved Ignore Toggle Mismatch Enable Pull Up Active USB Interface BIT7 VBUS Shows the state of the VBUS signal. 0: Disconnected state (VBUS = LOW) 1: Connected state (VBUS = HIGH) BIT2 IgnrTglMis Sets the operation mode at the time of toggle mismatch in Out transaction. 0: Asserts the OUTransACK status of the relevant endpoint at the time of toggle mismatch. 1: Does not assert the OUTransACK status of the relevant endpoint at the time of toggle mismatch. BIT1 Enable Pull Up The XPUENB pin becomes LOW by setting this bit to HIGH after checking the state of connection of the VBUS signal. Effective when pull up control of the USB bus is performed by XPUENB. Combining 5V input of VBUS and the AND condition of this bit causes the XPUENB pin to become LOW. BIT0 Active USB Interface After resetting, the USB interface ignores all packets until this bit is set. It activates by setting this bit to HIGH after completion of initialization. Rev.1.0 EPSON 21 S1R72105 Technical Manual 7.3.12 Reset (Reset) R/W Resets internal LSI. Each block is reset by writing HIGH to the corresponding bit. Has the same effect as hard reset. Automatically returns to LOW. Address 0Dh Register Name Reset Bit Symbol 7: 0 6: 0 5: 0 4: 0 3: 0 2: PORT 1: SCSI 0: USB Description Reserved Reserved Reserved Reserved Reserved Port Block Soft Reset SCSI Block Soft Reset USB Block Soft Reset 7.3.13 Port DMA Control (PortDMACtrl) R/W Performs transfer operation of the port DMA. Address 10h Register Name PortDMACtrl Bit Symbol 7: DMAmode1 6: DMAmode0 5: 0 4: 0 3: 0 2: 0 1: S_FIFO 0: DTGO Description DMA mode1 DMA mode0 Reserved Reserved Reserved Reserved SCSI FIFO Control DMA Transfer Go BIT7-6 DMA mode1-0 Sets the DMA transfer mode. mode1 mode0 Transfer mode 0 0 Performs DMA transfer between the port and USB 0 1 Performs DMA transfer between the port and SCSI 1 0 Performs DMA transfer between SCSI and USB 1 1 Reserve (Setting disabled) BIT1 SCSI FIFO Control Concurrent setting of this bit and DTGO to HIGH does not cause DMA transfer by hardware. Instead, the CPU transfers while monitoring the state of SCSI-FIFO (31-32H). The CPU must read or write data from or into SCSI-FIFO according to the FULL/EMPTY status of SCSI-FIFO. Alternatively, data may be written into SCSI-FIFO first to write HIGH into this bit and DTGO and to control, using the remaining data and FULL/EMPTY. However, the CPU must not access FIFO in the direction opposite to transfer. This bit is valid only in mode1:0 = 0:1 or 1:0. So use it when only SCSI needs to be transferred. BIT0 DMA Transfer Go Starts DMA transfer. The target transfer is specified by mode1:0 BIT. The direction of transfer is automatically determined from the OUTxIN BIT set in each endpoint for USB or from the command issued for SCSI 22 EPSON Rev.1.0 S1R72105 Technical Manual 7.3.14 Port DMA Size High (PortDMASize_H) R/W Sets the most significant byte of the byte-length (3 bytes) for port DMA transfer. Address 11h Register Name PortDMASize_H Bit Symbol 7: PortDMASize[23] 6: PortDMASize[22] 5: PortDMASize[21] 4: PortDMASize[20] 3: PortDMASize[19] 2: PortDMASize[18] 1: PortDMASize[17] 0: PortDMASize[16] Description Port DMA Size High 7.3.15 Port DMA Size Middle (PortDMASize_M) R/W Sets the second byte of the byte-length (3 bytes) for port DMA transfer. Address 12h Register Name PortDMASize_M Bit Symbol 7: PortDMASize[15] 6: PortDMASize[14] 5: PortDMASize[13] 4: PortDMASize[12] 3: PortDMASize[11] 2: PortDMASize[10] 1: PortDMASize[9] 0: PortDMASize[8] Description Port DMA Size Middle 7.3.16 Port DMA Size Low (PortDMASize_L) R/W Sets the least significant byte of the byte-length (3 bytes) for port DMA transfer. Address 13h Rev.1.0 Register Name PortDMASize_L Bit Symbol 7: PortDMASize[7] 6: PortDMASize[6] 5: PortDMASize[5] 4: PortDMASize[4] 3: PortDMASize[3] 2: PortDMASize[2] 1: PortDMASize[1] 0: PortDMASize[0] Description Port DMA Size Low EPSON 23 S1R72105 Technical Manual 7.3.17 Port Config 0 (PortConfig_0) R/W Sets the operation mode of the IC. Address 14h Register Name PortConfig_0 Bit Symbol 7:ActivePort 6: BUSC 5:PortSlave 4:0 3:PDREQlevel 2:Swap 1:OddStart 0:Bus8 Description Active Port Bus Configuration Port Slave Reserved PDREQ level Swap Port Interface Bus Odd Byte Start Port Interface 8 bit Bus BIT7 Active Port After reset, the port interface is in All Pins Input mode. Setting this bit to HIGH activates the port. BIT6 Bus Configuration Setting this bit to HIGH causes the listing order of DATA BUS of PORT interface in ascending order. PIN No. Bus Configuration 39 40 41 42 43 45 46 47 48 49 52 53 54 55 56 57 LOW PD15 PD0 PD14 PD1 PD13 PD2 PD12 PD3 PD11 PD4 PD10 PD5 PD9 PD6 PD8 PD7 HIGH PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD11 PD12 PD13 PD14 PD15 BIT5 Port Slave Determines the operation mode of the port interface. 0: Master mode (PDREQ = input, XPDACK/XPRD/XPWR = output) 1: Slave mode (PDREQ = output, XPDACK/XPRD/XPWR = input) BIT3 PDREQ level Determines the operation level of the PDREQ signal. 0: Positive logic 1: Negative logic BIT2 Swap Port Interface Bus Swaps higher order 8 bits with the lower ones when the port interface with 16 bits wide is used. 0: Higher order 1 byte data appears in PD[7:0], lower order 1 byte data in PD[15:8]. Lower order 1 byte data is transferred first. 1: Higher order 1 byte data appears in PD[15:8], lower order 1 byte data in PD[7:0]. Higher-order 1 byte data is transferred first. BIT1 Odd Byte Start Setting this bit to HIGH causes the 8 bit-data to be transferred first, which is due to be sent later, because of the SWAP setting when the port interface is used with 16 bits wide. It is effective only for the first one byte only. BIT0 Port Interface 8 bit Bus Sets this bit to HIGH to use the port interface with 8 bits wide. Only the lower 8 bits are valid. Connect the higher 8 bits to GND or HVDD externally. 24 EPSON Rev.1.0 S1R72105 Technical Manual * Operation settings of the port interface The following list shows the operational settings made by the bit setting: 1) Selecting master/slave of the port by PSLV bit PSLV=0 (Master) PSLV=1 (Slave) 2) PDREQ Input XPDACK Output XPRD/XPWR Output Output Input Input Remarks Data input during XPRD Data output during XPWR PortConfig_1 register setting enabled XPRD/XPWR pulse width: Assert40ns Negate40ns Data output during XPRD Data input during XPWR PortConfig_1 register setting disabled XPRD/XPWR pulse width: Assert30ns Negate30ns Selecting operation modes by BUS8/SWAP/ODS bit BUS8=0 BUS8=1 SWAP=0 PD7 to 0 is transferred first. If ODS = 1, PD7 to 0 is discarded when the first one word is transferred, and only PD15 to 8 is transferred. PD7 to 0 is used when the last data to be transferred is not a word but a byte. SWAP=1 PD15 to 8 is transferred first. If ODS = 1, PD15 to 8 is discarded when the first one word is transferred, and only PD7 to 0 is transferred. PD15 to 8 is used when the last data to be transferred is not a word but a byte. Only PD7 to 0 is used for transfer. PD15 to 8 goes into Input mode (connect to GND or HVDD). 7.3.18 Port Config 1 (PortConfig_1) R/W Sets the operation mode of the port interface. Address 15h Register Name PortConfig_1 Bit Symbol 7: AssertPulseWidth[3] 6: AssertPulseWidth[2] 5: AssertPulseWidth[1] 4: AssertPulseWidth[0] 3: NegatePulseWidth[3] 2: NegatePulseWidth[2] 1: NegatePulseWidth[1] 0: NegatePulseWidth[0] Description Assert Pulse Width Negate Pulse Width BIT7-4 Assert Pulse Width Sets the assert pulse width of XPRD/XPWR when the port interface operates in Master mode. The width is the internal operation clock cycle (40 MHz) multiplied by [AssertPulseWidth + 2]. ex. 0000: 2x25ns=50ns 0001: 3x25ns=75ns BIT3-0 Negate Pulse Width Sets the negate pulse width of XPRD/XPWR when the port interface operates in Master mode. The width is the internal operation clock cycle (40 MHz) multiplied by [NegatePulseWidth + 2]. ex. 0000: 2x25ns=50ns 0001: 3x25ns=75ns Rev.1.0 EPSON 25 S1R72105 Technical Manual 7.3.19 USB Index (USBIndex) R/W Set registers to be displayed in USBWindow_0 to USBWindow_7. For details of display by set values of the USBIndex register, refer to section "7.5 Detailed Description of Set Values of USBIndex Register." Address 17h Register Name USBIndex Bit Symbol 7: USBIndex[7] 6: USBIndex[6] 5: USBIndex[5] 4: USBIndex[4] 3: USBIndex[3] 2: USBIndex[2] 1: USBIndex[1] 0: USBIndex[0] Description USB Index 7.3.20 USB Window 0 (USBWindow_0) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section "7.5 Detailed Description of Set Values of USBIndex Register." Address 18h Register Name USBWindow_0 Bit Symbol 7: USBWindow_0[7] 6: USBWindow_0[6] 5: USBWindow_0[5] 4: USBWindow_0[4] 3: USBWindow_0[3] 2: USBWindow_0[2] 1: USBWindow_0[1] 0: USBWindow_0[0] Description USB Window 0 7.3.21 USB Window 1 (USBWindow_1) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section "7.5 Detailed Description of Set Values of USBIndex Register." Address 19h 26 Register Name USBWindow_1 Bit Symbol 7: USBWindow_1[7] 6: USBWindow_1[6] 5: USBWindow_1[5] 4: USBWindow_1[4] 3: USBWindow_1[3] 2: USBWindow_1[2] 1: USBWindow_1[1] 0: USBWindow_1[0] Description USB Window 1 EPSON Rev.1.0 S1R72105 Technical Manual 7.3.22 USB Window 2 (USBWindow_2) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section "7.5 Detailed Description of Set Values of USBIndex Register." Address 1Ah Register Name USBWindow_2 Bit Symbol 7: USBWindow_2[7] 6: USBWindow_2[6] 5: USBWindow_2[5] 4: USBWindow_2[4] 3: USBWindow_2[3] 2: USBWindow_2[2] 1: USBWindow_2[1] 0: USBWindow_2[0] Description USB Window 2 7.3.23 USB Window 3 (USBWindow_3) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section "7.5 Detailed Description of Set Values of USBIndex Register." Address 1Bh Register Name USBWindow_3 Bit Symbol 7: USBWindow_3[7] 6: USBWindow_3[6] 5: USBWindow_3[5] 4: USBWindow_3[4] 3: USBWindow_3[3] 2: USBWindow_3[2] 1: USBWindow_3[1] 0: USBWindow_3[0] Description USB Window 3 7.3.24 USB Window 4 (USBWindow_4) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section "7.5 Detailed Description of Set Values of USBIndex Register." Address 1Ch Rev.1.0 Register Name USBWindow_4 Bit Symbol 7: USBWindow_4[7] 6: USBWindow_4[6] 5: USBWindow_4[5] 4: USBWindow_4[4] 3: USBWindow_4[3] 2: USBWindow_4[2] 1: USBWindow_4[1] 0: USBWindow_4[0] Description USB Window 4 EPSON 27 S1R72105 Technical Manual 7.3.25 USB Window 5 (USBWindow_5) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section "7.5 Detailed Description of Set Values of USBIndex Register." Address 1Dh Register Name USBWindow_5 Bit Symbol 7: USBWindow_5[7] 6: USBWindow_5[6] 5: USBWindow_5[5] 4: USBWindow_5[4] 3: USBWindow_5[3] 2: USBWindow_5[2] 1: USBWindow_5[1] 0: USBWindow_5[0] Description USB Window 5 7.3.26 USB Window 6 (USBWindow_6) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section "7.5 Detailed Description of Set Values of USBIndex Register." Address 1Eh Register Name USBWindow_6 Bit Symbol 7: USBWindow_6[7] 6: USBWindow_6[6] 5: USBWindow_6[5] 4: USBWindow_6[4] 3: USBWindow_6[3] 2: USBWindow_6[2] 1: USBWindow_6[1] 0: USBWindow_6[0] Description USB Window 6 7.3.27 USB Window 7 (USBWindow_7) R/W Displays the USB-related register. The register to be displayed changes according to the value set at USBIndex register (17h). For details of display by set values of the USBIndex register, refer to section "7.5 Detailed Description of Set Values of USBIndex Register." Address 1Fh 28 Register Name USBWindow_7 Bit Symbol 7: USBWindow_7[7] 6: USBWindow_7[6] 5: USBWindow_7[5] 4: USBWindow_7[4] 3: USBWindow_7[3] 2: USBWindow_7[2] 1: USBWindow_7[1] 0: USBWindow_7[0] Description USB Window 7 EPSON Rev.1.0 S1R72105 Technical Manual 7.3.28 Main Interrupt Status SCSI (MAININTS) R/W When the IC causes an SCSI interruption to the CPU, the CPU identifies the interrupt status register responsible for interruption by reading this register first. Following the reading of this register, the CPU reads the interrupt status register corresponding to each bit and performs appropriate interrupt processing by identifying the bit as a source of interruption. Then, it writes the value read to the interrupt status register corresponding to each bit to clear the relevant bit. If GOOD, SABT, or DTCMP bit is a source of interruption, the CPU writes the value read to clear the bits. The register does not need to directly clear any other bits. Address 20h Register Name MAININTS Bit Symbol 7: GOOD 6: SABT 5: EXEC 4: SCSI1 3: SCSI2 2: 1: DTCMP 0: ASCMP Description SCSI COMMAND NORMAL COMPLETE ABORTED SCSI COMMAND EXECUTING SCSI COMMAND SCSI INTERRUPT STATUS 1 SCSI INTERRUPT STATUS 2 DMA TRANSFER COMPLETE AUTO SEQUENCE COMPLETE BIT7 SCSI COMMAND NORMAL COMPLETE When the SCSI control command is terminated normally, this bit becomes HIGH. BIT6 ABORTED SCSI COMMAND When the control command is forced to terminate by issuing Abort command, this bit becomes HIGH. BIT5 EXECUTING SCSI COMMAND This bit is HIGH during execution of the SCSI control command. This bit does not cause an interruption to the CPU. Even when it becomes HIGH no interruption is output. It is used to monitor the state of execution of the SCSI control command. BIT4 SCSI INTERRUPT STATUS 1 This bit becomes HIGH when there is any factor responsible for an interruption related to the SCSI interface shown in the SCSIINT1 register. BIT3 DMA INTERRUPT STATUS 2 This bit becomes HIGH when there is any factor responsible for interruption related to the SCSI interface shown in the SCSIINT2 register. BIT1 DMA TRANSFER COMPLETE This bit becomes HIGH when DMA data transfer activated by the DMACTL register is completed. It also becomes HIGH when the transfer is forced to terminate by writing "0" into the DTGO bit of the DMACTL register. After setting the DTGO bit of the DMACTL register, this bit becomes HIGH when a command is aborted by the Abort_SCSI command or when a command in the course of execution is aborted by the ATN assertion, because DMA terminates. At times other than mode1:0="00" of the PortDMACtrl register, XINTU is set by this factor. When mode1:0="00", XINTS is not set by this factor. * This bit has the same meaning as that of BIT(PortDMACmp) of MAINT(00h). registers. It can be cleared by using any of the BIT0 AUTO SEQUENCE COMPLETE This bit becomes HIGH when AUTO1 or AUTO2 bit of the SCSIMODE0 register is set and the specified command is terminated. Rev.1.0 EPSON 29 S1R72105 Technical Manual 7.3.29 SCSI Interrupt Status 1 (SCSIINT1) R/W Shows the result of executing the SCSI control command. The CPU identifies the source of interruption by reading this register after receiving the interrupt signal. It clears the bit by writing the value read again. Address 21h Register Name SCSIINT1 Bit Symbol 7: SPERR 6: IDERR 5: SELTO 4: SATN 3: BFREE 2: ILPHS 1: SCSEL 0: WOATN Description SCSI DATA PARITY ERROR DETECTED ID ERROR DETECTED SELECTION TIME OUT SCSI ATN ASSERTION DETECTED BUS FREE DETECTED ILLEGAL PHASE CHANGE DETECTED SCAM SELECTED SELECTED WITHOUT ATTENTION BIT7 SCSI DATA PARITY ERROR DETECTED This bit becomes HIGH when a parity error is detected on the SCSI data bus. BIT6 ID ERROR DETECTED This bit becomes HIGH when an error related to the ID bit is detected during the selection or reselection phase. The errors related to the ID bit are as described below: Only one ID bit is asserted, or Three or more ID bits are asserted. BIT5 SELECTION TIME OUT This bit becomes HIGH when time-out is detected during the selection or reselection phase. BIT4 SCSI ATN ASSERTION DETECTED This bit becomes HIGH when SCSI ATN is asserted. It is not set, however, in the regular sequence of assertion of SCSI ATN. In other words, this bit is not set in the message-out phase immediately following selection. BIT3 BUS FREE DETECTED This bit becomes HIGH when the bus-free phase is detected during execution of the SCSI control command. BIT2 ILLEGAL PHASE CHANGE DETECTED This bit becomes HIGH when unexpected phase transition is detected during execution of the SCSI control command. It is valid only in Initiator mode. BIT1 SCAM SELECTED This bit becomes HIGH when the SCAM selection is responded to. BIT0 SELECTED WITHOUT ATTENTION This bit becomes HIGH when the selection, which is not asserted ATTENTION, is responded to. Execution of the SCSI control command continues, even when this bit is set. If a command block is received continuously, however, the first byte of SCSI-FIFO has the command code. 30 EPSON Rev.1.0 S1R72105 Technical Manual 7.3.30 SCSI Interrupt Status 2 (SCSIINT2) R/W Shows the result of executing the SCSI control command. The CPU identifies the source of interruption by reading this register after receiving the interrupt signal. It clears the bit by writing the value read again. Address 22h Register Name SCSIINT2 Bit Symbol 7: 6: SRST 5: OFERR 4: UNDEF 3: CMDER 2: RESEL 1: SEL 0: LARBT Description SCSI RST ASSERTION DETECTED OFFSET ERROR IN SYNCHRONOUS TRANSFER UNDEFIND GROUP COMMAND COMMAND ERROR RESELECTED SELECTETD LOST ARBITRATION BIT7 RESERVED BIT6 SCSI RST ASSERTION DETECTED This bit becomes HIGH when SCSI RST is asserted. BIT5 OFFSET ERROR IN SYNCHRONOUS TRANSFER This bit becomes HIGH when an offset error occurs during synchronous transfer. The offset error means that the offset counter is not reset to "0" when transfer ends or that the counter overflows/underflows. BIT4 UNDEFIND GROUP COMMAND This bit becomes HIGH when SCSI command other than group 0, 1, 2, or 5 is received. BIT3 COMMAND ERROR This bit becomes HIGH when other control command is issued during execution of the command, although an undefined SCSI control command is issued. BIT2 RESELECTED This bit becomes HIGH when a re-selection is made from other device during execution of a command other than the SCSI control command that makes a re-selection. BIT1 SELECTED This bit becomes HIGH when selected from other device during execution of a command other than SCSI control command that makes a selection. BIT0 LOST ARBITRATION This bit becomes HIGH when defeated in the arbitration phase. When this bit is HIGH and it is not selected or re-selected by other device, the IC suspends operation of the control commands. Rev.1.0 EPSON 31 S1R72105 Technical Manual 7.3.31 SCSI Mode Select0 (SCSIMODE0) R/W Sets operation related to the SCSI interface. Address 29h Register Name SCSIMODE0 Bit Symbol 7: 6: 5: 4: ULTRA 3: AUTO1 2: AUTO2 1: AN_C 0: AN_D Description ULTRA SCSI AUTO1 (auto status) AUTO2 (status message stop) ACTIVE NEGATION CONTROL ACTIVE NEGATION DATA BIT4 ULTRA SCSI When this bit is HIGH, the ULTRA-SCSI transfer is enabled. It is valid only when the RATE bit of the SYNCMODE register is set at "0" or "1". BIT3 AUTO1 (auto status) Automatically executes STS_MSGBusfreeWait_SEL_CMD after executing the DMA_DATA_IN/OUT command. At the end of execution, ASCMP interrupt occurs. The bit setting is also valid in FIFO-DMA mode. BIT2 AUTO2 (status message stop) Executes automatically STS_MSG after executing the DMA_DATA_IN/OUT command. At the end of execution, ASCMP interrupt occurs. The bit setting is also valid in FIFO-DMA mode. *AUTO: During execution of AUTO1 or 2, the AUTO bit of the SCSIMODE1 register is assumed to be "1". The EXEC bit also becomes "1" during execution of AUTO1 or 2. Since the internal sequencer writes the command into the SCSI block in place of the CPU, the COMMAND register can read the command value in process of execution at that time. BIT1 ACTIVE NEGATION CONTROL When this bit is HIGH it enables the active negation function of the SCSI XSREQ/XSACK signals. BIT0 ACTIVE NEGATION DATA When this bit is HIGH it enables the active negation function of the SCSI data and parity signals. 32 EPSON Rev.1.0 S1R72105 Technical Manual 7.3.32 SCSI Mode Select1 (SCSIMODE1) R/W Sets operation related to the SCSI interface. Address 2Ah Register Name SCSIMODE1 Bit Symbol 7: STPPE 6: ATNPE 5: STATN 4: AUTO 3: RINH 2: SINH 1: DIRECT 0: SPCEN Description STOP BY PARITY ERROR ATN ASSERT BY PARITY ERROR STOP BY ATN ASSERT AUTO SEND STATUS/MESSAGE RESELECTION INHIBIT SELECTION INHIBIT SCSI DIRECT ACCESS ENABLE SCSI PARITY CHECK ENABLE BIT7 STOP BY PARITY ERROR When this bit is HIGH it suspends the SCSI control command in process of execution if a parity error is detected on the SCSI interface. BIT6 ATN ASSERT BY PARITY ERROR When this bit is HIGH it asserts a target device ATN if a parity error is detected on the SCSI interface. Any setting of this bit becomes invalid when the SCSI parity check is disabled. This bit is valid only in Initiator mode. BIT5 STOP BY ATN ASSERT When this bit is HIGH it suspends the SCSI control command in process of execution if assertion of ATN is detected. This bit is valid only in Target mode. BIT4 AUTO SEND STATUS/MESSAGE When this bit is HIGH it puts the SCSI control command "Status_Message" into Automatic Transmission mode. In this mode, the FLAG and LINK bits of the SCSI command block which have been received are checked. When the LINK bit is LOW status 00h(GOOD) and message 00h(COMMAND COMPLETE) are automatically sent. When the LINK bit is LOW status 10h(INTERMEDIATE GOOD) and message 0Ah(LINKED COMMAND COMPLETE) are automatically sent. When both LINK bit and FLAG bit are HIGH status 10h(INTERMEDIATE GOOD) and message 0Bh(LINKED COMMAND COMPLETE WITH FLAG) are automatically sent. BIT3 RESELECTION INHIBIT When this bit is HIGH it disables response to re-selection. BIT2 SELECTION INHIBIT When this bit is HIGH it disables response to selection. BIT1 SCSI DIRECT ACCESS ENABLE When this bit is set to HIGH SCSI signal lines of this bit can be directly controlled from the CPU by using the SCSI data register and SCSI control register. The status of the signal lines can always be monitored regardless of the status of this bit. BIT0 SCSI PARITY CHECK ENABLE When this bit is HIGH parity check of the SCSI data bus is performed during the selection phase (when it is selected) and when data from SCSI is input. Rev.1.0 EPSON 33 S1R72105 Technical Manual 7.3.33 SCSI Control (SCSICTL) R/W This register is accessed when the CPU directly controls SCSI signal lines. For such direct control, DIRECT (bit 1) must be set in the mode setting register (0Ah). The status of each signal is stored as "active high". Address 2Bh Register Name SCSICTL Bit Symbol 7: ACK 6: ATN 5: SEL 4: BSY 3: REQ 2: MSG 1: I/O 0: C/D Description SCSI ACK SCSI ATN SCSI SEL SCSI BSY SCSI REQ SCSI MSG SCSI I/O SCSI C/D 7.3.34 SCSI Data (SCSIDATA) R/W This register is accessed when the CPU directly controls the SCSI data bus. For such direct control, DIRECT (bit 1) must be set in the mode setting register (0Ah). The status of each signal is stored as "active high". The DIRECT setting does not determine whether the parity bit is output or not. It is output if it has been output before setting DIRECT, or it is not otherwise. Address 2Ch 34 Register Name SCSIDATA Bit Symbol 7: DB7 6: DB6 5: DB5 4: DB4 3: DB3 2: DB2 1: DB1 0: DB0 Description SCSIDATA EPSON Rev.1.0 S1R72105 Technical Manual 7.3.35 Synchronize Transfer Mode (SYNCMODE) R/W Sets the transfer rate and offset for SCSI synchronous transfer. Address 2Dh RATE3-0 Register Name SYNCMODE ASSERT Bit Symbol 7: RATE3 6: RATE2 5: RATE1 4: RATE0 3: OFF3 2: OFF2 1: OFF1 0: OFF0 NEGATE Description SYNCHRONOUS TRANSFER RATE[3] SYNCHRONOUS TRANSFER RATE[2] SYNCHRONOUS TRANSFER RATE[1] SYNCHRONOUS TRANSFER RATE[0] SYNCHRONOUS OFFSET[3] SYNCHRONOUS OFFSET[2] SYNCHRONOUS OFFSET[1] SYNCHRONOUS OFFSET[0] PERIOD OFF3-0 OFFSET 0000 1T(1T) 1T(1T) 2T 0000 Asynchronous Note 2 0001 2T(1T) 1T(2T) 3T 0001 1 0010 2T 2T 4T 0010 2 0011 3T 2T 5T 0011 3 0100 3T 3T 6T 0100 4 0101 4T 3T 7T 0101 5 0110 4T 4T 8T 0110 6 0111 5T 4T 9T 0111 7 1000 5T 5T 10T 1000 8 1001 6T 5T 11T 1001 9 1010 6T 6T 12T 1010 10 1011 7T 6T 13T 1011 11 1100 7T 7T 14T 1100 12 1101 8T 7T 15T 1101 13 1110 8T 8T 16T 1110 14 1111 9T 8T 17T 1111 15 Note 1) T is a cycle double the internal clock (40MHz). Note 2) When the ULTRA bit of the SCSIMODE0 register is set, T has the same cycle as the enclosed value of the internal clock (40MHz) only if the value set for the RATE3 to 0 bit is 1 or less. 7.3.36 SCSI Own ID (OWNID) R/W Sets the SCSI-ID of this IC itself. Address 2Eh Rev.1.0 Register Name OWNID Bit Symbol 7: 6: 5: 4: 3: 2: OID2 1: OID1 0: OID0 Description (MSB) SCSI OWN ID (LSB) EPSON 35 S1R72105 Technical Manual 7.3.37 Source/Destination ID (SDID) R/W Sets both the SCSI-ID of the selector side and the target SCSI-ID when selection is made. Address 2Fh Register Name SDID Bit Symbol 7: 6: SID2 5: SID1 4: SID0 3: 2: DID2 1: DID1 0: DID0 Description SOURCE ID[2] (R/W) SOURCE ID[1] (R/W) SOURCE ID[0] (R/W) DESTINATION ID[2] (R) DESTINATION ID[1] (R) DESTINATION ID[0] (R) In Initiator mode, sets the target SCSI-ID to be selected in DESTINATION ID. When re-selection is received, the target SCSI-ID that makes a re-selection is set in SOURCE ID. In Target mode, sets the initiator SCSI-ID to be re-selected in DESTINATION ID. When selection is received, the initiator SCSI-ID that makes a selection is set in SOURCE ID. 7.3.38 Selection Timeout Counter (SLTIME) R/W Sets time-out delay for selection and re-selection. Address 30h Register Name SLTIME Bit Symbol 7: ST7 6: ST6 5: ST5 4: ST4 3: ST3 2: ST2 1: ST1 0: ST0 Description (MSB) Selection Time out Counter (MSB) The time-out delay value is calculated according to the following formula: Delay value = count value x 215 x T x 2 Where T is an internal clock cycle (40MHz). Detecting time-out causes the following operation of the IC: Suspends output ID bit. Negates XSSEL 4000xTx2 (about 200s) after such suspension and outputs selection time-out interrupt. No time-out is detected when this register is set to "0." 36 EPSON Rev.1.0 S1R72105 Technical Manual 7.3.39 FIFO Control (FIFOCTL) R/W Used for clearing the SCSI-FIFO data and for checking its status. Address 31h Register Name FIFOCTL Bit Symbol 7: 6: 5: 4: 3: 2: FCLR 1: FULL 0: EMPTY Description CLEAR FIFO FIFO FULL FIFO EMPTY BIT7,6,5,4,3 RESERVED BIT2 CLEAR FIFO Setting this bit to HIGH clears data stored in SCSI-FIFO. The bit returns to LOW automatically after clearing. BIT1 FULL When this bit is HIGH it means that SCSI-FIFO is full. In this state, any data written into SCSI-FIFO is ignored. BIT0 EMPTY When this bit is HIGH it means that SCSI-FIFO is empty. In this state, any attempt to read data from SCSI-FIFO results in invalid data read out. 7.3.40 FIFO Data (FIFODATA) R/W This register allows access to SCSI-FIFO from the CPU. Address 32h Register Name FIFODATA Bit Symbol 7: FD7 6: FD6 5: FD5 4: FD4 3: FD3 2: FD2 1: FD1 0: FD0 Description (MSB) SCSI_FIFO data (LSB) 7.3.41 Non DMA Transfer Size (NDMASIZ) R/W This register sets the number of bytes of data transfer in Non-DMA mode. In Read mode, the register allows to read out the size of data yet to be transferred. Address 33h Rev.1.0 Register Name NDMASIZ Bit Symbol 7: NSZ7 6: NSZ6 5: NSZ5 4: NSZ4 3: NSZ3 2: NSZ2 1: NSZ1 0: NSZ0 Description (MSB) Non DMA Transfer Size (LSB) EPSON 37 S1R72105 Technical Manual 7.3.42 SCSI Command (COMMAND) R/W Sets SCSI control commands. Address 34h Register Name COMMAND Bit Symbol 7: CMD7 6: CMD6 5: CMD5 4: CMD4 3: CMD3 2: CMD2 1: CMD1 0: CMD0 Description (MSB) SCSI Command (LSB) For details of each command, refer to section "7.4 SCSI Control Commands." 7.3.43 Test (TEST) R Used for testing an LSI. Basically, writing into this register is inhibited. Address 3Eh Register Name TEST Bit Symbol 7: TM2 6: TM1 5: TM0 4: USEL1 3: USEL0 2: OFST 1: SCBC 0: DMBC Description - 7.3.44 Revision Reg.(REVISION) R Shows the revision No. of the IC. Address 3Fh Register Name REVISION Bit Symbol 7: REV7 6: REV6 5: REV5 4: REV4 3: REV3 2: REV2 1: REV1 0: REV0 Description (MSB) REVISION (LSB) In normal Read mode, the register allows to read out the revision No. of this model. The model name SPC number (72h, 15h) can be read by reading out twice after writing any value. 38 EPSON Rev.1.0 S1R72105 Technical Manual 7.4 Detailed Description of Set Values of INTINDEX Register 7.4.1 Register Showing IntStatWindow_0,1 and IntEnbWindow_0,1 for Set Values of IntIndex Register IntIndex_n 00h 01h 02h 03h 04h 05h 06h 07h *n=0 or 1 IntStatWindow_n EP0IntStat EPaIntStat EPbIntStat EPcIntStat Reserved Reserved Reserved Reserved IntEnbWindow_n EP0IntEnb EPaIntEnb EPbIntEnb EPcIntEnb Reserved Reserved Reserved Reserved 7.4.2 EP {r} (r=0,a,b,c) Interrupt Status (EP {r} IntStat) R/W Shows the interrupt status of each interrupt status register endpoint displayed in IntStatWindow_0,1. Following the reading of this register, the bit of a source of interruption is identified and it is cleared by writing the value read after appropriate interrupt processing. (The relevant bit is cleared by writing HIGH to each bit). IntIndex_n: 0h to 3h Address Register Name 02h,03h EP0IntStat, EPaIntStat, EPbIntStat, EPcIntStat, Bit Symbol 7: INtranACK 6: OUTtranACK 5: INtranErr 4: OUTtranErr 3: INtranNAK 2: OUTtranNAK 1: INtokenRcv 0: OUTtokenRcv Description IN Transaction ACK OUT Transaction ACK IN Transaction Error OUT Transaction Error IN Transaction NAK OUT Transaction NAK IN Token Received OUT Token Received BIT7 IN Transaction ACK This bit becomes HIGH when ACK is received during IN Transaction. BIT6 OUT Transaction Complete This bit becomes HIGH when OUT Transaction is normally completed. BIT5 IN Transaction Error This bit becomes HIGH when IN Transaction ends abnormally. Details can be obtained from the USBTransStatus register (0Bh). BIT4 OUT Transaction Error This bit becomes HIGH when OUT Transaction ends abnormally. Details can be obtained from the USBTransStatus register (0Bh). BIT3 IN Transaction NAK This bit becomes HIGH when NAK is returned during IN Transaction. BIT2 OUT Transaction NAK This bit becomes HIGH when NAK is returned during OUT Transaction. BIT1 IN Token Received This bit becomes HIGH when BIT1 IN Token Received IN Token is received. BIT0 OUT Token Received This bit becomes HIGH when OUT Token is received. Rev.1.0 EPSON 39 S1R72105 Technical Manual 7.4.3 EP {r} (r=0,a,b,c) Interrupt Enable (EP {r} IntEnb) R/W Appears in IntEnbWindow 0,1. This register enables/disables endpoint interruption shown in IntStatWindow_0,1. When the corresponding bit is set to HIGH an interruption to the CPU is enabled. IntIndex_n: 0h to 3h Address Register Name 07h,08h EP0IntStat, EPaIntStat EPbIntStat ,EPcIntStat 40 Bit Symbol 7: EnINtranACK 6: EnOUTtranCmp 5: EnINtranErr 4: EnOUTtranErr 3: EnINtranNAK 2: EnOUTtranNAK 1: EnINtokenRcv 0: EnOUTtokenRcv EPSON Description Enable IN Transaction ACK Enable OUT Transaction Complete Enable IN Transaction Error Enable OUT Transaction Error Enable IN Transaction NAK Enable OUT Transaction NAK Enable IN Token Received Enable OUT Token Received Rev.1.0 S1R72105 Technical Manual 7.5 Detailed Description of Set Values of USBIndex Register 7.5.1 List of Registers Showing USBWindow Register (8 bytes) Corresponding to Set Values of USBIndex Register(17h) USBIndex 00h 01h to 07h 08h 09h Address 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Register Name USBAddress EP0Config_1 EP0InControl EP0OutControl (Reserved) EP0FIFOremain EP0FIFOforCPU EP0FIFOCtrl EPrConfig_0 EPrConfig_1 EPrControl (Reserved) (Reserved) EP{r}FIFOremain EP{r}FIFOforCPU EP{r}FIFOCtrl EP0_SETUP [0] EP0_SETUP [1] EP0_SETUP [2] EP0_SETUP [3] EP0_SETUP [4] EP0_SETUP [5] EP0_SETUP [6] EP0_SETUP [7] FrameNumber_H FrameNumber_L (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) *{r}=a,b,c Rev.1.0 EPSON 41 S1R72105 Technical Manual 7.5.2 Description of Registers by Set Value of USBIndex 7.5.2.1 USB Address (USBAddress) R/W Sets the USB Address. This setting is cleared (set 00h) when the USB BusReset is detected. USBIndex : 00h Address Register Name 18h USBAddress Bit Symbol 7: 0 6: USBAddress[6] 5: USBAddress[5] 4: USBAddress[4] 3: USBAddress[3] 2: USBAddress[2] 1: USBAddress[1] 0: USBAddress[0] Description Reserved USB Address BIT7 RESERVED BIT6-0 Sets the USB Address. This setting is cleared (set 00h) when the USB BusReset is detected. Set the address specified by the host when control transfer of the SetAddress request is completed. 7.5.2.2 EP0 Config 1 (EP0Config_1) R/W Sets operation of the Endpoint 0. USBIndex : 00h Address Register Name 19h EP0Config_1 Bit Symbol 7: OUT x IN 6: 0 5: 0 4: 0 3: MaxPacketSize[3] 2: MaxPacketSize[2] 1: MaxPacketSize[1] 0: MaxPacketSize[0] Description OUT x IN Reserved Reserved Reserved Max Packet Size BIT7 OUT x IN Sets the direction of transfer of Endpoint 0. Set the direction of transfer in data stage by interpreting the request in SETUP stage. After completion of setting of the direction of the data stage, it can be executed by clearing the InForceNAK bit or OutForceNAK bit to LOW in either of the EP0InControl or EP0OutControl register, which controls the direction of data stage. 0: IN direction 1: OUT direction BIT3-0 Max Packet Size Sets MaxPacketSize of Endpoint 0. The list corresponding to these bits is as follows: After setting this field, AllFIFOClr in the EP0FIFOCtrl register must be set to HIGH once. (bit3, bit2, bit1, bit0) 0 0 0 1 : 8 bytes 0 0 1 0 : 16 bytes 0 0 0 0 : 32 bytes 1 0 0 0 : 64 bytes 42 EPSON Rev.1.0 S1R72105 Technical Manual 7.5.2.3 EP0 In Transaction Control (EP0InControl) R/W Sets operation to IN Transaction. USBIndex : 00h Address Register Name 1Ah EP0InControl Bit Symbol 7: InForceNAK 6: InForceSTALL 5: InEnShortPkt 4: 0 3: 0 2: InToggleStat 1: InToggleClr 0: InToggleSet Description IN Transaction Force NAK IN Transaction Force STALL IN Transaction Short Packet Enable Reserved Reserved IN Transaction Toggle Status IN Transaction Toggle Clear IN Transaction Toggle Set BIT7 IN Transaction Force NAK Setting this bit to HIGH returns NAK to IN Transaction. When the RcvEP0SETUP bit of the MainIntStat register is set to HIGH as a result of completing the SETUP stage, this bit is set to HIGH while the RcvEP0SETUP bit is HIGH. Therefore, the RcvEP0SETUP bit must be cleared to LOW to clear this bit to LOW. If the direction of transfer of data stage is IN, the data stage can be executed by clearing this bit to LOW after setting the direction by the OUTxIN bit of the EP0Config_1 register. If the direction of transfer of data stage is OUT, the data stage can be executed by clearing this bit to LOW after the status stage is ready. When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction becomes valid from the next transaction. BIT6 IN Transaction Force STALL When this bit is set to HIGH it becomes valid, taking precedence over the setting of the INForceNAK bit. Setting this bit to HIGH returns STALL to IN Transaction. When the RcvEP0SETUP bit of the MainIntStat register is set to HIGH as a result of completing the SETUP stage, this bit is set to LOW while the RcvEP0SETUP bit is HIGH. Therefore, the RcvEP0SETUP bit must be cleared to LOW to set this bit to HIGH. When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction becomes valid from the next transaction. BIT5 IN Transaction Short Packet Enable Setting this bit to HIGH returns data packet to IN Transaction independent of amount of data of FIFO. When packet transfer is completed after setting this bit to HIGH this bit returns to LOW. BIT2 IN Transaction Toggle Status Shows the state of Toggle Sequence bit during IN Transaction. It is set to 1 when SETUP Token is received. BIT1 IN Transaction Toggle Clear Clears the Toggle Sequence bit during IN Transaction to 0. BIT0 IN Transaction Toggle Set Sets the Toggle Sequence bit during IN Transaction to 1. Rev.1.0 EPSON 43 S1R72105 Technical Manual 7.5.2.4 EP0 OUT Transaction Control (EP0OutControl) R/W Sets operation to OUT Transaction. USBIndex : 00h Address Register Name 1Bh EP0OutControl Bit Symbol 7: OutForceNAK 6: OutForceSTALL 5: 0 4: 0 3: 0 2: OutToggleStat 1: OutToggleClr 0: OutToggleSet Description IN Transaction Force NAK IN Transaction Force STALL Reserved Reserved Reserved IN Transaction Toggle Status IN Transaction Toggle Clear IN Transaction Toggle Set BIT7 OUT Transaction Force NAK Setting this bit to HIGH returns NAK to IN Transaction. When the RcvEP0SETUP bit of the MainIntStat register is set to HIGH as a result of completing the SETUP stage, this bit is set to HIGH while the RcvEP0SETUP bit is HIGH. Therefore, the RcvEP0SETUP bit must be cleared to LOW to clear this bit to LOW. If the direction of transfer of data stage is IN, the data stage can be executed by clearing this bit to LOW after setting the direction by the OUTxIN bit of the EP0Config_1 register. If the direction of transfer of data stage is OUT, the data stage can be executed by clearing this bit to LOW after the status stage is ready. When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction becomes valid from the next transaction. BIT6 OUT Transaction Force STALL When this bit is set to HIGH it becomes valid, taking precedence over the setting of the INForceNAK bit. Setting this bit to HIGH returns STALL to IN Transaction. When the RcvEP0SETUP bit of the MainIntStat register is set to HIGH as a result of completing the SETUP stage, this bit is set to LOW while the RcvEP0SETUP bit is HIGH. Therefore, the RcvEP0SETUP bit must be cleared to LOW to set this bit to HIGH. When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction becomes valid from the next transaction. BIT2 OUT Transaction Toggle Status Shows the state of Toggle Sequence bit during OUT Transaction. It is set to 1 when SETUP Token is received. BIT1 OUT Transaction Toggle Clear Clears the Toggle Sequence bit during IN Transaction to 0. BIT0 OUT Transaction Toggle Set Sets the Toggle Sequence bit during IN Transaction to 1. 44 EPSON Rev.1.0 S1R72105 Technical Manual 7.5.2.5 EP0 FIFO remain Counter (EP0FIFOremain) R Shows the number of bytes of remaining data in FIFO of Endpoint 0. USBIndex : 00h Address Register Name 1Dh EP0FIFOremain Bit Symbol 7: EP0FIFOremainCount[7] 6: EP0FIFOremainCount[6] 5: EP0FIFOremainCount[5] 4: EP0FIFOremainCount[4] 3: EP0FIFOremainCount[3] 2: EP0FIFOremainCount[2] 1: EP0FIFOremainCount[1] 0: EP0FIFOremainCount[0] Description EP0 FIFO remain Counter 7.5.2.6 EP0 FIFO for CPU (EP0FIFOforCPU) R/W This register allows access to FIFO of Endpoint 0 from the CPU. When the EnFiFOwr bit of the EP0FIFOCtrl register is set, writing is enabled, when the EnFIFOrd bit is set, reading is enabled. It should be noted that reading or writing decreases the number of data in FIFO. USBIndex : 00h Address Register Name 1Eh EP0FIFOforCPU Rev.1.0 Bit Symbol 7: EP0FIFOdata[7] 6: EP0FIFOdata[6] 5: EP0FIFOdata[5] 4: EP0FIFOdata[4] 3: EP0FIFOdata[3] 2: EP0FIFOdata[2] 1: EP0FIFOdata[1] 0: EP0FIFOdata[0] EPSON Description EP0 FIFO for CPU 45 S1R72105 Technical Manual 7.5.2.7 EP0 FIFO Control (EP0FIFOCtrl) R/W Checks the status and sets operation of FIFO of Endpoint 0. USBIndex : 00h Address Register Name 1Fh EP0FIFOCtrl Bit Symbol 7: FIFOEmpty 6: FIFOFull 5: FIFOClr 4: ALLFIFOClr 3: 0 2: AutoForceNAK 1: EnFIFOwr 0: EnFIFOrd Description FIFO Empty FIFO Full FIFO Clear ALL FIFO Clear Reserved AutoForceNAK Enable FIFO Write Enable FIFO Read BIT7 FIFO Empty When this bit is HIGH it indicates that FIFO is empty. If a reading operation of FIFO is carried out in this state, invalid data is read out. BIT6 FIFO Full When this bit is HIGH it indicates that FIFO is full. If a writing operation into FIFO is carried out in this state, the data is ignored. BIT5 FIFO Clear Setting this bit to HIGH clears data stored in FIFO. The bit returns to LOW automatically after clearing. BIT4 ALL FIFO Clear Setting this bit to HIGH clears FIFO of all Endpoints. When the MaxPacketSize filed or DoubleBuf bit of each Endpoint is set, be sure to set this bit to HIGH once after completion of setting. The bit returns to LOW automatically after clearing FIFO. BIT2 AutoForceNAK Setting this bit to HIGH sets the InForceNAK bit of the EP0InControl register and the OutForceNAK bit of the EP0OutControl register when transaction is completed normally. BIT1 Enable FIFO Write Setting this bit to HIGH enables writing data into FIFO from the CPU. BIT0 Enable FIFO Read Setting this bit to HIGH enables reading data in FIFO from the CPU. 46 EPSON Rev.1.0 S1R72105 Technical Manual 7.5.2.8 EP {r}(r=a,b,c) Config 0 (EPrConfig_0) R/W Sets operation of Endpoint a, b, and c. USBIndex : 01h to 03h Address Register Name 18h EPrConfig_0 Bit Symbol 7: EndPointNumber[3] 6: EndPointNumber[2] 5: EndPointNumber[1] 4: EndPointNumber[0] 3: OUTxIN 2: 0 1: JoinPortDMA 0: Really Used Description Endpoint Number OUT x IN Reserved Join Port DMA Really Used BIT7-4 Endpoint Number Sets any Endpoint number of 1h to Fh. BIT3 OUT x IN Sets the direction of transfer of Endpoint. 0: IN direction 1: OUT direction BIT1 Join Port DMA Connects the endpoint to the port DMA. Connects the endpoint to the port DMA. The port DMA is connected to the endpoint that last set this bit to HIGH. When there is no endpoint set to HIGH the port DMA is connected to Endpoint c. Immediately after resetting, the JointPortDMA bit becomes LOW at all endpoints. BIT0 Really Used Setting this bit to HIGH allows to use the endpoints. When this bit is LOW it ignores access to the endpoint. Set in accordance with the SetConfiguration request from the host. 7.5.2.9 EP {r}(r=a,b,c) Config 1 (EPrConfig_1) R/W Sets operation of Endpoints a, b, and c. USBIndex : 01h to 03h Address Register Name 19h EPrConfig_1 Bit Symbol 7: DoubleBuf 6: 0 5: 0 4: 0 3: MaxPacketSize[3] 2: MaxPacketSize[2] 1: MaxPacketSize[1] 0: MaxPacketSize[0] Description Double Buffer Reserved Reserved Reserved Max Packet Size BIT7 Double Buffer Setting this bit to HIGH makes FIFO a double buffer, securing the area doubling the value of the size set for MaxPacketSize. BIT3-0 Max Packet Size Sets MaxPacketSize of endpoint. After setting MaxPacketSize and DoubleBuf of all endpoints, be sure to set the ALLFIFOCLR bit to HIGH. The list corresponding to these bits is as follows: (bit3, bit2, bit1, bit0) 0 0 0 0 : Not in active use (no area is reserved) 0 0 0 1 : 8 bytes 0 0 1 0 : 16 bytes 0 1 0 0 : 32 bytes 1 0 0 0 : 64 bytes Rev.1.0 EPSON 47 S1R72105 Technical Manual 7.5.2.10 EP {r}(r=a,b,c) Control (EPrControl) R/W Sets operation for transaction in the direction of the endpoint set in the EPrConfig_0 register. USBIndex : 01h to 03h Address Register Name 1Ah EPrControl Bit Symbol 7: ForceNAK 6: ForceSTALL 5: EnShortPkt 4: 0 3: ToggleMode 2: ToggleStat 1: ToggleClr 0: ToggleSet Description Force NAK Force STALL Short Packet (IN Transaction Only) Reserved Toggle Mode (IN Transaction Only) Toggle Status Toggle Clear Toggle Set BIT7 Force NAK Setting this bit to HIGH returns NAK to transaction. When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction becomes valid from the next transaction. BIT6 Force STALL Setting this bit to HIGH returns STALL to transaction. Setting this bit to HIGH gives a STALL response to transaction. When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction becomes valid from the next transaction. BIT5 Short Packet (IN Transaction Only) Setting this bit to HIGH returns packet to IN Transaction independent of amount of data of FIFO. When packet transfer is completed after setting this bit to HIGH this bit returns to LOW. BIT3 Toggle Mode (IN Transaction Only) Sets the Toggle Mode. 0: Normal Mode 1: Fake Mode BIT2 Toggle Status Shows the Toggle Sequence bit during transaction. Updated when transfer is completed by returning Short Packet for IN Transaction or when ACK is received from the host for OUT Transaction. BIT1 Toggle Clear Sets the Toggle Sequence bit during transaction to 0. BIT0 Toggle Set Sets the Toggle Sequence bit during transaction to 1. 48 EPSON Rev.1.0 S1R72105 Technical Manual 7.5.2.11 EP {r}(r=a,b,c) FIFO remain Counter (EPrFIFOremain) R Shows the number of bytes of remaining data in FIFO of the endpoint. USBIndex : 01h to 03h Address Register Name 1Dh EPrFIFOremain Bit Symbol 7: EPrFIFOremainCount[7] 6: EPrFIFOremainCount[6] 5: EPrFIFOremainCount[5] 4: EPrFIFOremainCount[4] 3: EPrFIFOremainCount[3] 2: EPrFIFOremainCount[2] 1: EPrFIFOremainCount[1] 0: EPrFIFOremainCount[0] Description EPr FIFO remain Counter 7.5.2.12 EPr FIFO for CPU (EPrFIFOforCPU) R/W This register allows access to FIFO of the endpoint from the CPU. When the EnFiFOwr bit of the EP0FIFOCtrl register is set, writing is enabled, when the EnFIFOrd bit is set, reading is enabled. It should be noted that reading or writing causes changes in the number of data in FIFO, as it is similar to access from the USB. USBIndex : 01h to 03h Address Register Name 1Eh EPrFIFOforCPU Rev.1.0 Bit Symbol 7: EPrFIFOdata[7] 6: EPrFIFOdata[6] 5: EPrFIFOdata[5] 4: EPrFIFOdata[4] 3: EPrFIFOdata[3] 2: EPrFIFOdata[2] 1: EPrFIFOdata[1] 0: EPrFIFOdata[0] EPSON Description EPr FIFO for CPU 49 S1R72105 Technical Manual 7.5.2.13 EPr FIFO Control (EPrFIFOCtrl) R/W Checks the status and sets operation of FIFO of the endpoint. USBIndex : 01h to 03h Address Register Name 1Fh EPrFIFOCtrl Bit Symbol 7: FIFOEmpty 6: FIFOFull 5: FIFOClr 4: 0 3: 0 2: AutoForceNAK 1: EnFIFOwr 0: EnFIFOrd Description FIFO Empty FIFO Full FIFO Clear Reserved Reserved AutoForceNAK Enable FIFO Write Enable FIFO Read BIT7 FIFO Empty When this bit is HIGH it indicates that FIFO is empty. If a reading operation of FIFO is carried out in this state, invalid data is read out. BIT6 FIFO Full When this bit is HIGH it indicates that FIFO is full. If a writing operation into FIFO is carried out in this state, the data is ignored. BIT5 FIFO Clear Setting this bit to HIGH clears data stored in FIFO. The bit returns to LOW automatically after clearing. BIT2 AutoForceNAK Setting this bit to HIGH sets the InForceNAK bit of the EP0InControl register and the OutForceNAK bit of the EP0OutControl register when transaction is completed normally. BIT1 Enable FIFO Write Setting this bit to HIGH enables writing data into FIFO from the CPU. BIT0 Enable FIFO Read Setting this bit to HIGH enables reading data in FIFO from the CPU. 7.5.2.14 EP0 SETUP [n](n=0,1,2,3,4,5,6,7) (EP0SETUP[n]) R Displays data received in the SETUP stage. USBIndex : 08h Address Register Name 18h to 1Fh Ep0SETUP[0] Ep0SETUP[7] 50 Bit Symbol 7: Ep0_RcvSETUPdata[7] 6: Ep0_RcvSETUPdata[6] 5: Ep0_RcvSETUPdata[5] 4: Ep0_RcvSETUPdata[4] 3: Ep0_RcvSETUPdata[3] 2: Ep0_RcvSETUPdata[2] 1: Ep0_RcvSETUPdata[1] 0: Ep0_RcvSETUPdata[0] EPSON Description Ep0_RcvSETUPdata Rev.1.0 S1R72105 Technical Manual 7.5.2.15 Frame Number H (FrameNumber_H) R Displays higher order 3 bits in the FrameNumber field of the SOF Packet received. USBIndex : 09h Address Register Name 18h FrameNumber_H Bit Symbol 7: 0 6: 0 5: 0 4: 0 3: 0 2: FrameNumber_[10] 1: FrameNumber_[9] 0: FrameNumber_[8] Description Reserved Reserved Reserved Reserved Reserved Frame Number High 7.5.2.16 Frame Number L (FrameNumber_L) R Displays lower order 8 bits in the FrameNumber field of the SOF Packet received. USBIndex : 09h Address Register Name 19h FrameNumber_L Rev.1.0 Bit Symbol 7: FrameNumber_[7] 6: FrameNumber_[6] 5: FrameNumber_[5] 4: FrameNumber_[4] 3: FrameNumber_[3] 2: FrameNumber_[2] 1: FrameNumber_[1] 0: FrameNumber_[0] EPSON Description Frame Number Low 51 S1R72105 Technical Manual 7.6 SCSI Control Commands 7.6.1 Control Commands and Command Codes Code 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Command names Summary of commands Reserved SCSI Abort command Abort_SCSI Reserved Assert_RST Busfree SCSI Bus Clear command Reserved Assert_ATN SEL_MSG_clear Select_WithoutATN Select_WithATN_Commannd SelectWithoutATN_Command Wait_Selection_Command Reselection Wait_Reselection Wait_SCAM_Selection_Command SCAM control commands Connection system commands Reserved Negate_ACK Command_Out DMA_Data_Out Non-DMA_Data_Out DMA_Data_In Non-DMA_Data_In Status_In Message_In Message_Out Status_Message Transfer system commands 7.6.2 Description of Each Control Command Abort_SCSI (01H) Aborts the SCSI control command in process of execution. After aborting the process, The SABT bit of the MAININT register is set. The status block is set. It causes an interruption. If this command is issued in the state of not operating, it is ignored. Assert_RST (04H) Asserts the SCSI RST signal (XSRST) for 768 x T x 2 (about 46s), and then negates it. This command releases all the signals it asserts, causing the busfree condition. The inside of the IC is not initialized. It sets the SCSIINT1 SRST bit after negating the RST signal, causing an interruption. When the SCSI control command is being executed, it is forced to terminate. Only RST bit is set, though. When the SCSI DMA command is being executed, the status block is set. Busfree (05H) Executes busfree. The command is valid only in Target mode. If issued in Initiator mode, it is ignored. It is invalid if issued while other SCSI-type command is in execution, causing a command error and a command error interruption. 52 EPSON Rev.1.0 S1R72105 Technical Manual Assert_ATN (07H) Asserts the SCSI ATN signal (XSATN). The command is valid only in Initiator mode. If issued in Target mode, it is ignored. Also, it is not asserted in the busfree condition, however, no error occurs. It causes no interruption after its execution. Any other command being executed continues execution. Negation of ATN occurs in any of the following cases: When the last byte is ACK-negated after the Message_Out command is issued. When busfree is detected. When the Assert_RST command is executed. When chip-reset is done. SEL_MSG_clear (08H) Negates the SCSI SEL/MSG signal (XSSEL/XSMSG). When SCAM is selectted by Wait_SCAM_Selection_Command, the SCAM protocol is processed in Direct mode, with SEL/MSG asserted left inside. This command is used to clear it. After issuing this command, release Direct mode. It causes no interruption after its execution. Any other command being executed continues execution. Select_WithoutATN (09H) Executes selection without asserting the SCSI ATN signal. This command is valid in both disconnected and connected conditions. Issuing this command while any other command in execution causes a command error. After the command is issued, operation of the IC is as follows: Waits until the SCSI bus becomes busfree. Enters arbitration after detecting busfree. If it beats arbitration, it asserts XSSEL and ID bit to data bus, going into the selection phase. It terminates selection and operation when its counterpart asserts XSBSY. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. After that, the IC goes into Initiator mode. Select_WithATN_Command (0AH) Asserts SCSI ATN signal, executes selection, and then executes the message-out command phase. This command is valid in both disconnected and connected condition. Issuing this command while any other command is in execution causes a command error. The CPU sets the message byte number in the NON-DMA data-size register before issuing this command. Then, the CPU write message data in FIFO. After transferring the message, it sets the number of byte of command in the NON-DMA data-size register and writes the command data into FIFO. The IC operates as follows: Waits for busfree. After detecting busfree, enters arbitration. When it beats arbitration, it asserts XSSEL and ID bit and then goes into the selection phase. Asserts XSATN at this time. After selection, it checks message-out at the timing when XSREQ is asserted and transfers messages in FIFO. Negates XSATN after asserting XSREQ and before asserting XSACK at the last byte of the messages. After transferring all the messages, it checks the command phase, detects data accumulated in FIFO, and transfers the command data in FIFO according to the byte number newly set. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. After that, the IC goes into Initiator mode. Note: Be sure to write data into FIFO after setting the number of bytes of transfer. Rev.1.0 EPSON 53 S1R72105 Technical Manual Select_WithoutATN_Command (0BH) Executes selection while SCSI ATN is being negated and continues to execute the command phase. This command is valid in both disconnected and connected condition. Issuing this command while any other command is in execution causes a command error. The CPU issues this command after setting the number of bytes of command in the NON_DMA data-size register. The command data is written into FIFO. The IC operates as follows: Waits for busfree. Enters arbitration after detecting busfree. When it beats arbitration, it asserts XSSEL and ID bit and then goes into the selection phase. After completing selection, it checks the command phase at the timing when XSREQ is asserted and transfers command data from FIFO. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. After that, the IC goes into Initiator mode. Wait_Select_Command (0CH) Waits for the selection phase and executes the command phase after selection. Valid only when it is not connected. Issuing this command in the connected condition sets SCSIINT2 and CMDER bits and causes an interruption. Any other command being executed continues execution. When this command is issued, set STATN(bit5) of the SCSIMODE register and clear it when the command is terminated. After issuing the command, the IC operates as follows: (1) Waits for the selection phase. (2) When selected, checks XSATN. If it is not asserted, the IC operates as mentioned in (5). If it is asserted, the IC sets the message-out phase and receives a message. (3) If the message received is other than "Identify", the IC operates as mentioned in (6) (The CPU checks the message in FIFO and responds to it). (4) When XSATN remains to be asserted after 1-byte message ("Identify") is received, the IC terminates its operation by setting the SATN bit of the SCSIINT1 register and causes an interruption. If XSATN is negated, (5) The command phase is set to receive a command. The IC distinguishes command groups and determines the number of bytes received automatically. (6) It sets the GOOD bit of the MAININT register and causes an interruption. After that, the IC goes into Target mode. Reselect (0DH) Executes the re-selection phase. Valid only when it is not connected. Issuing this command in the connected condition sets the SCSIINT2 and CMDER bits and causes an interruption. Any other command being executed continues execution. The IC operates as follows: Waits for busfree. Enters arbitration after detecting busfree. When it beats arbitration, it asserts the XSSEL, XSIO and ID bits and then goes into the re-selection phase. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. After that, the IC goes into Target mode. 54 EPSON Rev.1.0 S1R72105 Technical Manual Wait_Reselect(0EH) Waits for the re-selection phase. Valid only when it is not connected. Issuing this command in the connected condition sets the SCSIINT2 and CMDER bits and causes an interruption. Any other command being executed continues execution. The IC operates as follows: Enters a state of waiting for re-selection. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. After that, the IC goes into Initiator mode. Wait_SCAM_Selection_Command (0FH) Waits for SCAM selection and causes an interruption after the selection is made. Valid only when it is not connected. Issuing this command in the connected condition sets the SCSIINT2 and CMDER bits and causes an interruption. Any other command being executed continues execution. When issuing this command, set STATN (bit5) of the SCSIMODE register and clear it when the command is terminated. After issuing the command, the IC operates as follows: Waits for the SCAM/normal selection phase. Does not respond to, but ignores the SCSI selection with the selection time-out delay less than 4ms. Responds to the SCAM selection and causes an interruption. If no SCAM selection occurs, the IC responds to the selection which continues for 4ms or longer and after that it operates as in the case of Wait_Select_Command (0Ch). After that, the IC goes into Target mode. Negate_ACK (11H) Clears ACK left asserted by the last message transfer in Initiator mode when the LSI stops operation. Command_Out (12H) Executes the SCSI command phase. Valid only in the connected condition. It can be issued in either Target or Initiator mode. Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption. In Target mode The IC operates as follows: Enters this command into FIFO after setting the number of bytes of command in the NON-DMA data-size register. This control command does not distinguish command groups automatically. It is used for receiving a group command which has undefined command block length. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. The CPU reads a command from FIFO. In Initiator mode The CPU issues this command after setting the number of bytes of the command in the NON-DMA data-size register. Then it writes the command data into FIFO. The IC operates as follows: At the start of execution, negates XSACK if it is asserted. Transfers the command data in FIFO after checking the command phase at the timing of assertion of XSREQ. When FIFO is empty, places the REQ-ACK handshake on hold until data is accumulate in FIFO. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. Rev.1.0 EPSON 55 S1R72105 Technical Manual If any other phase is found when the command phase is checked, the IC sets ILPHS of SCSIINT1 and causes an interruption. Note: Be sure to set the number of bytes of transfer before writing data in FIFO. DMA_Data_Out (13H) Executes the data-out phase that carries out transfer between port and SCSI. Valid only in the connected condition. It can be issued in either Target or Initiator mode. Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption. In Target mode Combining this command issued and the AND condition of the DTGO bit of the DMACTL register causes DMA transfer to be started. When transfer of the count value set in the DTBC register is completed, the command is terminated, the GOOD and DTCMP bits of the MAININT register are set, and an interruption is caused. In Initiator mode At the start of execution, negates XSACK if it is asserted. After the data-out phase is checked at the timing of assertion of XSREQ, the AND condition of the DTGO bit of the DMACTL register causes actual DMA transfer to start. When a transfer of the count value set in the DTBC register is completed, the command is terminated, the GOOD and DTCMP bits of the MAININT register are set, and an interruption is caused. If any other phase is found when the data-out phase is checked, ILPHS of SCSIINT1 is set and an interruption is caused. Non-DMA_Data_Out (14H) Valid only when the command is connected, which executes the data-out phase between SCSI and CPU interface. It can be issued in either Target or Initiator mode. Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption. In Target mode Sets the number of transfer in the NON-DMA data-size register and issues this command. The CPU reads data from FIFO by checking the status of FIFO. The IC operates as follows: Enters data equivalent to the number of bytes set into FIFO after setting the data-out phase. When FIFO is full, the REQ-ACK handshake is held until when there is free space available in FIFO. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. In Initiator mode Sets the number of transfer in the NON-DMA data-size register and issues this command. The CPU writes data into FIFO by checking the status of FIFO. The IC operates as follows: At the start of execution, negates XSACK if it is asserted. Transfers data equivalent to the number of bytes set from FIFO after checking the data-out phase at the timing when XSREQ is asserted. When FIFO is empty, the REQ-ACK handshake is put on hold until when data is accumulated in FIFO. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. Note: Be sure to set the number of bytes of transfer before writing data into FIFO. 56 EPSON Rev.1.0 S1R72105 Technical Manual DMA_Data_In (15H) Executes the data-in phase between SCSI and buffer. Valid only in the connected condition. It can be issued in either Target or Initiator mode. Issuing in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption. In Target mode Combining this command issued and the AND condition of the DTGO bit of the DMACTL register causes DMA transfer to be started. When transfer equivalent to the count value set in the DTBC register is completed, the command is terminated, the GOOD and DTCMP bits of the MAININT register are set, and an interruption is caused. In Initiator mode At the start of execution, negates XSACK if it is asserted. After the data-out phase is checked at the timing of assertion of XSREQ, the AND condition of the DTGO bit of the DMACTL register causes actual DMA transfer to start. When a transfer equivalent to the count value set in the DTBC register is completed, the command is terminated, the GOOD and DTCMP bits of the MAININT register are set, and an interruption is caused. If any other phase is found when the data-in phase is checked, the IC sets ILPHS of SCSIINT1 and causes an interruption. Non-DMA_Data_In (16H) Valid only when the command is connected, which executes the data-in phase between SCSI and CPU interface. It can be issued in either Target or Initiator mode. Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption. In Target mode Sets the number of transfer in the NON-DMA data-size register and issues this command. The CPU writes data into FIFO by check the status of FIFO. The IC operates as follows: Outputs data equivalent to the number of bytes set from FIFO after setting the data-in phase. When FIFO is empty, the REQ-ACK handshake is put on hold until when data is accumulated in FIFO. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. Note: Be sure to set the number of bytes of transfer before writing data into FIFO. In Initiator mode Sets the number of transfer in the NON-DMA data-size register and issues this command. The CPU reads data from FIFO by checking the status of FIFO. The IC operates as follows: At the start of execution, negates XSACK if it is asserted. Enters data into FIFO after checking the data-in phase at the timing of assertion of XSREQ. When FIFO is full, the REQ-ACK handshake is put on hold until when there is free space available in FIFO. If any other phase is found when the data-in phase is checked, the IC sets ILPHS of SCSIINT1 and causes an interruption. Status_In (17H) Executes the status phase. Valid only in the connected condition. It can be issued in either Target or Initiator mode. Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption. Rev.1.0 EPSON 57 S1R72105 Technical Manual In Target mode The CPU issues this command after writing the status byte into SCSI FIFO. The IC transfers the status in FIFO after setting the status phase. It sets the GOOD bit of MAININT register and causes an interruption. In Initiator mode At the start of execution, negates XSACK if it is asserted. Enters 1-byte status into SCSI FIFO after checking the status phase at the first timing when XSREQ is asserted. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. The CPU checks the interrupt status and reads the status byte from SCSI FIFO if terminated normally. Message_In (18H) Executes the message-in phase. Valid only in the connected condition. It can be issued in either Target or Initiator mode. Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption. In Target mode The CPU sets the number of bytes of the message to be sent in the NON-DMA data-size register and issues this command. It writes messages to be transferred into FIFO. The IC sets the message phase and then sends data equivalent to the number of bytes set in FIFO. When FIFO is empty, the REQ-ACK handshake is put on hold until when data is accumulated in FIFO. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. Note: Be sure to set the number of bytes of transfer before writing data into FIFO. In Initiator mode The CPU sets the number of bytes of the message to be received in the NON-DMA data-size register before issuing this command. The IC operates as follows: At the start of execution, negates XSACK if it is asserted. Enters the message equivalent to the number of bytes into FIFO after checking the message-in phase at the timing when REQ is asserted. When FIFO is full, the REQ-ACK handshake is put on hold until when there is free space available in FIFO. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. Usually, the number of bytes of a message is unknown beforehand. So set the number of transfer to "1" when the command is issued first and then determine the number of bytes to be received from the second byte by checking the message code received. Message_Out (19H) Executes the message-out phase. Valid only in the connected condition. It can be issued in either Target or Initiator mode. Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption. In Target mode The CPU sets the number of bytes of the message to be received in the NON-DMA data-size register before issuing this command. After setting the message-out phase, the IC enters the message equivalent to the number of bytes set into FIFO. When FIFO becomes full, the REQ-ACK handshake put on hold until when the CPU reads out the message from FIFO to make some space available in it. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. Usually, the number of bytes of a message is unknown beforehand. So set the number of transfer to "1" when 58 EPSON Rev.1.0 S1R72105 Technical Manual the command is issued first and then determine the number of bytes to be received from the second byte by checking the message code received. In Initiator mode The CPU sets the number of bytes of a message to be sent in the NON-DMA data-size register before issuing this command. The CPU writes the message to be transferred into FIFO. The IC operates as follows: Asserts XSATN. At the start of execution, negates XSACK if it is asserted. Sends data in FIFO after checking the message phase at the timing when XSREQ is asserted. When FIFO is empty, the REQ-ACK handshake is put on hold until when data is accumulated in FIFO. Negates XSATN after sending the number of bytes to be transferred. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. Note: Be sure to set the number of bytes of transfer before writing data into FIFO. Status_Message (1AH) Executes the message-in phase after executing the status phase. Valid only in the connected condition. It can be issued in either Target or Initiator mode. Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption. In Target mode Writes the status and message to be sent into FIFO and issues this command. The status and message may be written after issuing the command. The IC operates as follows: Sets the status phase, fetches 1-byte status byte from FIFO, and transfers it. Sets the message-in phase, fetches 1-byte message byte from FIFO and transfers it. When FIFO is empty, the REQ-ACK handshake is put on hold until data is accumulated in FIFO. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. In Initiator mode When this command is issued, 1 byte each of status and message is fetched into FIFO. The CPU reads 1-byte status byte and then 1-byte message byte from FIFO. The IC operates as follows: At the start of execution, negates XSACK if it is asserted. Enters the status into FIFO after checking the status phase at the timing of assertion of XSREQ. After receiving the status, it enters the message into FIFO after checking the message-in phase at the timing of assertion of XSREQ. After completion, it sets the GOOD bit of the MAININT register. It causes an interruption. Note: The message length is fixed at one byte. Rev.1.0 EPSON 59 S1R72105 Technical Manual 7.6.3 Command Execution and Change of State The IC goes through the following three states from the viewpoint of execution of SCSI-type commands: Disconnected state (D) Connected state in Initiator mode (I) Connected state in Target mode (T) Changes in these states caused by specific commands are as shown in the figure below: D SELECT*** WAIT_RESELECT WAIT_SCAM_SELECT_COMMAND WAIT_SELECT_COMMAND RESELECT BUSFREE ASSERT_RST I T Change from I to D takes place implicitly except that by the Assert_RST command. It means that there is no command that causes such change explicitly. If busfree is found when the next connection-type command is issued, it is assumed to be the disconnected state and the command is executed. If busfree is not found, the disconnected state is waited for and the connection-related command is put on hold. The connection-type command can be executed in the disconnected state. It may be issued in such state. If it is issued while the SCSI control command is being executed, however, a command error occurs. A transfer-type command can be executed in the connected state. If it is issued in the disconnected state, a command error occurs. Both connection- and transfer-type commands can be executed when the IC is in the condition where no SCSI control command is being executed. If they are issued while SCSI control command is in execution, a command error occurs. 7.7 Others and Cautions in Operation Operation responding to the selection without the SCSI-1 arbitration phase The IC operates as mentioned below in response to the selection of only target ID of SCSI-1. Note that there occurs no (automatic) transition to the message or command phase after selection, as in the usual cases after the Wait_selection command. (1) If only a target ID is selected after the Wait_select_cmd command is issued, an IDERR interrupt occurs and the command is terminated. The inside is in the condition where connection is complete, though. So message_out/command_out and other commands can be issued, as in the usual case the selection is made with an initiator/target ID (except that message_out/command_out is not executed automatically). (2) If an ID of 3 bits or more is selected, an IDERR interrupt occurs. This distinguishes whether selection of 1 bit is completed or IDERR with an ID of 3 bits or more is selected. If 1 bit is selected, IDERR and SEL interrupts occur. If ATN is not asserted here, a WOATN interrupt occurs at the same time. * The firm is asked to check that the SCSI-1 selection has occurred by observing the SEL interrupt at the same time when an IDERR interrupt occurs. Also, issue message_out/command_out manually while observing the state of WOATN interrupt, because IDERR terminates the Wait_selection command. 60 EPSON Rev.1.0 S1R72105 Technical Manual Parity error in the SCSI data phase or command stop operation by detecting ATN The following points should be noted when the port interface is used as slave: If a setting has been made that a parity error or detection of ATN in SCSI data phase stops the operation of a command (STATN/STPPE/SPCEN bit of SCSIMODE register), the occurrence of such factor and subsequent command stop causes negation of PDREQ being output to the port interface at the internal timing of the IC. Accordingly, use such setting after checking that it causes no problem in handshake on the LSI side connected to the IC. In such a case, no problem occurs in the internal sequence of the IC if XPDACK or XPRD/XPWR may come from the port side. Though, data transfer to and from FIFO may be obstructed depending on timing (The data may not be written in or read from FIFO). In such a case, FIFO terminates in uncompleted manner, so it requires clearing before going to the status phase. Rev.1.0 EPSON 61 S1R72105 Technical Manual 8. ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Output current/pins (SCSI output pins) Output current/pins (Other than SCSI output pins) Storage temperature 8.2 Ratings -0.3 to +6.0 -0.3 to +4.6 -0.3 to HVDD +0.5 -0.3 to LVDD +0.5 -0.3 to HVDD +0.5 -0.3 to LVDD +0.5 50 IOUT2 30 mA Tstg -65 to +150 C Recommended Operating Conditions Item Supply voltage Input voltage Operating temperature Input signal rise time Normal input Input signal fall time Normal input Input signal rise time Schmitt input Input signal fall time Schmitt input 8.3 VSS = 0[V] Unit V V V V V V mA Symbol HVDD LVDD HVIN LVIN HVOUT LVOUT IOUT1 Symbol HVDD LVDD HVIN LVIN Topr VSS = 0[V] Unit V tri Min. 4.50 3.00 VSS VSS 0 - Typ. 5.00 3.30 25 - Max. 5.50 3.60 HVDD LVDD 70 50 tfi - - 50 ns tri - - 5 ms tfi - - 5 ms V V C ns DC Characteristics (1) I/O characteristics in the DC condition(Ta = 0 to 70C, VSS=0V) Item Static current Input leak current Input pins capacitance Output pins capacitance Input/output pins capacitance 62 Symbol Conditions HIDDS HVDD=5.0V10% LIDDS LVDD=3.3V0.3V ILI HVDD=5.5V LVDD=3.6V HVIH=HVDD LVIH=LVDD VIL=VSS CI f=1MHz HVDD=0V CO f=1MHz HVDD=0V CIO f=1MHz HVDD=0V EPSON Min. - Typ. - Max. 80 220 Unit A -1 - 1 A - - 10 pF - - 10 pF - - 10 pF Rev.1.0 S1R72105 Technical Manual (2) TTL input characteristics (Ta = 0 to 70C, VSS=0V) Names of signals covered: AD0 to 5, DB0 to 7, TESTEN, PD0 to 15, XSATN, XSBSY, XSRST, XSMSG, XSSEL, XSCD, XSIO Item HIGH level Input voltage LOW level Input voltage Symbol Conditions Min. Typ. Max. Unit VIH HVDD=5.5V 2.0 - - V VIL2H HVDD=4.5V - - 0.8 V Min. Typ. Max. Unit (3) CMOS input characteristics (Ta = 0 to 70C, VSS = 0V) Names of signals covered: CLKSEL, OSCIN, EXCLK Item HIGH level Input voltage LOW level Input voltage Symbol Conditions VIHIL LVDD=3.6V 1.9 - - V VILIL LVDD=3.0V - - 0.8 V (4) TTL Schmitt input characteristics (Ta = 0 to 70C, VSS = 0V) Names of signals covered: XRESET, XSREQ, XSACK, XSDB0 to 7, XSDBP, XCS, XRD, XWR, XPRD, XPWR, XPDACK, PDREQ Item HIGH level trigger Input voltage LOW level trigger Input voltage Symbol Hysteresis voltage VH VT2+ VT2- Conditions HVDD=5.5V LVDD=3.6V HVDD=4.5V LVDD=3.0V HVDD=5.0V LVDD=3.3V Min. Typ. Max. Unit 1.2 - 2.4 V 0.6 - 1.8 V 0.1 - - V Min. Typ. Max. Unit 1.1 - 1.8 V 1.0 - 1.5 V 0.1 - - V Min. Typ. Max. Unit - - 0.2 V (5) TTL Schmitt input characteristics (USB) (Ta = 0 to 70C, VSS = 0V) Names of signals covered: DP, DM Item HIGH level trigger Input voltage LOW level trigger Input voltage Hysteresis voltage Symbol Conditions VT+ LVDD=3.6V (USB) VTLVDD=3.0V (USB) VH LVDD=3.3V (USB) (6) USB differential input characteristics (Ta = 0 to 70C, VSS = 0V) Names of signals covered: A pair of DP and DM Item Differential input sensitivity Rev.1.0 Symbol VDS Conditions LVDD=3.0V Differential input voltage 0.8 to 2.5V EPSON 63 S1R72105 Technical Manual (7) Characteristics of pull-up and pull-down input (Ta = 0 to 70C, VSS=0V) Names of signals covered: XRESET, TESTEN Item Symbol Pull-up resistor Rpu Pull-down resistor Rpd Conditions VI=0V HVDD=5.0V VI= HVDD HVDD=5.0V Min. Typ. Max. Unit 50 100 200 k 50 100 200 k Min. LVDD -0.4 Typ. Max. Unit - - V - - 0.4 V Min. HVDD -0.4 Typ. Max. Unit - - V - - 0.4 V Min. HVDD -0.4 Typ. Max. Unit - - A - - 0.4 V Min. Typ. Max. Unit (8) Output characteristics (Ta = 0 to 70C, VSS = 0V) (IOL = 2mA ) Names of signals covered: TESTMON, XUSBOE Item HIGH level Output voltage LOW level Output voltage Symbol VOH VOL Conditions LVDD=3.0V IOH=-2mA LVDD=MIN IOL=-2mA (9) Output characteristics (Ta = 0 to 70C,VSS = 0V) (IOL = 3mA ) Names of signals covered: XPDACK, PD0 to 15, DB0 to 7, XPRD, XPWR Item HIGH level Output voltage LOW level Output voltage Symbol VOH VOL Conditions HVDD=5.0V IOH=-1.5mA HVDD=4.5V IOL=3mA (10) Output characteristics (Ta = 0 to 70C, VSS = 0V) (IOL = 6mA ) Names of signals covered: XINTU, XINTS, PDREQ Item HIGH level Output voltage LOW level Output voltage Symbol VOH VOL Conditions HVDD=5.0V IOH=-3mA HVDD=4.5V IOL=6mA (11) Output characteristics (Ta = 0 to 70C, VSS = 0V) (Open drain IOL = 6mA ) Names of signals covered: XPUENB Item OFF-state Leak current LOW level Output voltage Symbol Conditions IOZ HVDD=Max. -1 - 1 A VOL5 HVDD=Min. IOL=6mA - - 0.4 V (12) Output characteristics (Ta = 0 to 70C,VSS = 0V) (Open drain IOL = 48mA ) Names of signals covered: XSATN, XSBSY, XSRST, XSMSG, XSSEL, XSCD, XSIO Item OFF-state Leak current LOW level Output voltage 64 Symbol Conditions Min. Typ. Max. Unit IOZ HVDD=Max. -1 - 1 A VOL5 HVDD=Min. IOL=48mA - - 0.4 V EPSON Rev.1.0 S1R72105 Technical Manual (13) Output characteristics (Ta = 0 to 70C,VSS = 0V) (IOL = 48mA) Names of signals covered: XSDB0 to 7, XSDBP, XSREQ, XSACK Item Symbol Conditions Min. Typ. Max. Unit HVDD=Min. HIGH level *1 V VOH 1.5 Output voltage IOH=-20mA HVDD=Min. LOW level VOL 0.4 V Output voltage IOL=48mA *1: VOH of the active negation cell meets Active negation Current vs. Voltage defined in the American National Standard X3T10/1071D for Information Systems - SCSI-3 Fast20. (14) Output characteristics (Ta = 0 to 70C, VSS = 0V) Names of signals covered: DP, DM Item HIGH level Output voltage LOW level Output voltage 8.4 Symbol VOH VOL Conditions LVDD=Min. IOH=-0.5mA LVDD=Min. IOL=3.0mA Min. Typ. Max. Unit 2.8 - - V - - 0.3 V AC Characteristics Measurement conditions of AC characteristics: Ta = 0 to 70C HVDD = 5V10% VSS = 0V LVDD = 3.3V0.3V DC level to determine input 0.8V to 2.4V Operating clock foscin=20MHz (internal 40/48MHz operation):PLL operation Loading conditions of output pins except SCSI pins Drives load capacitance of 50pF and 1TTL. Load capacitance of SCSI pins Load capacitance = 100pF, pull-up resistance = 110/pull-down resistance = 165 Rev.1.0 EPSON 65 S1R72105 Technical Manual 8.4.1 CPU Interface 8.4.1.1 Register Read Timing XCS AD[4:0] T102 T101 DB[7:0] T105 T106 XRD T103 Symbol T101 T102 Item XCS fall XRD fall AD [4:0] Valid XRD fall XRD rise AD [4:0] Invalid XRD rise XCS rise T104 Min. Typ. Max. Unit 0 - - ns 0 - - ns T103 XRD LOW level pulse width 65 - - ns T104 XRD HIGH level pulse width 45 - - ns T105 XRD fall DB[7:0] output 2 - T106 Normal (Registers other than those below) FIFO area for USB *1 XRD rise DB[7:0] hold 65 ns 120 2 - 15 ns *1: The FIFO area for USB indicates acess to USBWindow_6(1Eh) in case of USBIndex(17h) = 00h to 03h. 66 EPSON Rev.1.0 S1R72105 Technical Manual 8.4.1.2 Register Write Timing XCS AD[4:0] T112 T111 DB[7:0] T115 T116 XWR T113 Symbol T111 T112 T113 T114 Item XCS fall XWR fall AD [4:0] Valid XWR fall XWR rise AD [4:0] Invalid XWR rise XCS rise XWR LOW level pulse width Normal (Registers other than those below) T114 XWR HIGH level FIFO area_A for USB pulse width FIFO area_B for USB Min. Typ. Max. Unit 0 - - ns 0 - - ns 40 - - ns - - ns 45 *1 80 *2 120 T115 DB[7:0] valid XWR rise 10 - - ns T116 XWR rise DB[7:0] hold 0 - - ns *1: When written into FIFO area for USB (see the previous page) and the next access also writes into FIFO area for USB. *2: When written into FIFO area for USB (see the previous page) and the next access reads FIFO area for USB or reads the FIFO full/Empty bit for USB. Rev.1.0 EPSON 67 S1R72105 Technical Manual 8.4.2 SCSI Interface 8.4.2.1 Selection Timing XSBSY(IN) T201 XSSEL T206 T202 T203 T204 XSBSY(OUT) T205 XSDB0-7,P XSATN XSIO Symbol T201 68 Specification XSBSY(IN) - XSBSY(OUT) , OWNID valid Min. Typ. Max. Unit 1600 - - ns T202 XSBSY(OUT) - XSSEL 3000 - - ns T203 XSSEL - SELID valid 1500 - - ns T204 SELID valid - XSBSY(OUT) 150 - - ns T205 XSBSY(OUT) - XSBSY(IN) 500 - - ns T206 XSBSY(IN) - XSSEL 250 - - ns EPSON Rev.1.0 S1R72105 Technical Manual 8.4.2.2 Re-selection Timing XSBSY(IN) T213 T207 XSSEL T208 T209 T210 T212 T211 XSBSY(OUT) XSDB0-7,P XSIO Symbol T207 Rev.1.0 Specification XSBSY(IN) - XSBSY(OUT) , OWNID valid Min. Typ. Max. Unit 1600 - - ns T208 XSBSY(OUT) - XSSEL 3000 - - ns T209 XSSEL -SELID valid, XSIO 1500 - - ns T210 SELID valid - XSBSY(OUT) 150 - - ns T211 XSBSY(OUT) - XSBSY(IN) 500 - - ns T212 XSBSY(IN) - XSBSY(OUT) 100 - - ns T213 XSBSY(OUT) - XSSEL 150 - - ns EPSON 69 S1R72105 Technical Manual 8.4.2.3 Timing of Being Selected XSBSY(IN) T215 T216 XSSEL XSBSY(OUT) XSDB0-7,P T214 Symbol 70 Specification T214 SELID valid - XSBSY(IN) T215 XSBSY(IN) - XSBSY(OUT) T216 XSBSY(OUT) - XSSEL Min. Typ. Max. Unit 0 - - ns 800 - - ns 0 - - ns EPSON Rev.1.0 S1R72105 Technical Manual 8.4.2.4 Timing of Being Selected XSBSY(IN) T218 T219 XSSEL T220 XSBSY(OUT) XSDB0-7,P T217 XSIO Symbol Rev.1.0 Specification Min. Typ. Max. Unit 0 - - ns 800 - - ns T217 SELID valid - XSBSY(IN) T218 XSBSY(IN) - XSBSY(OUT) T219 XSBSY(OUT) - XSSEL 0 - - ns T220 XSSEL - XSBSY(OUT) - - 200 ns EPSON 71 S1R72105 Technical Manual 8.4.2.5 XSATN Output Timing T221 XSATN XSREQ T222 XSACK XSDB0-7,P LAST MESSAGE XSMSG XSIO XSCD Symbol 72 Specification Min. Typ. Max. Unit T221 XSREQ - XSATN 25 - - ns T222 XSATN - XSACK 150 - - ns EPSON Rev.1.0 S1R72105 Technical Manual 8.4.2.6 Initiator Asynchronous Data-out Timing (Data output) T224 T226 XSDB0-7,P XSREQ T223 T225 XSACK Symbol Rev.1.0 Specification Min. Typ. Max. Unit T223 XSREQ - XSACK 25 - - ns T224 XSDB valid - XSACK 100 - - ns T225 XSREQ - XSACK 25 - 90 ns T226 XSACK - XSDB invalid 50 - - ns EPSON 73 S1R72105 Technical Manual 8.4.2.7 Initiator Asynchronous Data-in Timing (Data input) T227 T229 XSDB0-7,P T228 XSREQ T230 XSACK Symbol 74 Specification Min. Typ. Max. Unit T227 XSDB valid - XSREQ 30 - - ns T228 XSREQ - XSACK 25 - - ns T229 XSACK - XSDB invalid 0 - - ns T230 XSREQ - XSACK 25 - 90 ns EPSON Rev.1.0 S1R72105 Technical Manual 8.4.2.8 Initiator Synchronous Data-out Timing (Data output) T232 T231 XSDB0-7,P XSACK T233 Symbol Min. Typ. Max. Unit T231 XSDB valid - XSACK 25 - - ns T232 XSACK - XSDB invalid 25 - - ns T233 XSACK - XSACK 25 - - ns T234 XSACK - (NEXT) XSACK 25 - - ns Note: Rev.1.0 Specification T234 Value when RATE3 to 0bit is "0000." The timing of switching data is the same as in the case of XSREQ rise. EPSON 75 S1R72105 Technical Manual 8.4.2.9 Initiator Synchronous Data-in Timing (Data input) T236 T235 XSDB0-7,P XSREQ T237 Symbol 76 Specification T238 Min. Typ. Max. Unit 6.5 - - ns T235 XSDB0-7, P valid - XSREQ T236 XSREQ - XSDB0-7, P invalid 5 - - ns T237 XSREQ - XSREQ 11 - - ns T238 XSREQ - XSREQ 11 - - ns EPSON Rev.1.0 S1R72105 Technical Manual 8.4.2.10 Target Asynchronous Data-in Timing (Data output) T239 T241 XSDB0-7,P T240 XSREQ T242a XSACK T242b Symbol Rev.1.0 Specification Min. Typ. Max. Unit T239 XSDB valid - XSREQ 100 - - ns T240 XSACK - XSREQ 25 - 90 ns T241 XSREQ - XSDB invalid 50 - - ns T242a XSACK - (NEXT) XSREQ 25 - - ns T242b XSREQ - XSREQ 150 - - ns EPSON 77 S1R72105 Technical Manual 8.4.2.11 Target Asynchronous Data-out Timing (Data input) T243 T245 XSDB0-7,P XSREQ T244 T246a XSACK T246b Symbol 78 Specification Min. Typ. Max. Unit T243 XSDB valid - XSACK 30 - - ns T244 XSACK - XSREQ 25 - 90 ns T245 XSREQ - XSDB invalid 0 - - ns T246a XSACK - XSREQ 25 - - ns T246b XSREQ - XSREQ 150 - - ns EPSON Rev.1.0 S1R72105 Technical Manual 8.4.2.12 Target Synchronous Data-in Timing (Data output) T247 T248 XSDB0-7,P XSREQ T249 Symbol Min. Typ. Max. Unit T247 XSDB valid - XSREQ 25 - - ns T248 XSREQ - XSDB invalid 25 - - ns T249 XSREQ - XSREQ 25 - - ns T250 XSREQ - XSREQ 25 - - ns Note: Rev.1.0 Specification T250 Value when RATE3 to 0bit is "0000." The timing of switching data is the same as in the case of XSREQ rise. EPSON 79 S1R72105 Technical Manual 8.4.2.13 Target Synchronous Data-out Timing (Data input) T251 T252 XSDB0-7,P XSACK T253 Symbol 80 Specification T254 Min. Typ. Max. Unit 6.5 - - ns T251 XSDB valid - XSACK T252 XSACK - XSDB invalid 5 - - ns T253 XSACK - XSACK 11 - - ns T254 XSACK - XSACK 11 - - ns EPSON Rev.1.0 S1R72105 Technical Manual 8.4.3 Port Interface 8.4.3.1 DMA Read (PSLV=1: Slave mode) Direction of data transfer Prosessor S1R72105 HOST T303 PDREQ(0) (PRQLV=1) T304 T305 T306 T307 XPDACK(I) XPRD(I) PD15-0(0) T302 T308 T301 T309 XPWR(I) Symbol Specification Min. Typ. Max. XPWR XPDACK T301 5 XPDACK setup time XPDACK XPWR T302 5 XPDACK hold time XPRD PDREQ negate T303 10 37 PDREQ negate delay time XPDACK XPRD T304 0 XPRD setup time XPRD XPRD T305 30 XPRD assert pulse width XPRD XPRD T306 30 XPRD negate pulse width XPRD XPDACK T307 0 XPRD hold time XPRD PD T308 0 25 Data output delay time Note 1 XPRD PD(Hi-Z) T309 6 40 Data bus negate time Note 1 Note 1: Data is output to PD only while both XPDACK and XPRD are asserted. PD is always in Input mode except such time. Rev.1.0 EPSON Unit ns ns ns ns ns ns ns ns ns 81 S1R72105 Technical Manual 8.4.3.2 DMA Write (PSLV=1: Slave mode) Direction of data transfer Prosessor S1R72105 HOST T313 PDREQ(0) (PRQLV=1) T314 T315 T316 T317 XPDACK(I) XPWR(I) T318 PD15-0(I) T312 T311 T319 XPRD(I) Symbol T311 T312 T313 T314 T315 T316 T317 T318 T319 82 Specification XPRD XPDACK XPDACK setup time XPDACK XPRD XPDACK hold time XPWR PDREQ negate PDREQ negate delay time XPDACK XPWR XPWR setup time XPWR XPWR XPWR assert pulse width XPWR XPWR XPWR negate pulse width XPWR XPDACK XPWR hold time PD XPWR Data input delay time XPWR PD Data hold time Min. Typ. Max. Unit 5 - - ns 5 - - ns 10 - 37 ns 0 - - ns 30 - - ns 30 - - ns 0 - - ns 10 - - ns 0 - - ns EPSON Rev.1.0 S1R72105 Technical Manual 8.4.3.3 DMA Write (PSLV=0: Master mode) Direction of data transfer Prosessor S1R72105 T333 HOST T33A PDREQ(I) T335 T334 T336 T337 XPDACK(0) XPWR(0) PD15-0(0) T338 T339 Symbol Specification Min. Typ. Max. XPWR PDREQ negate T333 0 30 PDREQ negate delay time XPDACK XPWR T334 0 5 XPWR setup time XPWR XPWR T335 (AP+2)x25 XPWR assert pulse width XPWR XPWR T336 (NP+2)x25 XPWR negate pulse width XPWR XPDACK T337 0 5 XPWR hold time XPWR PD T338 0 25 Data output delay time Note 1 XPWR PD(Hi-Z) T339 5 40 Data bus negate time Note 1 PDREQ negate XPDACK T33A 5 XPDACK setup time Note 1: Data is output to PD only while both XPDACK and XPWR are asserted. PD is always in Input mode except such time. Rev.1.0 EPSON Unit ns ns ns ns ns ns ns ns 83 S1R72105 Technical Manual 8.4.3.4 DMA Read (PSLV=0: Master mode) Direction of data transfer Prosessor S1R72105 T343 HOST T34A PDREQ(I) T344 T345 T346 T347 XPDACK(0) XPRD(0) T348 PD15-0(I) T349 Symbol T343 T344 T345 T346 T347 T348 T349 T34A 84 Specification XPRD PDREQ negate PDREQ negate delay time XPDACK XPRD XPRD setup time XPRD XPRD XPRD assert pulse width XPRD XPRD XPRD negate pulse width XPRD XPDACK XPRD hold time PD XPRD Data input delay time XPRD PD Data hold time PDREQ negate XPDACK XPDACK setup time Min. Typ. Max. Unit 0 - 30 ns 0 - 5 ns - (AP+2)x25 - ns - (NP+2)x25 - ns 0 - 5 ns 10 - - ns 0 - - ns 5 - - ns EPSON Rev.1.0 S1R72105 Technical Manual 8.4.4 Others 8.4.4.1 OSCIN Input Clock ( ex.40MHz) Note: Maximum input voltage: LVDD T400 T401 1.9V 0.9V T403 Symbol T404 Specification Min. T402 Typ. 25 (1/f) Max. Unit - ns T400 CLK cycle *1 T401 CLK HIGH width *1 T402 CLK LOW width *1 T403 CLK rise time - - 5 ns T404 CLK fall time - - 5 ns 0 10 (1/f)x0.4 10 (1/f)x0.4 - 15 (1/f)x0.6 15 (1/f)x0.6 ns ns *1 T401+402=T400 *1 Specified in the same rate also in any cases other than CLK input = 20MHz. Rev.1.0 EPSON 85 S1R72105 Technical Manual 8.4.4.2 EXCLK Input Clock (48MHz) Note: Maximum input voltage: LVDD T410 T411 1.9V 0.9V T413 Symbol T414 Specification T412 Min. Typ. Max. Unit - 20.83 - ns T410 CLK cycle *1 T411 CLK HIGH width *1 8.33 - 12.5 ns T412 CLK LOW width *1 8.33 - 12.5 ns T413 CLK rise time - - 5 ns T414 CLK fall time - - 5 ns *1 T411+412=T410 86 EPSON Rev.1.0 S1R72105 Technical Manual 8.4.4.3 XRESET Input Pulse Width XRESET T420 Symbol T420 Specification XRESET LOW width Min. Typ. Max. Unit 150 - - ns 8.4.4.4 USB Interface Access Timing Conformity to the USB 1.1 Specification. For the USB1.1 Specification, visit http://www.usb.org/developers/docs.html. Rev.1.0 EPSON 87 S1R72105 Technical Manual 9. EXAMPLES OF CONNECTION (When 20MHz OSC oscillation is used) S1R72105 CPU Interface(5V type) XCS USB Interface XCS XRD XRD VBUS XWR XWR XPUENB AD [5:0] AD [5:0] DP DB [7:0] DB [7:0] DM XINT0 XINTS XINT1 XINTU Use figure 2 XUSBOE PORT Interface(5V type) PD [15:0] PD [15:0] PDREQ PDREQ XPDACK XPDACK XPWR XPWR XPRD XPRD SCSI Interface active terminater XSDB [7:0] EXCLK GND 3.3V CLKSEL DB [7:0] XSDBP DBP XSATN ATN XSBSY BSY XSACK ACK XSRST RST XSMSG MSG XSSEL SEL XSCD C/D XSREQ 100pF REQ XSIO 4.7k I/O VC 3pF XRESET XRESET GND 5V 5pF HVDD OSCIN 3.3V LV DD 1M 20.0MHz VSS 5pF GND TESTEN OSCOUT GND GND open Fig.1. 88 GND TESTMON General View EPSON Rev.1.0 S1R72105 Technical Manual S1R72105 VBUS 0.1F 330k 100k GND GND 3.3V 10k XPUENB 2SA USB Connector Series B Receptacle 5.6k VBUS D+ GND 1SS133 3.3V 1SS133 3.3V 1.5k D- DP 24 GND DM GND GND GND NNCD5.6LG 22pF 22pF 1SS133 1SS133 24 GND GND Fig.2. USB Connection Diagram 1) Connect the VBUS pin to the VBUS pin of the connector by providing chattering prevention circuit. 2) The XPUENB outputs LOW by inputting 5V in VBUS pin and setting the EnPullUp(bit1) bit of the USBCommon register (0Ah). XPUENB is asserted when USB is ready for operation after checking that VBUS is HIGH (5V). 3) How to handle DP and DM pins. Add Zener diode for electrostatic protection onto the connector side. Add 24 resistor for adjusting impedance. Add 22pF condensor for adjusting edge rate. Add a diode onto the pin side to protect from a short in the wiring of the USB cable. Rev.1.0 EPSON 89 S1R72105 Technical Manual 10. EXTERNAL DIMENSIONS DRAWING Plastic QFP15-100 pin 160.4 140.1 75 51 50 76 INDEX 26 100 1 25 0.5 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.50.2 1 90 EPSON Unit:mm Rev.1.0 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS EPSON (CHINA) CO., LTD. 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 23F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 FAX: 64107319 FAX: +1-408-922-0238 SHANGHAI BRANCH SALES OFFICES West 1960 E.Grand Avenue El Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 FAX: +1-310-955-5400 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 FAX: +1-815-455-7633 7F, High-Tech Bldg., 900, Yishan Road, Shanghai, 200233, CHINA Phone: 86-21-5423-5577 FAX: 86-21-5423-4677 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 FAX: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. Northeast 301 Edgewater Place, Suite 120 Wakefield, MA 01880, U.S.A. Phone: +1-781-246-3600 FAX: +1-781-246-5443 10F, No. 287, Nanking East Road, Sec. 3 Taipei Phone: 02-2717-7360 FAX: 02-2712-9164 Telex: 24444 EPSONTB Southeast HSINCHU OFFICE 3010 Royal Blvd. South, Suite 170 Alpharetta, GA 30005, U.S.A. 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EPSON EUROPE ELECTRONICS GmbH HEADQUARTERS No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone: +65-6337-7911 FAX: +65-6334-2716 Riesstrasse 15 80992 Munich, GERMANY Phone: +49-(0)89-14005-0 FAX: +49-(0)89-14005-110 DUSSELDORF BRANCH OFFICE Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone: +49-(0)2171-5045-0 FAX: +49-(0)2171-5045-10 UK & IRELAND BRANCH OFFICE Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone: +44-(0)1344-381700 FAX: +44-(0)1344-381701 SEIKO EPSON CORPORATION KOREA OFFICE 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: 02-784-6027 FAX: 02-767-3677 GUMI OFFICE 6F, Good Morning Securities Bldg., 56 Songjeong-Dong, Gumi-City, Seoul, 730-090, KOREA Phone: 054-454-6027 FAX: 054-454-6093 FRENCH BRANCH OFFICE - JAPAN SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 FAX: +33-(0)1-64862355 IC Marketing Department IC Marketing & Engineering Group BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Testa, Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 FAX: +34-93-544-2491 Scotland Design Center Integration House, The Alba Campus Livingston West Lothian, EH54 7EG, SCOTLAND Phone: +44-1506-605040 FAX: +44-1506-605041 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 FAX: +81-(0)42-587-5624 ED International Marketing Department 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 FAX: +81-(0)42-587-5117 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1R72105 Technical Manual SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epsondevice.com/ First issue October, 2002 Printed in Japan H A