3.0 V to 5.5 V, ±12 kV IEC ESD Protected,
500 kbps/50 Mbps RS-485 Transceivers
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. G Document Feedback
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FEATURES
TIA/EIA RS-485 compliant over full supply range
3.0 V to 5.5 V operating voltage range on VCC
1.62 V to 5.5 V VIO logic supply option available
ESD protection on the bus pins
IEC 61000-4-2 ≥ ±12 kV contact discharge
IEC 61000-4-2 ≥ ±12 kV air discharge
HBM ≥ ±30 kV
Full hot swap support (glitch free power-up/power-down)
High speed 50 Mbps data rate (ADM3065E/ADM3066E/
ADM3067E/ADM3068E)
Low speed 500 kbps data rate for long cables (ADM3061E/
ADM3062E/ADM3063E/ADM3064E)
Full receiver short-circuit, open circuit, and bus idle fail-safe
Extended temperature range up to 125°C
PROFIBUS compliant at VCC ≥ 4.5 V
Half duplex and full duplex models available
Allows connection of up to 128 transceivers onto the bus
Space-saving package options
10-lead, 3 mm × 3 mm LFCSP
8-lead and 10-lead, 3 mm × 3 mm MSOP
8-lead and 14-lead, narrow body SOIC
APPLICATIONS
Industrial fieldbuses
Process control
Building automation
PROFIBUS networks
Motor control servo drives and encoders
FUNCTIONAL BLOCK DIAGRAMS
RO
RE
DE
DI
V
CC
A
B
GND
D
R
ADM3061E/ADM3065E
14666-001
Figure 1. ADM3061E/ADM3065E Functional Block Diagram
RO
RE
DE
DI
V
CC
A
B
GND
D
R
ADM3063E/ADM3067E
Z
Y
14666-103
Figure 2. ADM3063E/ADM3067E Functional Block Diagram
RO
RE
DE
DI
V
CC
A
B
GND
D
R
V
IO
ADM3062E/ADM3066E
LEVEL
TRANSLATOR
14666-002
Figure 3. ADM3062E/ADM3066E Functional Block Diagram
RO
RE
DE
DI
V
CC
A
B
GND
D
R
V
IO
ADM3064E/ADM3068E
LEVEL
TRANSLATOR
Y
Z
14666-104
Figure 4. ADM3064E/ADM3068E Functional Block Diagram
ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. G | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 4
Specifications ..................................................................................... 5
Timing Specifications .................................................................. 7
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 15
Test Circuits ..................................................................................... 19
Theory of Operation ...................................................................... 20
IEC ESD Protected RS-485 ....................................................... 20
High Driver Differential Output Voltage ................................ 20
IEC 61000-4-2 ESD Protection ................................................ 20
Truth Tables................................................................................. 21
Receiver Fail-Safe ....................................................................... 21
Hot Swap Capability................................................................... 21
128 Transceivers on the Bus ...................................................... 21
Driver Output Protection .......................................................... 21
Applications Information .............................................................. 22
Isolated High Speed RS-485 Node ........................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 26
REVISION HISTORY
7/2019—Rev. F to Rev. G
Added ADM3064E ............................................................. Universal
Changes to Features Section and Figure 4 ..................................... 1
Added Table 1; Renumbered Sequentially .................................... 4
Changes to Table 3 ............................................................................ 5
Changes to Figure 5, Figure 6, Figure 7, and Figure 8 ................. 9
Change to Table 6 ........................................................................... 10
Change to Figure 13 Caption ........................................................ 13
Changes to Figure 14 ...................................................................... 14
Changes to Figure 32 Caption ....................................................... 17
Changes to Figure 43 and Figure 44 ............................................. 19
Changes to Ordering Guide .......................................................... 26
6/2019—Rev. E to Rev. F
Added ADM3068E ............................................................. Universal
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Features Section and Figure 4 ..................................... 1
Changes to Table 1 Title ................................................................... 5
Changes to Table 2 ............................................................................ 5
Changes to ADM3061E/ADM3062E/ADM3062E Section and
Table 3 ................................................................................................ 7
Changes to ADM3065E/ADM3066E/ADM3067E/ADM3068E
Section and Table 4 ........................................................................... 8
Changes to Figure 5 and Figure 7 ................................................... 9
Changes to Figure 8 ........................................................................ 10
Added Endnote 1 to Digital Input and Output Voltage (DE, RE,
DI, and RO) Parameter, Table 5 .................................................... 11
Changes to Digital Input and Output Voltage (DE, RE, DI, and
RO) Parameter, Table 5 .................................................................. 11
Changes to Table 8 .......................................................................... 13
Added Figure 14 and Table 10; Renumbered Sequentially ....... 15
Changes to Figure 19 Caption ....................................................... 16
Changes to Figure 43 and Figure 44 ............................................. 20
Changes to Isolated High Speed RS-485 Node Section ............. 24
Changes to Ordering Guide .......................................................... 27
4/2019—Rev. D to Rev. E
Added ADM3063E ............................................................. Universal
Change to Features Section .............................................................. 1
Changes to Figure 3 ........................................................................... 1
Changes to Table 1 ............................................................................. 4
Changes to Table 2 ............................................................................. 5
Added Endnote 1, Table 2; Renumbered Sequentially ................. 5
Change to Table 7 ........................................................................... 11
Changes to Table 8 .......................................................................... 12
Changes to Figure 12 and Table 9................................................. 13
Changes to Figure 14, Figure 15, Figure 16, and Figure 18
Captions ........................................................................................... 14
Changes to Figure 19, Figure 20, Figure 23, and Figure 24
Captions ........................................................................................... 15
Change to Figure 25 Caption ........................................................ 14
Changes to Figure 39 ...................................................................... 18
Changes to IEC ESD Protected RS-485 Section ......................... 19
Change s to Tr uth Tables Section , Table 11, Tabl e 12, and
Receiver Fail-Safe Section ............................................................. 20
Added Table 10; Renumbered Sequentially ................................ 20
Changes to Isolated High Speed RS-485 Node Section and
Figure 47 .......................................................................................... 22
Changes to Ordering Guide ................................................................... 25
3/2019—Rev. C to Rev. D
Added ADM3067E and 14-Lead SOIC_N, R-14 ........... Universal
Changes to Feature Section ...................................................................... 1
Added Figure 3; Renumbered Sequentially .......................................... 1
Moved Table 1 to ........................................................................................ 4
Changes to Table 2 ..................................................................................... 5
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. G | Page 3 of 27
Changes to ADM3065E/ADM3066E/ADM3067E Section .............. 7
Change to Pin 3, Description Column, Table 7 ................................. 11
Changes to Figure 10, Figure 11, and Table 8 ..................................... 12
Added Figure 12 and Table 9; Renumbered Sequentially ................ 13
Changes to Figure 14 ............................................................................... 14
Moved Test Circuits to ............................................................................ 18
Changes to Table 10 and Table 11 ......................................................... 20
Updated Outline Dimensions ............................................................... 26
Changes to Ordering Guide ................................................................... 27
1/2018—Rev. B to Rev. C
Added ADM3062E ............................................................. Universal
Changes to Figure 2 and Table 1 ............................................................. 1
Changes to ADM3061E/ADM3062E Timing Specifications
Section and Figure 3 ................................................................................ 6
Changes to Figure 5 and Figure 6 ........................................................... 7
Changes to Figure 9 and Figure 10 ....................................................... 11
Changes to Figure 16 and Figure 17 ..................................................... 12
Changes to Figure 44 ............................................................................... 21
Changes to Figure 45 ............................................................................... 22
Changes to Ordering Guide ................................................................... 25
12/2017—Rev. A to Rev. B
Added ADM3061E ............................................................. Universal
Changes to Product Title, Features Section, Figure 1, and Table 1... 1
Changes to General Description Section ....................................... 3
Changes to Table 2 ............................................................................ 4
Added ADM3061E Timing Specification Section and Table 3;
Renumbered Sequentially ................................................................ 6
Moved Figure 3 .................................................................................. 6
Moved Figure 4, Figure 5, and Figure 6 .......................................... 7
Changes to ADM3065E/ADM3066E Timing Specification
Section Title ....................................................................................... 8
Added 10-Lead MSOP Parameter and 10-Lead LFCSP Parameter,
Table 5 .................................................................................................. 9
Changes to Operating Temperature Range Parameter, Table 5
and Table 6 ......................................................................................... 9
Changes to Figure 7, Figure 8, and Table 7 ..................................... 10
Changes to Table 8 .......................................................................... 11
Changes to Figure 11 ...................................................................... 12
Added Figure 23; Renumbered Sequentially ............................... 13
Added Figure 24, Figure 25, Figure 26, Figure 27, and Figure 28 ... 14
Changed High Speed IEC ESD Protected RS-485 Section to IEC
ESD Protected RS-485 Section .............................................................. 17
Changes to IEC ESD Protected RS-485 Section ................................ 17
Added Endnote 4, Table 9 ...................................................................... 18
Changes to Table 10 ................................................................................. 18
Changes to Figure 44 ............................................................................... 21
Changes to Figure 45 ............................................................................... 22
Changes to Ordering Guide ........................................................... 25
5/2017—Rev. 0 to Rev. A
Added ADM3066E............................................................. Universal
Changes to Features Section, Figure 1, and Table 1 ...................... 1
Added Figure 2; Renumbered Sequentially ................................... 1
Moved General Description Section .............................................. 3
Changes to General Description Section ....................................... 3
Changes to Specifications Section and Table 2 ............................. 4
Changes to Timing Specifications Section and Figure 3 ............. 5
Changes to Figure 4, Figure 5, and Figure 6 .................................. 6
Added VIO to GND Parameter, Table 4 .......................................... 7
Changes to Thermal Resistance Section and Table 5 ................... 7
Added Figure 8 .................................................................................. 8
Changes to Table 6 ............................................................................ 8
Added Figure 9 and Figure 10 ......................................................... 9
Added Table 7; Renumbered Sequentially ..................................... 9
Changes to Figure 14, Figure 16, and Figure 17 .......................... 10
Changes to Table 8 and Table 9 ..................................................... 15
Added Figure 42 and Figure 43 ..................................................... 20
Changes to Ordering Guide ........................................................... 21
3/2017—Revision 0: Initial Version
ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. G | Page 4 of 27
GENERAL DESCRIPTION
The ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E are 3.0 V to
5.5 V, IEC electrostatic discharge (ESD) protected RS-485
transceivers, allowing the devices to withstand ±12 kV contact
discharges on the transceiver bus pins without latch-up or
damage. The ADM3062E/ADM3064E/ADM3066E/ADM3068E
feature a VIO logic supply pin that allows a flexible digital interface
capable of operating as low as 1.62 V.
The ADM3065E/ADM3066E/ADM3067E/ADM3068E are
suitable for high speed, 50 Mbps, bidirectional data commu-
nication on multipoint bus transmission lines. The ADM3061E/
ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/
ADM3067E/ADM3068E feature a 1/4 unit load input
impedance that allows up to 128 transceivers on a bus. The
ADM3061E/ADM3062E/ADM3063E/ADM3064E models offer
all of the same features as the ADM3065E/ADM3066E/
ADM3067E/ADM3068E models at a low 500 kbps data rate that
is suitable for operation over long cable runs.
The ADM3061E/ADM3062E/ADM3065E/ADM3066E are half-
duplex RS-485 transceivers, fully compliant to the PROFIBUS®
standard with increased 2.1 V bus differential voltage at VCC
4.5 V. The ADM3063E/ADM3064E/ADM3067E/ADM3068E
are full duplex RS-485 transceiver options.
The RS-485 transceivers are available in a number of space-
saving packages, including the 10-lead, 3 mm × 3 mm lead frame
chip-scale package (LFCSP), the 8-lead or 10-lead, 3 mm × 3 mm
mini small outline package (MSOP), and the 8-lead or 14-lead,
narrow body standard small outline packages (SOIC_N).
Models with operating temperature ranges of −40°C to +125°C
and −40°C to +85°C are available.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit. If a
significant temperature increase is detected in the internal driver
circuitry during fault conditions, this feature forces the driver
output into a high impedance state.
The ADM3061E/ADM3062E/ADM3063E/ADM3064E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E guarantee a
logic high receiver output when the receiver inputs are shorted,
open, or connected to a terminated transmission line with all
drivers disabled.
Table 2 presents an overview of the ADM3061E/ADM3062E/
ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/
ADM3068E data rate capability across temperature, power supply,
and package options. Refer to the Ordering Guide section for
model numbering.
Table 1. Generic Description Table
Device No. Duplex Maximum Data Rate VIO Logic Supply Available Temperature Range Packages Available
ADM3061E Half 500 kbps1 No
A grade: −40°C to +85°C
B grade: −40°C to +125°C
8-lead SOIC_N, 8-lead MSOP
ADM3062E Half 500 kbps1 Yes 10-lead MSOP, 10-lead LFCSP
ADM3063E Full 500 kbps1 No 14-lead SOIC_N
ADM3064E Full 500 kbps1 Yes 14-lead SOIC_N
ADM3065E Half 50 Mbps No 8-lead SOIC_N, 8-lead MSOP
ADM3066E Half 50 Mbps Yes 10-lead MSOP, 10-lead LFCSP
ADM3067E Full 50 Mbps No 14-lead SOIC_N
ADM3068E Full 50 Mbps Yes 14-lead SOIC_N
1 Driver outputs are slew rate limited to minimize common-mode emissions over long cable runs.
Table 2. Summary of the ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Operating Conditions—Data Rate Capability Across Temperature, Power Supply, and Package
Maximum Data Rate1 Maximum VCC (V) Maximum Temperature Package Description
50 Mbps 5.5 −40°C to +125°C 10-lead LFCSP
50 Mbps 5.5 −40°C to +105°C 8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, and 14-lead SOIC_N
50 Mbps 3.6 −40°C to +125°C 8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, and 14-lead SOIC_N
500 kbps 5.5 −40°C to +125°C 8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, 10-lead LFCSP, and
14-lead SOIC_N
1 The ADM3065E/ADM3066E/ADM3067E/ADM3068E data input (DI) transmits 50 Mbps (or 500 kbps for the ADM3061E/ADM3062E/ADM3063E/ADM3064E) clock data, and
the ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E driver enable (DE) is enabled for 50% of the DI transmit time.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. G | Page 5 of 27
SPECIFICATIONS
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3064E/ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless
otherwise noted. All typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
No Load Supply Current ICC 3.5 7.5 mA
DE = VIO1, RE = 0 V
3.5 7.5 mA
DE = VIO, RE = VIO
3 4.5 mA
DE = 0 V, RE = 0 V
ADM3065E/ADM3066E/ADM3067E/
ADM3068E Supply Current,
Data Rate = 50 Mbps
ICC 107 172 mA
Load resistance (RL) = 54 Ω, DE = VIO,
RE = 0 V (VCC ≥ 4.5 V)
67 75 mA
RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V)
ADM3061E/ADM3062E/ADM3063E/
ADM3064E Supply Current,
Data Rate = 500 kbps
ICC 100 165 mA
RL = 54 Ω, DE = VIO, RE = 0 V (VCC ≥ 4.5 V)
56 74 mA
RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V)
Supply Current in Shutdown Mode ISHDN 210 450 μA
DE = 0 V, RE = VIO
VIO Shutdown Current2 I
IOSHDN 1 50 μA
DE = 0 V, RE = VIO
DRIVER
Differential Outputs
Output Voltage, Loaded |VOD2| 2.0 2.5 VCC V VCC ≥ 3.0 V, RL = 50 Ω, see Figure 38
|VOD2| 1.5 2.1 VCC V VCC ≥ 3.0 V, RL = 27 Ω (RS-485), see Figure 38
|VOD2| 2.1 3.5 VCC V VCC ≥ 4.5 V, RL = 50 Ω, see Figure 38
|VOD2| 2.1 3 VCC V VCC ≥ 4.5 V, RL = 27 Ω (RS-485), see Figure 38
|VOD3| 1.5 2.1 VCC V
VCC 3.0 V, −7 V ≤ common-mode voltage
(VCM) ≤ +12 V, see Figure 39
|VOD3| 2.1 3 VCC V VCC4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 39
Change in Differential Input Voltage for
Complementary Output States
∆|VOD| 0.2 V RL = 27 Ω or 50 Ω, see Figure 38
Common-Mode Output Voltage VOC 1.6 3.0 V RL = 27 Ω or 50 Ω, see Figure 38
Change in Common-Mode Voltage for
Complementary Output States
∆|VOC| 0.2 V RL = 27 Ω or 50 Ω, see Figure 38
Output Short-Circuit Current IOS −250 +250 mA −7 V < output voltage (VOUT) < +12 V
Output Leakage (Y, Z)3 I
O +100 μA
DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
input voltage (VIN) = 12 V
−100 μA
DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
Logic Inputs (DE, RE, DI)
Input Voltage
Low VIL 0.33 × VIO V DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V
High VIH 0.67 × VIO V
DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V
Input Current II −2 +2 μA
DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V, 0 V ≤ VINVIO
ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. G | Page 6 of 27
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
RECEIVER
Differential Inputs
Differential Input Threshold Voltage VTH −200 −125 −30 mV −7 V < VCM < +12 V
Input Voltage Hysteresis VHYS 30 mV −7 V < VCM < +12 V
Input Current (A, B) II 0.1 0.25 mA DE = 0 V, VCC = powered/unpowered, VIN = 12 V
−0.20 −0.1 mA DE = 0 V, VCC = powered/unpowered, VIN = −7 V
Line Input Resistance RIN 48 96 −7 V ≤ VCM ≤ +12 V
Logic Outputs
Output Voltage
Low VOL 0.4 V
VIO = 3.6 V, output current (IOUT) = 2 mA,
VID4 ≤ −0.2 V
0.4 V VIO = 2.7 V, IOUT = 1 mA, VID ≤ −0.2 V2
0.2 V VIO = 1.95 V, IOUT = +500 μA, VID ≤ −0.2 V2
High VOH 2.4 V VIO = 3.0 V, IOUT = −2 mA, VID ≥ −0.03 V
2.0 V VIO = 2.3 V, IOUT = −1 mA, VID ≥ −0.03 V2
V
IO − 0.2 V VIO = 1.65 V, IOUT = −500 μA, VID ≥ −0.03 V2
Short-Circuit Current 85 mA VOUT = GND or VIO
Three-State Output Leakage IOZR ±2 μA RO pin = 0 V or VIO
1 VIO = VCC for ADM3061E/ADM3063E/ADM3065E/ADM3067E.
2 ADM3062E/ADM3064E/ADM3066E/ADM3068E only.
3 ADM3063E/ADM3064E/ADM3067E/ADM3068E only.
4 VID is the receiver input differential voltage.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. G | Page 7 of 27
TIMING SPECIFICATIONS
ADM3061E/ADM3062E/ADM3063E/ADM3064E
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3064E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All
typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate1 500 kbps
Propagation Delay tDPLH, tDPHL 220 800 ns RLDIFF capacitor = 54 Ω, CL1 capacitor = CL2 capacitor =
100 pF, see Figure 5 and Figure 40
Skew tDSKEW 5 100 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Rise/Fall Times tDR, tDF 120 300 800 ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Enable to Output High tDZH 100 1000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable to Output Low tDZL 100 1000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Disable Time from Low tDLZ 350 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Disable Time from High tDHZ 600 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable Time from Shutdown to High tDZH(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable Time from Shutdown to Low tDZL(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RECEIVER
Maximum Data Rate 500 kbps
Propagation Delay tRPLH, tRPHL 200 ns CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
Skew/Pulse Width Distortion tRSKEW 50 ns
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
Enable to Output High tRZH 10 50 ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8
and Figure 44
Enable to Output Low tRZL 10 50 ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8
and Figure 44
Disable Time from Low tRLZ 10 50 ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
Disable Time from High tRHZ 10 50 ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
Enable from Shutdown to High tRZH(SHDN)3 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
Enable from Shutdown to Low tRZL(SHDN)3 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
TIME TO SHUTDOWN tSHDN4 40 ns
1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:0.5:1.
2 tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. RE = VCC for this condition.
3 tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when RE changes from VCC to 0 V. DE = 0 V for this condition.
4 Minimum time required to put the device into shutdown: DE and RE must be disabled for more than 40 ns for the device to go into shutdown.
ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. G | Page 8 of 27
ADM3065E/ADM3066E/ADM3067E/ADM3068E
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All
typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate1 50 Mbps
Propagation Delay tDPLH, tDPHL 9 15 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Skew tDSKEW 1 2 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Rise/Fall Times tDR, tDF 4 6.7 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Enable to Output High tDZH 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable to Output Low tDZL 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Disable Time from Low tDLZ 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Disable Time from High tDHZ 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable Time from Shutdown to High tDZH(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable Time from Shutdown to Low tDZL(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RECEIVER
Maximum Data Rate 50 Mbps
Propagation Delay tRPLH, tRPHL 20 35 ns CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
Skew/Pulse Width Distortion tRSKEW 1 3 ns
CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
Enable to Output High tRZH 10 35 ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 8 and Figure 44
Enable to Output Low tRZL 10 35 ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 8 and Figure 44
Disable Time from Low tRLZ 10 35 ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
Disable Time from High tRHZ 10 35 ns
RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
Enable from Shutdown to High tRZH(SHDN)3 450 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
Enable from Shutdown to Low tRZL(SHDN)3 450 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
TIME TO SHUTDOWN tSHDN4 40 ns
1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:1:1.
2 tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. RE = VCC for this condition.
3 tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when RE changes from VCC to 0 V. DE = 0 V for this condition.
4 Minimum time required to put the device into shutdown: DE and RE must be disabled for more than 40 ns for the device to go into shutdown.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. G | Page 9 of 27
Timing Diagrams
V
CC
VOD
0V
+VOD
NOTES
1. VOD IS THE DIFFERENCE BETWEEN A AND B,
WITH +VOD BEING THE MAXIMUM POINT OF V
OD,
AND –VOD BEING THE MINIMUM POINT OF V
OD.
–VOD
Y, A
B, Z
VOD
t
DR
t
DF
t
DPLH
t
DPHL
90% POINT
10% POINT
90% POINT
10% POINT
1/2VOD
1/2VCC 1/2VCC
2. VCC = VIO FOR ADM3062E/ADM3064E/ADM3066E/ADM3068E.
VOD = V(A) – V(B)
14666-003
t
SKEW =
t
DPLH
t
DPHL
Figure 5. Driver Propagation Delay Rise and Fall Timing Diagram
A
OR B
A
OR B
DE
V
IO
VCC
0V
0V
VOH
VOL
1/2VIO 1/2VIO
1/2 (VCC + VOL)
1/2VOH
tDLZ
tDZL
tDZH tDHZ
VOL + 0.5V
VOH – 0.5V
NOTES
1. VIO = VCC FOR ADM3061E/ADM3063E/ADM3065E/ADM3067E.
2
. A = Y, B = Z FOR ADM3063E/ADM3064E/ADM3066E/ADM3068E
14666-004
Figure 6. Driver Enable and Disable Timing Diagram
1/2V
CC
1/2V
CC
t
RPLH
t
RPHL
RO
V
OH
0VA – B 0V
V
OL
NOTES
1. V
CC
= V
IO
FOR ADM3062E/ADM3064E/ADM3066E/ADM3068E.
t
RSKEW
=
|t
RPLH
t
RPHL
|
14666-005
Figure 7. Receiver Propagation Delay Timing Diagram
RO
RO
RE
V
CC
0V
0V
1/2V
CC
1/2V
CC
OUTPUT LOW
OUTPUT HIGH
t
RLZ
t
RZL
t
RHZ
t
RZH
V
OL
+ 0.5V
V
OH
– 0.5V
V
OH
V
OL
1/2V
CC
1/2V
CC
NOTES
1. V
CC
= V
IO
FOR ADM3062E/ADM3064E/ADM3066E/ADM3068E.
14666-006
V
CC
Figure 8. Receiver Enable and Disable Timing Diagram
ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. G | Page 10 of 27
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
VCC to GND 6 V
VIO to GND −0.3 V to +6 V
Digital Input and Output Voltage (DE, RE, DI,
and RO)
−0.3 V to
VIO1 + 0.3 V
Driver Output and Receiver Input Voltage −9 V to +14 V
Operating Temperature Ranges −40°C to +85°C
−40°C to +125°C
Storage Temperature Range −65°C to +150°C
Continuous Total Power Dissipation
8-Lead SOIC_N 0.225 W
8-Lead MSOP 0.151 W
10-Lead MSOP 0.151 W
10-Lead LFCSP 0.450 W
14-Lead SOIC_N 0.239 W
Maximum Junction Temperature (TJ) 150°C
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
ESD on the Bus Pins (A, B, Y, Z)
IEC 61000-4-2 Contact Discharge ±12 kV
IEC 61000-4-2 Air Discharge
10 Positive and 10 Negative
Discharges
≥±12 kV
Three Positive or Three Negative
Discharges
±15 kV
ESD Human Body Model (HBM)
On the Bus Pins (A, B, Y, Z) ≥±30 kV
All Other Pins ±8 kV
1 VIO = VCC on the ADM3061E/ADM3063E/ADM3065E/ADM3067E.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
Table 7. Thermal Resistance
Package Type θJA1 θ
JC1 Unit
R-8 110.88 58.63 °C/W
RM-8 165.69 49.61 °C/W
RM-10 165.69 49.61 °C/W
R-14 104.5 42.90 °C/W
CP-10-9 55.65 33.22 °C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with no bias. See JEDEC JESD-51.
ESD CAUTION
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. G | Page 11 of 27
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO
1
RE
2
DE
3
DI
4
V
CC
8
B
7
A
6
GND
5
14666-007
ADM3061E/
ADM3065E
TOP VIEW
(Not to Scale)
Figure 9. ADM3061E/ADM3065E 8-Lead Narrow Body SOIC_N
Pin Configuration
RO
1
RE
2
DE
3
DI
4
V
CC
8
B
7
A
6
GND
5
ADM3061E/
ADM3065E
TOP VIEW
(Not to Scale)
14666-008
Figure 10. ADM3061E/ADM3065E 8-Lead MSOP Pin Configuration
Table 8. ADM3061E/ADM3065E Pin Function Descriptions
Pin No. Mnemonic Description
1 RO Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled, that is, when RE is driven high.
2 RE Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high
disables the receiver.
3 DE Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver
output into a high impedance state.
4 DI Transmit Data Input. Data to be transmitted by the driver is applied to this input.
5 GND Ground.
6 A Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is
put into a high impedance state to avoid overloading the bus.
7 B Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put
into a high impedance state to avoid overloading the bus.
8 VCC 3.0 V to 5.5 V Power Supply. Adding a 0.1 μF decoupling capacitor between the VCC pin and the GND pin is recommended.
ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. G | Page 12 of 27
1V
IO
2RO
3DE
4RE
5DI
10 V
CC
9B
8A
7NIC
6GND
ADM3062E/
ADM3066E
TOP VIEW
(Not to Scale)
14666-009
NOTES
1. NIC = NO INTERNAL CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. THE EXPOSED PAD
MUST BE CONNECTED TO GROUND.
Figure 11. ADM3062E/ADM3066E 10-Lead LFCSP Pin Configuration
V
IO 1
RO
2
DE
3
RE
4
DI
5
V
CC
10
B
9
A
8
NIC
7
GND
6
ADM3062E/
ADM3066E
TOP VIEW
(Not to Scale)
1. NIC = NO INTERNAL CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
14666-010
Figure 12. ADM3062E/ADM3066E 10-Lead MSOP Pin Configuration
Table 9. ADM3062E/ADM3066E Pin Function Descriptions
Pin No. Mnemonic Description
1 VIO 1.62 V to 5.5 V Logic Supply. Adding a 0.1 μF decoupling capacitor between the VIO pin and the GND pin is recommended.
2 RO Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
3 DE Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver
output into a high impedance state.
4 RE Receiver Enable Input. This is an active low input. Driving this input low enables the receiver, and driving it high
disables the receiver.
5 DI Transmit Data Input. Data to be transmitted by the driver is applied to this input.
6 GND Ground.
7 NIC No Internal Connection. This pin is not internally connected.
8 A Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is
put into a high impedance state to avoid overloading the bus.
9 B Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put
into a high impedance state to avoid overloading the bus.
10 VCC 3.0 V to 5.5 V Power Supply. Adding a 0.1 μF decoupling capacitor between the VCC pin and the GND pin is recommended.
EPAD Exposed Pad. The exposed pad must be connected to ground.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. G | Page 13 of 27
NIC
1
RO
2
RE
3
DE
4
DI
5
GND
6
GND
7
V
CC
14
V
CC
13
A
12
B
11
Z
10
Y
9
NIC
8
NIC = NO INTERN
A
L CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
ADM3063E/
ADM3067E
TOP VIEW
(Not to Scale)
14666-111
Figure 13. ADM3063E/ADM3067E 14-Lead SOIC_N Pin Configuration
Table 10. ADM3063E/ADM3067E Pin Function Descriptions
Pin No. Mnemonic Description
1, 8 NIC No Internal Connection. This pin is not internally connected.
2 RO Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled, that is, when RE is driven high.
3 RE Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high
disables the receiver.
4 DE Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver
output into a high impedance state.
5 DI Transmit Data Input. Data to be transmitted by the driver is applied to this input.
6, 7 GND Ground.
9 Y Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high
impedance state to avoid overloading the bus.
10 Z Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high
impedance state to avoid overloading the bus.
11 B Inverting Receiver Input.
12 A Noninverting Receiver Input.
13, 14 VCC 3.0 V to 5.5 V Power Supply. Adding a 0.1 μF decoupling capacitor between the VCC pin and the GND pin is
recommended.
ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. G | Page 14 of 27
V
IO 1
RO
2
RE
3
DE
4
DI
5
GND
6
NIC
7
V
CC
14
NIC
13
A
12
B
11
Z
10
Y
9
GND
8
NIC = NO INTERN
A
L CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
ADM3064E/
ADM3068E
TOP VIEW
(Not to Scale)
14666-113
Figure 14. ADM3064E/ADM3068E 14-Lead SOIC_N Pin Configuration
Table 11. ADM3064E/ADM3068E Pin Function Descriptions
Pin No. Mnemonic Description
1 VIO 1.62 V to 5.5 V Logic Supply. Adding a 0.1 μF decoupling capacitor between the VIO pin and the GND pin is
recommended.
2 RO Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled, that is, when RE is driven high.
3 DE Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver
output into a high impedance state.
4 RE Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high
disables the receiver.
5 DI Transmit Data Input. Data to be transmitted by the driver is applied to this input.
6, 8 GND Ground.
7, 13 NIC No Internal Connection. This pin is not internally connected.
9 Y Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high
impedance state to avoid overloading the bus.
10 Z Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high
impedance state to avoid overloading the bus.
11 B Inverting Receiver Input.
12 A Noninverting Receiver Input.
14 VCC 3.0 V to 5.5 V Power Supply. Adding a 0.1 μF decoupling capacitor between the VCC pin and the GND pin is
recommended.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. G | Page 15 of 27
TYPICAL PERFORMANCE CHARACTERISTICS
0
50
100
150
200
250
300
350
400
–40 –25 –10 5 20 35 50 65 80 95 110 125
SHUTDOWN CURRENT (I
SHDN
) (µA)
TEMPERATURE (°C)
V
CC
= 3.3V
V
CC
= 4.5V
V
CC
= 5.5V
14666-018
Figure 15. Shutdown Current (ISHDN) vs. Temperature
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
–40 –25 –10 5 20 35 50 65 80 95 110 125
SUPPLY CURRENT (I
CC
) (A)
TEMPERATURE (°C)
R
L
= 120
NO LOAD
R
L
= 54
14666-019
Figure 16. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps,
50 Mbps Models, VCC = 3.3 V
0
0.02
0.04
0.06
0.10
0.08
–55 –35 –15 125105856545255
SUPPLY CURRENT (I
CC
) (A)
TEMPERATUREC)
R
L
= 120
NO LOAD
R
L
= 54
14666-020
Figure 17. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps,
50 Mbps Models, VCC = 5.0 V
0
0.02
0.04
0.06
0.08
0.10
0.12
0 5 10 15 20 25 30 35 40 45 50
SUPPLY CURRENT (I
CC
) (A)
DATA RATE (Mbps)
V
CC
= 3.3V
V
CC
= 5.0V
V
CC
= 5.5V
14666-021
Figure 18. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance,
50 Mbps Models
0
0.01
0.02
0.04
0.06
0.08
0.03
0.05
0.07
0 5 10 15 20 25 30 35 40 45 50
SUPPLY CURRENT (I
CC
) (A)
DATA RATE (Mbps)
V
CC
= 3.3V
V
CC
= 5.0V
V
CC
= 5.5V
14666-022
Figure 19. Supply Current (ICC) vs. Data Rate with No Load Resistance,
50 Mbps Models
0
0.02
0.04
0.06
0.08
0.10
0.12
0 50 100 150 200 250 300 350 400 450 500
SUPPLY CURRENT (I
CC
) (A)
DATA RATE (kbps)
V
CC
= 3.3V, NO LOAD
V
CC
= 3.3V, 54 LOAD
V
CC
= 5V, NO LOAD
V
CC
= 5V, 54 LOAD
14666-123
Figure 20. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance and
No Load Resistance, 500 kbps Models
ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. G | Page 16 of 27
0
10
20
30
40
50
60
SUPPLY CURRENT (I
CC
) (mA)
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105 125
14666-124
Figure 21. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps,
500 kbps Models, VCC = 3.0 V
SUPPLY CURRENT (I
CC
) (mA)
TEMPERATURE (°C)
0
20
40
60
80
100
120
140
–60 –40 –20 0 20 40 60 80 100 120 140
14666-125
Figure 22. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps,
500 kbps Models, VCC = 5.5 V
140
160
180
200
220
240
260
280
300
–60 –40 –20 0 20 40 60 80 100 120 140
DRIVER DIFFERENTI
L PROPA
TION DEL
Y (ns)
TEMPERATURE (C)
t
DPLH
AT 5.5V
t
DPHL
AT 5.5V
t
DPLH
AT 3.0V
t
DPHL
AT 3.0V
14666-126
Figure 23. Driver Differential Propagation Delay vs. Temperature,
500 kbps Models
CH1 1.0V A CH1 0V
BWCH2 1.0V BW
1
2
R
OUT
V
ID
14666-127
Figure 24. Receiver Propagation Delay (Oscilloscope Plot),
Data Rate = 500 kbps, VID ≥ 1.5 V
CH1 3.0V CH2 2.0V A CH1 1.98V
BWBW
CH3 2.0V M1 2.5V
BW
1
2
M1
VOD
DI
A
B
14666-128
Figure 25. Driver Propagation Delay (Oscilloscope Plot),
Data Rate = 500 kbps, 500 kbps Models
4
5
6
7
8
9
10
11
12
–40 –25 –10 5 20 35 50 65 80 95 110 125
DRIVER DIFFERENTIAL PROPAGATION DELAY (ns)
TEMPERATURE (°C)
t
DPHL
,V
CC
= 3.0V
t
DPLH
,V
CC
= 3.0V
t
DPHL
,V
CC
= 5.5V
t
DPLH
,V
CC
= 5.5V
14666-023
Figure 26. Driver Differential Propagation Delay vs. Temperature, 50 Mbps Models
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. G | Page 17 of 27
C1 1.0V/DIV
C2 2.0V/DIV
50BW: 1.5G
50BW: 1.5G
20ns/DIV
5.0GS/s
200ps/pt
A C1 1.34V
1
2
VOD
DI
14666-024
Figure 27. Driver Propagation Delay (Oscilloscope Plot),
Data Rate = 50 Mbps, 50 Mbps models
–0.12
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
DRIVER OUTPUT CURRENT (A)
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 3.0V
14666-025
Figure 28. Driver Output Current vs. Driver Differential Output Voltage
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
–40 –25 –10 5 20 35 50 65 80 95 110 125
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
V
CC
= 3.0V
V
CC
= 4.5V
14666-026
Figure 29. Driver Differential Output Voltage vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
–7 –5 –3 –1–6 –4 –2 0 1 3245
DRIVER OUTPUT CURRENT (A)
DRIVER OUTPUT HIGH VOLTAGE (V)
V
IO
= V
CC
= 3.3 V
14666-027
Figure 30. Driver Output Current vs. Driver Output High Voltage
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
02 4 6 81012
DRIVER OUTPUT CURRENT (A)
DRIVER OUTPUT LOW VOLTAGE (V)
V
IO
= V
CC
= 3.3 V
14666-028
Figure 31. Driver Output Current vs. Driver Output Low Voltage
C1 1.0V/DIV
C2 1.0V/DIV
50
BW
: 1.5G
50
BW
: 1.5G
20ns/DIV
5.0GS/s
200ps/pt
A C1 0.0V
1
2
RO
V
ID
14666-029
Figure 32. Receiver Propagation Delay (Oscilloscope Plot) at 50 Mbps,
|VID| ≥ 1.5 V
ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. G | Page 18 of 27
16
18
20
22
24
26
28
–40 –25 –10 5 20 35 50 65 80 95 110 125
RECEIVER PROPAGATION DELAY (ns)
TEMPERATURE (°C)
t
RPHL
t
RPLH
14666-030
Figure 33. Receiver Propagation Delay vs. Temperature, 50 Mbps
0
0.005
0.010
0.015
0.020
0.025
0.030
0.035
0 0.51.01.52.02.53.03.5
RECEIVER OUTPUT CURRENT (A)
RECEIVER OUTPUT LOW VOLTAGE (V)
V
CC
= 3.3V
14666-031
Figure 34. Receiver Output Current vs. Receiver Output Low Voltage
(VCC = 3.3 V)
–0.040
–0.035
–0.030
–0.025
–0.020
–0.015
–0.005
–0.010
0
0 0.51.01.52.02.53.03.5
RECEIVER OUTPUT CURRENT (A)
RECEIVER OUTPUT HIGH VOLTAGE (V)
V
CC
= 3.3V
14666-032
Figure 35. Receiver Output Current vs. Receiver Output High Voltage
(VCC = 3.3 V)
5.0
5.2
5.4
5.6
5.8
6.0
RECEIVER OUTPUT HIGH VOLT
A
GE (V)
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
14666-033
Figure 36. Receiver Output High Voltage vs. Temperature
0
0.05
0.10
0.15
0.20
0.25
RECEIVER OUTPUT LOW VOLT
A
GE (V)
–40 –25 –10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
14666-034
Figure 37. Receiver Output Low Voltage vs. Temperature