NCV7356D2R2G - ON Semiconductor - Datasheet.Directory

January, 2010 − Rev. 8

1Publication Order Number:

NCV7356/D

NCV7356

Single Wire CAN Transceiver

The NCV7356 is a physical layer device for a single wire data link

capable of operating with various Carrier Sense Multiple Access

with Collision Resolution (CSMA/CR) protocols such as the Bosch

Controller Area Network (CAN) version 2.0. This serial data link

network is intended for use in applications where high data rate is not

required and a lower data rate can achieve cost reductions in both the

physical media components and in the microprocessor and/or

dedicated logic devices which use the network.

The network shall be able to operate in either the normal data rate

mode or a high−speed data download mode for assembly line and

service data transfer operations. The high−speed mode is only

intended to be operational when the bus is attached to an off−board

service node. This node shall provide temporary bus electrical loads

which facilitate higher speed operation. Such temporary loads should

be removed when not performing download operations.

The bit rate for normal communications is typically 33 kbit/s, for

high−speed transmissions like described above a typical bit rate of

83 kbit/s is recommended. The NCV7356 features undervoltage

lockout, timeout for faulty blocked input signals, output blanking

time in case of bus ringing and a very low sleep mode current.

The device is compliant with GMW3089V2.4

General Motors Corporation specification.

Features

•Fully Compatible with J2411 Single Wire CAN Specification

•60 mA (max) Sleep Mode Current

•Operating Voltage Range 5.0 to 27 V

•Up to 100 kbps High−Speed Transmission Mode

•Up to 40 kbps Bus Speed

•Selective BUS Wake−Up

•Logic Inputs Compatible with 3.3 V and 5 V Supply Systems

•Control Pin for External Voltage Regulators (14 Pin Package Only)

•Standby to Sleep Mode Timeout

•Low RFI Due to Output Wave Shaping

•Fully Integrated Receiver Filter

•Bus Terminals Short−Circuit and Transient Proof

•Loss of Ground Protection

•Protection Against Load Dump, Jump Start

•Thermal Overload and Short Circuit Protection

•ESD Protection of 4.0 kV on CANH Pin (2.0 kV on Any Other Pin)

•Undervoltage Lock Out

•Bus Dominant Timeout Feature

•Internally Fused Leads in SO−14 Package

•NCV Prefix for Automotive and Other Applications Requiring Site

and Control Changes

•Pb−Free Packages are Available

SOIC−14

D SUFFIX

CASE 751A

PIN CONNECTIONS

Device Package Shipping†

ORDERING INFORMATION

NCV7356D1G SOIC−8

(Pb−Free)

98 Units / Rail

http://onsemi.com

MARKING DIAGRAMS

NCV7356G

AWLYWW

(Top View)

TxD

MODE1

CANHMODE0

RxD VBAT

LOAD

132

123

114

105

GND GND

NC INH

GND GND

NCV7356D1R2G SOIC−8

(Pb−Free)

2500 Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

NCV7356D2 SOIC−14 55 Units / Rail

NCV7356D2R2 SOIC−14 2500 Tape & Reel

SOIC−8

D SUFFIX

CASE 751

V7356

ALYW

A = Assembly Location

WL, L = Wafer Lot

Y = Year

WW, W = Work Week

G or G = Pb−Free Package

1TxD 8 GND

2MODE0

3MODE1

4RxD

7 CANH

6 LOAD

BAT

(Top View)

NCV7356D2R2G SOIC−14

(Pb−Free)

2500 Tape & Reel

NCV7356D2G SOIC−14

(Pb−Free)

55 Units / Rail

NCV7356

http://onsemi.com

Figure 1. 8−Pin Package Block Diagram

VBAT

NCV7356

5 V Supply

and

References

Biasing and

VBAT Monitor

RC−OSC

Wave Shaping

Time Out

TxD

MODE

CONTROL

MODE0

MODE1

RxD

Reverse

Current

Protection

CAN Driver

Feedback

Loop

Input Filter

Receive

Comparator

Loss of

Ground

Detection

CANH

LOAD

GND

Reverse

Current

Protection

RxD Blanking

Time Filter

NCV7356

http://onsemi.com

Figure 2. 14−Pin Package Block Diagram

VBAT

NCV7356

5 V Supply

and

References

Biasing and

VBAT Monitor

RC−OSC

Wave Shaping

Time Out

TxD

MODE

CONTROL

MODE0

MODE1

RxD

Reverse

Current

Protection

CAN Driver

Feedback

Loop

Input Filter

Receive

Comparator

Loss of

Ground

Detection

CANH

LOAD

GND

Reverse

Current

Protection

RxD Blanking

Time Filter

INH

NCV7356

http://onsemi.com

PACKAGE PIN DESCRIPTION

SOIC−8 SOIC−14 Symbol Description

1 2 TxD Transmit data from microprocessor to CAN.

2 3 MODE0 Operating mode select input 0.

3 4 MODE1 Operating mode select input 1.

4 5 RxD Receive data from CAN to microprocessor.

5 10 VBAT Battery input voltage.

611 LOAD Resistor load (loss of ground detection low side switch).

7 12 CANH Single wire CAN bus pin.

81, 7, 8, 14 GND Ground

−6, 13 NC No Connection (Note 1)

−9 INH Control pin for external voltage regulator (high voltage high side switch) (14 pin package only)

1. PWB terminal 13 can be connected to ground which will allow the board to be assembled with either the 8 pin package or the 14 pin package.

NCV7356

http://onsemi.com

Electrical Specification

All voltages are referenced to ground (GND). Positive

currents flow into the IC. The maximum ratings given in

the table below are limiting values that do not lead to a

permanent damage of the device but exceeding any of these

limits may do so. Long term exposure to limiting values

may affect the reliability of the device.

MAXIMUM RATINGS

Rating Symbol Condition Min Max Unit

Supply Voltage, Normal Operation VBAT − −0.3 18 V

Short−Term Supply Voltage, Transient VBAT.LD Load Dump; t < 500 ms −40 V (peak)

Jump Start; t < 1.0 min −27 V

Transient Supply Voltage VBAT.TR1 ISO 7637/1 Pulse 1 (Note 2) −50 −V

Transient Supply Voltage VBAT.TR2 ISO 7637/1 Pulses 2 (Note 2) −100 V

Transient Supply Voltage VBAT.TR3 ISO 7637/1 Pulses 3A, 3B −200 200 V

CANH Voltage VCANH VBAT < 27 V −20

VBAT = 0 V −40

Transient Bus Voltage VCANHTR1 ISO 7637/1 Pulse 1 (Note 3) −50 −V

Transient Bus Voltage VCANHTR2 ISO 7637/1 Pulses 2 (Note 3) −100 V

Transient Bus Voltage VCANHTR3 ISO 7637/1 Pulses 3A, 3B (Note 3) −200 200 V

DC Voltage on Pin LOAD VLOAD Via RT > 2.0 kW−40 40 V

DC Voltage on Pins TxD, MODE1, MODE0, RxD VDC − −0.3 7.0 V

ESD Capability of CANH VESDBUS Human Body Model

(with respect to VBAT and GND)

Eq. to Discharge 100 pF with 1.5 kW

−4000 4000 V

ESD Capability of Any Other Pin VESD Human Body Model

Eq. to Discharge 100 pF with 1.5 kW

−2000 2000 V

Maximum Latchup Free Current at Any Pin ILATCH − −500 500 mA

Storage Temperature TSTG − −55 150 °C

Junction Temperature TJ− −40 150 °C

Lead Temperature Soldering

Reflow: (SMD styles only)

SOIC−14 Tsld 60 s − 150 s above 183°C−240 peak °C

SOIC−860 s − 150 s above 217°C−260 peak

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. ISO 7637 test pulses are applied to VBAT via a reverse polarity diode and >1.0 mF blocking capacitor.

3. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF.

4. ESD measured per Q100−002 (EIA/JESD22−A114−A).

TYPICAL THERMAL CHARACTERISTICS

Parameter

Test Condition, Typical Value

Unit

Min Pad Board 1, Pad Board

SOIC−8

Junction−to−Lead (psi−JL7, YJL8) or Pins 6−757 (Note 5) 51 (Note 6) °C/W

Junction−to−Ambient (RqJA, qJA)187 (Note 5) 128 (Note 6) °C/W

SOIC−14

Junction−to−Lead (psi−JL8, YJL8)30 (Note 7) 30 (Note 8) °C/W

Junction−to−Ambient (RqJA, qJA)122 (Note 7) 84 (Note 8) °C/W

5. 1 oz copper, 53 mm2 coper area, 0.062″ thick FR4.

6. 1 oz copper, 716 mm2 coper area, 0.062″ thick FR4.

7. 1 oz copper, 94 mm2 coper area, 0.062″ thick FR4.

8. 1 oz copper, 767 mm2 coper area, 0.062″ thick FR4.

NCV7356

http://onsemi.com

ELECTRICAL CHARACTERISTICS (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.)

Characteristic Symbol Condition Min Typ Max Unit

GENERAL

Undervoltage Lock Out VBATuv −3.5 −4.8 V

Supply Current, Recessive,

All Active Modes

IBATN VBAT = 18 V,

TxD Open

Not High Speed Mode −5.0 6.0 mA

High Speed Mode − − 8.0

Normal Mode Supply Current,

Dominant

IBATN

(Note 10)

VBAT = 27 V, MODE0 = MODE1 = H,

TxD = L, Rload = 200 W

−30 35 mA

High−Speed Mode Supply Current,

Dominant

IBATN

(Note 10)

VBAT = 16 V, MODE0 = H, MODE1 = L,

TxD = L, Rload = 75 W

−70 75 mA

Wake−Up Mode Supply Current,

Dominant

IBATW

(Note 10)

VBAT = 27 V,

MODE0 = L, MODE1 = H,

TxD = L, Rload = 200 W

−60 75 mA

Sleep Mode Supply Current (Note 9) IBATS VBAT = 13 V, TA = 85°C,

TxD, RxD, MODE0,

MODE1 Open

−30 60 mA

Thermal Shutdown (Note 10) TSD −155 −180 °C

Thermal Recovery (Note 10) TREC −126 −150 °C

CANH

Bus Output Voltage Voh RL > 200 W, Normal Mode

6.0 V < VBAT < 27 V

4.4 −5.1 V

Bus Output Voltage

Low Battery

Voh RL > 200 W, Normal High−Speed Mode

5.0 V < VBAT < 6.0 V

3.4 −5.1 V

Bus Output Voltage

High−Speed Mode

Voh RL > 75 W, High−Speed Mode

8.0 V < VBAT < 16 V

4.2 −5.1 V

HV Fixed Wake−Up

Output High Voltage

VohWuFix Wake−Up Mode, RL > 200 W,

11.4 V < VBAT < 27 V

9.9 −12.5 V

HV Offset Wake−Up

Output High Voltage

VohWuOffset Wake−Up Mode, RL > 200 W,

5.0 V < VBAT < 11.4 V

VBAT –1.5 −VBAT V

Recessive State

Output Voltage

Vol Recessive State or Sleep Mode,

Rload = 6.5 kW

−0.20 −0.20 V

Bus Short Circuit Current −ICAN_SHORT VCANH = 0 V, VBAT = 27 V, TxD = 0 V 50 −350 mA

Bus Leakage Current

During Loss of Ground

ILKN_CAN

(Note 11)

Loss of Ground, VCANH = 0 V −50 −10 mA

Bus Leakage Current, Bus Positive ILKP_CAN TxD High −10 −10 mA

Bus Input Threshold Vih Normal, High−Speed Mode, HVWU

6.0 v VBAT v 27 V

2.0 2.1 2.2 V

Bus Input Threshold Low Battery Vihlb Normal, VBAT = 5.0 V to 6.0 V 1.6 1.7 2.2 V

Fixed Wake−Up from Sleep

Input High Voltage Threshold

VihWuFix

(Note 10)

Sleep Mode, VBAT > 10.9 V 6.6 −7.9 V

Offset Wake−Up from Sleep

Input High Voltage Threshold

VihWuOffset

(Note 10)

Sleep Mode VBAT −4.3 −VBAT −3.25 V

LOAD

Voltage on Switched Ground Pin VLOAD_1mA ILOAD = 1.0 mA − − 0.1 V

Voltage on Switched Ground Pin VLOAD ILOAD = 5.0 mA − − 0.5 V

Voltage on Switched Ground Pin VLOAD_LOB ILOAD = 7.0 mA, VBAT = 0 V − − 1.0 V

Load Resistance During Loss of

Battery

RLOAD_LOB VBAT = 0 RLOAD

−10%

−RLOAD

+35%

9. Characterization data supports IBATS < 65 mA with conditions VBAT = 18 V, TA = 125°C

10. Thresholds not tested in production, guaranteed by design.

11. Leakage current in case of loss of ground is the summary of both currents ILKN_CAN and ILKN_LOAD.

NCV7356

http://onsemi.com

ELECTRICAL CHARACTERISTICS (continued) (VBAT = 5.0 to 27 V, TA = −40 to +125°C, unless otherwise specified.)

Characteristic Symbol Condition Min Typ Max Unit

TXD, MODE0, MODE1

High Level Input Voltage Vih 6.0 < VBAT < 27 V 2.0 − − V

Low Level Input Voltage Vil 6.0 < VBAT < 27 V − − 0.8 V

TxD Pullup Current −IIL_TXD TxD = L, MODE0 and 1 = H

5.0 < VBAT < 27 V

10 −50 mA

MODE0 and 1 Pulldown Resistor RMODE_pd 10 −50 kW

RXD

Low Level Output Voltage Vol_rxd IRxD = 2.0 mA − − 0.4 V

High Level Output Leakage Iih_rxd VRxD = 5.0 V −10 −10 mA

RxD Output Current Irxd VRxD = 5.0 V − − 70 mA

INH (14 Pin Package Only)

High Level Output Voltage Voh_INH IINH = −180 mA VBAT −0.8 VBAT −0.5 VBAT V

Leakage Current IINH_lk MODE0 = MODE1 = L, INH = 0 V −5.0 −5.0 mA

NCV7356

http://onsemi.com

TIMING MEASUREMENT LOAD CONDITIONS

Normal and High Voltage Wake−Up Mode High−Speed Mode

min load / min tau 3.3 kW / 540 pF Additional 140 W tool resistance

to ground in parallel

min load / max tau 3.3 kW / 1.2 nF

max load / min tau 200 W / 5.0 nF Additional 120 W tool resistance

to ground in parallel

max load / max tau 200 W / 20 nF

ELECTRICAL CHARACTERISTICS (5.0 V ≤ VBAT ≤ 27 V, −40°C ≤ TA ≤ 125°C, unless otherwise specified.)

AC CHARACTERISTICS (See Figures 3, 4, and 5)

Characteristic Symbol Condition Min Typ Max Unit

Transmit Delay in Normal and Wake−Up Mode,

Bus Rising Edge (Notes 12, 13)

tTr Min and Max Loads per Timing

Measurement Load Conditions

2.0 −6.3 ms

Transmit Delay in Wake−Up Mode to VihWU,

Bus Rising Edge (Notes 12, 14)

tTWUr Min and Max Loads per Timing

Measurement Load Conditions

2.0 −18 ms

Transmit Delay in Normal Mode,

Bus Falling Edge (Notes 15, 16)

tTf Min and Max Loads per Timing

Measurement Load Conditions

1.8 −10 ms

Transmit Delay in Wake−Up Mode,

Bus Falling Edge (Notes 15, 16)

tTWU1f Min and Max Loads per Timing

Measurement Load Conditions

3.0 −13.7 ms

Transmit Delay in High−Speed Mode,

Bus Rising Edge (Notes 12, 17)

tTHSr Min and Max Loads per Timing

Measurement Load Conditions

0.1 −1.5 ms

Transmit Delay in High−Speed Mode,

Bus Falling Edge (Notes 16, 18)

tTHSf Min and Max Loads per Timing

Measurement Load Conditions

0.04 −3.0 ms

Receive Delay, All Active Modes (Note 19) tDR CANH High to Low Transition 0.3 −1.0 ms

Receive Delay, All Active Modes (Note 19) tRD CANH Low to High Transition 0.3 −1.0 ms

Input Minimum Pulse Length,

All Active Modes (Note 17)

tmpDR

tmpRD

CANH High to Low Transition

CANH Low to High Transition

0.1

−

1.0

Wake−Up Filter Time Delay tWUF See Figure 4 10 −70 ms

Receive Blanking Time, After TxD L−H Transition trb See Figure 5 0.5 −6.0 ms

TxD Timeout Reaction Time ttout Normal and High−Speed Mode −17 −ms

TxD Timeout Reaction Time ttoutwu Wake−Up Mode −17 −ms

Delay from Normal to High−Speed and

High Voltage Wake−Up Mode

tdnhs − − − 30 ms

Delay from High−Speed and High Voltage

Wake−Up to Normal Mode

tdhsn − − − 30 ms

Delay from Normal to Standby Mode tdsby VBAT = 6.0 V to 27 V − − 500 ms

Delay from Sleep to Normal Mode tdsnwu VBAT = 6.0 V to 27 V − − 50 ms

Delay from Sleep to High Voltage Mode tdshv VBAT = 6.0 V to 27 V − − 50 ms

Delay from Standby to Sleep Mode (Note 20) tdsleep VBAT = 6.0 V to 27 V 100 250 500 ms

12.Minimum signal delay time is measured from the TxD voltage threshold to CANH = 1.0 V. t load should be min per the Timing Measurement

Load Conditions table.

13.Maximum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V at VBAT = 27 V, CANH = 2.8 V at VBAT = 5.0 V. t load

should be max per the Timing Measurement Load Conditions table.

14. Maximum signal delay time is measured from the TxD voltage threshold to CANH = 9.2 V. Vihwumax = Vihwufix,

max + Vgoff = 7.9 V + 1.3 V = 9.2 V. t load should be max per the Timing Measurement Load Conditions table.

15.Minimum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V at VBAT = 27 V, CANH = 2.8 V at VBAT = 5.0 V. t load

should be min per the Timing Measurement Load Conditions table.

16. Maximum signal delay time is measured from the TxD voltage threshold to CANH = 1 V. t load should be max per the Timing Measurement

Load Conditions table.

17.Maximum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V. t load should be max per the Timing Measurement

Load Conditions table.

18. Minimum signal delay time is measured from the TxD voltage threshold to CANH = 3.5 V. t load should be min per the Timing Measurement

Load Conditions table.

19. Receive delay time is measured from the rising / falling edge crossing of the nominal Vih value on CANH to the falling (Vcmos_il_max) / rising

(Vcmos_ih_min) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising

and falling edges is 50 V/ms. The low level on bus is always 0 V. For normal mode and high−speed mode testing the high level on bus is 4 V.

For HVWU mode testing the high level on bus is VBAT − 2 V. Relaxation of this non−critical parameter from 0.15 ms to 0.10 ms may be addressed

in future revisions of GMW3089.

20. Tested on 14 Pin package only.

NCV7356

http://onsemi.com

BUS LOADING REQUIREMENTS

Characteristic Symbol Min Typ Max Unit

Number of System Nodes −2−32 −

Network Distance Between Any Two ECU Nodes Bus Length − − 60 m

Node Series Inductor Resistance (If required) Rind − − 3.5 W

Ground Offset Voltage Vgoff −−1.3 V

Ground Offset Voltage, Low Battery Vgofflowbat −0.1 x VBAT 0.7 V

Device Capacitance (Unit Load) Cul 135 150 300 pF

Network Total Capacitance Ctl 396 −19000 pF

Device Resistance (Unit Load) Rul 6435 6490 6565 W

Device Resistance (Min Load) Rmin 2000 − − W

Network Total Resistance Rtl 200 −4596 W

Network Time Constant (Note 21) t1.0 −4.0 ms

Network Time Constant in High−Speed Mode t− − 1.5 ms

High−Speed Mode Network Resistance to GND Rload 75 −135 W

21. The network time constant incorporates the bus wiring capacitance. The minimum value is selected to limit radiated emission. The maximum

value is selected to ensure proper communication modes. Not all combinations of R and C are possible.

TIMING DIAGRAMS

Figure 3. Input/Output Timing

Vihmax + Vgoffmax

VCANH

VRxD

1 V

50%

VTxD

50%

tRtF

tDtDR

NCV7356

http://onsemi.com

TIMING DIAGRAMS

Figure 4. Wake−Up Filter Time Delay

VCANH

VRxD

tWU

tWUF

tWU

tWU < tWUF

Vih + Vgoff

wake−up

interrupt

Figure 5. Receive Blanking Time

Vih

VCANH

VRxD

50%

VTxD

50%

tRB

NCV7356

http://onsemi.com

FUNCTIONAL DESCRIPTION

TxD Input Pin

TxD Polarity

•TxD = logic 1 (or floating) on this pin produces an

undriven or recessive bus state (low bus voltage)

•TxD = logic 0 on this pin produces either a bus normal

or a bus high voltage dominant state depending on the

transceiver mode state (high bus voltage)

If the TxD pin is driven to a logic low state while the sleep

mode (Mode 0 = 0 and Mode 1 = 0) is activated, the

transceiver can not drive the CANH pin to the dominant

state.

The transceiver provides an internal pullup current on the

TxD pin which will cause the transmitter to default to the

bus recessive state when TxD is not driven.

TxD input signals are standard CMOS logic levels.

Timeout Feature

In case of a faulty blocked dominant TxD input signal,

the CANH output is switched off automatically after the

specified TxD timeout reaction time to prevent a dominant

bus.

The transmission is continued by next TxD L to H

transition without delay.

MODE0 and MODE1 Pins

The transceiver provides a weak internal pulldown

current on each of these pins which causes the transceiver

to default to sleep mode when they are not driven. The

mode input signals are standard CMOS logic level for

3.3 V and 5 V supply voltages. See Electrical

Characteristics table for timing limitations for mode

changes.

MODE0 MODE1 Mode

L L Sleep Mode

H L High−Speed Mode

L H High Voltage Wake−Up

H H Normal Mode

Sleep Mode

Transceiver is in low power state, waiting for wake−up

via high voltage signal or by mode pins change to any state

other than 0,0. In this state, the CANH pin is not in the

dominant state regardless of the state of the TxD pin.

High−Speed Mode

This mode allows high−speed download with bit rates up

to 100 Kbit/s. The output wave shapingaping circuit is

disabled in this mode. Bus transmitter drive circuits for

those nodes which are required to communicate in

high−speed mode are able to drive reduced bus resistance

in this mode.

High Voltage Wake−Up Mode

This bus includes a selective node awake capability,

which allows normal communication to take place among

some nodes while leaving the other nodes in an undisturbed

sleep state. This is accomplished by controlling the signal

voltages such that all nodes must wake−up when they

receive a higher voltage message signal waveform. The

communication system communicates to the nodes

information as to which nodes are to stay operational

(awake) and which nodes are to put themselves into a non

communicating low power “sleep” state. Communication

at the lower, normal voltage levels shall not disturb the

sleeping nodes.

Normal Mode

Transmission bit rate in normal communication is

33 Kbits/s. In normal transmission mode the NCV7356

supports controlled waveform rise and overshoot times.

Waveform trailing edge control is required to assure that

high frequency components are minimized at the

beginning of the downward voltage slope. The remaining

fall time occurs after the bus is inactive with drivers off and

is determined by the RC time constant of the total bus load.

RxD Output Pin

Logic data as sensed on the single wire CAN bus.

RxD Polarity

•RxD = logic 1 on this pin indicates a bus recessive

state (low bus voltage)

•RxD = logic 0 on this pin indicates a bus normal or

high voltage bus dominant state

RxD in Sleep Mode

RxD does not pass signals to the microprocessor while in

sleep mode until a valid wake−up bus voltage level is

received or the MODE0 and MODE 1 pins are not 0, 0

respectively. When the valid wake−up bus voltage signal

awakens the transceiver, the RxD pin signals an interrupt

(logic 0). If there is no mode change within 250 ms (typ),

the transceiver re−enters the sleep mode.

When not in sleep mode all valid bus signals will be sent

out on the RxD pin.

RxD will be placed in the undriven or off state when in

sleep mode.

RxD Typical Load

Resistance: 2.7 kW

Capacitance: < 25 pF

NCV7356

http://onsemi.com

Bus LOAD Pin

Resistor ground connection with internal open−on−loss−

of−ground protection

When the ECU experiences a loss of ground condition,

this pin is switched to a high impedance state.

The ground connection through this pin is not interrupted

in any transceiver operating mode including the sleep

mode. The ground connection only is interrupted when

there is a valid loss of ground condition.

This pin provides the bus load resistor with a path to

ground which contributes less than 0.1 V to the bus offset

voltage when sinking the maximum current through one

unit load resistor. This path exists in all operating modes,

including the sleep mode.

The transceiver’s maximum bus leakage current

contribution to Vol from the LOAD pin when in a loss of

ground state is 50 mA over all operating temperatures and

3.5 < VBAT < 27 V.

VBAT Input Pin

Vehicle Battery Voltage

The transceiver is fully operational as described in the

Electrical Characteristics Table over the range 6.0 V <

VBAT < 18 V as measured between the GND pin and the

VBAT pin.

For 5.0 V < VBat < 6.0 V, the bus operates in normal

mode with reduced dominant output voltage and reduced

receiver input voltage. High voltage wake−up is not

possible (dominant output voltage is the same as in normal

or high−speed mode).

The transceiver operates in normal mode when 18 V <

VBat < 27 V at 85°C for one minute.

CAN BUS

Input/Output Pin

Wave Shaping in Normal and High Voltage Wake−Up

Mode

Wave shaping is incorporated into the transmitter to

minimize EMI radiated emissions. An important

contributor to emissions is the rise and fall times during

output transitions at the “corners” of the voltage waveform.

The resultant waveform is one half of a sin wave of

frequency 50−65 kHz at the rising waveform edge and one

quarter of this sin wave at falling or trailing edge.

Wave Shaping in High−Speed Mode

Wave shaping control of the rising and falling waveform

edges are disabled during high−speed mode. EMI

emissions requirements are waived during this mode. The

waveform rise time in this mode is less than 1.0 ms.

Short Circuits

If the CAN BUS pin is shorted to ground for any duration

of time, the current is limited as specified in the Electrical

Characteristics Table until an overtemperature shutdown

circuit disables the output high side drive source transistor

preventing damage to the IC.

Loss of Ground

In case of a valid loss of ground condition, the LOAD pin

is switched into high impedance state. The CANH

transmission is continued until the undervoltage lock out

voltage threshold is detected.

Loss of Battery

In case of loss of battery (VBAT = 0 or open) the

transceiver does not disturb bus communication. The

maximum reverse current into the power supply system

(VBAT) doesn’t exceed 500 mA.

INH Pin (14 pin package only)

The INH pin is a high−voltage highside switch used to

control the ECU’s regulated microcontroller power supply.

After power−on, the transceiver automatically enters an

intermediate standby mode, the INH output will go high

(up to VBAT) turning on the external voltage regulator. The

external regulator provides power to the ECU. If there is no

mode change within 250 ms (typ), the transceiver re−enters

the sleep mode and the INH output goes to logic 0

(floating).

When the transceiver has detected a valid wake−up

condition (bus HVWU traffic which exceeds the wake−up

filter time delay) the INH output will become high (up to

VBAT) again and the same procedure starts as described

after power−on. In case of a mode change into any active

mode, the sleep timer is stopped and INH stays high (up to

VBAT). If the transceiver enters the sleep mode, INH goes

to logic 0 (floating) after 250 ms (typ) when no wake−up

signal is present.

NCV7356

http://onsemi.com

Figure 6. State Diagram, 8 Pin Package

HVWU Mode

MODE1

high

VBATon

MODE0

low

High−Speed Mode

MODE1

low

MODE0

high

Normal Mode

MODE1

high

MODE0

high

Sleep Mode

CAN

float

(1) low after HVWU, high after VBAT on & VCCECU present

wake−up

request

from Bus

after 250 ms

−> no mode change

−> no valid wake−up

MODE0/1 => High

(If VCC_ECU on)

MODE0&1 => Low

MODE0/1 => High

VBAT standby

RxD

high/low(1)

MODE0/1

low

CAN

float

MODE0/1

low

NCV7356

http://onsemi.com

Figure 7. State Diagram, 14 Pin Package

HVWU Mode

MODE1

high

VBATon

INH

VBAT

MODE0

low

High−Speed Mode

MODE1

low

INH

VBAT

MODE0

high

Normal Mode

MODE1

high

INH

VBAT

MODE0

high

Sleep Mode

INH/CAN

floating

MODE0/1

low

(1) low after HVWU, high after VBAT on & VCCECU present

wake−up

request

from Bus

after 250 ms

−> no mode change

−> no valid wake−up

MODE0/1 => High

(If VCC_ECU on)

MODE0&1 => Low

MODE0/1 => High

VBAT standby

INH

VBAT

RxD

high/low(1)

MODE0/1

low

CAN

float

NCV7356

http://onsemi.com

Figure 8. Application Circuitry, 8 Pin Package

NCV7356

VBAT *

CAN Controller

2.7 kW

RxD

MODE0

MODE1

TxD

LOAD

CANH

6.49 kW

VBAT_ECU

100 pF

VBAT

GND

100 pF

47 mH

ESD Protection −

NUP1105L

ECU Connector to

Single Wire CAN Bus

*Recommended capacitance at VBAT_ECU > 1.0 mF (immunity to ISO7637/1 test pulses)

MRA4004T3

1 k

100 nF

Voltage Regulator

+5 V

VBAT

NCV7356

http://onsemi.com

Figure 9. Application Circuitry, 14 Pin Package

NCV7356

VBAT *

Voltage Regulator

VBAT

+5 V

CAN Controller

2.7 kW

RxD

MODE0

MODE1

TxD

LOAD

CANH

6.49 kW

VBAT_ECU

100 pF

VBAT

1, 7, 8, 14

GND

100 pF

47 mH

ESD Protection −

NUP1105L

ECU Connector to

Single Wire CAN Bus

*Recommended capacitance at VBAT_ECU > 1.0 mF (immunity to ISO7637/1 test pulses)

MRA4004T3

INH

1 k

100 nF

NCV7356

http://onsemi.com

SOIC−8 Thermal Information

Parameter

Test Condition, Typical Value

Unit

Min Pad Board

(Note 22)

1, Pad Board

(Note 23)

Junction−to−Lead (psi−JL7, YJL8) or Pins 6−7 57 51 °C/W

Junction−to−Ambient (RqJA, qJA) 187 128 °C/W

22. 1 oz copper, 53 mm2 coper area, 0.062″ thick FR4.

23. 1 oz copper, 716 mm2 coper area, 0.062″ thick FR4.

Package Construction

with and without Mold Compound

Figure 10. Internal construction of the

package simulation.

Figure 11. Min pad is shown as the red traces.

1, pad includes the yellow area. Internal

construction is shown for later reference.

Various copper areas used

for heat spreading

Active Area (red)

Lead #1

0 100 200 300 400 500 600 800

2.0 oz. Cu

Figure 12. SOIC−8, qJA as a Function of the Pad Copper

Area Including Traces,

Board Material

qJA (°C/W)

160

Copper Area (mm2)

1.0 oz. Cu

700

150

140

130

120

110

100

190

180

170

NCV7356

http://onsemi.com

Table 1. SOIC−8 Thermal RC Network Models*

53 mm2719 mm2Copper Area 53 mm2 719 mm2Copper Area

Cauer Network Foster Network

C’s C’s Units Tau Tau Units

5.86E−06 5.86E−06 W−s/C 1.00E−06 1.00E−06 sec

2.29E−05 2.29E−05 W−s/C 1.00E−05 1.00E−05 sec

6.98E−05 6.97E−05 W−s/C 1.00E−04 1.00E−04 sec

3.68E−04 3.68E−04 W−s/C 1.99E−04 1.99E−04 sec

3.75E−04 3.74E−04 W−s/C 1.00E−03 1.00E−03 sec

1.57E−03 1.56E−03 W−s/C 1.64E−02 1.64E−02 sec

2.05E−02 2.24E−02 W−s/C 5.60E−01 5.60E−01 sec

9.13E−02 7.35E−02 W−s/C 4.50E+00 4.50E+00 sec

2.64E−01 1.22E+00 W−s/C 7.61E+01 7.61E+01 sec

1.66E+01 9.74E+00 W−s/C 3.00E+01 3.00E+01 sec

R’s R’s R’s R’s

0.22 0.22 C/W 1.30E−01 1.30E−01 C/W

0.50 0.50 C/W 2.82E−01 2.82E−01 C/W

1.30 1.30 C/W 8.91E−01 8.91E−01 C/W

1.80 1.79 C/W 0.17 0.18 C/W

0.95 0.96 C/W 1.88 1.88 C/W

7.43 7.37 C/W 7.15 7.24 C/W

31.19 31.59 C/W 19.80 16.27 C/W

59.97 47.70 C/W 30.1 54.7 C/W

75.79 28.63 C/W 14.1 23.3 C/W

4.41 6.15 C/W 109.0 21.3 C/W

*Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network

are computed by the square root of time constant R(t) = 130 * sqrt(time(sec)). The constant is derived based on the active area of the device

with silicon and epoxy at the interface of the heat generation.

The Cauer networks generally have physical

significance and may be divided between nodes to separate

thermal behavior due to one portion of the network from

another. The Foster networks, though when sorted by time

constant (as above) bear a rough correlation with the Cauer

networks, are really only convenient mathematical models.

Both Foster and Cauer networks can be easily implemented

using circuit simulating tools, whereas Foster networks

may be more easily implemented using mathematical tools

(for instance, in a spreadsheet program), according to the

following formula:

R(t) +

i+1

Riǒ1−e−tńtauiǓ

NCV7356

http://onsemi.com

Junction

Ambient

(thermal ground)

R1R2

C1C2C3Cn

Time constants are not simple RC products.

Amplitudes of mathematical solution are not the resistance values.

Figure 13. Grounded Capacitor Thermal Network (“Cauer” Ladder)

Figure 14. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)

Junction

Ambient

(thermal ground)

R1R2

C1C2C3Cn

Each rung is exactly characterized by its RC−product time constant; Am-

plitudes are the resistances

100

1000

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

Figure 15. SOIC−8 Single Pulse Heating Curve

Cu Area = 53 mm2 1.0 oz.

Cu Area = 719 mm2 1.0 oz.

Rq (°C/W)

0.1

Cu Area = 93 mm2 1.0 oz.

0.20

100

1000

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

D = 0.50

Rq (°C/W)

0.1 Single Pulse

0.10

0.02

0.01

Figure 16. SOIC−8 Thermal Duty Cycle Curves on 1, Spreader Test Board

0.05

NCV7356

http://onsemi.com

SOIC−14 Thermal Information

Parameter

Test Condition, Typical Value

Unit

Min Pad Board

(Note 24)

1, Pad Board

(Note 25)

Junction−to−Lead (psi−JL8, YJL8) 30 30 °C/W

Junction−to−Ambient (RqJA, qJA) 122 84 °C/W

24. 1 oz copper, 94 mm2 coper area, 0.062″ thick FR4.

25. 1 oz copper, 767 mm2 coper area, 0.062″ thick FR4.

Figure 17. Internal construction of the package

simulation.

Figure 18. Min pad is shown as the red traces.

1 inch pad includes the yellow area. Pin 1, 7, 8 and

14 are connected to flag internally to the package

and externally to the heat spreading area.

100

110

120

130

140

150

0 100 200 300 400 500 600 800

2.0 oz. Cu

qJA (°C/W)

Copper Area (mm2)

1.0 oz. Cu

700

Figure 19. SOIC−14, qJA as a Function of the Pad Copper Area Including Traces,

Board Material

900

Sim 1.0 oz.

Sim 2.0 oz.

NCV7356

http://onsemi.com

Table 2. SOIC−14 Thermal RC Network Models*

96 mm2767 mm2Copper Area 96 mm2767 mm2Copper Area

Cauer Network Foster Network

C’s C’s Units Tau Tau Units

3.12E−05 3.12E−05 W−s/C 1.00E−06 1.00E−06 sec

1.21E−04 1.21E−04 W−s/C 1.00E−05 1.00E−05 sec

3.53E−04 3.50E−04 W−s/C 1.00E−04 1.00E−04 sec

1.19E−03 1.19E−03 W−s/C 0.028 0.001 sec

4.86E−03 5.05E−03 W−s/C 0.001 0.009 sec

2.17E−02 7.16E−03 W−s/C 0.280 0.047 sec

8.94E−02 3.51E−02 W−s/C 2.016 0.875 sec

0.304 0.262 W−s/C 16.64 7.53 sec

1.71 2.43 W−s/C 59.47 68.4 sec

411 W−s/C 92.221 sec

R’s R’s R’s R’s

0.041 0.041 °C/W 2.44E−02 2.44E−02 °C/W

0.095 0.096 °C/W 5.28E−02 5.28E−02 °C/W

0.279 0.281 °C/W 1.67E−01 1.67E−01 °C/W

1.154 0.995 °C/W 3.5 0.7 °C/W

5.621 6.351 °C/W 0.7 0.1 °C/W

13.180 1.910 °C/W 8.7 5.8 °C/W

23.823 21.397 °C/W 15.9 16.4 °C/W

53.332 27.150 °C/W 31.9 27.1 °C/W

24.794 25.276 °C/W 61.3 29.0 °C/W

0.218 °C/W 4.3 °C/W

*Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network

are computed by the square root of time constant R(t) = 24.4 * sqrt(time(sec)). The constant is derived based on the active area of the device

with silicon and epoxy at the interface of the heat generation.

The Cauer networks generally have physical

significance and may be divided between nodes to separate

thermal behavior due to one portion of the network from

another. The Foster networks, though when sorted by time

constant (as above) bear a rough correlation with the Cauer

networks, are really only convenient mathematical models.

Both Foster and Cauer networks can be easily implemented

using circuit simulating tools, whereas Foster networks

may be more easily implemented using mathematical tools

(for instance, in a spreadsheet program), according to the

following formula:

R(t) +

i+1

Riǒ1−e−tńtauiǓ

Junction

Ambient

(thermal ground)

R1R2

C1C2C3Cn

Time constants are not simple RC products.

Amplitudes of mathematical solution are not the resistance values.

Figure 20. Grounded Capacitor Thermal Network (“Cauer” Ladder)

Figure 21. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)

Junction

Ambient

(thermal ground)

R1R2

C1C2C3Cn

Each rung is exactly characterized by its RC−product time constant; Am-

plitudes are the resistances

NCV7356

http://onsemi.com

0.01

100

1000

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Time (s)

Figure 22. SOIC−14 Single Pulse Heating

Cu Area = 96 mm2 1.0 oz.

Cu Area = 767 mm2 1.0 oz.

Rq (°C/W)

0.1

Cu Area = 767 mm2 1.0 oz. 1S2P

0.20

0.01

100

1000

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

PULSE DURATION (sec)

D = 0.50

(

)

0.1

Cu Area = 717 mm2 1.0 oz.

0.10

0.05

0.01

Figure 23. SOIC−14 Thermal Duty Cycle Curves on 1, Spreader Test Board

NCV7356

http://onsemi.com

PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

P7 PL

14 8

0.25 (0.010) B M

0.25 (0.010) A S

−T−

RX 45

SEATING

PLANE D14 PL K

_DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

__ __

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

NCV7356

http://onsemi.com

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45_

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental

damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over

time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under

its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,

or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,

subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.

SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

NCV7356/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your loc

Sales Representative