1/53
AN1762
APPLICATION NOTE
December 2003
1 INTRODUCTION
The L6205, L6206, L6207 are highly integrated, mixed-signal power ICs that allow the user to easily design a
control system for two-phase bipolar stepper motors, multiple DC motors and a wide range of inductive loads.
Figu re 1 to Figu re 3 s how the L6205, L6206, L6207 block di agram s. Eac h IC integ rates eight Power DMOS plus
other added features for safe operation and flexibility. T he L6207 also features a constant t
OFF
PWM current
control technique (
Synchronous mode
) for each of the two full bridges.
Figure 1. L6205 block diagram.
D99IN1091A
GATE
LOGIC
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
V
BOOT
5V
10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V 10V
BRIDGE A
BRIDGE B
SENSE
B
OCD
A
OCD
B
by Vincenzo Marano
L6205, L6206, L6207 DUAL FULL BRIDGE DRIVERS
Modern motion control applications need more flexibility that can be addressed only with specialized IC
products. The L6205, L6206, L6207 are dual full bridge drivers ICs specifically developed to drive a wide
range of motors. These ICs are one-chip cost effective solutions that include sever al unique circuit design
features. These features allow the devices to be used in many applications including DC and stepper motor
drivi ng. The principal aim of this developm ent project was to produce easy to use, ful ly protected pow er ICs.
In addi tion se veral k ey functi ons s uch as protection circuit and PWM cur rent c ontrol dr astic ally reduce ex ter-
nal components count to meet requirements for many different applications.
AN1762 APP LICATION NOTE
2/53
Figure 2. L6206 block diagram.
Figure 3. L6207 block diagram.
D99IN1088A
GATE
LOGIC
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
V
BOOT
5V
10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V 10V
BRIDGE A
BRIDGE B
SENSE
B
PROGCL
B
OCD
B
OCD
A
PROGCL
A
OCD
A
OCD
B
D99IN1085A
GATE
LOGIC
OCD
A
OCD
B
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
VREF
A
V
BOOT
5V10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR ONE SHOT
MONOSTABLE MASKING
TIME
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V 10V
BRIDGE A
SENSE
COMPARATOR
BRIDGE B
RC
A
+
-
SENSE
B
VREF
B
RC
B
PWM
3/53
AN1762 APPLICATION NOTE
Table of Contents
1 INTRODUCTION................................................................................................................................1
2 MAIN DIFFERENCES BETW EEN L6205 , L6206, L6207 .... ................. ............ .............. ............... ....4
3 DES IGN ING AN A PPLICA TION WI TH L620 5, L6206 , L6207 ................ . ..................................... . ....4
3.1 Current Ratings........................................................................................................................4
3.2 Vol tage Ratings and Op erating Range .... ..................................... . ..................................... . ....4
3.3 Ch oosing the Bulk Capacitor. ..................................... . ..................................... . .......................6
3.4 Layout Consid erations .............................................................................................................7
3.5 Sensing Resistors...... ......................................................... .....................................................9
3.6 Charge pump external components... .... ................... ................... ................... ................... ....10
3.7 Shari ng the Charge Pump Circuitry .......................................................................................11
3.8 Reference Voltage fo r PWM Current Control (L6207 ONLY)............... . ................ ................. 12
3.9 Input Logic pins......................................................................................................................13
3.10 EN pins...................................................................................................................................13
3.11 Program mab le off-time Monost able (L6207 ON LY)............................................... . ..............14
3.11.1 Off-time Selection and minimum on-time (L6207 ONLY)................................................16
3.11.2 Slow Decay Mode (L6207 ONLY ) .......................................... .........................................17
3.12 Over Current Protectio n........................................................................................................18
3.13 Adjusting the Ove r Current Detection tri p point (L6206 ONLY) ............................................21
3.14 Paralleling two Full Bridges................................ . ................................ ..................................23
3.14.1 Paralleling t wo Ful l Bridges to get a single Full Bridge ....................................................23
3.14.2 Paralleling th e four Half Bridges to get a single Half Bridge.............................................26
3.15 Power Managem ent. ................ ........................ ..................... ................... . ............. ...............27
3.15.1 Maximum o utpu t current vs. selectable devices..............................................................27
3.15.2 P owe r Dissipation Formulae for different sequences.................... ................... . ..............28
4 APPLICATION EXAMPLE (L6207)..................................................................................................32
4.1 Decay mode, sensing resistors and reference voltage..........................................................32
5 APPE N DIX - EVAL UATION BOARDS.. ........................................................ ...................................33
5.1 PractiSPIN..............................................................................................................................33
5.2 EVAL6205N ...........................................................................................................................34
5.2.1 Imp o r ta n t Not e s..................... ........................................................ .............................. .....35
5.3 EVAL6206N ...........................................................................................................................39
5.3.1 Imp o r ta n t Not e s..................... ........................................................ .............................. .....40
5.4 EVAL6206PD.........................................................................................................................44
5.4.1 Imp o r ta n t Not e s..................... ........................................................ .............................. .....45
5.5 EVAL6207N ...........................................................................................................................49
5.5.1 Imp o r ta n t Not e s..................... ........................................................ .............................. .....50
6 REFERENCES.................................................................................................................................53
AN1762 APP LICATION NOTE
4/53
2 MAIN DIFFERENC ES BETWE EN L6205, L6206, L6207
L6205, L6206 and L6207 are DMOS Dual Full Bridge ICs.
L6205 (see F igure 1) includes logic for CMOS/TTL interface, a charge pump that provide auxiliary voltage to
drive the high-side DMOS, non dissipative over current protection circuitry on the high-side DMOS, with fixed
trip point set at 5.6 A (see
Over Current Protection
Section), over tem perat ure protection, Under Voltage Lock-
Out for reliable start-up.
In addition, L6206 gives the possibility of adjusting the trip point of the over current protection for each of the
two full-bridges (through two external resistors), and its internal open-drain mosfets (see
Over Current Protec-
tion
S ecti on) are not internal ly connecte d to
EN
pins but to separat e
OCD
pins,
allo wing easier e xternal diagnos-
ti cs and overcurrent managem ent.
L6207 has Over Current protection function with fixed trip point set at 5.6 A and internal open-drain mosfets
connected to
EN
pins, as the L6205, but it also integrates tw o PWM current controller for each of the two full-
bridges (see
Programmable off-time Monostable
section).
3 DESIGNI NG AN APPLICATION WITH L6205, L6206, L6207
3.1 Current Ratings
With MOSFET (DMOS) devices, unlike bipolar transistors, current under short circuit conditions is, at first ap-
prox imation, limited by the R
DS(ON)
of the DMOS themselves and could reach very high values. L6205, L6206,
L6207
Out
pins and the two V
SA
and V
SB
pins are rated for a maximum of 2.8A r.m.s. and 5.6A peak (typical
values), corresponding to a total (for the whole IC) 5.6A rms ( 11.2A peak). These values are meant to avoid
damaging metal structures, including the metallization on the die and bond wires. In practical applications,
though, maximum allowable current is less than these values, due to power dissipation limits (
see
Power
Management
section
). The devices have a built-in Over Current Detection (OCD) that provides protection
against short circuits between the outputs and between an output and ground (
see
Over Current Protection
section
).
3.2 Voltage Ratin gs an d Operat ing Range
The L6205, L6206, L6207 requires a single suppl y voltage (V
S
), for the motor supply . Internal voltag e regu lators
provide the 5V and 10V required for the internal circuitry. The operating range for V
S
is 8 to 52V. To prevent
working into undesir abl e low supply voltage an
Under Voltage Loc k Out
(
UVLO
) circuit shuts down the device
when supply voltage falls below 6V; to resume normal operating condi tions, V
S
must then exceed 7V. The hys-
teresis is provided to avoid false intervention of the UVLO function during fast V
S
ringings. It should be noted,
however, that DMOS's R
DS(ON)
is a function of the V
S
supply voltage. Actually, when V
S
is less than 10V,
R
DS(ON)
is adversely affected, and this is particularly true for the High Side DMOS that are driven from V
BOOT
supply. This supply is obtained through a charge pump from the internal 10V supply, which will tend to reduce
its output voltage when V
S
goes below 10V. Figure 4 shows the supply voltage of the high side gate drivers
(V
BOOT
- V
S
) versus the supply voltage (V
S
).
5/53
AN1762 APPLICATION NOTE
Figure 4. High side gate drivers sup ply voltage versu s sup ply voltage.
Note that V
S
must be c onnected to both V
SA
and V
SB
since the bootstrap voltage (at V
BOOT
pin) i s the same for
the tw o H-bridges. The integrated DMOS have a rated Drain-Source breakdown voltage of 60V. However V
S
should be kept below 52V, since in normal working conditions the DMOS see a V
ds
voltage that will exceed V
S
supply. In par tic ular, during a phase change ( when each output of the same H-bridge sw itches from V
S
to GND
or vice versa, for example to reverse the current in the load) at the beginning of the dead-time (when all the
DMOS are off) the
SENSE
pin sees a negative spike due to a not negligible parasitic inductance of the PCB
path from the pin to G ND. This spike is followed by a stable negative voltage due to the drop on R
SENSE
. One
of the two
OUT
pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forw ard
reco very time of the integrated freewheeling di ode and the forward voltage drop acr oss it (see Figure 5). Typical
durati on of this spike is 30ns . At the same time, the other
OUT
pin of the sam e bridge sees a vol tage above V
S
,
due to the PCB in ductance and v oltage drop acr oss the h igh-side (integr ated) freewheeling diode, as the current
rever ses direction and flows into the bulk capacitor . It turns out that the highest differential voltage can be ob-
served between the two
OUT
pins of the same bridge, during the dead-time at a phase change, and this must
always be kept below 60V [3].
Figure 5. Currents and voltages d uri ng the
dead tim e
at a pha se chan ge.
VS [V]
VBOOT - VS
[V]
6
6.4
6.8
7.2
7.6
8
8 8.5 9 9.5 10 10.5
V
S
SENSE
OUT1
OUT2
RSENSE*I
RSENSE*I+VF(Diode)
PC B Pa r a s i ti c
Inductance
PCB Parasitic
Inductance
Bulk Capacitor
Equivalent Circuit
ESR
ESL
RSENSE
VS+VF(Diode)
Dangerous
High Differential Voltage
AN1762 APP LICATION NOTE
6/53
Figu re 6 shows the voltage waveforms at the two OUT pins r eferring to a pos sible practical situation, w ith a peak
output current of 2.8A, V
S
= 52V, R
SENSE
= 0.33
Ω
, T
J
= 25°C (approximately) and a good PCB layout. B elow
ground spike amplitude is -2.65V for one output; the other
OUT
pin is at about 57V . In these conditions, total
differ ential v oltage reaches almost 60V, which is the a bsolute max imum rating for the DMOS. Keeping differ en-
tial voltage between two Output pins belonging to the same Full Bridge within rated values is a must that can
be accomplished with proper selection of Bulk capacitor value and equivalent series resistance (ESR), accord-
ing to current peaks and chopping style and adopting good layout practices to minimize PCB parasitic induc-
tances (see below) [3].
Figu re 6. V ol ta ge a t th e tw o outputs during the
dead time
at a pha se chan ge.
3.3 Choosing the Bulk Capacitor
Sinc e the bulk capacitor, placed between V
S
and
GND
pi ns, is char ged and discharged during IC operation, its
AC current capability
must be greater than the r.m.s. value of the charge/discharge current. In the case of a
PWM current regulation, the current flows from the capacitor to the IC during the on-time (t
ON
) and from the IC
(implementing a fast decay current recirculation technique) or from the power supply (implementing a slow de-
cay current recirculation technique) to the capacitor during the off-time (t
OFF
). The r.m.s. value of the current
flowing into the bulk capacito r depends on peak output current, output current rippl e, sw itchin g frequency, duty-
cycle and chopping style. It also depends on power supply characteristics. A power supply with poor high fre-
quency performances (or long, inductive connections to the IC) will cause the bulk capacitor to be recharged
slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s.
current in the capacitor, however, does not exceed the r.m.s. output current. Bulk capacitor value (
C
) and the
ESR
determine the amount of voltage ripple on the capacitor itself and on the IC. In slow decay, neglecting the
dead-time
and output cur rent ripple, and assuming that during the
on-time
the capacitor is not recharged by the
power supply, the voltage at the end of the
on-time
is:
,
so the supply voltage ripple is:
,
Out 2
Out 1
VSIOUT
–ESR tON
C
---------+
⋅
I
OUT ESR tON
C
---------+
⋅
7/53
AN1762 APPLICATION NOTE
where I
OUT
is the outp ut current. Wit h f ast decay, i nstead, recirculating current r echarges the capacitor, caus ing
the supply voltage to exceed the nominal voltage. This can be very dangerous if the nominal supply voltage is
close to the maximum recommended supply voltage (52V). In fast decay the supply voltage ripple is about:
,
always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple
and the dead-tim e. Usually (if C > 100 µF) the capacitance role is much less than the ESR, then supply v oltage
ripple can be estimated as:
I
OUT
· ESR in slow decay
2 · I
OUT
· ESR in fast decay
For Example, i f a maximum r i pple of 500mV is all owed and I
OUT
= 2A, the capac itor ESR should be low er than:
in slow decay, and
in fast decay.
Actually, cur rent sunk by V
SA
and V
SB
pins of the device is subject to higher peaks due to reverse recovery
charge of internal freewheeling diodes. D uration of these peaks is, tough, very short, and can be filtered using
a small value (100÷200 nF), good quality ceramic capacitor, connected as close as possible to the V
SA
, V
SB
and GND pins of the IC. Bulk capac itor will be chosen with
maximum operating voltage
25% gr eater than the
maximum supply voltage, considering also power supply tolerances. For example, with a 48V nominal pow er
supply, with 5% tol eranc e, maximum voltage is 50.4V, then operati ng voltage for the capacitor s hould be at l east
63V.
3.4 Layout Considerations
Working with devices that combine high power switches and control logic in the same IC, careful attention has
to be paid to the PCB lay out. In extreme cases, Power DM OS commutati on can i nduce nois es that could c ause
improper operation in the logic section of the device. Noise can be radiated by high dv/dt nodes or high di/dt
paths, or cond ucted through G ND or Supply connectio ns. Logic connec tions, es pecial ly hi gh-i mpedance nodes
(act ually all logic inputs, see further ), must be kept far from switching nodes and paths. With the L6205, L6206,
L6207, in particular , external components for the charge pump circuitry should be connected together through
short paths, since these components are subject to voltage and current switching at relatively high frequency
(600kHz). Primary mean in minimizing conducted noise is working on a good GND layout (see Figure 7).
IOUT 2 ESR⋅tON tOFF
+
C
----------------------------+
⋅
ESR 0.5V
2A
------------
<250mΩ=
ESR 1
2
--- 0.5V
2A
------------
⋅< 125mΩ=
AN1762 APP LICATION NOTE
8/53
Figu re 7. Typical Applicat i on an d Layou t su ggestions .
High cur rent GN D tracks (i.e. the tracks connected to the sensing resistors) must be connected directly to the
negative terminal of the bulk capacitor. A good quality, high-frequency bypass capacitor is also required (typi-
cally a 100nF ÷200nF ceramic would suffice), since electrolytic capacitors show a poor high frequency perfor-
manc e. Both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to
V
SA
, V
SB
and GND. On the L6205, L6206 , L6207 GND pins are the
Logic
GND, since onl y the quiescent cur rent
flows through them. Logic GND and Pow er GND should be connected together in a
single point
, the bulk ca-
pacitor, to keep noise in the Power GND fr om affecting Logic GN D. Specific car e should be paid layouting the
path from the
SENSE
pins through the sensing resistor s to the negative terminal of the bulk capacitor (Power
Ground) . These tracks must be as short as possible in order to minimize parasitic inductances that can cause
danger ous voltage spikes on
SENSE
and
OUT
pins (see the
Voltage Ratings and Operating Range
section);
for the same reason the capacitors on V
SA
, V
SB
and G ND should be very close to the GND and supply pins.
Refer to the Sensing Resistors section for information on selecting the sense resistors. Traces that connect to
V
SA
, V
SB
, SENSE
A
, SENSE
B
, and the four
OUT
pins must be designed with adequate width, since high currents
are flowing through these traces, and layer changes should be avoided. Should a layer change prove neces-
sary, multiple and large via holes have to be used. A wide GND copper area can be used to improve power
dissipation for the device.
Figu re 8 shows two typical situations that must be avoided. An important considerati on about the location of the
bulk capaci t ors is the abi lity to abs orb the inductiv e energy fr om the load, without all owing the s upply voltage to
exceed the maximum rating. The diode shown in Figure 8 prevents the recirculation current from reaching the
capacitor s and will result in a hi gh voltage on the IC pins th at can destroy the device. H aving a switch or a power
connection that c an dis connect the c apacitors fr om the IC, w hile there is still cur rent in the motor, will a lso result
in a high voltage transient since there is no capacitance to absorb the recirculation current.
+
-
VS = 8 ÷ 52 V
GND
GND GND
GND
SENSEA
SENSEB
VSA VSB
VBOOT CP
OUT1B OUT2B
OUT1A OUT2A
D1 D2
R1
RS1 RS2
C3
C4
C1
C2
L 6205, L6206, L6207
Motors or
other loads
Logic
GND
9/53
AN1762 APPLICATION NOTE
Figure 8. Two situations that must be avoided.
3.5 Sensing Resistors
Each motor winding current is flowing through the corr esponding sensing resistor, causing a voltage dr op that
can be used, by the logic (integrated in the L6207; an external logic can be used with L6205 and L6206), to
control the peak value of the load current. Two issues must be taken into account when choosing the R
SENSE
value:
– The sensing resistor dissipates energy and provides dangerous negative voltages on the
SENSE
pin
during the current recirculation. For thi s reason the resistance of this c om pon ent shoul d be kept l ow.
– The voltage drop across RSENSE is compared with a reference voltage (on Vref pin) by the internal c om-
parator (L6 207 only). The lo wer is the RSENSE value, the higher is the peak curre nt error du e t o noise
on Vref pin and to the input offs et of the current sense comparator: too small values of RSENSE must be
avoided.
A good compromis e i s calculating the sensi ng res istor value so that the voltage drop, corresponding to the peak
current in the load (I
peak
), is about 0.5 V: R
SENSE
= 0.5 V / I
peak
.
It should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous neg-
ative spik es on
SENSE
pins. Wire-w ounded resistor s c annot be used here, whi le Metall ic film res istors ar e rec-
ommended for their high peak current capability and low inductance. For the same reason the connections
between the
SENSE
pins, C6, C7, V
SA
, V
SB
and
GND
pins (see Figure 7) must be taken as short as possible
(see also the
Layout Considerations
section).
The average power dissipated by the sensing resistor is:
Fast Decay Recirculation: P
R
≈
I
rms2
· R
SENSE
Slow Decay Recir culation: P
R
≈
I
rms2
· R
SENSE
· D,
D is the duty-cycle of the PWM current control, I
rms
is the r.m.s. value of the load current.
GND
GND
GND
GND
SENSE
A
SENSE
B
V
SA
V
SB
R5
C7
C6
L6205, L6206, L6207
DON ’T conne ct the Logi c GND h ere
Voltage drop du e to current in s ens e
path can dis turb lo gic GND.
DON’T put a di ode here!
Rec ircul ating c urrent c ann ot flo w i nto t he
bulk c apaci t or and causes a high v olt age
spike that c an des troy the IC .
+
-
V
S
= 8 ÷ 52 V
AN1762 APP LICATION NOTE
10/53
Nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissi-
pated power:
,
where I
pk
is the peak value of the load current.
Using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and re-
duce the inductance.
R
SENSE
tolerance reflects on the peak current error: 1% resistors should be preferred.
The following table show s R
SENSE
recommended values (to ha ve 0.5V d rop on it) and power ratings for typical
examples of current peak values.
3.6 Charge pump external components
An internal oscillator, with its output at
CP
pin, switches from GND to 10V w ith a typical frequency of 600kHz
(see Figure 9).
Figu re 9. Cha rge Pum p .
When the oscillator output is at ground, C
5
is charged by V
S
through D
2
. When it rises to 10V, D
2
is rev er se
biased and the charge flows from C
5
to C
8
through D
1
, so the V
BOOT
pin, after a few cycles, reaches the max-
imum voltage of V
S
+ 10V - V
D1
- V
D2
, which supplies the high-side gate drivers.
With a differenti al vol tage betw een V
S
and V
BOOT
of about 9V and both the bridges swit ching at 50kHz, the typ-
ical current drawn by the V
BOOT
pin is 1.85 mA.
Ipk RSENSE Value
[Ω]
RSENSE Power Rating
[W] Alternatives
0.5 1 0.25
1 0.5 0.5 2 X 1Ω, 0.25W paralleled
1.5 0.33 0.75 3 X 1Ω, 0.25W paralleled
2 0.25 1 4 X 1Ω, 0.25W paralleled
PRIpk2RSENSE
⋅≈
L6205, L6206, L6207
VS + 10 V - VD1
VS - VD1
f = 600 kHz
VSA VSB
VBOOT CP
D1 D2
R4
C8
C5
RDS(ON) = 70Ω
10 V
10 V
5 V
RDS(ON) = 70Ω
To High-Side
Gate Drivers
10 V
f = 600 kHz
Charge Pump
Oscillator
VS + 10 V - VD1 - VD2
11/53
AN1762 APPLICATION NOTE
Resistor
R4
is added to r educe the maxi mum cur rent i n the external components and to r educe the slew r ate of
the rising and falling edges of the voltage at the
CP
pin, in order to minimize interferences w ith the rest of the
cir cuit. For the same reason care must be taken in r ealiz ing the PC B layout of
R4
,
C5
,
D1
,
D2
connections ( see
also the
Layout Considerations
section). Recommended values for the charge pump circuitry are:
D1, D2 : 1N4148
R4 : 100
Ω (1/8 W)
C5 : 10nF 100V ceramic
C8 : 220nF 25V ceramic
Due to the high charge pump frequency, fast diodes ar e requi red. C onnecting the cold side of the bulk capacitor
(C8) to V
S
instead of GND the average current in the external diodes during operation is less than 10 mA (with
R4 = 100
Ω
); at startup ( when V
S
is provided to the IC) is less than 200 mA while the reverse voltage is about
10 V in all condi tions. 1N4148 diodes withstand about 200 mA DC (1 A peak ), and the maximum reverse v oltage
is 75 V, so they should fit for the majority of applications.
3.7 Sharing the Charge Pump Circuitry
If more than one device is used in the application, it's possible to use the charge pump from one L6205, L6206
or L6207 to supply the V
BOOT
pins of several ICs. The unused
CP
pins on the slaved devices are left uncon-
nected, as shown in Figure 10. A 100nF capacitor (C8) should be connected to the V
BOOT
pin of each device.
Supply voltage pins (V
S
) of the devices sharing the charge pump must be connected together.
The higher the number of devices sharing the same char ge pump, the lowe r will be the d ifferential voltage avail-
able for gate drive (V
BOOT
- V
S
), causing a higher R
DS(ON)
for the high s ide DMO S, s o higher dissipating po wer .
In this case it's recommended to omit the resistor on the
CP
pin, obtaining a higher current capability of the
charge pump circuitry.
Better per formance can als o be obtained using a 33nF capacitor for C5 and using s chottky diodes (for ex ample
BAT47 are recommended).
Sharing the same char ge pump ci rcuitr y fo r more than 3÷4 devices is not r ecommended, sinc e it wil l reduce the
V
BOOT
voltage increasing the high-side MOS on-resistance and thus power dissipation.
Figu re 10 . Sha r in g th e c harge pu m p cir c ui tr y.
V
SA
V
SB
V
BOOT
CP
C18 = 100 nF
To High-Side
Gate Drivers
V
SA
V
SB
V
BO OT
C8 = 100nF
To High-Side
Gate Dr iver s
To other Devi ces
CP
L6205, L6206, L6207
L6205, L6206, L6207
D1 = BAT47 D2 = BAT47
C5 = 33nF
AN1762 APP LICATION NOTE
12/53
3.8 Reference Voltage for PWM Current Control (L6207 ONLY)
The L6207 has two analog inputs, V
refA
and V
refB
, connected to the internal sense comparators, to control the
peak val ue of the motor current thr ough th e integrated PWM circuitry . In ty pical applic ations these p ins ar e con-
nected together , in order to obtain the same cur rent i n the two m otor windings. A fixed referenc e vol tage can be
easily obtained through a resistive divider from an available 5 V voltage rail (maybe the one supplying the µC
or the rest of the application) and GND.
A very simple way to obtain a var iable voltage without using a DAC is to low-pass filter a PWM output of a µC
(see Figure 11).
Assuming that the PWM output swings from 0 to 5V, the resulting voltage will be:
where D
µC
is the duty-cycle of the PWM output of the µC.
Assuming that the µC output impedance is lower than 1k
Ω,
with R
LP
= 56k
Ω
, R
DIV
= 15k
Ω
, C
LP
= 10nF and a
µC PW M switchi ng fr om 0 to 5V at 100kHz, the low pass fi lter tim e consta nt is about 0.12 ms an d the remai ning
ripple on the V
re f
voltage will be about 20 mV. Using higher values for R
LP
, R
DIV
and C
LP
will reduce the ripple,
but the reference voltage w ill take mor e time to vary after changing the duty -cycle of the µC PWM, and too high
values of R
LP
will als o increase the im pedance of the V
ref
net at low frequen cies, causing a poor nois e immunity.
As sensing resistor values are typically kept small, a small noise on V
ref
input pins might cause a considerable
error in the output cur rent. It's then recomm ended to decouple these pins with cerami c capaci tors of some tens
of nF, placed very close to V
ref
and GND pins. Note that V
ref
pins cannot be left unconnec ted, while, if connected
to GND, zero current is not guaranteed due to voltage offset in the sense comparator. The best way to c ut down
(IC) power consumption and clear the load current is pulling down the
EN
pins. With very small reference volt-
age, PWM integrated circuitry can loose control of the current due to the minimum allowed duration of t
ON
(see
the
Programmable off-time Monostable
section).
Figure 11. Obtaining a vari able voltage thr ough a PW M outpu t of a µC.
Vref 5V DµCRDIV
⋅⋅
R
LP RDIV
+
-----------------------------------------=
RLP
CLP
Vref
GND
PWM Output
of a µC
RDIV
13/53
AN1762 APPLICATION NOTE
3.9 I np ut Log ic pins
IN1
A
, IN2
A
, I N 1
B
, IN2
B
are CM OS /TTL compa tible logic i nput pins . The input comparator has been realized with hys-
ter esis t o ensure t he require d noise i mmuni ty. Typ ical val ues for tur n-on and t urn-of f thresh olds ar e V
th,ON
= 1.8V and
V
th,OFF
= 1.3 V. Pins are ESD protected (s ee Figure 12 ) (2kV human- body electro- static discharge), and can be d irectly
connec ted to the logi c outp uts of a µC; a ser ies resis tor is gen erall y not r ecommende d, as i t could hel p induct ed nois e
to di sturb the inputs . All l ogi c pins e nforce a specifi c behavior and cannot be left unconnect ed.
Figure 12. Logic i nput pins.
3.1 0EN pi ns
The
EN
A
, EN
B
pins are, ac tually, bi-directional: as an input, with a comparator similar to the other logic input pins (TTL/
CMOS with hysteresis), they control t he stat e of the PowerDMOS. When each of the t wo pins i s at a l ow logic level,
al l the PowerDMOS of the cor responding H-bridge (A or B) are t urned off. In L6205 and L6207 the EN pins are also
connected to the two corresponding open drain outputs of the pr otect ion circuits that will pull the pins to GND if over
current in the corresponding H-bridge or over temperature conditions exist. In L6206 the open drain output s are on
separate pi ns, O C D
A
and OCD
B
, al lowing eas ie r external di agnostic s and overcur rent management. For th is reason,
with L6205 and L6207 (and L6206 if EN pins are connected to DIAG pins) EN pins must be driven through a series
resistor of 2.2k
Ω
m i nimum (for 5V logic), t o allow the voltag e at the pin t o be pulled below the turn-o ff thr eshold.
A capacitor (C
EN
in Fi gure 13) connec ted between each EN pin and GND is also r ecommended, to reduce the r.m.s.
value of the output cur rent when overcurrent conditions persi st (see
Over Current Protection
section). EN pin must
n ot be left unconnected.
Figure 13. ENA and ENB in put pi ns.
5V
D01IN1329
ESD
PROTECTION
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
A
or EN
B
OCD
A
or OCD
B
5V
PUSH-PULL
OUTPUT
R
EN
C
EN
EN
A
or EN
B
EN
A
or EN
B
L6205, L6207 L6206
AN1762 APP LICATION NOTE
14/53
3.11 Programmab le off-time Monostab le (L6207 ONL Y)
The L6207 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected be-
tween the source of the two lower power MOS transistors and ground, as shown in Figure 14. As the current in
the load builds up the voltag e across the sens e re sistor increases pr oportionally . When the voltage drop ac ross
the sense resistor becomes greater than the voltage at the reference input (VREF
A
or VRE F
B
) the sense com-
parator triggers the monostable switc hing the low-side MOS off. The low-side MOS remain off for the time set
by the monostable and the motor current recirculates in the upper path. When the monostable times out the
bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays
the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time.
Figure 14. PWM Current Control Circuitry (L6207 ONLY).
Figure 15 shows the typical operating waveforms of the output current, the voltage drop across the sensing re-
sistor, the R C pin voltage and the status of the bridge. Immediately after the low-side Power MOS turns on, a
high peak current flow s through the sen sing resistor due to the rev ers e recovery of the freewheeling diodes . The
L620 7 provides a 1
µs
Blanki ng Time t
BLANK
that inhibits the com parator output s o that this current spike cannot
prematurely re-trigger the monostable.
DRIVERS
+
DEAD TIME
S
Q
RDRIVERS
+
DEAD TIME
2H 1H
2L 1L
OUT2A(or B)
SENSEA(or B)
RSENSE
D02IN1352
RCA(or B)
ROFF
COFF
VREFA(or B)
IOUT
OUT1A(or B)
+
+
-
-
1µs
5mA
BLANKER
SENSE
COMPARATOR
COMPARATOR
OUTPUT
MONOSTABLE
RESET
2.5V
5V
FROM THE
LOW-SIDE
GATE DRIVERS
LOADA
(or B)
BLANKING TIME
MONOSTABLE
VSA (or B)
TO GATE LOGIC
(0) (1)
15/53
AN1762 APPLICATION NOTE
Figure 15. PWM Output Current Regulatio n Waveforms (L6207 ONLY).
Figur e 16 shows the magnitude of the Off Time t
OFF
versus C
OFF
and R
OFF
values. It can be approximately
calculated from the equations:
t
RCFALL
= 0.6 · R
OFF
· C
OFF
t
OFF
= t
RCFALL
+ t
DT
= 0.6 · R
OFF
· C
OFF
+ t
DT
where R
OFF
and C
OFF
are the external component values and t
DT
is the internally generated Dead Time with:
20K
Ω
≤
R
OFF
≤
100K
Ω
0.47nF
≤
C
OFF
≤
100nF
t
DT
= 1µs (typical value)
Therefore:
t
OFF(MIN)
= 6.6µs
t
OFF(MAX)
= 6ms
These values allow a sufficient range of t
OFF
to implement the drive circuit for most motors.
The capacitor value chosen for C
OFF
also affects the Ri se Time t
RCRISE
of the voltage at the pin RC
A
(or RC
B
).
The Rise Time t
RCRISE
will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time t
ON
, which depends by motors and supply parameters, has to
OFF BCDDA
t
ON
t
OFF
BC
ON
2.5V
0Slow Decay Slow Decay
1µs t
BLANK
t
RCRISE
t
RCRISE
SYNCHRONOUS RECTIFICATION
1µs t
BLANK
5V
V
RC
V
SENSE
V
REF
I
OUT
V
REF
R
SENSE
D02IN1351
t
OFF
1µs t
DT
1µs t
DT
t
RCFALL
t
RCFALL
AN1762 APP LICATION NOTE
16/53
be bigger than t
RCRISE
for allowing a good current regulation by the PWM stage. Furthermore, the on time t
ON
can not be smaller than the minimum on time t
ON(MIN)
.
t
RCRISE
= 600 · C
OFF
3.11.1 Off-time Selection and minim um on-time (L6207 ONLY)
Figur e 16 also shows the lower limit for the on time t
ON
for having a good PWM current regulation capacity. It
has to be said that t
ON
is always bigger than t
ON(MIN)
because the device imposes this condition, but it can be
smaller than t
RCRISE
- t
DT
. In this last case the device continues to work but the off time t
OFF
is not more con-
stant.
So, small C
OFF
value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for C
OFF
, the more influential will be the noises on the cir cuit
performance.
Figure 16. Off-time selection and minimum on-time (L6207 ON LY).
tON tON MIN()
>1.5µs (typ. value )=
tON tRCRISE tDT
–>
0.1 1 10 100
1
10
100
1.10 3
1.10 4
Co ff [nF]
to f f [us]
0.1 1 10 100
1
10
100
Coff [nF]
to n ( m in ) [ u s]
R = 20 k
Ω
R = 47 k
Ω
R = 100 kΩ
17/53
AN1762 APPLICATION NOTE
3.11.2 Slow Decay Mode (L6207 ONLY)
Figu re 17 s hows the operation of the bridge i n the Sl ow De cay mode. At the start of the off ti me, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the s ynchro-
nous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 17. Slow Decay Mode Output Stage Configuration s
In some conditions (short off-time, ver y low regulated current, high motor winding L / R) the system may need
an on-time shorter than 1.5µs. In these cases the PWM current controller can loose the regulation.
Figur e 18 shows the operation of the circuit in this condition. W hen the current first reaches the threshold, the
brid ge is turned off for a fixed time and the cur rent decays. During the foll owing on-ti me current increases above
the threshold, but the bridge cannot be turned off until the minimum 1.5µs on-time expires. Since current in-
crea ses more i n ea ch o n-ti me th an i t dec ays during the o ff-time, it keeps growing during each cycle, wi th s teady
state asymptotic value set by duty- cycle and load DC resistance: the resulting peak current will be
I
pk
= V
S
· D / R
LOAD
,
where D = t
ON
/ (t
ON
+ t
OFF
) is the duty-cycle and R
LOAD
is the load DC resistance.
Figure 18. Minimum on-time can cause the PWM controll er to loose the regulation ( L6207 ONLY).
A) ON TIME B) 1µs DEAD TIME C) SYNCHRONOUS
RECTIFICATION D) 1µs DEAD TIME
D01IN1336
needed tON is
less
than 1.5 µs
minimum t
ON
is about 1.5 µs
Vref / RSENSE
AN1762 APP LICATION NOTE
18/53
3.12 Over Current Protection
To implement an Over C urre nt (i.e. short ci rcuit) Protection, a dedicated Over Current D etection (OCD) cir c uitry
(see Figu re 19 for a simpli fied schematic) senses the current in each high side. P ower DMO S are actuall y made
up with thousands of individual identical cells, each carrying a fraction of the total current flow ing. The current
sensing element, connected in par allel to the Power DMOS, is made onl y w ith few such cells , havi ng a 1:N ratio
compared to the power DMOS. The total drain current is split between the output and the sense element ac-
cording to the cell ratio. Sensed current is, then, a small fraction of the output current and will not contribute
significantly to power dissipation.
Figure 19. Over Curren t Detection si mplified ci rcuitry.
+
OVER
TEMPERATURE
I
REF
I
REF
(I
1A
+I
2A
) / n
I
1A
/ n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1
A
OUT2
A
VS
A
I
1A
I
2A
I
2A
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40Ω TYP.
C
ENA
R
ENA
R
CLA
.
EN
A
OCD
A
PROGCL
A,
+5V
1.2V
-
+
µC or LOGIC
+
OVER TEMPERATURE
I
REF
(I
1A
+I
2A
) / n
I
1A
/ n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1
A
OUT2
A
VS
A
I
1A
I
2A
I
2A
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40Ω TYP.
C
EN
R
EN
EN
A
+5V
µC or LOGIC
L6206
L6205, L6207
19/53
AN1762 APPLICATION NOTE
This sensed cur rent is co mpared to an inter nall y generated reference ( adj ustable through the exter nal resi stors
R
CLA
and
R
CLB
for L6206) to detec t an over cur rent conditi on. A n i nternal open drain mosfet turns on when the
sum of the currents in the bridges 1A and 2A or 1B and 2B reaches the threshold (5.6A typical value for L6205
and L6207; adjus table through the external resistors
R
CLA
and
R
CLB
for L6206); in L6205 and L6207 the open
drai n are internally c onnected to the
EN
pins; with L6206
OCD
pins s hould be c onnected to
EN
pins to allow the
protection w orking. To ensure an over current protection, connect these pins to an external R C network (see
Figure 19).
Figur e 20 shows the device operating in overcurrent condition (short to ground). When an over current is de-
tected the internal open drain mosfet pull the
EN
pin to GND switching off all 4 pow er DMOS of the interested
bridge and allowing the cur rent to decay. Under a persistent over current condition, like a short to ground or a
shor t between two output pins, the external RC network on the
EN
pin (see Figure 19) reduces the r.m.s. value
of the output curr ent by imposing a fixed disable-time after each over cur rent occurrence. The values of
R
EN
and
C
EN
are se lected to ens ure proper operation of the dev ice under a shor t circui t conditi on. When the curr ent
flowing through the hi gh side DMOS reac hes the OCD threshold (5.6 A typ. for L6205 and L6207, adjustable for
L6206), after an internal propagation delay (t
OCD(ON)
) the open drain starts discharging
C
EN
. When the
EN
pin
voltage falls below the tur n-off thr eshold (V
TH(OFF)
) all the Pow er D MOS turn off after the internal propagation
delay ( t
D(OFF)EN
). The c urrent begins to decay as it ci rculates throu gh the freewheeling diodes. Since the DMOS
are
off
, there is no current flowing through them and no current to sense so the O CD circuit, after a short delay
(t
OCD(OFF)
), switches the internal open drain device off, and
R
EN
can charge
C
EN
. When the voltage at
EN
pin
reaches the turn-on threshold (V
TH(ON)
), after the t
D(ON)EN
delay, the DMOS turn on and the current restarts.
Even if the maximum output current can be very high, the external RC network provides a disable time (t
DISABLE
)
to ensure a safe r.m.s. value (see Figure 20).
Figure 20. Over Current Operation.
The maximum value reached by the current depends on its slew-rate, so on the short circuit nature and supply
voltage, and on the total intervention delay (t
DELAY
). It can be noticed that after the first current peak, the max-
imum value reached by the output current becomes lower, because the capacitor on
EN
pins is discharged start-
ing from a lower voltage, resulting in a shorter t
DELAY
.
The following approximate relatio ns estimate the disable time and the first OCD intervention delay after the short
circuit (worst case).
EN
O ut p ut Cu rrent
VTH(OFF)
tD(OFF)EN
IS OVER
tOCD(ON)
tDIS ABLE
tOC D(OFF)
tDELAY
tEN(FALL)
tEN(RIS E)
VEN(LOW)
EN
Ou tp ut Curr ent
tDISAB LE
VTH(ON )
tD(ON)EN
AN1762 APP LICATION NOTE
20/53
The time the device remains disabled is:
where
V
EN(LOW)
is the minimum voltage reached by the
EN
pin, and can be estimated with the relation:
The total intervention time is
where
t
OCD(OFF)
, t
OCD(ON)
, t
D(ON)EN
, t
D(OFF)EN
, and R
OPDR
are device intrinsic parameters, V
DD
is the pull-up voltage
applied to R
EN
.
The external RC network, C
EN
in par ticular, must be chosen obtaining a r easonable fast OCD intervention (short
t
DELAY
) and a safe dis able ti me (long t
DISABLE
). Figure 21 show s both t
DISABLE
and t
DELAY
as a function of C
EN
:
at least 100µs for t
DISABLE
are recommended, keeping the delay time below 1÷2µs at the same time.
The internal open drain can als o be turned on if the device experiences an
over temperature
(OVT) condition.
The OVT will cause the device to shut down when the die temperature exceeds the OVT threshold
(T
J
>165 °C typ.). S ince the OVT is also connected directly to the gate drive circuits (see Figure 1 to Figure 3),
all the Power DMOS will shut down, even if
EN
pin voltage is still over V
th(OFF)
. When the junction temperature
falls be low the OVT turn-off threshold ( 150 °C ty p.), the open drai n turn off,
C
EN
is recharged up to V
TH(ON)
and
then the PowerDMOS are turned on back.
ENONDRISEENOFFOCDDISABLE tttt )()()( ++=
)(
)(
)( ln
ONTHDD
LOWENDD
ENENRISEEN VV
VV
CRt −
−
⋅⋅=
ENOPDR
OFFOCDENOFFD CR
tt
OFFTHLOWEN eVV ⋅
+
−
⋅= )()(
)()(
ENOFFDFALLENONOCDDELAY tttt )()()( ++=
)(
)( ln
OFFTH
DD
ENOPDRFALLEN VV
CRt ⋅⋅=
21/53
AN1762 APPLICATION NOTE
Figure 21. Typical disable and delay time as a funct ion of CEN, for several values of REN.
3.13 Adjusting the Over Current Detection trip point (L6206 ONLY)
The L6206 allows the user to set the Over Curr ent Detection threshold separately for the two full bridges con-
necting two resistors (R
CL
) to pins
PROGCL
A
and
PROGCL
B
. The OCD threshold (I
SOVER
) follow s the equa-
tions:
–I
SOVER
= 5.6A ±30% at -25 °C < T
j
< 125 °C if R
CL
= 0
Ω
(
PROGCL
connected to GND)
–I
SOVER
= ±10% at -25 °C < T
j
< 125 °C if 5K
Ω <
R
CL
< 40k
Ω
Figure 22 show s the OCD threshold versus R
CL
value in the range from 5k
Ω
to 40k
Ω
.
110100
0.1
1
10
t
DELAY [µs]
CEN [nF]
110100
1
10
100
1.103
CEN [nF]
t
DISABLE [µs]
REN = 220 kΩ R
EN = 100 kΩ REN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
22100
RCL
----------------
AN1762 APP LICATION NOTE
22/53
Figure 22. Output Current Detection Threshold versus R
CL
Value (L6206 ONLY)
The Over Current Detection threshold can als o be adjusted through an external reference voltage , as shown in
Figu re 23. The external reference v oltage source s hould be able to sink c urrent (about 300 µA maximum) . More-
over , if supply voltage i s provided to the L6 206 before V
EXT
, and its
EN
pins are at a high l ogic lev el, the devi ce
starts working with minimum OCD threshold (actually the capacitor placed at the bottom of R
CL
allows a short
start-up time with higher OCD threshold). V
EXT
can also be obtained through a PWM output of a µC, adding a
series resistor to obtain a low-pass filter.
The OCD threshold (I
SOVER
) follows the equation:
I
SOVER
= ±10%, at -25 °C < T
j
< 125 °C if 0.5 A < I
SOVER
< 4.5 A
Figure 23. Adjustin g the OCD Thresh old thro ugh an external refer ence vo ltage (L6206 ONL Y )
5k 10k 15k 20k 25k 30k 35k 40k
0
0.5
1
1.5
2
2.5
3
3.5
5
R
CL
[
Ω ]
4
4.5
I
SOVER
[A]
18416.7 1.2V Vext–()
R
CL
-----------------------------------------------------------
R
CL
PROGCL
A
L6206
V
ext
= 0 ÷ 1.2 V
23/53
AN1762 APPLICATION NOTE
3.1 4 Paralleling two Full Bridges
3.1 4.1Paralleling two F ull Bridges to get a single Full Bridge
The outputs of L6205, L6206, L6207 can be paralleled to increase the output current capability or reduce the
power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond
connections fr om the di e to the power or sens e pins of the pac kage must carry curr ent i n both of th e assoc iated
half bridges (see Figure 24). When the two halves of one full bridge (for example OUT1
A
and OUT2
A
) are con-
nected in par allel, the peak current rating is not increased since the total current mus t still flow through one bond
wire on the power supply or sense pin. In addition, the over current detection senses the sum of the current in
the upper devices of each bridge (A or B) so connecting the tw o halves of one bridge in parallel does not in-
crease the over current detection threshold.
Figure 24. VS and SENSE pins maximum current handling
This configuration has to be used when two separate loads are driven, since the ICs has only two ENABLE in-
puts, one for the ful l bridge A and the other for the bridge B . In this case pull ing to G ND one of the two ENA BLE
pins will disable only one load (see Figure 25).
This configuration can also be used if a 5.6A OCD threshold is desired (instead of 11.2A).
Half Bridge 1 and the Half Bridge 2 of the Bridge A are connected in parallel and the same done for the Bridge
B as shown in Figure 25. In this configuration, the peak current for each half bridge is still limited by the bond
wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating
is not increased. Using this configuration with L6206, two separate resistors connected to pins
PROGCL
A
and
PROGCL
B
must be used. With L6207, two separate RC networ k should be used on
RC
pins. When two different
loads ar e driven (see Figure 25) by the two equivalent hal f bri dges, two separate sensing r esi stors are needed,
while if the two equivalent half bridges drive two separate loads, they must be connected from the
OUT
pins to
V
S
(see Figure 25) to make the P WM current control working properly.
In this configuration, the resulting bridge has the following characteristics (typical values).
- Equivalent De vice: FULL BRIDGE
- R
DS(ON)
0.15
Ω
Typ. Value @ T
J
= 25°C
- 2.8A max RMS Load C urrent
- 5.6A OCD Threshold
OVER
CURRENT
DETECTION
VS
A
OUT2
A
SENSE
A
BRIDGE A
2.8A rms
5.6A peak
SOURCED:
IOUT1 + IOUT2 = I
SUPPLY
< 2.8A rms, 5.6A pk.
SOURCED Current
OCD Threshold:
I
OUT1
+ I
OUT2
= 5.6A typ.
OUT1
A
SINKED:
IOUT1 + IOUT2 = I
SENSE
< 2.8A rms, 5.6A pk.
OVER
CURRENT
DETECTION
VS
B
OUT2
B
SENSE
B
BRIDGE B
2.8A rms
5.6A peak
SOURCED:
IOUT1 + IOUT2 = I
SUPPLY
< 2.8A rms, 5.6A pk.
SOURCED Current
OCD Threshold:
I
OUT1
+ I
OUT2
= 5.6A typ.
OUT1
B
VS
A
OUT2
A
SENSE
A
BRIDGE A
2.8A rms
5.6A peak
OUT1
A
SINKED:
IOUT1 + IOUT2 = I
SENSE
< 2.8A rms, 5.6A pk.
VS
B
OUT2
B
SENSE
B
BRIDGE B
2.8A rms
5.6A peak
OUT1
B
AN1762 APP LICATION NOTE
24/53
Figure 25. Paralle l connec tion with lower Over curr ent Th resho ld (L6205, L620 6, L62 07)
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4
VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN
A
IN1
A
IN2
A
2
6
7
9
EN
A
EN
B
C
EN
R
EN
EN
23
IN2
B
12
IN1
B
IN
B
11
14
24
17
3
15
22
SENSE
B
R
CLA
10
PROGCL
B
13 R
CLB
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
4
18 16
157
13
OUT2
A
GND
GND
GND
GND
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
VS
B
VCP
VBOOT
C
1
SENSE
A
17
6
5
14
3
12
19
SENSE
B
8
10
IN
A
IN2
B
IN2
A
2
IN1
A
1
IN1
B
IN
B
9
EN
B
EN
A
C
EN
R
EN
EN11
20
L6205
L6206
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
5
21 16
15
8
16
OUT2
A
GND
GND
GND
GND
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
VS
B
VCP
VBOOT
C
1
SENSE
A
20
6
5
17
3
15
22
SENSE
B
10 12
IN
A
IN2
B
IN2
A
2
IN1
A
1
IN1
B
IN
B
11
EN
B
EN
A
C
EN
R
EN
EN14
23
L6207
13
VREF
B
24
VREF
A
9RC
B
R
B
C
B
4RC
A
R
A
C
A
V
REF
= 0 ÷ 1 V
R
SENSE
LOAD
LOAD
LOAD
LOAD
LOAD
R
SENSE
LOAD
VS
VS
25/53
AN1762 APPLICATION NOTE
For some applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half
Bridge 1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 26.
Figure 26. Paral le l connec tion for highe r current (L 6205 and L6206 ONLY)
This configuration cannot be used with L6207, because of its internal PWM current controllers that work sepa-
rately for bridge A and bridge B. Using this configuration with the L6207 may damage the device.
In this configuration the resulting Bridge has the following characteristics (typical values).
- Equivalent De vice: FULL BRIDGE
- R
DS(ON)
0.15
Ω
Typ. Value @ T
J
= 25°C
- 5.6A max RMS Load C urrent
- 11.2A OCD Threshold
It sh ould be noted that using two s epara te l oads for the two equivalent half bridges the maxi mum current cannot
be sourced or sinked simultaneously by the two equivalent half bridges (for example to drive two separate
loads), due to the 5.6 A maximum current limit for
V
S
and
SENSE
pins (s ee Figure 24). W hen a single load is
driven (see Figure 26) R
CLA
and R
CLB
resistors connected to PR OGCL pins of L6206 should have the same
value.
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
LOAD
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4
VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN2
IN1
A
IN2
B
12
6
7
9
EN
A
EN
B
R
EN
EN23
IN1
B
11
IN2
A
IN1
2
14
24
17
3
15
22
SENSE
B
R
CLA
10
C
EN
PROGCL
B
13 R
CLB
OUT1
A
4
7
16
15
18
13
OUT1
B
GND
GND
GND
GNDOUT2
B
OUT2
A
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
VS
B
VCP
VBOOT
C
1
SENSE
A
17
6
5
EN
B
11
14
3
12
19
SENSE
B
LOAD
8
EN
A
C
EN
R
EN
EN20
1
IN2
IN1
A
IN2
B
10
IN1
B
9
IN2
A
IN1
2
C
P
C
BOOT
R
P
D
2
D
1
C
2
L6205
L6206
AN1762 APP LICATION NOTE
26/53
3.1 4.2Paralleling the fou r Half Bridges to get a single Half Bridge
It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as shown in Figure 27.
This configuration cannot be used with L6207, because of its internal PWM current controllers that work sepa-
rately for bridge A and bridge B. Using this configuration with the L6207 may damage the device.
The resulting half bridge has the following characteristics (typical values).
- Equivalent De vice: HALF BRIDGE
- R
DS(ON)
0.075
Ω
Typ. Value @ T
J
= 25°C
- 5.6A max RMS Load C urrent
- 11.2A OCD Threshold
With L6206 R
CLA
and R
CLB
resistors connected to PROGCL pins must have the same value.
Figure 27. Paralleling the four Half Bridges (L6205 and L6206 ONLY)
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
4
7
16
15
18
13
OUT1
B
GND
GND
GND
GND
OUT2
B
OUT2
A
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
VS
B
VCP
VBOOT
C
1
SENSE
A
17
6
5
EN
B
1114
3
12
19
SENSE
B
8
EN
A
C
EN
R
EN
EN20
1IN1
A
IN2
B
10
IN1
B
9
IN2
A
2
LOAD
IN
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
LOAD
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN
IN1
A
IN2
A
2
6
7
9
EN
A
EN
B
C
EN
R
EN
EN
23
IN2
B
12
IN1
B
11
14
24
17
3
15
22
SENSE
B
R
CLA
10
PROGCL
B
13 R
CLB
L6205
L6206
27/53
AN1762 APPLICATION NOTE
3.15 P ower Mana gem ent
Even when operati ng at current l evels well below the maximum r atings of the devi ce, the operating juncti on tem-
perature must be kept below 125 °C.
Figur e 28 shows the IC dissipated power versus the r.m.s. load current, in the case of a single IC driving two
loads (for instance 2 DC motors or a two-phase stepper motor) or a single IC, with two full bridges paralleled
(see
Paralleling two Fu ll Bridges
section
) driving one load (for instance 1 D C motor or one phase of a two-
phase stepper motor) and assuming the supply voltage is 24V.
Figure 28. IC Dissipated Power versus Output Current.
3.15.1 Maximum output current vs. selectable devices
Figur e 29 reports a performance comparison between different devices of the PowerSPIN family, for different
packages and in paralleled configuration, with the following assumptions:
- Each equivalent full bridge drives a load.
- Supply voltage: 24 V; Switching frequency: 30 kHz.
- T
amb
= 25 °C, T
J
= 125 °C.
- Maximum R
DS(ON)
(taking into account process spread) has been considered, @ 125 °C.
- Maximum quiescent current I
Q
(taking into account process spread) has been considered.
- PCB i s a FR4
with a diss ipating co pper surface on t he top s ide of 6 cm2 (with a t hicknes s of 3 5 µm) for
SO and PowerDIP packages (D, N suffixes).
- PCB is a FR4
with a dissipating copper s urface on the t op side of 6 cm2 (with a thicknes s of 35 µ m ), 16
via holes and a ground layer for the PowerSO package (PD suff ix).
- For each device configuration (on the x axis) y axis reports the maximum output (load) current.
- 2 x ’device’ means that the two loads are driven by two equivalent full bridges obtained paralleling two full bridg-
es for each of the two IC used. The current reported in Figure 29 is the maximum output current an equivalent
full bridge (a paralleled IC).
0 0.5 1 1.5 2 2.5 3
0
2
4
6
8
10
I
OUT
[A]
P
D
[W]
f
SW
= 30 kHz (synch. slow decay)
No PWM
2 Full Bridges Paralleled
2 Fu ll Br i dges
driving one load
driv ing t wo loads
AN1762 APP LICATION NOTE
28/53
Figure 29. Maxi mum outp ut current vs. selectab le devices.
3.15.2 Power Dissi pation Formulae for different sequences
Figur e 30 to Figure 33 are screenshots of a spreadsheet that helps calculating power dissipation in specified
conditions (applic ation and motor data), and estimates the resulting junction temperature for a given package
and copper area available on the PCB [4].
The model ass umes that the devic e is dri ving a two-phase bipolar stepper motor and that a PWM current contr ol
with slow decay recirculation technique is implemented (L6207 integrates the PWM controller); it considers pow-
er dissipation during the on-time and the off-time, rise and fall time (when a phase change occurs) considering
the operating sequence (N ormal, Wave or Hal f Step Mode), the switching losses and t he quiesc ent current pow-
er dissipation.
L622X D
L622X N
L622X PD
L620X D
L620X N
L620X PD
2 x L622X D
2 x L622X N
2 x L622X PD
2 x L620X D
2 x L620X N
2 x L620X PD
0.50
1.00
1.50
2.00
2.50
3.00
Load Current
[A]
29/53
AN1762 APPLICATION NOTE
Figure 30. Definition of parameters for the three different sequences. The current in only one phase
is shown.
Figure 31. Input Data.
TrTf
Tload
∆
∆∆
∆I
Ipk
I
t
T
Iload
NORMAL
TrTf
Tload
∆
∆∆
∆I
Ipk
I
t
T/2
Iload
WAVE
TrTf
Tload
∆
∆∆
∆I
Ipk
I
t
T
Iload
HALF STE P
Inp ut D a ta
M aximum Dra in-So urce ON R esistance Ron = 5.60E -01 [O h m ] A verage Value between High-S ide and Low-Side
M axim u m diode voltage Vd = 1.20E+ 00 [V ]
Quiescent Current Iq = 5.5 0E-03 [mA]
Maximum BEMF Voltage Vb = 1.50E+01 [V]
Mo to r In duc tance L m = 7 .90E - 0 3 [H ]
M otor Resis tance Rm = 6.6 0E+ 00 [O h m ]
Su pply V oltage V s = 2.4 0E+ 01 [V]
Pea k Current Ipk = 1.00E +00 [A]
Off-Time tOFF = 1.50E-05 [s]
S tep Frequency fC K = 1.0 0E+03 [H z]
S ensing R esistance Rs = 5.00E -01 [O h m ]
Decay Type -
"SLOW" = Synchronous Slow Dec ay
"FAS T" = Q u asi-Synchronous Fast decay
Stepping se quen ce - "NO R M A L", "HALF " or "WA VE "
SLOW
WAVE
Dev ice In put Values
Motor Input V alue
s
Application Input Values
AN1762 APP LICATION NOTE
30/53
Figure 32. Power Dissipation f ormul ae and results.
Result
PowerDMOS
Commutation
Time
Tcom =
9.60E-08 [s] Vs / (250V/ µs)
Rise Tim e Trise = 4.03E-04 [s]
Fall Time Tfall = 3.16E-04 [s]
NO RMAL Mode
HALF or WAVE
Mode
Dut y Cycl e D = 6.25E-01 - Vb / Vs Sync. Slow Decay
Switching
Frequency fSW =
2.50E+04
[Hz]
(1 -D) / tOFF
Current Ripple
∆I = 2.85E- 02 [A ] (Vs - Vb)*D / (Lm* fSW)
Period T = 2.00E-03 [s] 2 / fCK
4 / fCK
2 / fCK
NO RMAL Mode
HALF Mode
WAVE Mode
Load T i m e
Tload =
5.97E-04 [s] T-Trise-Tfall
(3/4)T-rise
(T/2)-Trise
NO RMAL Mode
HALF Mode
WAVE Mode
A v erage Cur-
rent during
Load T i m e I = 9.86E-01 [A]
r .m.s. Current
duri ng Load
Time Irms = 9.86E-01 [A]
Ris e T i m e
Di ssi p a ti n g
Energy Erise = 1.50E-04 [J]
Fall Time
Dissipating
Energy
E fall =
3.62E-04 [J]
MORMAL Mode
HALF or WAVE
Mode
Load T i m e
Dis s. En ergy
Eload =
6.50E-05 [J] 2Ron · Irms2 · Tload Sync. Slow Decay
Ipk Rm 2 Ipk Ron Ipk Rs Vs+⋅–⋅⋅–⋅–()
Vs
--------------------------------------------------------------------------------------------------------------- Lm
Rm Rs 2Ron++
----------------------------------------------
⋅ln–
Vs
Ipk Rm 2+Ipk Ron Ipk Rs Vs+⋅+⋅⋅⋅()
------------------------------------------------------------------------------------------------------------- Lm
Rm 2 Ron Rs+⋅+()
-------------------------------------------------------
⋅ln–
Vs 2 Vd⋅–()
Ipk Rm Ipk Rs Vs 2 Vd⋅–+⋅+⋅()
------------------------------------------------------------------------------------------- Lm
Rm Rs+()
----------------------------
⋅ln–
Ipk I∆
2
-----–
Ipk Ipk I∆–()
I
2
∆
3
-------+⋅
2Ron Ipk2Trise
3
---------------
⋅⋅
2Ron Ipk2Tfall
3
-------------
⋅⋅
2VdTfall Vs–2Vd⋅+()
Rm Rs+()
--------------------------------------
m
Ipk Rm Ipk Rs Vs 2 Vd⋅–+⋅+⋅()
1
T–fall
Lm
---------------- Rm Rs+()⋅exp–
Rm Rs+()
2
---------------------------------------------------------------------------------
⋅⋅
+⋅⋅
31/53
AN1762 APPLICATION NOTE
Figure 33. Thermal Data inputs and results.
Commutatiion
Time
Diss ipa ting P w
Ecom =
6.78E-05 [J] 2Vs · I · Tcom · Tloa d · f SW
Quiescent
Diss ipa ting P w
Pq = 1.32E-01
[W]
Vs · Iq
Total Dissi-
pating Power P =
1.36E+00
[W]
·(Erise + Efall + Eload + E com) + Pq
2
T
---
Input Data
Packa
g
e SO24
Co pper Area 4.0 1÷10 sq. cm
Coppe r A re a is on S ame side of the device
G roun d Layer N/A
Ambient T em perature 50 -25 ÷ 100 ºC
Results
Therm al Resistance
Junction to Ambient
53.36
ºC / W
Therm al Resistance
Junction to P ins / Slug
14.00
ºC / W
Estima ted J un ction
Temperature 122.66 ºC
Estimated
Pins / Slu
g
T emperature
103.60
AN1762 APP LICATION NOTE
32/53
4 APPLICATION EXAMPLE (L6207)
Application Data Motor Data
Rotation Speed: 300 rpm (f
CK
= 1kHz) Winding Resistance: 6.6
Ω
Winding peak Cur rent: 1A Winding Inductance: 7.9mH
Maximum Ripple: 50mA Step Angle: 1.8°/step
Supply Voltage: 24V ±5% Maximum BEMF at 300rpm: 15V
Sequence: Wave Mode
4.1 D ec ay m ode , sensing resistors and refere nce voltag e.
Referr ing to approximated formulae i n Figure 32, it's poss ible to calculat e the Duty -C ycle (D), the Swi tching Fre-
quency (f
SW
), the Current Ripple (
∆
I). With a 15 µs off-time, we will have:
D
≅
63%, f
SW
≅
25kHz,
∆
I
≅
29mA. The on-time is t
ON
= D / f
SW
≅
25µs, which is far from the minimum allow ed
(1.5µs), so slow decay can be used.
The bulk capacitor need to withstand at least 24V + 5% + 25%
≅
32V. A 50V capacitor will be used. Allowing a
voltage ripple of 200mV, the capacitor ESR should be lower than 200mV / 1A = 200m
Ω
; the AC current capa-
bility should be about 1A.
Providi ng a refer ence voltage of 0.5V, 0.5
Ω
se nsing resistor are needed. The res istors power r ating i s abo ut P
R
≅
I
rms2
· R
SENSE
· D
≅
0.32W. Two 1
Ω
- 0.25W - 1% resistors in parallel are used. The charge pump us es rec-
ommended components (1N4148 diodes, ceramic capacitors and a 100
Ω
resistor to reduce EMI).
R = 18k
Ω
, C = 1.2 nF are connected to the RC pins, obtaining t
OFF
≅
16µs. On the EN pins 5.6nF capacitors
have been placed, and the pins are driven by the µC through 100k
Ω
resistors. With these values, in case of
short circuit between two OUT pins or an OUT pin and G ND, the PowerDMOS turns off after about 1µs, and
t
DISABLE
≅
240µs.
Figure 34. Application Example.
With Wave Drive selected, referring to Figure 31 to Figure 33, the dissipating power is about 1.36 W. If the am-
bient temper ature is lower than 50°C, with 4c m
2
of copper a rea on th e PC B and a SO24 pac kage, the estimated
junction temperature is about 123°C. Using more copper area or a PowerDIP package will reduce the junction
temperature.
+
-
VS = 24 V
Vref = 0.5 V
ENB
IN2B
IN2A
IN1B
IN1A
VrefA VrefB RCA RCB GND
GND GND
GND
SENSEA
SENSEB
VSA VSB
VBOOT CP
OUT1B OUT2B
OUT1A OUT2A
1N4148 1N4148
100 kΩ
1.2 nF
Ceramic
18 kΩ
5%
100Ω
0.25W
5.6 nF
Ceramic
47nF
Ceramic
18 kΩ
5%
1.2 nF
Ceramic
100nF 50V
Ceramic
220nF 50V
Ceramic
10nF 50V
Ceramic
100µF 50V
ESR<200mΩ
L62 07
µC
or
Custom Logic
2-Phase
Stepper Motor
+
- 4 X
1 Ω, 0.25 W, 1%
2 kΩ 0.25 W
1%
18 kΩ 0.25 W
1%
Logic S upply
5 V ENA
100 kΩ
5.6 nF
Ceramic
33/53
AN1762 APPLICATION NOTE
5 APPENDIX - EVALUATI ON BOARDS
5.1 PractiSPIN
PractiSP IN is an eval uation and demonstratio n system that can be used with the PowerSPIN fami ly (L62XX) of
devices. A Graphical User Interface (GUI) (see Figure 35) program runs on an IBM-PC under windows and com-
municates with a common ST7 based interface board (see Figure 36) through the RS 232 serial port. The ST7
inter face board connects to a device spec ific ev aluation board (tar get board) via a standar d 34 pin ribbon c able
interface.
Depending on the target device the PractiSPIN can drive a stepper motor, 1 or 2 DC motors or a brushless DC
(BLDC) m otor, operatin g signific ant parameters s uch as SPEED, CURRENT, VOLTAGE, DIRECTION, ACCEL-
ERATION and DECELERATION RATES from a user friendly graphic interface, and programming a sequence
of movements.
The software also allows evaluating the power dissipated by the selected device and, for a given package and
dissipating copper area on the PCB, estimates the device's junction temperature.
Fig ur e 35. PractiSPIN PC Softw a re
AN1762 APP LICATION NOTE
34/53
Fig ur e 36. PractiSPIN ST7 Eval uat ion Boar d
5.2 EVAL6205N
An evaluation board has been produced to help the evaluation of the device in PowerDIP package. It imple-
ments a typical application with several added components. Figure 38 shows the electrical schematic of the
board; in the table below the part list is reported.
CN1, CN2, CN3, CN4 2-poles connector R1 100Ω resistor
CN5 34-poles connector R2 700Ω 0.6W resistor
C1 220nF/100V Ceramic or Polyester capacitor R3, R4, R13 10kΩ resistor
C2 220nF/100V Ceramic or Polyester capacitor R5, R6 4.7kΩ resisto r
C3 100µF/63V capacitor R7, R8, R9, R10, R11, R12 1Ω 0.4W resistor
C4 10nF/100V Ceramic capacitor R18, R14 1kΩ resistor
C5 10µF/16V Capacitor R15, R19 20kΩ resistor
C6, C7, C11 100nF Capacitor R16, R20 2.2kΩ resistor
C8, C10 470pF Capacitor R21, R17 5kΩ trimmer
C9, C12 68nF Capacitor R22 12kΩ resistor
C13 2.2nF Capacitor R23 50kΩ trimmer
D1, D2 1N4148 Diode U1 L6205N
D3 BZX79C5V1 5.1V Zener Diode U2 L6506
JP1 3-pin jumper JP2, JP3, JP4, JP5 2-pin jumper
The Eval uation Board provides exter nal connectors for the supply voltage, an external 5V reference for the logi c
inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an
external
µ
C board or the PractiSPIN tool. T he board also accommodates the L6506 P WM current controller.
R23 sets the PWM operating frequency. If the L6506 does not need to be used, simply connect the two V
REF
inputs to a voltage high enough to keep current control inactive.
The Pr actiSPIN tool is composed of a graphic inter face software running on a PC that connects with the hard-
ware based on the ST7 µC, w hich contains an upgradeable fir mware. This tool allows a fast and easy eval uation
of the PowerSPIN family devices, givi ng the ability of driving DC, BLD C and St epper motors, depending on the
target dev ice. The PractiS PIN
connected to the E VAL6205N can drive D C motors and inducti ve loads , allowing
output voltage and current settings
The PC-so ftware also prov ides a Power Di ssipa tion and Thermal A nalysi s secti on, intended to help a fas t eval-
uation of the device, package and dissipating copper area required by the user’s application, and to be a good
starting point designing an application (from the power dissipation and thermal point of view).
35/53
AN1762 APPLICATION NOTE
Running the evaluation board in stand-alone mode, instead, R17 and R21 set the r eference volta ge separately
for the two bridges, while R16, C9 and R20, C 12 are low-pass filters to provide an external reference voltage
by a P WM output of a
µ
C (see also the Micr oste pping sec tion). U sing e xternal V
REF
inputs R15, R17, R19, R21
can be disconnecte d through JP4 and JP5, unless the P ractiSPIN ST7 evaluat ion board is used. This board, in
fact, is provided with an offset cancellation circuitry trimmable through a potentiometer (see PractiSP IN docu-
mentation).
Closing JP2 and JP3 is recommended for safe Over Current Protection.
The 5V voltage for logic inputs and for references (V
refA
and V
refB
) is obtained from R2, D3. Depending on the
supply voltage, the value of resistor R2 should be changed in order to ensure a correct biasing of D3.
The jumper JP1 allows choosing the 5V voltage from the inter nal zener diode network or pin 11 of CN5 (for ex-
ample an external µC board can provide 5V to the evaluation board). Also CN2 connector can be used to pro-
vide an external 5V voltage to the board (in that case R2, D3 should be disconnected). C N2, or pin 1 of CN5,
can also be used to provide a 5V voltag e to external c ircuits (as, for example, the PractiS PIN ST7 board) . In thi s
case the current that can be drawn form the board depends on the supply voltage and on R2 value.
Figure 39 to Figure 41 show the component placement and the two layers layout of the L6205N Evaluation
Board. A lar ge GND area has b een used, to guarantee mini mal noise and good p ower dissipation for the device.
Figure 37. EVAL6205N.
5.2.1 I mportant Notes
JP1 : close in INT position for use with PractiSPIN ST7 board
C6, C7 : recommended change to 5.6 nF for safe Overcurrent protection
R3, R4 : recommended change to 100 k for safe Overcurrent protection
R5, R6 : recommended change to 100 k if EN pins are driven from the CN5 connector (for example with Prac-
tiSPIN ST7 board) for safe O vercurrent protection
R17, R21 : set the maximum current obtainable through PractiSPIN (see PractiSP IN documentation)
R2 : recommended change to adequate value (depending on supply voltage) to obtain 5V across D3
JP2, JP3 : close for safe Overcurrent protection
JP4, JP5 : close for use with PractiSPIN ST7 board
JP1 C6
C7
R3
R4
R6
R5
R17
R21 JP2
JP3
JP4
JP5
AN1762 APP LICATION NOTE
36/53
Figure 38. EVAL6205N Electrical schematic.
PullUp
PullUp
+5V
PullUp
3
2
PullUp
1
PullUp
+5V
4
PullUp
VCCREF
PullUp
GND
INT6
ext.
CW
OCMPA1 P4.2
int.
TI NA0 P2.0
TINB0 P2.1
CW
OC MPB1/ ICAP B1 P4.3 TINA1 P2.4
INT3
TOUTB0 P2.3
T INB1 P2.5
TOUTA1 P2.6
CW
ADC_REF
INT0
TOUTPB1 2.7
INT2
R19
C9
CN3
1
2
D2
C4
C12
JP4
JP2
D3
CN1
1
2
R1
JP3
R4
D1
CN4
1
2
C6
R5
U2
L6506Dip
In1 5
In2 6
In3 7
In4 8
Out1
14 Out2
13 Out3
12 Out4
11 EN
4
Vsense2
15
Vref 2
17
Vsense1
10 R/C 1
Vref 1
16 Sync 3
VCC 18
Osc_Out 2
GND
9
R6
JP1
13
2
JP5
CN2
1
2
R14
R13
C1
C2
R3
R20
CN5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
C11
R22
R23
C13
R17
R16
R2
C5
C8 C10
R18
R21
C7
R15
R9
R10
R7
C3
R11
U1
L6205
OUT1B
7
OUT2A
18
IN1 1
IN2 2
SENSEA 3
OUT1A
4
GND
5GND
6
SENSEB 8
IN3 9
IN4 10
ENB 11
VBOOT
12
OUT2B
13
VSB
14
GND
16 GND
15
VSA
17
VCP
19
ENA 20
R8
R12
IN1
_2 ENA LIMIT_A
_4
ENB
_1
IN3
_3 LIMIT_B
VREF_A
_2
SENSE_A SENSE_B
VREF_B
ENA
IN4
LIMIT_B
IN2
SENSE_A
SENSE_B
_1
IN3
ENB _4
_3
LIMIT_A
IN4
IN2
IN1
VREFB
VREFA
37/53
AN1762 APPLICATION NOTE
Figure 39. EVAL6205N Component placemen t.
Figure 40. EVAL6205N Top Layer L ayout.
Power GND
(B ulk C ap acitor)
Signa l GN D
AN1762 APP LICATION NOTE
38/53
Figure 41. EVAL6205N Bottom Layer Layo ut.
Short SEN SE
Paths
39/53
AN1762 APPLICATION NOTE
5.3 EVAL6206N
An evaluation board has been produced to help the evaluation of the device in PowerDIP package. It imple-
ments a typical application with several added components. Figure 43 shows the electrical schematic of the
board; in the table below the part list is reported.
CN1, CN2, CN3, CN4 2-poles connector R1 100Ω resistor
CN5 34-poles connector R2 700Ω 0.6W resistor
C1 220nF/100V Ceramic or Polyester capacitor R3, R4, R16 10kΩ resistor
C2 220nF/100V Ceramic or Polyester capacitor R5, R6 4.7kΩ resisto r
C3 100µF/63V capacitor R7, R8 50kΩ trimmer
C4 10nF/100V Ceramic capacitor R9, R10, R11, R12, R13, R14 1Ω 0.4W resistor
C5, C8, C10 10µF/16V Capacitor R15, R21 2.2kΩ resisto r
C6, C7 47nF Capacitor R17, R23 20kΩ resistor
C9, C13 68nF Capacitor R18, R22 750Ω resistor
C11 100nF Capacitor R19, R25 2.2kΩ resistor
C12, C14 470pF Capacitor R20, R26 5kΩ trimmer
C15 2.2nF Capacitor R27, R24 1kΩ resistor
D1, D2 1N4148 Diode R28 12kΩ resistor
D3 BZX79C5V1 5.1V Zener Diode R29 50kΩ trimmer
JP1 3-pin jumper U1 L6205N
JP2 to JP7 2-pin jumper U2 L6506
The Eval uation Board provides exter nal connectors for the supply voltage, an external 5V reference for the logi c
inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an
external
µ
C board or the PractiS PIN tool. The board also accomodate the L6506 PWM current controller. R29
sets the PWM operating frequen cy. If the L6506 does not need to be used , simply connect the two V
REF
inputs
to a voltage high enough to keep current control inactive.
The Pr actiSPIN tool is composed of a graphic inter face software running on a PC that connects with the hard-
ware based on the ST7 µC, w hich contains an upgradeable fir mware. This tool allows a fast and easy eval uation
of the PowerSPIN family devices, givi ng the ability of driving DC, BLD C and St epper motors, depending on the
target dev ice. The PractiS PIN
connected to the E VAL6206N can drive D C motors and inducti ve loads , allowing
output voltage and current settings
The PC-so ftware also prov ides a Power Di ssipa tion and Thermal A nalysi s secti on, intended to help a fas t eval-
uation of the device, package and dissipating copper area required by the user’s application, and to be a good
starting point designing an application (from the power dissipation and thermal point of view).
Running the evaluation board in stand-alone mode, instead, R20 and R26 set the r eference volta ge separately
for the two bridges, while R19, C9 and R25, C 13 are low-pass filters to provide an external reference voltage
by a P WM output of a
µ
C (see also the Micr oste pping sec tion). U sing e xternal V
REF
inputs R17, R20, R23, R26
can be disconnecte d through JP6 and JP7, unless the P ractiSPIN ST7 evaluat ion board is used. This board, in
fact, is provided with an offset cancellation circuitry trimmable through a potentiometer (see PractiSP IN docu-
mentation).
Closing JP4 and JP5, R7 and R8 allow adjusting the Over Cur rent Detection threshold separately for the two
full br idges. Leaving JP4 and J P5 opened, the OCD threshold can be pr ogrammed providing r eference voltages
at the bottom of R 7 and R8, through pins 27 and 29 of CN5. R15, R18, C8, R21, R 22, C10 provide low-pass
filtering to obtain these reference voltages from an external PWM output of a µC.
Closing JP2 and JP3 allows Over Current Protection to work, connecting each
EN
pin to the cor res ponding
OCD
pin.
The 5V voltage for logic inputs and for references (V
refA
and V
refB
) is obtained from R2, D3. Depending on the
supply voltage, the value of resistor R2 should be changed in order to ensure a correct biasing of D3.
The jumper JP1 allows choosing the 5V voltage from the inter nal zener diode network or pin 11 of CN5 (for ex-
ample an external µC board can provide 5V to the evaluation board). Also CN2 connector can be used to pro-
vide an external 5V voltage to the board (in that case R2, D3 should be disconnected). C N2, or pin 1 of CN5,
AN1762 APP LICATION NOTE
40/53
can also be used to provide a 5V voltag e to external c ircuits (as, for example, the PractiS PIN ST7 board) . In thi s
case the current that can be drawn form the board depends on the supply voltage and on R2 value.
Figure 44 to Figure 46 show the component placement and the two layers layout of the L6206N Evaluation
Board. A lar ge GND area has b een used, to guarantee mini mal noise and good p ower dissipation for the device.
Figure 42. EVAL6206N.
5.3.1 I mportant Notes
JP1 : close in INT position for use with PractiSPIN ST7 board
C6, C7 : recommended change to 5.6 nF for safe Overcurrent protection
R3, R4 : recommended change to 100 k for safe Overcurrent protection
R5, R6 : recommended change to 100 k if EN pins are driven from the CN5 connector (for example with Prac-
tiSPIN ST7 board), for safe O vercurrent protection
R20, R26 : set the maximum current obtainable through PractiSPIN (see PractiSP IN documentation)
R2 : recommended change to adequate value (depending on supply voltage) to obtain 5V across D3
JP2, JP3 : close to allow Overcurrent protection
JP4, JP5 : close for on-board OCD threshold adjusting through R7, R8
JP6, JP7 : close for use with PractiSPIN ST7 board
JP1
C7
C6
R4
R3
R6
R5
R20
R26 R2
JP3 JP5
JP2 JP4
JP6
JP7
41/53
AN1762 APPLICATION NOTE
Figure 43. EVAL6206N Electrical schematic.
PullUp
3
PullUp
VCCREF
PullUp
2
PullUp
GND
4
+5V
1
+5V PullUp
PullUp
PullUp
CW
TOU TB0 P2.3
TOU TA1 P2.6
INT2
ADC_REF
INT6
ext.
CW
TINA1 P2.4
CW
int.
INT0
TINA0 P2.0
TOUTPB1 2.7
TINB1 P2.5
OCMPA1 P4.2
CW
OCM PB1/ ICAPB1 P4.3
CW
TINB0 P2.1
INT3
JP6
C2
R19
R5
JP1
13
2
R20
R15
CN1
1
2
R4
R26
JP2
R17
C15
R18
CN2
1
2
R22
U2
L6506Dip
In1 5
In2 6
In3 7
In4 8
Out1
14 Out2
13 Out3
12 Out4
11 EN
4
Vsense2
15
Vref2
17
Vsense1
10 R/C 1
Vref1
16 Sync 3
VCC 18
Osc_Out 2
GND
9
D1
CN5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
C6
C4
C1
C7
R24 R27
R8
R1
R16
R21
R23
D2 R9
CN4
1
2
C10
R2
C11
C9
R28
C13
R7
R29
C12
C8
R25
C14
JP7
CN3
1
2
D3
C5
R6
R3
JP3
JP5
U1
L6206
IN1 1
IN2 2
SENSEA 3
PROGCLA 24
OUT1A
5
GND
6GND
7
OUT1B
8
PROGCLB 13
SENSEB 10
IN3 11
IN4 12
OCDB 9
ENB 14
VBOOT
15
OUT2B
16
VSB
17
GND
18 GND
19
VSA
20
OUT2A
21
VCP
22
ENA 23
OCDA 4
R12
R14
R10
C3
JP4
R13
R11
_4
SENSE_B
IN4
_4
IN2
_1 ENA
SENSE_A
SENSE_B
_3
IN4
SENSE_A
VREF_A
OCDB
ENB _3 PROGCLA
ENA
PROGCLB
IN1
IN3
VREFA
PROGCLA
OCDA
_1
ENB
VREFB
IN3
IN2
_2
_2 IN1
PROGCLB
OCDA
VREF_B
OCDB
AN1762 APP LICATION NOTE
42/53
Figure 44. EVAL6206N Component placemen t.
Figure 45. EVAL6206N Top Layer L ayout.
Power GND
(Bulk Capacitor)
Signal GND
43/53
AN1762 APPLICATION NOTE
Figure 46. EVAL6206N Bottom Layer Layo ut.
Short S ENS E
Paths
AN1762 APP LICATION NOTE
44/53
5.4 EVAL6206PD
An evaluation board has been pr oduced to help the evaluation of the devic e in PowerSO pac kage. It implem ents
a typical application with several added components. Figure 48 shows the electrical sc hematic of the board; in
the table below the part list is reported.
CN1, CN2, CN3, CN4 2-poles connector JP2 to JP5 2-pin jumper
CN5 34-poles connector R1 750Ω 0.6W resistor
C1 220nF/100V Ceramic or Polyester capacitor R2, R3, R26 10kΩ resistor
C2 220nF/100V Ceramic or Polyester capacitor R4, R5 4.7kΩ resisto r
C3 100µF/63V capacitor R6, R7 50kΩ trimmer
C4 10nF/100V Ceramic capacitor R8, R9, R10, R11 0.4Ω 1W resistor
C5, C8, C10 10µF/16V Capacitor R12, R19 20kΩ resistor
C6, C7 100 nF Capac itor R13, R14, R17, R20 2.2kΩ resisto r
C9, C13 68nF Capacitor R15, R18 750Ω resistor
C11 100nF Capacitor R16, R22 5kΩ trimmer
C12, C15 470pF Capacitor R23, R21 1kΩ resistor
C14 2.2nF Capacitor R24 12kΩ resistor
D1 Bat46SW Diodes R25 50kΩ trimmer
D2 BZX79C5V1 5.1V Zener Diode U1 L6205N
JP1 3-pin jumper U2 L6506
The Eval uation Board provides exter nal connectors for the supply voltage, an external 5V reference for the logi c
inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an
external
µ
C board or the PractiS PIN tool. The board also accomodate the L6506 PWM current controller. R25
sets the PWM operating frequen cy. If the L6506 does not need to be used , simply connect the two V
REF
inputs
to a voltage high enough to keep current control inactive.
The Pr actiSPIN tool is composed of a graphic inter face software running on a PC that connects with the hard-
ware based on the ST7 µC, w hich contains an upgradeable fir mware. This tool allows a fast and easy eval uation
of the PowerSPIN family devices, givi ng the ability of driving DC, BLD C and St epper motors, depending on the
target device. The PractiSPIN
connected to the EVAL6206PD can drive DC motors and inductive loads, allow-
ing output voltage and current settings
The PC-so ftware also prov ides a Power Di ssipa tion and Thermal A nalysi s secti on, intended to help a fas t eval-
uation of the device, package and dissipating copper area required by the user’s application, and to be a good
starting point designing an application (from the power dissipation and thermal point of view).
Running the evaluation board in stand-alone mode, instead, R16 and R22 set the r eference volta ge separately
for the two bridges, while R14, C9 and R20, C 13 are low-pass filters to provide an external reference voltage
by a P WM output of a
µ
C (see also the Micr oste pping sec tion). U sing e xternal V
REF
inputs R12, R16, R19, R22
should be disconnected, unless the Pr actiSPIN ST7 evaluation board is used. This board, in fact, is provided
with an offset cancellation circuitry trimmable through a potentiometer (see PractiSPIN documentation).
Closing JP4 and JP5, R6 and R7 allow adjusting the Over Cur rent Detection threshold separately for the two
full br idges. Leaving JP4 and J P5 opened, the OCD threshold can be pr ogrammed providing r eference voltages
at the bottom of R 6 and R7, through pins 27 and 29 of CN5. R13, R15, C8, R17, R 18, C10 provide low-pass
filtering to obtain these reference voltages from an external PWM output of a µC.
Closing JP2 and JP3 allows Over Current Protection to work, connecting each
EN
pin to the cor res ponding
OCD
pin.
The 5V voltage for logic inputs and for references (V
refA
and V
refB
) is obtained from R1, D2. Depending on the
supply voltage, the value of resistor R1 should be changed in order to ensure a correct biasing of D2.
The jumper JP1 allows choosing the 5V voltage from the inter nal zener diode network or pin 11 of CN5 (for ex-
ample an external µC board can provide 5V to the evaluation board). Also CN2 connector can be used to pro-
vide an external 5V voltage to the board (in that case R1, D2 should be disconnected). C N2, or pin 1 of CN5,
can also be used to provide a 5V voltag e to external c ircuits (as, for example, the PractiS PIN ST7 board) . In thi s
45/53
AN1762 APPLICATION NOTE
case the current that can be drawn form the board depends on the supply voltage and on R1 value.
Figur e 49 to Figure 51 show the component placement and the two layers layout of the L6206PD Evaluation
Board. A lar ge GND area has b een used, to guarantee mini mal noise and good p ower dissipation for the device.
Figure 47. EVAL6206PD.
5.4.1 I mportant Notes
JP1 : close in INT position for use with PractiSPIN ST7 board
C6, C7 : recommended change to 5.6 nF for safe Overcurrent protection
R2, R3 : recommended change to 100 k for safe Overcurrent protection
R4, R5 : recommended change to 100 k if EN pins are driven from the CN5 connector (for example with Prac-
tiSPIN ST7 board) for safe O vercurrent protection
R16, R22 : set the maximum current obtainable through PractiSPIN (see PractiSP IN documentation)
R1 : recommended change to adequate value (depending on supply voltage) to obtain 5V across D2
JP2, JP3 : close to allow Overcurrent protection
JP4, JP5 : close for on-board OCD threshold adjusting through R6, R7
CN5 : VrefA and VrefB positions are inverted if compared to other EVAL62XX boards.
JP1
C7
C6
R3
R2
R5
R4
R16
R22
R1
JP4
JP5
JP2
JP3
CN5
AN1762 APP LICATION NOTE
46/53
Figure 48. EVA L6206 PD Ele ctrical schem atic .
PullUp
PullUp
PullUp
VCCREF
PullUp
PullUp
PullUp
+5V
PullUp
+5V
ADC_REF INT3
L6206PD
INT2A0 IN6 P7.6
TINA0 P2.0
TINA1 P2.4
TOUT PB1 2.7
A1 IN6 P8.1
OCMPB1/ICAPB1 P4.3
TINB0 P2.1
TOUTA1 P2.6
INT0
INT6
TINB1 P2.5
TOUTB0 P2.3
CW CW
CW
CW
CW
int.
ext.
OCMPA1 P4.2
R15
R13
R18
R17
C8
C10
CN4
1
2
CN3
1
2
C12 C15
R23R21
R11
R24
R25
R12
R14
R16
R20
R7
R6
C9 C13
C7C6
JP3
JP2
CN1
1
2
CN2
1
2
C5
D2
R1
C2
C1
U2
In1 5
In2 6
In3 7
In4 8
Out1
16 Out2
15 Out3
14 Out4
13 EN
4
Vsense2
17
Vref2
19
Vsense1
12 R/C 1
Vref1
18 Sync 3
VCC 20
Osc_Out 2
GND
9NC 10
NC 11
C11
C14
R22
R19
R26
CN5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
JP1
13
2
D1
1 3
2C4
R5
R3
R4
R2
R10
JP4
JP5
R8
C3
U1
GND
36
IN1 10
GND
1
SENSEA 12
VBOOT
30
IN2 11
GND
18
VSB
33
GND
19
PROGCLA 9
IN3 26
VSA
4
VCP
7PROGCLB 28
ENB 29
ENA 8
IN4 27
OCDB 24
OCDA 13
OUT1A
15
SENSEB 25
OUT1B
22
OUT2A
5
OUT2B
32
NC
2NC
3NC
6NC
14 NC
16
NC
17 NC
20
NC
21 NC
23 NC
31 NC
34 NC
35
R9
PROGCLA PROGCLB SENSE_BSENSE_A
IN1
IN4
IN2
IN3
_2
_1
_3
_4
VREF_A VREF_B
SENSE_B
SENSE_A
OCDB_3 OCDA_1 _2 _4
IN4
PROGCLA
ENA
IN2
OCDB
ENB
IN3
IN1
OCDA
SENSE_A
PROGCLB
VREFA
VREFB
ENBENA
SENSE_B
47/53
AN1762 APPLICATION NOTE
Figure 49. EVAL6206 PD Com po nent placem ent.
Figure 50. EV AL6206PD Top Layer Layo ut.
Power GND
(Bulk Capacito r)
Signal GND
AN1762 APP LICATION NOTE
48/53
Figure 51. EVA L6206 PD Bottom Layer L ayou t.
Signal GND
49/53
AN1762 APPLICATION NOTE
5.5 EVAL6207N
An evaluation board has been produced to help the evaluation of the device in PowerDIP package. It imple-
ments a typical application with several added components. Figure 53 shows the electrical schematic of the
board; in the table below the part list is reported.
CN1, CN2, CN3, CN4 2-poles connector JP1 3-pin jumper
CN5 34-poles connector JP2, JP32-pin jumper
C1 220nF/100V Ceramic or Polyester capacitor R1 100Ω resistor
C2 220nF/100V Ceramic or Polyester capacitor R2 3.17kΩ 0.6W resistor
C3 100µF/63V capacitor R3, R4 4.7kΩ resistor
C4 10nF/100V Ceramic capacitor R5, R16 20kΩ resistor
C5 10µF/16V Capacitor R6, R7 100kΩ trimmer
C6, C7 100nF Capacitor R8, R17 2.2kΩ 0.4W resist or
C8, C9 68nF Capacitor R9 to R14 1Ω 0.4Ω resistor
C10, C11 820pF Capacitor R18, R15 5kΩ trimmer
D1, D2 1N4148 Diode U1 L6205N
D3 BZX79C5V1 5.1V Zener Diode U2 L6506
The Eval uation Board provides exter nal connectors for the supply voltage, an external 5V reference for the logi c
inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an
external
µ
C board or the PractiSPIN tool.
The Pr actiSPIN tool is composed of a graphic inter face software running on a PC that connects with the hard-
ware based on the ST7 µC, w hich contains an upgradeable fir mware. This tool allows a fast and easy eval uation
of the PowerSPIN family devices, givi ng the ability of driving DC, BLD C and St epper motors, depending on the
target dev ice. The PractiS PIN
connected to the E VAL6207N can drive D C motors and inducti ve loads , allowing
output voltage and current settings
The PC-so ftware also prov ides a Power Di ssipa tion and Thermal A nalysi s secti on, intended to help a fas t eval-
uation of the device, package and dissipating copper area required by the user’s application, and to be a good
starting point designing an application (from the power dissipation and thermal point of view).
Running the evaluation board in stand-alone mode, instead, R15 and R18 set the r eference volta ge separately
for the tw o bridges, while R8, C8 and R17, C 9 are low -pass filters to provide an external reference voltage by
a PWM output of a
µ
C (see also the Microstepping section). Using external V
REF
inputs R5, R15, R16, R18
should be disconnected, unless the Pr actiSPIN ST7 evaluation board is used. This board, in fact, is provided
with an offset cancellation circuitry trimmable through a potentiometer (see PractiSPIN documentation).
R6, C10 and R7, C11 are used to set the off-time of the two channels of the IC.
Closing JP2 and JP3 is recommended for safe Over Current Protection.
The 5V voltage for logic inputs and for references (V
refA
and V
refB
) is obtained from R2, D3. Depending on the
supply voltage, the value of resistor R2 should be changed in order to ensure a correct biasing of D3.
The jumper JP1 allows choosing the 5V voltage from the inter nal zener diode network or pin 11 of CN5 (for ex-
ample an external µC board can provide 5V to the evaluation board). Also CN2 connector can be used to pro-
vide an external 5V voltage to the board (in that case R2, D3 should be disconnected). C N2, or pin 1 of CN5,
can also be used to provide a 5V voltag e to external c ircuits (as, for example, the PractiS PIN ST7 board) . In thi s
case the current that can be drawn form the board depends on the supply voltage and on R2 value.
Figure 54 to Figure 56 show the component placement and the two layers layout of the L6207N Evaluation
Board. A lar ge GND area has b een used, to guarantee mini mal noise and good p ower dissipation for the device.
AN1762 APP LICATION NOTE
50/53
Figure 52. EVAL6207N.
5.5.1 I mportant Notes
JP1 : close in INT position for use with PractiSPIN ST7 board
C6, C7 : recommended change to 5.6 nF for safe Overcurrent protection
R3, R4 : recommended change to 100 k for safe Overcurrent protection
R15, R18 : set the maximum current obtainable through PractiSPIN (see PractiSP IN documentation)
R2 : recommended change to adequate value (depending on supply voltage) to obtain 5V across D3
JP2, JP3 : close for safe Overcurrent protection
JP1
C6
C7
R3
R4
R15
R18
R2
JP2
JP3
51/53
AN1762 APPLICATION NOTE
Figure 53. EVAL6207N Electrical schematic.
+5V
VREF B
SENSEA
LIMITB
VCCREF
LIMITA
PullUp
PullUp
PullUp
+5V
VREF A
VCCREF
GND
SENSEB
L6207
INT2
ADC_REF
CW
TINPB0 P2.1
A1IN6 P8.1 TOUTAO P2.2
int.
TINPAO P2.0
OCMPB1/ICAPB1 P4.3
TOUTA1 P2.6
TOUTB1 P2.7
CW
OCMPA0/ICAPA0 P3.2
A0IN6 P7.6
ext.
CW
INT0
OCMPB0 P3.3
OCMPA1 P4.2
R7
R5
C5
CN3
1
2
R12
R2
R4
R16
R6
R14
R18
C9
JP3
R15
JP2
R8
CN5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
CN4
1
2
C11
R9
C3
D2
D3
C8
CN2
1
2
CN1
1
2
C2
R1
D1
JP1
13
2
C4
R3
R17
C1
C10
R13
R10
U1
IN1A 1
IN2A 2
SENSEA 3
RCA/INH 4
OUT1A
5
GND
6GND
7
OUT1B
8
RCB 9
SENSEB 10
IN1B 11
IN2B 12
VR EF B 13
ENB 14
VBOOT
15
OUT2B
16
VSB
17
GND
18 GND
19
VSA
20
OUT2A
21
VCP
22
ENA 23
VR EF A 24
C7
C6
R11
LIMIT_B
IN3 IN4
LIMIT_A
LIMIT_A
IN1
VREF_A
ENA
IN2
IN2
RCA/INH
IN1
IN3
ENA
VREFB
LIMIT_A
IN4
VREFA
LIMIT_B
ENB
LIMIT_B
RCA
SENSE_B
SENSE_A
ENB
VREF_B
AN1762 APP LICATION NOTE
52/53
Figure 54. EVAL6207N Component placemen t.
Figure 55. EVAL6207N Top Layer L ayout.
Power GND
(Bulk Capacitor)
Signal GND
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53/53
AN1762 APPLICATION NOTE
Figure 56. EVAL6207N Bottom Layer Layo ut.
6 REFERENCES
1] D. Arrigo, A . Genova, T. Hopkins, V. Marano, A. Novelli, "A New Fully Integrated Stepper Motor Driver IC",
Proceedings of PCIM 2001, September 2001, Intertech C ommunication.
2] H. Sax, "Stepper Motor Driving" (AN235).
3] T. Hopkins, "Controlling Voltage Transients in Full Bridge Driver Applications" (AN280).
4] P. Casati and C. Cognetti, "A New High Power IC Surface Mount Package Family" (AN 668)
Short SEN SE
Paths
Short SEN SE
Paths
Signal GND
