Kinetis V Series KV10 and KV11,
128/64 KB Flash
75 MHz Cortex-M0+ Based Microcontroller
The Kinetis V Series KV11x MCU family is built on ARM Cortex-
M0+ core and enabled by innovative 90nm thin film storage
(TFS) flash process technology. The KV11x is an extension of
the existing KV10x family providing increased memory, higher
pin count, additional FTMs and a FlexCAN serial interface.
• Dual 16-bit ADCs sampling at up to 1.2 MS/s in 12-bit
mode
• Highly accurate and flexible motor control timers
• Ideal for industrial motor control applications, inverters, and
low-end power conversion applications
• Enabled to support Kinetis Motor Suite (KMS), a bundled
hardware and software solution that enables rapid
configuration of BLDC and PMSM motor drive systems
Performance
• Up to 75 MHz ARM Cortex-M0+ based core
Memories and memory interfaces
• Up to 128 KB of program flash memory
• Up to 16 KB of RAM
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• 8-channel DMA controller
• SWD interface and Micro Trace buffer
• Bit Manipulation Engine (BME)
• External watchdog timer
• Advanced independent clocked watchdog
• Memory Mapped Divide and Square Root (MMDVSQ)
module
Clocks
• 32-40 kHz or 4-32 MHz external crystal oscillator
• Multipurpose clock generator (MCG) with frequency-
locked loop referencing either internal or external
reference clock
Security and integrity modules
• 80-bit unique identification (ID) number per chip
• Hardware CRC module
Communication interfaces
• One 16-bit SPI module
• One I2C module
• Two UART modules
• One FlexCAN module1
Timers
• Programmable delay block
• Two 6-channel FlexTimers (FTM) for motor control/
general purpose applications
• Four 2-channel FlexTimers (FTM) with quadrature
decoder functionality
• 16-bit low-power timer (LPTMR)
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C
Analog modules
• Two 16-bit SAR ADCs
• 12-bit DAC
• Two analog comparators (ACMP) containing a 6-bit
DAC and programmable reference input
Human-machine interface
• General-purpose I/O
MKV11Z128VXX7
MKV11Z64VXX7
MKV10Z64VXX7
MKV10Z128VXX7
MKV11Z128VLX7P
MKV10Z64VLX7P
32 QFN
5 x 5 x 1.23 mm Pitch
0.5 mm
64 LQFP
10 x 10 x 1.4 mm Pitch
0.5 mm
32 LQFP
7 x 7 x 1.4 mm Pitch
0.8 mm
48 LQFP
7 x 7 x 1.4 mm Pitch
0.5 mm
NXP Semiconductors KV11P64M75
Data Sheet: Technical Data Rev. 4, 05/2017
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Kinetis Motor Suite
• Supports Velocity and Position control of BLDC &
PMSM motors
• Implements Field Orient Control (FOC) using Back
EMF to improve motor efficiency
• Utilizes SpinTAC control theory that improves
overall system performance and reliability
1. Available only on KV11 parts
Ordering Information
Part Number 1Memory FlexCAN Maximum number of
I\O's
Flash (KB) SRAM (KB)
MKV11Z128VLH7 128 16 Yes 46
MKV11Z128VLF7 128 16 Yes 35
MKV11Z128VLC7 2128 16 Yes 26
MKV11Z128VFM7 128 16 Yes 26
MKV11Z64VLH7 64 16 Yes 46
MKV11Z64VLF7 64 16 Yes 35
MKV11Z64VLC7 264 16 Yes 26
MKV11Z64VFM7 64 16 Yes 26
MKV11Z128VLH7P 120 16 Yes 46
MKV11Z128VLF7P 120 16 Yes 35
MKV11Z128VLC7P 2120 16 Yes 26
MKV11Z128VFM7P 120 16 Yes 26
MKV10Z64VLH7P 56 16 Yes 46
MKV10Z64VLF7P 56 16 Yes 35
MKV10Z64VLC7P 256 16 Yes 26
MKV10Z64VFM7P 56 16 No 26
MKV10Z64VLH7 64 16 No 46
MKV10Z64VLF7 64 16 No 35
MKV10Z64VLC7 264 16 No 26
MKV10Z64VFM7 128 16 No 26
MKV10Z128VLH7 128 16 No 46
MKV10Z128VLF7 128 16 No 35
MKV10Z128VLC7 2128 16 No 26
MKV10Z128VFM7 128 16 No 26
1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search.
2. The 32-pin LQFP package supporting this part number is not yet available, however it is included in a Package Your
Way program for Kinetis MCUs. Please visit http://www.nxp.com/KPYW for more details.
2Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Related Resources
Type Description Resource
Selector
Guide
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Selector Guide
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KV10PB 1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KV10P48M75RM 1
Data Sheet The Data Sheet includes electrical characteristics and signal
connections.
This document
KMS User
Guide
The KMS User Guide provides a comprehensive description of the
features and functions of the Kinetis Motor Suite solution.
Kinetis Motor Suite User’s
Guide (KMS100UG) 1
KMS API
Reference
Manual
The KMS API reference manual provides a comprehensive description
of the API of the Kinetis Motor Suite function blocks.
Kinetis Motor Suite API
Reference Manual
(KMS100RM)1
Chip Errata The chip mask set Errata provides additional or corrective information
for a particular device mask set.
• KV10Z_1N81H1
• KINETIS_V_0N63P1
Package
drawing
Package dimensions are provided in package drawings. • QFN 32-pin:
98ASA00473D1
• LQFP 32-pin:
98ASH70029A1
• LQFP 48-pin:
98ASH00962A1
• LQFP 64-pin:
98ASS23234W1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 3
NXP Semiconductors
LEGEND
Not available on all parts. See ordering information table.
Figure 1. KV11 block diagram
4Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table of Contents
1 Ratings................................................................................ 6
1.1 Thermal handling ratings............................................. 6
1.2 Moisture handling ratings.............................................6
1.3 ESD handling ratings................................................... 6
1.4 Voltage and current operating ratings..........................6
2 General............................................................................... 7
2.1 AC electrical characteristics.........................................7
2.2 Nonswitching electrical specifications..........................8
2.2.1 Voltage and current operating requirements....8
2.2.2 LVD and POR operating requirements............ 9
2.2.3 Voltage and current operating behaviors......... 10
2.2.4 Power mode transition operating behaviors.....10
2.2.5 KV11x Power consumption operating
behaviors......................................................... 11
2.2.6 EMC radiated emissions operating behaviors..17
2.2.7 Designing with radiated emissions in mind...... 18
2.2.8 Capacitance attributes..................................... 18
2.3 Switching specifications...............................................18
2.3.1 Device clock specifications.............................. 18
2.3.2 General switching specifications......................19
2.4 Thermal specifications................................................. 20
2.4.1 Thermal operating requirements......................20
2.4.2 Thermal attributes............................................ 20
3 Peripheral operating requirements and behaviors.............. 21
3.1 Core modules...............................................................21
3.1.1 SWD Electricals .............................................. 21
3.2 System modules.......................................................... 22
3.3 Clock modules............................................................. 22
3.3.1 MCG specifications.......................................... 22
3.3.2 Oscillator electrical specifications.................... 24
3.4 Memories and memory interfaces................................26
3.4.1 Flash electrical specifications...........................26
3.5 Security and integrity modules.....................................28
3.6 Analog..........................................................................28
3.6.1 ADC electrical specifications............................28
3.6.2 CMP and 6-bit DAC electrical specifications....32
3.6.3 12-bit DAC electrical characteristics................ 34
3.7 Timers..........................................................................37
3.8 Communication interfaces........................................... 37
3.8.1 DSPI switching specifications (limited voltage
range)...............................................................37
3.8.2 DSPI switching specifications (full voltage
range)...............................................................40
3.8.3 I2C................................................................... 44
3.8.4 UART............................................................... 44
4 Kinetis Motor Suite.............................................................. 44
5 Dimensions..........................................................................44
5.1 Obtaining package dimensions....................................44
6 Pinout.................................................................................. 45
6.1 KV11 Signal Multiplexing and Pin Assignments.......... 45
6.2 KV11 Pinouts............................................................... 48
7 Ordering parts..................................................................... 52
7.1 Determining valid orderable parts................................52
8 Part identification.................................................................52
8.1 Description...................................................................53
8.2 Format..........................................................................53
8.3 Fields........................................................................... 53
8.4 Example.......................................................................53
9 Terminology and guidelines................................................ 54
9.1 Definition: Operating requirement................................54
9.2 Definition: Operating behavior..................................... 54
9.3 Definition: Attribute.......................................................54
9.4 Definition: Rating..........................................................55
9.5 Result of exceeding a rating........................................ 55
9.6 Relationship between ratings and operating
requirements................................................................56
9.7 Guidelines for ratings and operating requirements......56
9.8 Definition: Typical value...............................................57
9.9 Typical Value Conditions............................................. 58
10 Revision history...................................................................58
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 5
NXP Semiconductors
1 Ratings
1.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human-body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
-500 +500 V 2
ILAT Latch-up current at ambient temperature of 105 °C -100 +100 mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
1.4 Voltage and current operating ratings
Ratings
6Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Symbol Description Min. Max. Unit
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 120 mA
VIO Digital pin input voltage (except open drain pins) –0.3 VDD + 0.31V
Open drain pins (PTC6 and PTC7) –0.3 5.5 V
IDInstantaneous maximum current single pin limit (applies to
all port pins)
–25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
1. Maximum value of VIO (except open drain pins) must be 3.8 V.
2 General
Electromagnetic compatibility (EMC) performance depends on the environment in
which the MCU resides. Board design and layout, circuit topology choices, location,
characteristics of external components, and MCU software operation play a significant
role in EMC performance.
See the following applications notes available on nxp.com for guidelines on
optimizing EMC performance.
•AN2321: Designing for Board Level Electromagnetic Compatibility
•AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
•AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
•AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
•AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
General
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 7
NXP Semiconductors
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume:
1. output pins
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICIO Pin negative DC injection current—single pin
• VIN < VSS–0.3V -5 — mA
1
Table continues on the next page...
General
8Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 1. Voltage and current operating requirements (continued)
Symbol Description Min. Max. Unit Notes
IICcont Contiguous pin DC injection current—regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection –25 — mA
VRAM VDD voltage required to retain RAM 1.2 — V
1. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed, then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/IICIO.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— ±60 — mV
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— ±40 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising thresholds are falling threshold + hysteresis voltage
General
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 9
NXP Semiconductors
2.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol Description Min. Max. Unit Notes
VOH Output high voltage — Normal drive pad
All port pins, except PTC6 and PTC7
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
VOH Output high voltage — High drive pad
PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6,
PTD7 pins
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT Output high current total for all ports — 100 mA
VOL Output low voltage — Normal drive pad
All port pins
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
—
0.5
0.5
V
V
VOL Output low voltage — High drive pad
PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6,
PTD7 pins
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
—
—
0.5
0.5
V
V
IOLT Output low current total for all ports — 100 mA
IIN Input leakage current (per pin) for full temperature
range
— 1 μA
IIN Input leakage current (per pin) at 25 °C — 0.025 μA 1
IIN Input leakage current (total all pins) for full
temperature range
— 41 μA 1
IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA
RPU Internal pullup resistors 20 50 kΩ 2
1. Measured at VDD = 3.6 V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
General
10 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 75 MHz
• Bus and flash clock = 25 MHz
• FEI clock mode
Table 4. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
tPOR After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
— — 300 μs 1
• VLLS0 → RUN
—
123
132
μs
• VLLS1 → RUN
—
123
132
μs
• VLLS3 → RUN
—
67
72
μs
• VLPS → RUN
—
4
5
μs
• STOP → RUN
—
4
5
μs
1. Normal boot FTFA_FOPT[LPBOOT]=11
2.2.5 KV11x Power consumption operating behaviors
Table 5. KV11x power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — 5 mA 1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
• at 1.8 V 50 MHz (25 MHz Bus)
• at 3.0 V 50 MHz (25 MHz Bus)
• at 1.8 V 75 MHz (25 MHz Bus)
• at 3.0 V 75 MHz (25 MHz Bus)
—
—
—
—
5.3
5.4
7.2
7.3
6.2
6.3
8.3
8.3
mA
mA
mA
mA
Target IDD
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
Target IDD
Table continues on the next page...
General
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 11
NXP Semiconductors
Table 5. KV11x power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• at 1.8 V 50 MHz
• at 3.0 V 50 MHz
• at 1.8 V 75 MHz
• at 3.0 V 75 MHz
—
—
—
—
8.5
8.5
11.6
11.7
9.7
9.8
13.0
13.2
mA
mA
mA
mA
IDD_WAIT Wait mode high frequency 75 MHz current at
3.0 V — all peripheral clocks disabled
— 4 — mA —
IDD_WAIT Wait mode reduced frequency 50 MHz current
at 3.0 V — all peripheral clocks disabled
— 3.4 — mA —
IDD_VLPR Very-Low-Power Run mode current 4 MHz at
3.0 V — all peripheral clocks disabled
— 268 — μA 4 MHz CPU
speed, 1
MHz bus
speed.
IDD_VLPR Very-Low-Power Run mode current 4 MHz at
3.0 V — all peripheral clocks enabled
— 437 — μA 4 MHz CPU
speed, 1
MHz bus
speed.
IDD_VLPW Very-Low-Power Wait mode current at 3.0 V
— all peripheral clocks enabled
— 348.9 — μA 4 MHz CPU
speed, 1
MHz bus
speed.
IDD_VLPW Very-Low-Power Wait mode current at 3.0 V
— all peripheral clocks disabled
— 173.4 — μA 4 MHz CPU
speed, 1
MHz bus
speed.
IDD_STOP Stop mode current at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
247.2
260.7
286
324
422.7
286
300
312
353
494
μA
—
IDD_VLPS Very-Low-Power Stop mode current at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
2.9
6.8
15.4
29.1
66.4
3
5.9
13
39
86
μA
—
IDD_VLLS3 Very-Low-Leakage Stop mode 3 current at 3.0
V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
—
—
—
—
1.3
2
3.7
6.7
1.6
2.3
4.3
7.5
μA —
Table continues on the next page...
General
12 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 5. KV11x power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• at 85 °C
• at 105 °C
— 15.1 16
IDD_VLLS1 Very-Low-Leakage Stop mode 1 current at 3.0
V
• -40°C to 25°C
• at 50°C
• at 70°C
• at 85°C
• at 105°C
—
—
—
—
—
0.8
1.2
2.2
4.0
9.4
1.2
1.4
2.7
5.1
11.8
μA —
IDD_VLLS0 Very-Low-Leakage Stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
0.279
0.638
1.63
3.4
8.9
0.386
0.854
2.2
4.5
11.2
μA —
IDD_VLLS0 Very-Low-Leakage Stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0 V
• -40 °C to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
—
—
0.098
0.448
1.4
3.19
8.47
0.452
0.674
1.9
4.3
10.6
μA 2
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. No brownout
Table 6. Low power mode peripheral adders — typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52 52 52 52 52 52 µA
Table continues on the next page...
General
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 13
NXP Semiconductors
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206 228 237 245 251 258 uA
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
VLLS3
VLPS
STOP
440
440
510
510
490
490
560
560
540
540
560
560
560
560
560
560
570
570
610
610
580
580
680
680
nA
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
consumption.
22 22 22 22 22 22 µA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
ISPI SPI peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
II2C I2C peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
Table continues on the next page...
General
14 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IFTM FTM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100Hz clock signal. No load
is placed on the I/O generating the
clock signal. Includes selected clock
source and I/O switching currents.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
150
300
150
300
150
300
150
320
150
340
150
350
µA
IBG Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
366 366 366 366 366 366 µA
IWDOG WDOG peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
waiting for RX data at 115200 baud
rate. Includes selected clock source
power consumption.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode (except for 75 MHz which is in FEE mode), and
BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
General
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 15
NXP Semiconductors
Figure 3. Run mode supply current vs. core frequency
General
16 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol Description Frequency
band
(MHz)
Typ. Unit Notes
VRE1 Radiated emissions voltage, band 1 0.15–50 15 dBμV 1, 2
VRE2 Radiated emissions voltage, band 2 50–150 17 dBμV
VRE3 Radiated emissions voltage, band 3 150–500 12 dBμV
VRE4 Radiated emissions voltage, band 4 500–1000 4 dBμV
VRE_IEC IEC level 0.15–1000 M — 2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -
Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
General
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 17
NXP Semiconductors
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 75 MHz, fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
fSYS System and core clock — 48 MHz
fBUS Bus clock — 24 MHz
fFLASH Flash clock — 24 MHz
fLPTMR LPTMR clock — 24 MHz
High Speed run mode
fSYS System and core clock — 75 MHz
fBUS Bus clock — 25 MHz
fFLASH Flash clock — 25 MHz
fLPTMR LPTMR clock — 25 MHz
Table continues on the next page...
General
18 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 9. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fFTM FTM clock — 75 MHz
VLPR mode
fSYS System and core clock — 4 MHz
fBUS Bus clock — 1 MHz
fFLASH Flash clock — 1 MHz
fLPTMR LPTMR clock — 25 MHz
fERCLK External reference clock — 16 MHz
fLPTMR_pin LPTMR clock — 25 MHz
fLPTMR_ERCL
K
LPTMR external reference clock — 16 MHz
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range) (MCG_C2[RANGE]=1x)
— 16 MHz
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, and I2C signals.
Table 10. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 — ns 2
GPIO pin interrupt pulse width — Asynchronous path 16 — ns 2
Port rise and fall time
Fast slew rate
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
—
—
8
7
ns
ns
3
Port rise and fall time
Slow slew rate
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
—
—
15
25
ns
ns
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. For high drive pins with high drive enabled, load is 75pF; other pins load (low drive) is 25pF.
General
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 19
NXP Semiconductors
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol Description Min. Max. Unit
TJDie junction temperature –40 125 °C
TAAmbient temperature 1–40 105 °C
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 12. Thermal attributes
Board type Symb
ol
Description 64 LQFP 48
LQFP
32
LQFP
32
QFN
Unit Notes
Single-layer
(1S)
RθJA Thermal resistance,
junction to ambient
(natural convection)
64 81 85 98 °C/W 1
Four-layer
(2s2p)
RθJA Thermal resistance,
junction to ambient
(natural convection)
46 57 57 34 °C/W
Single-layer
(1S)
RθJMA Thermal resistance,
junction to ambient (200
ft./min. air speed)
52 68 72 82 °C/W
Four-layer
(2s2p)
RθJMA Thermal resistance,
junction to ambient (200
ft./min. air speed)
39 51 50 28 °C/W
— RθJB Thermal resistance,
junction to board
28 35 33 14 °C/W 2
— RθJC Thermal resistance,
junction to case
15 25 25 2.5 °C/W 3
—ΨJT Thermal characterization
parameter, junction to
package top outside
center (natural
convection)
2 7 7 8 °C/W 4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
General
20 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD Electricals
Table 13. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 SWD_CLK frequency of operation
• Serial wire debug
0
25
MHz
J2 SWD_CLK cycle period 1/J1 — ns
J3 SWD_CLK clock pulse width
• Serial wire debug
20
—
ns
J4 SWD_CLK rise and fall times — 3 ns
J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns
J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns
J11 SWD_CLK high to SWD_DIO data valid — 32 ns
J12 SWD_CLK high to SWD_DIO high-Z 5 — ns
J2
J3 J3
J4 J4
SWD_CLK (input)
Figure 5. Serial wire clock input timing
Peripheral operating requirements and behaviors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 21
NXP Semiconductors
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
Figure 6. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 14. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
fints_t Internal reference frequency (slow clock) —
user trimmed
31.25 — 39.0625 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
— ± 0.3 ± 0.6 %fdco 1
Table continues on the next page...
Peripheral operating requirements and behaviors
22 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 14. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Δfdco_t Total deviation of trimmed average DCO output
frequency over voltage and temperature
— +0.5/-0.7 ±2 %fdco 1, 2
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0 - 70 °C
— ± 0.4 ± 1.5 %fdco 1, 2
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
— 4 — MHz
Δfintf_ft Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
— +1/-2 ± 3 %fintf_ft 2
fintf_t Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 — 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
— — kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
— — kHz
FLL
ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS = 00,
DMX32 = 0)
640 × ffll_ref
20 20.97 25 MHz 3, 4
Mid range (DRS = 01,
DMX32 = 0)
1280 × ffll_ref
40 41.94 48 MHz
Mid range (DRS = 10,
DMX32 = 0)
1920 x ffll_ref
60 62.915 75 MHz
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS = 00,
DMX32 = 1)
732 × ffll_ref
— 23.99 — MHz 5
6
Mid range (DRS = 01,
DMX32 = 1)
1464 × ffll_ref
— 47.97 — MHz
Mid range (DRS = 10,
DMX32 = 1)
2197 × ffll_ref
– 71.991 – MHz
Jcyc_fll FLL period jitter
• fVCO = 75 MHz
— 180 — ps 7
tfll_acquire FLL target frequency acquisition time — — 1 ms 8
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
Peripheral operating requirements and behaviors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 23
NXP Semiconductors
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or there is a change from FLL disabled (BLPE, BLPI) to FLL enabled
(FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
950
1.2
1.5
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1
IDDOSC Supply current — high gain mode (HGO=1)
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
500
600
2.5
3
4
—
—
—
—
—
μA
μA
mA
mA
mA
1
CxEXTAL load capacitance — — — 2, 3
CyXTAL load capacitance — — — 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — MΩ 2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 — MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
— — — MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 — MΩ
Table continues on the next page...
Peripheral operating requirements and behaviors
24 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 15. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
— 200 — kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
0
—
kΩ
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 — 32 MHz
fec_extal Input clock frequency (external clock mode) — — 50 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 25
NXP Semiconductors
Table 16. Oscillator frequency specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— 1000 — ms 3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— 250 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 17. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time — 7.5 18 μs —
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversall Erase All high-voltage time — 104 904 ms 1
1. Maximum time based on expectations at cycling end-of-life.
Peripheral operating requirements and behaviors
26 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
3.4.1.2 Flash timing specifications — commands
Table 18. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1sec2k Read 1s Section execution time (flash sector) — — 60 μs 1
tpgmchk Program Check execution time — — 45 μs 1
trdrsrc Read Resource execution time — — 30 μs 1
tpgm4 Program Longword execution time — 65 145 μs —
tersscr Erase Flash Sector execution time — 14 114 ms 2
trd1all Read 1s All Blocks execution time — — 0.9 ms 1
trdonce Read Once execution time — — 30 μs 1
tpgmonce Program Once execution time — 100 — μs —
tersall Erase All Blocks execution time — 140 1150 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 19. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage
flash programming operation
— 2.5 12.0 mA
IDD_ERS Average current adder during high voltage
flash erase operation
— 1.5 8.0 mA
3.4.1.4 Reliability specifications
Table 20. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years —
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years —
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
Peripheral operating requirements and behaviors
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 27
NXP Semiconductors
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
ADC electrical specifications
3.6.1.1 16-bit ADC operating conditions
Table 21. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V
VREFL ADC reference
voltage low
VSSA VSSA VSSA V
VADIN Input voltage • 16-bit differential mode
• All other modes
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
V
CADIN Input
capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit
modes
—
—
8
4
10
5
pF
RADIN Input resistance — 2 5 kΩ
RAS Analog source
resistance
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
3
fADCK ADC conversion
clock frequency
≤ 13-bit mode 1.0 — 24.0 MHz 4
fADCK ADC conversion
clock frequency
16-bit mode 2.0 — 12.0 MHz 4
Crate ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20.000
—
1200
Ksps
5
Table continues on the next page...
3.6.1
ADC electrical specifications
28 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 21. 16-bit ADC operating conditions (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
Crate ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37.037
—
461.467
Ksps
5
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
RAS
VAS
CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PININPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 7. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
Table continues on the next page...
ADC electrical specifications
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 29
NXP Semiconductors
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
fADACK
ADC
asynchronous
clock source
• ADLPC = 1, ADHSC =
0
• ADLPC = 1, ADHSC =
1
• ADLPC = 0, ADHSC =
0
• ADLPC = 0, ADHSC =
1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK =
1/fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.7
±0.2
–1.1 to
+1.9
–0.3 to 0.5
LSB45
INL Integral non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±1.0
±0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB45
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
–4
–1.4
–5.4
–1.8
LSB4VADIN =
VDDA5
EQQuantization
error
• 16-bit modes
• ≤13-bit modes
—
—
–1 to 0
—
—
±0.5
LSB4
ENOB Effective number
of bits
16-bit differential mode
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
• Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.7
13.1
—
—
—
—
bits
bits
bits
bits
6, 7
SINAD Signal-to-noise
plus distortion
See ENOB 6.02 × ENOB + 1.76 dB 7
THD Total harmonic
distortion
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
—
—
–97
–91
—
—
dB
dB
7, 8
SFDR Spurious free
dynamic range
16-bit differential mode
82
100
—
dB
7, 8
Table continues on the next page...
ADC electrical specifications
30 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 22. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1. Min. Typ.2Max. Unit Notes
• Avg = 32
16-bit single-ended mode
• Avg = 32
78
92
—
dB
EIL Input leakage
error
IIn × RAS mV IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C 9
VTEMP25 Temp sensor
voltage
25 °C 706 716 726 mV 9
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. This data was collected with an external clock.
8. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
9. ADC conversion clock < 3 MHz
ADC electrical specifications
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 31
NXP Semiconductors
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
12.30
12.00
1 2 3 4 5 6 7 8 9 10 1211
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
14.00
13.75
13.25
13.00
12.75
12.50
12.00
11.75
11.50
11.25
11.00
1 2 3 4 5 6 7 8 9 10 1211
Averaging of 4 samples
Averaging of 32 samples
13.50
12.25
Figure 9. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 23. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
Table continues on the next page...
ADC electrical specifications
32 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 23. Comparator and 6-bit DAC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit
IDDHS Supply current, high-speed mode (EN = 1, PMODE =
1)
— — 200 μA
IDDLS Supply current, low-speed mode (EN = 1, PMODE =
0)
— — 20 μA
VAIN Analog input voltage VSS — VDD V
VAIO Analog input offset voltage — — 20 mV
VHAnalog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 — — V
VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN = 1,
PMODE = 1)
20 35 200 ns
tDLS Propagation delay, low-speed mode (EN = 1, PMODE
= 0)
80 100 600 ns
Analog comparator initialization delay2— — 40 μs
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to
DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
ADC electrical specifications
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 33
NXP Semiconductors
CMP Hysteresis vs Vinn
0
1
2
HYSTCTR
Setting
000.00E+00
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
Vinn (V)
3
30.00E-03
20.00E-03
10.00E-03
40.00E-03
50.00E-03
60.00E-03
70.00E-03
80.00E-03
90.00E-03
CMP Hysteresis (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
180.00E-03
CMP Hysteresis vs Vinn
0
1
2
HYSTCTR
Setting
60.00E-03
0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1
CMP Hysteresis (V)
Vinn (V)
3
-20.00E-03
000.00E+00
20.00E-03
40.00E-03
80.00E-03
100.00E-03
120.00E-03
140.00E-03
160.00E-03
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
ADC electrical specifications
34 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
3.6.3.1 12-bit DAC operating requirements
Table 24. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
CLOutput load capacitance — 100 pF 2
ILOutput load current — 1 mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
3.6.3.2 12-bit DAC operating behaviors
Table 25. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode — — 150 μA
IDDA_DACH
P
Supply current — high-speed mode — — 700 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs 1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs 1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08)—high-speed mode
— 1 — μs 1
—low-power mode — — 5 μs 1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
— — 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— — ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— — ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— — ±1 LSB 4
VOFFSET Offset error — ±0.4 ±0.8 %FSR 5
EGGain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB
TCO Temperature coefficient offset voltage — 3.7 — μV/C 6
TGE Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance (load = 3 kΩ) — — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h V/μs
Table continues on the next page...
ADC electrical specifications
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 35
NXP Semiconductors
Table 25. 12-bit DAC operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• High power (SPHP)
• Low power (SPLP)
1.2
0.05
1.7
0.12
—
—
BW 3dB bandwidth
• High power (SPHP)
• Low power (SPLP)
550
40
—
—
—
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
Digital Code
DAC12 INL (LSB)
0
500 1000 1500 2000 2500 3000 3500 4000
2
4
6
8
-2
-4
-6
-8
0
Figure 12. Typical INL error vs. digital code
ADC electrical specifications
36 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Temperature °C
DAC12 Mid Level Code Voltage
25 55 85 105 125
1.499
-40
1.4985
1.498
1.4975
1.497
1.4965
1.496
Figure 13. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
ADC electrical specifications
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 37
NXP Semiconductors
3.8.1 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 26. Master mode DSPI timing (limited voltage range)
Symbol Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation 25 MHz 1
DS1 DSPI_SCK output cycle time 2 x tBUS – ns 2
DS2 DSPI_SCK output high/low time (tSCK/2) – 2 (tSCK/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK
delay
(tSCK/2) – 2 – ns 3
DS4 DSPI_SCK to DSPI_PCSn invalid
delay
(tSCK/2) – 2 – ns 4
DS5 DSPI_SCK to DSPI_SOUT valid – 8.7 ns
DS6 DSPI_SCK to DSPI_SOUT invalid –2 − ns
DS7 DSPI_SIN to DSPI_SCK input setup 17 – ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 – ns
Frequency of operation –25 MHz 5
DS1 DSPI_SCK output cycle time 2 x tBUS – ns 2
DS2 DSPI_SCK output high/low time (tSCK/2) – 2 (tSCK/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK
delay
(tSCK/2) – 2 – ns 3
DS4 DSPI_SCK to DSPI_PCSn invalid
delay
(tSCK/2) – 2 – ns 4
DS5 DSPI_SCK to DSPI_SOUT valid – 14.7 ns
DS6 DSPI_SCK to DSPI_SOUT invalid –2 − ns
DS7 DSPI_SIN to DSPI_SCK input setup 17 – ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 – ns
Frequency of operation –37.5 MHz 6
DS1 DSPI_SCK output cycle time 2 x tBUS – ns 2
DS2 DSPI_SCK output high/low time (tSCK/2) – 2 (tSCK/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK
delay
(tSCK/2) – 2 – ns 3
DS4 DSPI_SCK to DSPI_PCSn invalid
delay
(tSCK/2) – 2 – ns 4
DS5 DSPI_SCK to DSPI_SOUT valid – 8.7 ns
DS6 DSPI_SCK to DSPI_SOUT invalid –2 − ns
Table continues on the next page...
ADC electrical specifications
38 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 26. Master mode DSPI timing (limited voltage range) (continued)
Symbol Description Min. Max. Unit Notes
DS7 DSPI_SIN to DSPI_SCK input setup 13 – ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 – ns
1. Normal pads
2. The SPI module is clocked by the system clock
3. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
4. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
5. Open Drain pads: SIN: PTC7, SOUT:PTC6
6. Fast pads: SIN: PTD7, SOUT:PTD6, SCK: PTD5, PCS:PTD4
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 14. DSPI classic SPI timing — master mode
Table 27. Slave mode DSPI timing (limited voltage range)
Symbol Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation –12.5 MHz 1
DS9 DSPI_SCK input cycle time 4 x tBUS – ns 2
DS10 DSPI_SCK input high/low time (tSCK/2) – 2 (tSCK/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid – 21 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 – ns
DS13 DSPI_SIN to DSPI_SCK input setup 2.2 – ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 – ns
DS15 DSPI_SS active to DSPI_SOUT driven – 15 ns
DS16 DSPI_SS inactive to DSPI_SOUT not
driven
– 15 ns
Frequency of operation –12.5 MHz 3
DS9 DSPI_SCK input cycle time 4 x tBUS — ns 2
DS10 DSPI_SCK input high/low time (tSCK/2) – 2 (tSCK/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid – 27 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 – ns
Table continues on the next page...
ADC electrical specifications
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 39
NXP Semiconductors
Table 27. Slave mode DSPI timing (limited voltage range) (continued)
Symbol Description Min. Max. Unit Notes
DS13 DSPI_SIN to DSPI_SCK input setup 2.2 – ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 – ns
DS15 DSPI_SS active to DSPI_SOUT driven – 15 ns
DS16 DSPI_SS inactive to DSPI_SOUT not
driven
– 21 ns
Frequency of operation –18.75 MHz 4
DS9 DSPI_SCK input cycle time 4 x tBUS — ns 2
DS10 DSPI_SCK input high/low time (tSCK/2) – 2 (tSCK/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid – 17 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 – ns
DS13 DSPI_SIN to DSPI_SCK input setup 2.2 – ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 – ns
DS15 DSPI_SS active to DSPI_SOUT driven – 15 ns
DS16 DSPI_SS inactive to DSPI_SOUT not
driven
– 11 ns
1. Normal pads
2. The SPI module is clocked by the system clock
3. Open Drain pads: SIN: PTC7, SOUT:PTC6
4. Fast pads: SIN: PTD7, SOUT:PTD6, SCK: PTD5, PCS:PTD4
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 15. DSPI classic SPI timing — slave mode
ADC electrical specifications
40 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
3.8.2 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 28. Master mode DSPI timing (full voltage range)
Symbol Description Min. Max. Unit Notes
Operating voltage 1.7 3.6 V 1
Frequency of operation –18.75 MHz 2
DS1 DSPI_SCK output cycle
time
2 x tBUS – ns 3
DS2 DSPI_SCK output
high/low time
(tSCK/2) – 4 (tSCK/2) + 4 ns
DS3 DSPI_PCSn valid to
DSPI_SCK delay
(tSCK/2) – 4 – ns 4
DS4 DSPI_SCK to
DSPI_PCSn invalid delay
(tSCK/2) – 4 – ns 5
DS5 DSPI_SCK to
DSPI_SOUT valid
– 10
DS6 DSPI_SCK to
DSPI_SOUT invalid
–7.8 – ns
DS7 DSPI_SIN to DSPI_SCK
input setup
24 – ns
DS8 DSPI_SCK to DSPI_SIN
input hold
0 – ns
Frequency of operation –18.75 MHz 6
DS1 DSPI_SCK output cycle
time
2 x tBUS – ns 3
DS2 DSPI_SCK output
high/low time
(tSCK/2) – 4 (tSCK/2) + 4 ns
DS3 DSPI_PCSn valid to
DSPI_SCK delay
(tSCK/2) – 4 – ns 4
DS4 DSPI_SCK to
DSPI_PCSn invalid delay
(tSCK/2) – 4 – ns 5
DS5 DSPI_SCK to
DSPI_SOUT valid
– 26
DS6 DSPI_SCK to
DSPI_SOUT invalid
–7.8 – ns
DS7 DSPI_SIN to DSPI_SCK
input setup
24 – ns
DS8 DSPI_SCK to DSPI_SIN
input hold
0 – ns
Table continues on the next page...
ADC electrical specifications
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 41
NXP Semiconductors
Table 28. Master mode DSPI timing (full voltage range) (continued)
Symbol Description Min. Max. Unit Notes
Frequency of operation –25 MHz 7
DS1 DSPI_SCK output cycle
time
2 x tBUS – ns 3
DS2 DSPI_SCK output
high/low time
(tSCK/2) – 4 (tSCK/2) + 4 ns
DS3 DSPI_PCSn valid to
DSPI_SCK delay
(tSCK/2) – 4 – ns 4
DS4 DSPI_SCK to
DSPI_PCSn invalid delay
(tSCK/2) – 4 – ns 5
DS5 DSPI_SCK to
DSPI_SOUT valid
– 10
DS6 DSPI_SCK to
DSPI_SOUT invalid
–7.8 – ns
DS7 DSPI_SIN to DSPI_SCK
input setup
17 – ns
DS8 DSPI_SCK to DSPI_SIN
input hold
0 – ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. Normal pads
3. The SPI module is clocked by the system clock
4. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
5. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC]
6. Open Drain pads: SIN: PTC7, SOUT:PTC6
7. Fast pads: SIN: PTD7, SOUT:PTD6, SCK: PTD5, PCS:PTD4
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 16. DSPI classic SPI timing — master mode
Table 29. Slave mode DSPI timing (full voltage range)
Symbol Description Min. Max. Unit Notes
Operating voltage 1.7 3.6 V
Frequency of operation –9.375 MHz 1
Table continues on the next page...
ADC electrical specifications
42 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 29. Slave mode DSPI timing (full voltage range) (continued)
Symbol Description Min. Max. Unit Notes
DS9 DSPI_SCK input cycle time 4 x tBUS — ns 2
DS10 DSPI_SCK input high/low time (tSCK/2) – 4 (tSCK/2) + 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid – 27.8 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 – ns
DS13 DSPI_SIN to DSPI_SCK input setup 2.7 – ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 – ns
DS15 DSPI_SS active to DSPI_SOUT driven – 22 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven – 22 ns
Frequency of operation –9.375 MHz 3
DS9 DSPI_SCK input cycle time 4 x tBUS — ns 2
DS10 DSPI_SCK input high/low time (tSCK/2) – 4 (tSCK/2) + 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid – 43.8 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 – ns
DS13 DSPI_SIN to DSPI_SCK input setup 2.7 – ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 – ns
DS15 DSPI_SS active to DSPI_SOUT driven – 22 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven – 38 ns
Frequency of operation 12.5 MHz 4
DS9 DSPI_SCK input cycle time 4 x tBUS — ns 2
DS10 DSPI_SCK input high/low time (tSCK/2) – 4 (tSCK/2) + 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid – 20.8 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 – ns
DS13 DSPI_SIN to DSPI_SCK input setup 2.7 – ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 – ns
DS15 DSPI_SS active to DSPI_SOUT driven – 22 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven – 15 ns
1. Normal pads
2. The SPI module is clocked by the system clock
3. Open Drain pads: SIN: PTC7, SOUT:PTC6
4. Fast pads: SIN: PTD7, SOUT:PTD6, SCK: PTD5, PCS:PTD4
ADC electrical specifications
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 43
NXP Semiconductors
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 17. DSPI classic SPI timing — slave mode
3.8.3 I2C
See General switching specifications.
3.8.4 UART
See General switching specifications.
4Kinetis Motor Suite
Kinetis Motor Suite is a bundled software solution that enables the rapid configuration
of motor drive systems, and accelerates development of the final motor drive
application. Several members of the KV1x family are enabled with Kinetis motor suite.
The enabled devices can be identified within the orderable part numbers in this table.
For more information refer to Kinetis Motor Suite User's Guide (KMS100UG ) and
Kinetis Motor Suite API Reference Manual (KMS100RM, 1).
5Dimensions
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
Kinetis Motor Suite
44 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
5.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package Then use this document number
32-pin QFN 98ASA00473D
32-pin LQFP 198ASH70029A
48-pin LQFP 98ASH00962A
64-pin LQFP 98ASS23234W
1. The 32-pin LQFP package for this product is not yet available, however it is included in a Package Your Way program
for Kinetis MCUs. Please visit http://www.nxp.com/KPYW for more details.
6 Pinout
6.1 KV11 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
• PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, PTD7
are high current pins.
• PTC6 and PTC7 have open drain outputs
64
LQFP
48
QFP
32
QFN
32
LQFP
Pin Name DEFAULT ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
— — 7 7 VDDA/
VREFH
VDDA/
VREFH
VDDA/
VREFH
— — 8 8 VREFL/
VSSA
VREFL/
VSSA
VREFL/
VSSA
1 — — — PTE0 ADC1_SE12 ADC1_SE12 PTE0 UART1_TX
2 — — — PTE1/
LLWU_P0
ADC1_SE13 ADC1_SE13 PTE1/
LLWU_P0
UART1_RX
3 1 1 1 VDD VDD VDD
4 2 2 2 VSS VSS VSS
5 3 3 3 PTE16 ADC0_SE1/
ADC0_DP1/
ADC1_SE0
ADC0_SE1/
ADC0_DP1/
ADC1_SE0
PTE16 SPI0_PCS0 UART1_TX FTM_
CLKIN0
FTM0_FLT3
Pinout
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 45
NXP Semiconductors
64
LQFP
48
QFP
32
QFN
32
LQFP
Pin Name DEFAULT ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
6 4 4 4 PTE17/
LLWU_P19
ADC0_DM1/
ADC0_SE5/
ADC1_SE5
ADC0_DM1/
ADC0_SE5/
ADC1_SE5
PTE17/
LLWU_P19
SPI0_SCK UART1_RX FTM_
CLKIN1
LPTMR0_
ALT3
7 5 5 5 PTE18/
LLWU_P20
ADC0_SE6/
ADC1_SE1/
ADC1_DP1
ADC0_SE6/
ADC1_SE1/
ADC1_DP1
PTE18/
LLWU_P20
SPI0_SOUT UART1_
CTS_b
I2C0_SDA SPI0_SIN
8 6 6 6 PTE19 ADC0_SE7/
ADC1_SE7/
ADC1_DM1
ADC0_SE7/
ADC1_SE7/
ADC1_DM1
PTE19 SPI0_SIN UART1_
RTS_b
I2C0_SCL SPI0_SOUT
9 7 — — PTE20 ADC0_SE0/
ADC0_DP0
ADC0_SE0/
ADC0_DP0
PTE20 FTM1_CH0 UART0_TX
10 8 — — PTE21 ADC0_SE4/
ADC0_DM0
ADC0_SE4/
ADC0_DM0
PTE21 FTM1_CH1 UART0_RX
11 — — — PTE22 ADC0_SE12 ADC0_SE12 PTE22
12 — — — PTE23 ADC0_SE13 ADC0_SE13 PTE23
13 9 — — VDDA VDDA VDDA
14 10 — — VREFH VREFH VREFH
15 11 — — VREFL VREFL VREFL
16 12 — — VSSA VSSA VSSA
17 13 — — PTE29 CMP1_IN5/
CMP0_IN5
CMP1_IN5/
CMP0_IN5
PTE29 FTM0_CH2 FTM_
CLKIN0
18 14 9 9 PTE30 ADC1_SE4/
CMP1_IN4/
DAC0_OUT
ADC1_SE4/
CMP1_IN4/
DAC0_OUT
PTE30 FTM0_CH3 FTM_
CLKIN1
19 — — — PTE31 ADC0_SE14/
CMP0_IN4
ADC0_SE14/
CMP0_IN4
PTE31
20 15 10 10 PTE24 DISABLED PTE24 CAN0_TX FTM0_CH0 I2C0_SCL EWM_OUT_
b
21 16 11 11 PTE25/
LLWU_P21
DISABLED PTE25/
LLWU_P21
CAN0_RX FTM0_CH1 I2C0_SDA EWM_IN
22 17 12 12 PTA0 SWD_CLK SWD_CLK PTA0 UART0_
CTS_b
FTM0_CH5 EWM_IN SWD_CLK
23 18 13 13 PTA1 DISABLED PTA1 UART0_RX FTM2_CH0 CMP0_OUT FTM2_QD_
PHA
FTM1_CH1 FTM4_CH0
24 19 14 14 PTA2 DISABLED PTA2 UART0_TX FTM2_CH1 CMP1_OUT FTM2_QD_
PHB
FTM1_CH0 FTM4_CH1
25 20 15 15 PTA3 SWD_DIO SWD_DIO PTA3 UART0_
RTS_b
FTM0_CH0 FTM2_FLT0 EWM_OUT_
b
SWD_DIO
26 21 16 16 PTA4/
LLWU_P3
NMI_b NMI_b PTA4/
LLWU_P3
FTM0_CH1 FTM4_FLT0 FTM0_FLT3 NMI_b
27 — — — PTA5 DISABLED PTA5 FTM0_CH2 FTM5_FLT0
28 — — — PTA12 DISABLED PTA12 CAN0_TX FTM1_CH0 FTM1_QD_
PHA
29 — — — PTA13/
LLWU_P4
DISABLED PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 FTM1_QD_
PHB
30 22 — — VDD VDD VDD
Pinout
46 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
64
LQFP
48
QFP
32
QFN
32
LQFP
Pin Name DEFAULT ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
31 23 — — VSS VSS VSS
32 24 17 17 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_
CLKIN0
FTM3_CH2
33 25 18 18 PTA19 XTAL0 XTAL0 PTA19 FTM0_FLT0 FTM1_FLT0 FTM_
CLKIN1
LPTMR0_
ALT1
34 26 19 19 PTA20 RESET_b PTA20 RESET_b
35 27 20 20 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8
ADC0_SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
UART0_RX
36 28 21 21 PTB1 ADC0_SE9/
ADC1_SE9
ADC0_SE9/
ADC1_SE9
PTB1 I2C0_SDA FTM1_CH1 FTM0_FLT2 EWM_IN FTM1_QD_
PHB
UART0_TX
37 29 — — PTB2 ADC0_SE10/
ADC1_SE10/
ADC1_DM2
ADC0_SE10/
ADC1_SE10/
ADC1_DM2
PTB2 I2C0_SCL UART0_
RTS_b
FTM0_FLT1 FTM0_FLT3
38 30 — — PTB3 ADC1_SE2/
ADC1_DP2
ADC1_SE2/
ADC1_DP2
PTB3 I2C0_SDA UART0_
CTS_b
FTM0_FLT0
39 31 — — PTB16 DISABLED PTB16 UART0_RX FTM_
CLKIN2
CAN0_TX EWM_IN
40 32 — — PTB17 DISABLED PTB17 UART0_TX FTM_
CLKIN1
CAN0_RX EWM_OUT_
b
41 — — — PTB18 DISABLED PTB18 CAN0_TX FTM3_CH2
42 — — — PTB19 DISABLED PTB19 CAN0_RX FTM3_CH3
43 33 — — PTC0 ADC1_SE11 ADC1_SE11 PTC0 SPI0_PCS4 PDB_
EXTRG0
CMP0_OUT FTM0_FLT0 SPI0_PCS0
44 34 22 22 PTC1/
LLWU_P6
ADC1_SE3 ADC1_SE3 PTC1/
LLWU_P6
SPI0_PCS3 UART1_
RTS_b
FTM0_CH0 FTM2_CH0
45 35 23 23 PTC2 ADC0_SE11/
CMP1_IN0
ADC0_SE11/
CMP1_IN0
PTC2 SPI0_PCS2 UART1_
CTS_b
FTM0_CH1 FTM2_CH1
46 36 24 24 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT FTM3_FLT0
47 — — — VSS VSS VSS
48 — — — VDD VDD VDD
49 37 25 25 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT
50 38 26 26 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
CMP0_OUT FTM0_CH2
51 39 27 27 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_SOUT PDB_
EXTRG1
UART0_RX I2C0_SCL
52 40 28 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN UART0_TX I2C0_SDA
53 — — — PTC8 ADC1_SE14/
CMP0_IN2
ADC1_SE14/
CMP0_IN2
PTC8 FTM3_CH4
54 — — — PTC9 ADC1_SE15/
CMP0_IN3
ADC1_SE15/
CMP0_IN3
PTC9 FTM3_CH5
55 — — — PTC10 ADC1_SE16 ADC1_SE16 PTC10 FTM5_CH0 FTM5_QD_
PHA
Pinout
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 47
NXP Semiconductors
64
LQFP
48
QFP
32
QFN
32
LQFP
Pin Name DEFAULT ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
56 — — — PTC11/
LLWU_P11
ADC1_SE17 ADC1_SE17 PTC11/
LLWU_P11
FTM5_CH1 FTM5_QD_
PHB
57 41 — — PTD0/
LLWU_P12
DISABLED PTD0/
LLWU_P12
SPI0_PCS0 UART0_
CTS_b
FTM0_CH0 UART1_RX FTM3_CH0
58 42 — — PTD1 ADC0_SE2 ADC0_SE2 PTD1 SPI0_SCK UART0_
RTS_b
FTM0_CH1 UART1_TX FTM3_CH1
59 43 — — PTD2/
LLWU_P13
DISABLED PTD2/
LLWU_P13
SPI0_SOUT UART0_RX FTM0_CH2 FTM3_CH2 I2C0_SCL
60 44 — — PTD3 DISABLED PTD3 SPI0_SIN UART0_TX FTM0_CH3 FTM3_CH3 I2C0_SDA
61 45 29 29 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI0_PCS1 UART0_
RTS_b
FTM0_CH4 FTM2_CH0 EWM_IN SPI0_PCS0
62 46 30 30 PTD5 ADC0_SE3 ADC0_SE3 PTD5 SPI0_PCS2 UART0_
CTS_b
FTM0_CH5 FTM2_CH1 EWM_OUT_
b
SPI0_SCK
63 47 31 31 PTD6/
LLWU_P15
ADC1_SE6 ADC1_SE6 PTD6/
LLWU_P15
FTM4_CH0 UART0_RX FTM0_CH0 FTM1_CH0 FTM0_FLT0 SPI0_SOUT
64 48 32 32 PTD7 DISABLED PTD7 FTM4_CH1 UART0_TX FTM0_CH1 FTM1_CH1 FTM0_FLT1 SPI0_SIN
6.2 KV11 Pinouts
The following figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
Pinout
48 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
PTE24
PTE31
PTE30
PTE29
VSSA
VREFL
VREFH
VDDA
PTE23
PTE22
PTE21
PTE20
PTE19
PTE18/LLWU_P20
PTE17/LLWU_P19
PTE16
VSS
VDD
PTE1/LLWU_P0
PTE0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
64
63
62
61
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC11/LLWU_P11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VDD
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTC0
PTB19
PTB18
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
PTA18
VSS
VDD
PTA13/LLWU_P4
PTA12
PTA5
PTA4/LLWU_P3
PTA3
PTA2
PTA1
PTA0
PTE25/LLWU_P21
Figure 18. 64 LQFP Pinout Diagram
Pinout
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 49
NXP Semiconductors
VSSA
VREFL
VREFH
VDDA
PTE21
PTE20
PTE19
PTE18/LLWU_P20
PTE17/LLWU_P19
PTE16
VSS
VDD
12
11
10
9
8
7
6
5
4
3
2
1
48
47
46
45
44
43
42
41
40
39
38
37
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
36
35
34
33
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTC0
32
31
30
29
28
27
26
25
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
PTA3
PTA2
PTA1
PTA0
24
23
22
21
20
19
18
17
PTE25/LLWU_P21
PTE24
PTE30
PTE29
16
15
14
13
PTA18
VSS
VDD
PTA4/LLWU_P3
Figure 19. 48 QFP Pinout Diagram
Pinout
50 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
32
31
30
29
28
27
26
25
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTA0
PTE25/LLWU_P21
PTE24
PTE30
12
11
10
9
PTA4/LLWU_P3
PTA3
PTA2
PTA1
16
15
14
13
PTB0/LLWU_P5
PTA20
PTA19
PTA18
24
23
22
21
20
19
18
17
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTB1
VREFL/VSSA
VDDA/VREFH
PTE19
PTE18/LLWU_P20
PTE17/LLWU_P19
PTE16
VSS
VDD
8
7
6
5
4
3
2
1
Figure 20. 32 LQFP Pinout Diagram
Pinout
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 51
NXP Semiconductors
32
31
30
29
28
27
26
25
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
PTA0
PTE25/LLWU_P21
PTE24
PTE30
12
11
10
9
PTA4/LLWU_P3
PTA3
PTA2
PTA1
16
15
14
13
PTB0/LLWU_P5
PTA20
PTA19
PTA18
24
23
22
21
20
19
18
17
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTB1
VREFL/VSSA
VDDA/VREFH
PTE19
PTE18/LLWU_P20
PTE17/LLWU_P19
PTE16
VSS
VDD
8
7
6
5
4
3
2
1
Figure 21. 32 QFN Pinout Diagram
7Ordering parts
7.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.nxp.com and perform a part number search for the
MKV11 device numbers.
8Part identification
Ordering parts
52 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
8.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
8.2 Format
Part numbers for this device have the following format:
Q KV## M FFF R T PP CC S N
8.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field Description Values
Q Qualification status • M = Fully qualified, general market flow
• P = Prequalification
KV## Kinetis family • KV10 and KV11
M Key attribute • Z = M0+ core
FFF Program flash memory size • 128 = 128 KB
T Temperature range (°C) • V = –40 to 105
PP Package identifier • LC = 32 LQFP (7 mm x 7 mm)
• FM = 32 QFN (5 mm x 5 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
CCC Maximum CPU frequency (MHz) • 7 = 75 MHz
S Software type • P = KMS-PMSM and BLDC
• (Blank) = Not software enabled
N Packaging type • R = Tape and reel
• (Blank) = Trays
8.4 Example
This is an example part number:
MKV11Z128VFM7
Part identification
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 53
NXP Semiconductors
9 Terminology and guidelines
9.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
9.1.1 Example
This is an example of an operating requirement:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
0.9 1.1 V
9.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
9.2.1 Example
This is an example of an operating behavior:
Symbol Description Min. Max. Unit
IWP Digital I/O weak pullup/
pulldown current
10 130 µA
Terminology and guidelines
54 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
9.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
9.3.1 Example
This is an example of an attribute:
Symbol Description Min. Max. Unit
CIN_D Input capacitance:
digital pins
— 7 pF
9.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if
exceeded, may cause permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
9.4.1 Example
This is an example of an operating rating:
Symbol Description Min. Max. Unit
VDD 1.0 V core supply
voltage
–0.3 1.2 V
Terminology and guidelines
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 55
NXP Semiconductors
9.5 Result of exceeding a rating
40
30
20
10
0
Measured characteristic
Operating rating
Failures in time (ppm)
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
9.6 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
9.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
Terminology and guidelines
56 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
9.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
9.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol Description Min. Typ. Max. Unit
IWP Digital I/O weak
pullup/pulldown
current
10 70 130 µA
9.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
Terminology and guidelines
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 57
NXP Semiconductors
0.90 0.95 1.00 1.05 1.10
0
500
1000
1500
2000
2500
3000
3500
4000
4500
5000
150 °C
105 °C
25 °C
–40 °C
VDD (V)
I(μA)
DD_STOP
TJ
9.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD 3.3 V supply voltage 3.3 V
10 Revision history
The following table provides a revision history for this document.
Table 30. Revision history
Rev. No. Date Substantial Changes
0 11/2014 Initial Prelim release.
1 02/2015 Updated the following sections:
• DSPI switching specifications (limited voltage range)
• DSPI switching specifications (full voltage range)
• KV11 Signal Multiplexing and Pin Assignments
Table continues on the next page...
Revision history
58 Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017
NXP Semiconductors
Table 30. Revision history (continued)
Rev. No. Date Substantial Changes
2 04/2015 Updated the following sections:
• Power mode transition operating behaviors
• Power consumption operating behaviors
• 16-bit ADC operating conditions
• Fields
• Updated the table "16-bit ADC electrical characteristics" with a
footnote
• Added the figure "Run mode supply current vs. core frequency" to
the section "Diagram: Typical IDD_RUN operating behavior"
3 06/2015 • Added a footnote to the ambient temperature entry in the table
"Thermal operating requirements"
4 05/2017 • Added KMS related information in front matter
• Added the section "KMS Motor Suite"
• Added "S" in the sections "Format" and "Fields" to specify software
type in part number
• Updated the section "Example" to add an example for KMS part
number
• Added the KMS supported part numbers in the table "Ordering
information"
• Updated the table "Related resources," to include references to
KMS documents
• Updated the figure "KV11 block diagram"
• Added a note to the tPOR in the table "Power mode transition
operating behaviors."
• Changed freescale.com to nxp.com throughout
Revision history
Kinetis V Series KV10 and KV11, 128/64 KB Flash, Rev. 4, 05/2017 59
NXP Semiconductors
How to Reach Us:
Home Page:
nxp.com
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nxp.com/support
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
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on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
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©2014-2017 NXP B.V.
Document Number KV11P64M75
Revision 4, 05/2017
