PD - 94538B IRLR7821 IRLU7821 (R) HEXFET Power MOSFET Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use VDSS RDS(on) max 10m: 30V Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current D-Pak IRLR7821 Qg 10nC I-Pak IRLU7821 Absolute Maximum Ratings Parameter Max. Units 30 V VDS Drain-to-Source Voltage VGS Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V 20 65 IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current 260 ID @ TC = 25C ID @ TC = 100C c PD @TC = 25C Maximum Power Dissipation PD @TC = 100C Maximum Power Dissipation TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range f 47f g g A W 75 37.5 W/C C 0.50 -55 to + 175 Thermal Resistance Parameter RJC RJA Junction-to-Case Junction-to-Ambient (PCB Mount) RJA Junction-to-Ambient g Typ. Max. --- 2.0 --- 50 --- 110 Units C/W Notes through are on page 11 www.irf.com 1 4/5/04 IRLR/U7821 Static @ TJ = 25C (unless otherwise specified) Parameter Min. Typ. Max. Units BVDSS Drain-to-Source Breakdown Voltage 30 --- --- VDSS/TJ Breakdown Voltage Temp. Coefficient --- 23 --- RDS(on) Static Drain-to-Source On-Resistance V Conditions VGS = 0V, ID = 250A --- 7.5 10 mV/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 15A --- 9.5 12.5 VGS = 4.5V, ID = 12A VGS(th) Gate Threshold Voltage 1.0 --- --- V VGS(th) Gate Threshold Voltage Coefficient --- -5.3 --- mV/C IDSS Drain-to-Source Leakage Current --- --- 1.0 A VDS = 24V, VGS = 0V --- --- 150 IGSS Gate-to-Source Forward Leakage --- --- 100 nA VGS = 20V Gate-to-Source Reverse Leakage --- --- -100 gfs Qg Forward Transconductance 46 --- --- S VDS = 15V, ID = 12A f f VDS = VGS, ID = 250A VDS = 24V, VGS = 0V, TJ = 125C VGS = -20V Total Gate Charge --- 10 14 Qgs1 Pre-Vth Gate-to-Source Charge --- 2.0 --- Qgs2 Post-Vth Gate-to-Source Charge --- 1.2 --- Qgd Gate-to-Drain Charge --- 2.5 --- ID = 12A Qgodr --- 4.3 --- See Fig. 16 Qsw Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) --- 3.7 --- Qoss Output Charge --- 8.5 --- td(on) Turn-On Delay Time --- 11 --- VDD = 15V, VGS = 4.5V tr Rise Time --- 4.2 --- ID = 12A td(off) Turn-Off Delay Time --- 10 --- tf Fall Time --- 3.2 --- Ciss Input Capacitance --- 1030 --- Coss Output Capacitance --- 360 --- Crss Reverse Transfer Capacitance --- 120 --- VDS = 16V nC nC ns VGS = 4.5V VDS = 16V, VGS = 0V f Clamped Inductive Load VGS = 0V pF VDS = 15V = 1.0MHz Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy c dh c Typ. Max. Units --- 230 mJ --- 12 A --- 7.5 mJ Diode Characteristics Parameter Min. Typ. Max. Units f Conditions IS Continuous Source Current --- --- 65 ISM (Body Diode) Pulsed Source Current --- --- 260 showing the integral reverse VSD (Body Diode) Diode Forward Voltage --- --- 1.0 V p-n junction diode. TJ = 25C, IS = 12A, VGS = 0V trr Reverse Recovery Time --- 26 38 ns Qrr Reverse Recovery Charge --- 15 23 nC ton Forward Turn-On Time 2 ch MOSFET symbol A D G S f TJ = 25C, IF = 12A, VDD = 15V di/dt = 100A/s f Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) www.irf.com IRLR/U7821 1000 10000 VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V 2.5V 1000 100 BOTTOM VGS 10V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V 2.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 10 1 2.5V 100 BOTTOM 10 2.5V 20s PULSE WIDTH Tj = 175C 20s PULSE WIDTH Tj = 25C 1 0.1 0.1 1 10 0.1 100 1 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.0 C 10 TJ = 25 C V DS= 15V 20s PULSE WIDTH 1 2.0 4.0 6.0 8.0 V GS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 10.0 I D = 65A 1.5 (Normalized) R DS(on) , Drain-to-Source On Resistance I D , Drain-to-Source Current (A) 1000 TJ = 175 100 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) 100 10 1.0 0.5 V GS = 10V 0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ, Junction Temperature (C) Fig 4. Normalized On-Resistance vs. Temperature 3 IRLR/U7821 10000 6 VGS , Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd C, Capacitance(pF) Coss = Cds + Cgd Ciss 1000 Coss Crss 100 ID= 12A 4 3 2 1 0 10 1 10 0 100 4 6 8 10 12 Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 1000 ID, Drain-to-Source Current (A) 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100 I SD , Reverse Drain Current (A) 2 Q G Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) TJ = 175 C 10 T J= 25 C 1 V GS = 0 V 0.0 0.5 1.0 1.5 V SD,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 100sec 10 1msec 1 10msec Tc = 25C Tj = 175C Single Pulse 0.1 0.1 4 VDS= 24V VDS= 16V 5 2.0 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRLR/U7821 2.5 70 VGS(th) Gate threshold Voltage (V) LIMITED BY PACKAGE 60 I D , Drain Current (A) 50 40 30 20 10 2.0 ID = 250A 1.5 1.0 0.5 0 25 50 75 100 125 150 175 -75 -50 -25 TC , Case Temperature ( C) 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature (Z thJC ) 10 1 D = 0.50 Thermal Response 0.20 0.10 0.05 0.1 0.02 0.01 P DM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 t1/ t 2 J = P DM x Z thJC +T C 0.1 1 t1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 RDS(on), Drain-to -Source On Resistance (m ) IRLR/U7821 30 1000 ID = 15A ID 4.9A 8.5A 12A TOP 25 EAS , Single Pulse Avalanche Energy (mJ) 800 20 TJ = 125C 15 10 TJ = 25C 5 0 2 3 4 5 6 7 8 9 10 BOTTOM 600 400 200 0 25 50 75 100 125 150 175 ( C) Starting Tj, Junction Temperature V GS, Gate -to -Source Voltage (V) Fig 12. On-Resistance vs. Gate Voltage Fig 13. Maximum Avalanche Energy vs. Drain Current Current Regulator Same Type as D.U.T. V(BR)DSS 15V tp VDS 50K .2F 12V DRIVER L .3F + V - DS D.U.T. D.U.T RG + V - DD IAS 20V VGS tp VGS A 3mA 0.01 I AS IG ID Current Sampling Resistors Fig 14. Unclamped Inductive Test Circuit and Waveform Fig 15. Gate Charge Test Circuit LD VDS VDS + 90% VDD D.U.T VGS Pulse Width < 1s Duty Factor < 0.1% Fig 16. Switching Time Test Circuit 6 10% VGS td(on) tr td(off) tf Fig 17. Switching Time Waveforms www.irf.com IRLR/U7821 D.U.T Driver Gate Drive + - - * D.U.T. ISD Waveform Reverse Recovery Current + RG * * * * dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD P.W. Period VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple 5% * VGS = 5V for Logic Level Devices Fig 18. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 19. Gate Charge Waveform www.irf.com 7 IRLR/U7821 Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms x Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg x Vg x f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput Q + oss x Vin x f + (Qrr x Vin x f ) 2 This can be expanded and approximated by; *dissipated primarily in Q1. Ploss = (Irms 2 x Rds(on ) ) Qgd +I x x Vin x ig Qgs 2 f + I x x Vin x f ig + (Qg x Vg x f ) + Qoss x Vin x f 2 This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRLR/U7821 D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 2.38 (.094) 2.19 (.086) 6.73 (.265) 6.35 (.250) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 10.42 (.410) 9.40 (.370) 1.02 (.040) 1.64 (.025) 1 2 LEAD ASSIGNMENTS 3 1 - GATE -B- 1.52 (.060) 1.15 (.045) 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) 2 - DRAIN 0.51 (.020) MIN. 3 - SOURCE 4 - DRAIN 0.58 (.023) 0.46 (.018) M A M B NOTES: 2.28 (.090) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4.57 (.180) 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). D-Pak (TO-252AA) Part Marking Information 1RWHV7KLVSDUWPDUNLQJLQIRUPDWLRQDSSOLHVWRGHYLFHVSURGXFHGEHIRUH (;$03/( 7+,6,6$1,5)5 :,7+$66(0%/< /27&2'(83 ,17(51$7,21$/ 5(&7,),(5 /2*2 ,5)8 8 3 '$7(&2'( <($5 :((. $66(0%/< /27&2'( 1RWHV7KLVSDUWPDUNLQJLQIRUPDWLRQDSSOLHVWRGHYLFHVSURGXFHGDIWHU (;$03/( 7+,6,6$1,5)5 3$57180%(5 :,7+$66(0%/< /27&2'( $66(0%/('21:: ,17(51$7,21$/ 5(&7,),(5 /2*2 ,17+($66(0%/</,1($ ,5)8 $ '$7(&2'( <($5 :((. /,1($ $66(0%/< /27&2'( www.irf.com 9 IRLR/U7821 I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) 2.38 (.094) 2.19 (.086) -A- 0.58 (.023) 0.46 (.018) 1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) LEAD ASSIGNMENTS 4 1 - GATE 2 - DRAIN 6.45 (.245) 5.68 (.224) 1 2 3 -B2.28 (.090) 1.91 (.075) 3X 3 - SOURCE 4 - DRAIN 6.22 (.245) 5.97 (.235) 1.52 (.060) 1.15 (.045) 1.14 (.045) 0.76 (.030) 2.28 (.090) 3X 9.65 (.380) 8.89 (.350) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 0.89 (.035) 0.64 (.025) 1.14 (.045) 0.89 (.035) 0.25 (.010) M A M B 0.58 (.023) 0.46 (.018) 2X I-Pak (TO-251AA) Part Marking Information 1RWHV7KLVSDUWPDUNLQJLQIRUPDWLRQDSSOLHVWRGHYLFHVSURGXFHGEHIRUH (;$03/( 7+,6,6$1,5)5 :,7+$66(0%/< /27&2'(83 ,17(51$7,21$/ 5(&7,),(5 '$7(&2'( ,5)8 /2*2 <($5 :((. 8 3 $66(0%/< /27&2'( 1RWHV7KLVSDUWPDUNLQJLQIRUPDWLRQDSSOLHVWRGHYLFHVSURGXFHGDIWHU (;$03/( 3$57180%(5 7+,6,6$1,5)5 :,7+$66(0%/< /27&2'( ,17(51$7,21$/ 5(&7,),(5 /2*2 $66(0%/('21:: ,5)8 $ '$7(&2'( <($5 :((. ,17+($66(0%/</,1($ $66(0%/< /,1($ /27&2'( 10 www.irf.com IRLR/U7821 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Notes: Repetitive rating; pulse width limited by Calculated continuous current based on maximum allowable max. junction temperature. Starting TJ = 25C, L = 3.2mH RG = 25, IAS = 12A. Pulse width 400s; duty cycle 2%. When mounted on 1" square PCB (FR-4 or G-10 Material). junction temperature. Package limitation current is 30A. For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.04/04 www.irf.com 11