www.irf.com 1
4/5/04
IRLR7821
IRLU7821
HEXFET® Power MOSFET
Notes through are on page 11
Applications
Benefits
lVery Low RDS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
lHigh Frequency Synchronous Buck
Converters for Computer Processor Power
lHigh Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
D-Pak
IRLR7821 I-Pak
IRLU7821
VDSS RDS(on) max Qg
30V
10m
:
10nC
PD - 94538B
Absolute Maximum Ratings
Parameter Units
V
DS Dr ain-t o- Source Voltag e V
V
GS Gat e- to-S ource Voltage
ID @ TC = 25 °C
Co nti n uous D r ai n C ur rent, V
GS
@ 10V
I
D
@ T
C
= 100°C
Co nti n uous D r ai n C ur rent, V
GS
@ 10V
A
IDM
Pulsed Dr ain Current
c
P
D
@T
C
= 25 °C
Maximum Power D issi pation
g
W
PD @TC = 100°C
Maximum Power D issi pation
g
Linear Derating Factor W/°C
TJ Operating Junc ti on and °C
T
STG Stor ag e Tem per atur e Ra ng e
Therm al Resistanc e
Parameter Typ. Max. Units
R
θJC Junction-to-Case ––– 2.0
R
θJA
Junc tio n- t o- Am bient ( PC B Mo un t )
g
––– 50 °C/W
R
θJA Junction-to-Ambient ––– 110
-55 to + 175
75
0.50
37.5
Max.
65
f
47
f
260
± 20
30
IRLR/U7821
2www.irf.com
S
D
G
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BV
DSS Dr ai n- to- Sour c e B reakd ow n Volta ge 30 ––– ––– V
∆Β
V
DSS
/
∆
T
J Br eakdown Voltag e Temp. Coefficient ––– 23 –– – mV/°C
R
DS(on) Static Dr ain- to- Sour c e O n-R es i s tanc e ––– 7. 5 10
m
Ω
––– 9.5 12.5
V
GS(th) G at e Thr es hold Vol t age 1. 0 ––– ––– V
∆
V
GS(th) G at e Thr es hold V o ltage C oe f ficien t ––– -5 .3 ––– mV/ ° C
I
DSS Dr ai n- to- Sour c e Leak age Cu r rent ––– ––– 1. 0 µA
––– ––– 150
I
GSS Gate-to- Sou r c e For war d Leak age ––– ––– 100 nA
Gate- to- Sour c e R ev e r s e Leaka ge ––– ––– -10 0
gfs For ward Tra nsconductance 46 ––– ––– S
Q
gTotal Gate Charge ––– 10 14
Q
gs1 Pre-Vth Gate-to-Source Charge ––– 2.0 –––
Q
gs2 Post - Vth Gate- to-Source Cha rge ––– 1.2 ––– nC
Q
gd Gate-to-D r ain Char ge ––– 2.5 –––
Q
godr G ate Cha rge Ov e r dr i ve ––– 4. 3 ––– Se e Fi g. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
––– 3.7 –––
Q
oss Output Charge ––– 8.5 ––– nC
t
d(on) Turn-On Delay Time ––– 11 –––
t
rRise Time ––– 4 .2 –––
t
d(off) Turn-Off Delay Ti me ––– 10 ––– n s
t
fFall Tim e –– – 3.2 –––
C
iss Input Capacitance ––– 1030 –––
C
oss Out pu t Capac ita nc e ––– 360 ––– pF
C
rss Reve r s e Tr a ns fer Capac it a nc e ––– 120 –––
Aval anc he Cha racteri stics
Parameter Units
E
AS
Si ngle P ul se Avalanch e E n er g y
dh
mJ
I
AR
Avalanche Current
c
A
E
AR
Repeti ti ve Avalanche Ener gy
c
mJ
Diode Charac teri stics
Pa r a me te r Min. T y p . Max . Units
I
SContin uous Source Cu rren t ––– –––
65
f
(Body Diode) A
I
SM Pulsed Source Current ––– ––– 260
(Body Diode)
ch
V
SD Diode Forward Voltage –– – ––– 1.0 V
t
rr Reverse Recovery Time ––– 26 38 ns
Q
rr Reverse Recovery Charge ––– 15 23 nC
t
on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
MOSFET symbol
VGS = 4.5V, ID = 12 A
f
–––
VGS = 4.5V
Typ.
–––
–––
ID = 12A
VGS = 0V
VDS = 15V
TJ = 25°C, IF = 12 A , V DD = 15V
di /dt = 100A/µ s
f
TJ = 25°C, IS = 12A, VGS = 0V
f
showing the
integra l revers e
p-n junct ion diode.
VDS = VGS, ID = 250µ A
VDS = 24V , V GS = 0V
VDS = 24V , V GS = 0V , TJ = 125°C
Cla m ped I n duc t iv e Load
VDS = 15V , I D = 12A
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 15A
f
Conditions
7.5
Max.
230
12
ƒ = 1. 0M H z
VDS = 16V , V GS = 0V
VDD = 15V, VGS = 4. 5V
f
ID = 12A
VDS = 16V
VGS = 20V
VGS = -20V
IRLR/U7821
www.irf.com 3
Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
1000
2.0 4.0 6.0 8.0 10.0
V = 15V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 175 C
J°
T = 25 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
R , Drain-to-Source On Resistance
(Normalized)
DS(on)
°
V =
I =
GS
D
10V
65A
0.1 110 100
VDS, Drai n-to-Source V oltage (V)
0.1
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
2.5V
20µs PU LSE WIDT H
Tj = 25°C
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
0.1 110 100
VDS, Dr ain-to-Source V oltage ( V)
1
10
100
1000
ID, Drain-to-Source Current (A)
2.5V
20µs PU LSE WIDT H
Tj = 175°C
VGS
TOP 10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
TJ, Junction Temperature (°C)
IRLR/U7821
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drai n-to-Source V oltage (V )
10
100
1000
10000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss
= C
gs + Cgd, C
ds SHORTED
Crss
= C
gd
Coss
= Cds + Cgd
Coss
Crss
Ciss
0.1
1
10
100
1000
0.0 0.5 1.0 1.5 2.0
V ,Source-to-Drain Voltage (V)
I , R ev ers e Drain Current (A)
SD
SD
V = 0 V
GS
T = 175 C
J°
T = 25 C
J°
1 10 100
VDS, Dr ain-to-Source V oltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
024681012
QG Total Gat e Charge (nC)
0
1
2
3
4
5
6
VGS, Gate-to-Source Voltage (V)
VDS= 24V
VDS= 16V
ID= 12A
IRLR/U7821
www.irf.com 5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
25 50 75 100 125 150 175
0
10
20
30
40
50
60
70
T , Case Temperature ( C)
I , Drain C urr ent (A)
°
C
D
LIMITED BY PACKAGE
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Therm al Res ponse (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SING LE PULSE
(THERMAL RESPONSE)
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
Fig 10. Threshold Voltage vs. Temperature
IRLR/U7821
6www.irf.com
25 50 75 100 125 150 175
0
200
400
600
800
1000
Starting Tj, Junction Temperature ( C)
E , Single Pul s e Avalanc he Energy (mJ)
AS
°
ID
TOP
BOTTOM
4.9A
8.5A
12A
Fig 13. Maximum Avalanche Energy
vs. Drain Current
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 15. Gate Charge Test Circuit
Fig 14. Unclamped Inductive Test Circuit
and Waveform
tp
V
(BR)DSS
I
AS
Fig 16. Switching Time Test Circuit Fig 17. Switching Time Waveforms
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
VGS
VDS
9
0%
10%
td(on) td(off)
trtf
VGS
Pul se Width < 1µs
Duty F ac tor < 0.1%
VDD
VDS
LD
D.U.T
+
-
2345678910
VGS, Gate -to -Source Voltage (V)
0
5
10
15
20
25
30
RDS(on), Drain-to -Source On Resistance (mΩ)
ID = 15A
TJ = 125°C
TJ = 25°C
Fig 12. On-Resistance vs. Gate Voltage
IRLR/U7821
www.irf.com 7
Fig 18. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 19. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
IRLR/U7821
8www.irf.com
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms 2×Rds(on)
()
+I×Qgd
ig
×Vin ×f
+I×Qgs2
ig
×Vin ×
f
+Qg×Vg×f
()
+Qoss
2×Vin ×f
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
+Qrr ×Vin ×
f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and of f there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
IRLR/U7821
www.irf.com 9
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
6.73 (.265)
6.35 (.250)
- A -
4
1 2 3
6.22 (.245)
5.97 (.235)
- B -
3X 0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
4. 57 (.180 )
2.28 (.090)
2X 1.14 (.045)
0.76 (.030)
1. 52 (.060 )
1. 15 (.045 )
1
.02 (.040)
1
.64 (.025)
5.46 (.215)
5.21 (.205) 1.27 (.050)
0.88 (.035)
2.38 (.094)
2.19 (.086) 1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018)
6.45 (.245)
5.68 (.224)
0.51 (.020)
MIN.
0. 58 (.023 )
0. 46 (.018 )
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
10.42 (.410)
9.40 (.370)
NOTES:
1 DIMENSI ONING & TOLERANCING PER ANSI Y14.5M, 1982
.
2 CONTROL LIN G DIME NSIO N : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIM ENSI O NS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
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IRLR/U7821
10 www.irf.com
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
6.73 (.265)
6.35 (.250)
- A -
6.22 (.245)
5.97 (.235)
- B -
3X 0.89 (.035)
0.64 (.025)
0.25 (.010) M A M B
2.28 (.090)
1.14 (.045)
0.76 (.030)
5.46 ( .215 )
5.21 ( .205 ) 1.27 (.050)
0.88 (.035)
2.38 (.094)
2.19 (.086)
1.14 (.045)
0.89 (.035)
0.58 (.023)
0.46 (.018) LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SO URCE
4 - DRAIN
NOTES:
1 DI ME NS I O NING & TO LE RA NCING PER ANSI Y14.5M, 1982
.
2 CON TRO LL ING DI MENSIO N : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
9.65 (.380)
8.89 (.350)
2X
3X
2
.28 (.090)
1
.91 (.075)
1.52 (.060)
1.15 (.045)
4
1 2 3
6.45 ( .24 5)
5.68 ( .22 4)
0.58 (.023)
0.46 (.018)
:((.
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7+,6,6$1,5)5
:,7+$66(0%/<
$66(0%/<
,17(51$7,21$/
5(&7,),(5
/2*2
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,5)8
8 3
,17(51$7,21$/
/2*2
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$66(0%/<
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IRLR/U7821
www.irf.com 11
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 3.2mH
RG = 25Ω, IAS = 12A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Notes:
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/04
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRE CTION
16.3 ( .641
)
15.7 ( .619
)
TRR TRL
N
OTES :
1
. CONTROLLIN G DIMENSION : MILLIMETE R.
2
. ALL D IMENS IONS ARE SHOWN IN MILL IMET ERS ( IN C H ES ) .
3
. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
