1. General description
The 74HC123; 74HCT123 ar e hig h-sp eed Si-g ate CMOS d evices and ar e pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output
pulse width control by three methods:
1. The basic pulse is programmed by selection of an external resistor (R EXT) and
capacitor (CEXT).
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW- going edge input (nA) or the active HIGH-going edge in put (nB). By
repeating this process, the ou tput pulse period ( nQ = HIGH, nQ = LOW) can be made
as long as desired. Alternatively an output delay can be terminated at any time by a
LOW-going edge on input nRD, which also inhibits the triggering.
3. An internal connection from nRD to the input gates makes it possible to trigger the
circuit by a HIGH-going signal at input nRD as shown in Table 3.
Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower
input rise and fall times.
The 74HC123; 74HCT123 are identical to the 74HC423; 74HCT423 but can be triggered
via the reset input.
2. Features and benefits
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output puls e
Schmitt-trigger action on all inputs except for the reset input
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 Cto+85C and fr om 40 Cto+125C
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
Rev. 9 — 19 January 2015 Product data sheet
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 2 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
3. Ordering information
4. Functional diagram
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC123N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT123N
74HC123D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HCT123D
74HC123DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT123DB
74HC123PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74HCT123PW
74HC123BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
Fig 1. Functional di agram
4
4
5'
5'
6
5(;7&(;7

&(;7

4
4
DDD
5'
$
$

%

%
7
4
5'
6
5(;7&(;7
&(;7
4
44

7
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 3 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
Fig 2. Logic symbol Fig 3. IEC logic symbol
4
4
5'
5'
6
5(;7&(;7

5(;7&(;7
&(;7
&(;7 
4
4
4
4 
PQD
5'
$
$
 %

%
7
PQD
&;

5&;
5


&;


5&;
5

Fig 4. Logic diag ram
PQD
Q5(;7&(;7
9&&
9&& 9&&
5
Q5'
Q$
Q% 5
&/
&/ &/
&/ &/
Q4
Q4
5
5
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 4 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land sho uld remain
floating or be connected to VCC.
Fig 5. Pin configuratio n for DIP16, SO16, SSOP16
and TSSOP16 Fig 6. Pin configuration for DHVQFN16
+&
+&7
$ 9
&&
% 5(;7&(;7
5' &(;7
4 4
4 4
&(;7 5'
5(;7&(;7 %
*1' $
DDD







DDI
+&
5(;7&(;7 %
&(;7 5'
4 4
4 4
5' &(;7
% 5(;7&(;7
*1'
$
$
9&&
7UDQVSDUHQWWRSYLHZ







WHUPLQDO
LQGH[DUHD
9&&
Table 2. Pin description
Symbol Pin Description
1A 1 negative-edge triggered input 1
1B 2 positive-edge triggered input 1
1RD 3 direct reset LOW and positive-edge triggered input 1
1Q 4 active LOW output 1
2Q 5 active HIGH output 2
2CEXT 6 external capacitor connection 2
2REXT/CEXT 7 external resistor and capacitor connection 2
GND 8 ground (0 V)
2A 9 negative-edge triggered input 2
2B 10 positive-edge triggered input 2
2RD 11 direct reset LOW and positive-edge triggered input 2
2Q 12 active LO W output 2
1Q 13 active HIGH output 1
1CEXT 14 external capacitor connection 1
1REXT/CEXT 15 external resistor and capacitor connection 1
VCC 16 supply vol tage
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 5 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH transition; = HIGH-to-LOW transition;
= one HIGH level output pulse; = one LOW level output pulse.
[2] If the monostable was triggered before this condition was established, the pulse will continue as programmed.
7. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
Table 3. Function table[1]
Input Output
nRD nA nB nQ nQ
LXXLH
XHXL
[2] H[2]
XXLL
[2] H[2]
HL
HH
LH
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO > VCC + 0.5 V - 20 mA
IOoutput current except for pins nREXT/CEXT;
VO=0.5 V to (VCC +0.5V) -25 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation
DIP16 package [1] - 750 mW
SO16 package [2] - 500 mW
SSOP16 package [3] - 500 mW
TSSOP16 package [3] - 500 mW
DHVQFN16 package [4] - 500 mW
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 6 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions 74HC123 74HCT123 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
t/V input transition rise and
fall rate nRD input
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC123
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO=4mA; V
CC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO=5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO=4mA; V
CC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =6.0V - - 0.1 - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 7 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
CIinput
capacitance -3.5- - - - -pF
74HCT123
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A 4.4 4.5 - 4.4 - 4.4 - V
IO=4 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =5.5V - - 0.1 - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 8.0 - 80 - 160 A
ICC additional
supply current per input pin; IO=0A;
VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pins nA, nB - 35 125 - 160 - 170 A
pin nRD - 50 180 - 225 - 245 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 8 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC123
tpd propagation
delay nRD, nA, nB to nQ or nQ;
CEXT = 0 pF;
REXT =5k;
see Figure 9
[1]
VCC = 2.0 V - 83 255 - 320 - 385 ns
VCC = 4.5 V - 30 51 - 64 - 77 ns
VCC = 5 V; CL = 15 pF - 26 - - - - - ns
VCC = 6.0 V - 24 4 3 - 54 - 65 ns
nRD (reset) to nQ or nQ;
CEXT =0pF;
REXT =5k;
see Figure 9
VCC = 2.0 V - 66 215 - 270 - 325 ns
VCC = 4.5 V - 24 43 - 54 - 65 ns
VCC = 5 V; CL = 15 pF - 20 - - - - - ns
VCC = 6.0 V - 19 3 7 - 46 - 55 ns
tttransition time see Figure 9 [1]
VCC = 2.0 V - 19 7 5 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tWpulse width nA LOW; see Figure 10
VCC = 2.0 V 100 8 - 125 - 150 - ns
VCC = 4.5 V 20 3 - 25 - 30 - ns
VCC = 6.0 V 17 2 - 21 - 26 - ns
nB HIGH; see Figure 10
VCC = 2.0 V 100 17 - 125 - 150 - ns
VCC = 4.5 V 20 6 - 25 - 30 - ns
VCC = 6.0 V 17 5 - 21 - 26 - ns
nRD LOW; see Figure 11
VCC = 2.0 V 100 14 - 125 - 150 - ns
VCC = 4.5 V 20 5 - 25 - 30 - ns
VCC = 6.0 V 17 4 - 21 - 26 - ns
nQ HIGH and nQ LOW;
VCC =5.0V;
see Figure 10 and 11
[2]
CEXT = 100 nF;
REXT = 10 k-450- - - - - s
CEXT = 0 pF;
REXT =5k-75- - - - -ns
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 9 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
trtrig retrigger time nA,nB; C
EXT = 0 pF;
REXT = 5 k; VCC = 5.0 V ;
see Figure 10
[3][4] -110- - - - - ns
REXT external timing
resistor see Figure 7
VCC = 2.0 V 10 - 1000 - - - - k
VCC = 5.0 V 2 - 10 00 - - - - k
CEXT external timing
capacitor VCC = 5.0 V; see Figure 7 [4] --- - - - -pF
CPD power
dissipation
capacitance
per monostable;
VI= GND to VCC
[5] -54- - - - -pF
74HCT123
tPHL HIGH to LOW
propagation
delay
nRD, nA, nB to nQ or nQ;
CEXT = 0 pF; REXT =
5k; see Figure 9
VCC = 4.5 V - 30 5 1 - 64 - 77 ns
VCC = 5 V; CL=15pF - 26 - - - - - ns
nRD (reset) to nQ or nQ;
CEXT =0pF;
REXT =5k;
see Figure 9
VCC = 4.5 V - 27 4 6 - 58 - 69 ns
VCC = 5 V; CL=15pF - 23 - - - - - ns
tPLH LOW to HIGH
propagation
delay
nRD, nA, nB to nQ or nQ;
CEXT = 0 pF;
REXT =5k;
see Figure 9
VCC = 4.5 V - 28 5 1 - 64 - 77 ns
VCC = 5 V; CL=15pF - 26 - - - - - ns
nRD (reset) to nQ or nQ;
CEXT =0pF; R
EXT =
5k; see Figure 9
VCC = 4.5 V - 23 4 6 - 58 - 69 ns
VCC = 5 V; CL=15pF - 23 - - - - - ns
tttransition time VCC = 4.5 V; see Figure 9 [1] - 7 15 - 19 - 22 ns
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 10 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
[1] tpd is the same as tPHL and tPLH; tt is the same as tTHL and tTLH
[2] For other REXT and CEXT combinations see Figure 7. If CEXT > 10 nF, the next formula is valid.
tW=KREXT CEXT, where:
tW= typical output pulse width in ns;
REXT = external resistor in k;
CEXT = external capacitor in pF;
K = constant = 0.45 for VCC = 5.0 V and 0.55 for VCC =2.0V.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF.
[3] The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width will only be
extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT >10 pF,
the next formula (at VCC = 5.0 V) for the setup time of a retrigger pulse is valid:
trtrig = 30 + 0.19 REXT CEXT0.9 +13REXT1.05, where:
trtrig = retrigger time in ns;
CEXT = external capacitor in pF; REXT = external resistor in k.
The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF.
[4] When the device is powered-up, initiate the device via a reset pulse, when CEXT <50pF.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fi+(CLVCC2fo) + 0.75 CEXT VCC2fo+D16 VCC where:
fi= input frequency in MHz;
fo= output frequency in MHz;
D = duty factor in %;
CL= output load capacitance in pF;
VCC = supply voltage in V;
CEXT = timing capacitance in pF;
(CLVCC2 fo) sum of outputs.
tWpulse width VCC = 4.5 V
nA LOW; see Figure 10 20 3 - 25 - 30 - ns
nB HIGH; see Figure 10 20 5 - 25 - 30 - ns
nRD LOW; see Figure 11 20 7 - 25 - 30 - ns
nQ HIGH and nQ LOW;
VCC =5.0V;
see Figure 10 and 11
[2]
CEXT = 100 nF;
REXT = 10 k-450- - - - - s
CEXT = 0 pF;
REXT =5k-75- - - - -ns
trtrig retrigger time nA,nB; C
EXT = 0 pF;
REXT = 5 k; VCC = 5.0 V ;
see Figure 10
[3][4] -110- - - - - ns
REXT external timing
resistor VCC = 5.0 V; see Figure 7 2-1000- - - -k
CEXT external timing
capacitor VCC = 5.0 V; see Figure 7 [4] --- - - - -pF
CPD power
dissipation
capacitance
per monostable;
VI= GND to VCC 1.5 V [5] -56- - - - -pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL= 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 11 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
VCC = 5.0 V; Tamb = 25 C.
(1) REXT = 100 k
(2) REXT = 50 k
(3) REXT = 10 k
(4) REXT = 2 k
CEXT = 10 nF; REXT = 10 k to 100 k.
Tamb = 25 C.
Fig 7. Typical output puls e width as a fun ction of the
external capacitor value Fig 8. 74HC12 3 typical ‘K’ factor as function of VCC
DDD





W:
QV

&(;7S)


 




9&&9

DDD




.IDFWRU
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 12 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ) and output transition times
DDD
Q%
LQSXW
W:
W:
W3/+
90
92+
90
90
W:
W3/+
W7+/
W:
W3+/
W3+/
90
W:
W3/+
Q$
LQSXW
Q5'LQSXW
Q4
RXWSXW
Q4
RXWSXW
90
W7/+
9<
9;
9<
9;
W3+/
W3+/ W3/+
UHVHW
UHVHW
92/
92+
92/
9,
9,
9
,
*1'
*1'
*1'
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 13 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
nRD = HIGH
Fig 10. Output pulse control using retrigger pulse
nA = LOW
Fig 11. Output pulse cont rol using reset input nRD
PQD
W:W:
W:
Q%LQSXW
Q5'LQSXW
Q4RXWSXW
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 14 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
Test data is given in Table 8.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 12. Test circuit for measuring switching times
9
0
9
0
W
:
W
:


9
9
,
9
,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9
0
9
0


W
I
W
U
W
U
W
I
DDG
'87
9
&&
9
&&
9,92
57
5/6
&/
RSHQ
*
Table 8. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH
74HC123 VCC 6 ns 15 pF, 50 pF 1 kopen
74HCT123 3 V 6 ns 15 pF, 50 pF 1 kopen
74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 15 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
12. Application information
12.1 T iming component connections
The basic output pulse wid th is essentially determined by the values of the external timing
components REXT and CEXT.
12.2 Power-up considerations
When the monostable is powered-up it may produce an output pulse, with a pulse width
defined by the values of REXT and CEXT. This output pulse can be eliminated using the
circuit shown in Figure 14.
(1) For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT)
externally to pin 8 (GND).
Fig 13. Timing component connections
DDD
&(;7 5(;7
Q$
Q%
9
&&
Q&(;7
Q5'
Q5(;7&(;7
Q4
Q4
*1'
 






Fig 14. Power-up output pulse eliminat ion circuit
DDD
9&&
5(6(7
Q5'
&(;7 5(;7
Q$
Q%
9&&
Q&(;7*1' Q5(;7&(;7
Q4
Q4
 





74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 16 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
12.3 Power-down considerations
A large capacitor CEXT may cause problems when powering-d own the mono stable due to
the energy stored in this capacitor. When a system containing this device is
powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain
damage, due to the capacitor discharging through the input protection diodes. To avoid
this possibility, use a damping diode (DEXT) pr ef er ab ly a ge rm a nium or Scho tt ky typ e
diode able to withstand large current surges and connect as shown in Figure 15.
Fig 15. Power-down protection circuit
DDD
'(;7
Q5'
&(;7 5(;7
Q$
Q%
9&&
Q&(;7 Q5(;7&(;7
Q4
Q4
 





*1'

74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 9 — 19 January 2015 17 of 25
NXP Semiconductors 74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
13. Package outline
Fig 16. Package outline SOT38-4 (DIP16)
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
627 


0
+
F
H

0
(
$
/
VHDWLQJSODQH
$

Z 0
E

E

H
'
$

=




(
SLQLQGH[
E
  PP
VFDOH
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG
81,7 $
PD[   E
   
E
 F ' ( H 0 =
+
/
PP
',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV
$
PLQ
$
PD[ E PD[
Z
0
(
H












   


   
LQFKHV 














   


   
',3SODVWLFGXDOLQOLQHSDFNDJHOHDGVPLO 627