DATA SH EET
Product specification
Supersedes data of 2003 Aug 19 2004 July 12
INTEGRATED CIRCUITS
TDA8024
IC card interface
2004 July 12 2
Philips Semiconductors Product specification
IC card interface TDA8024
CONTENTS
1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 QUICK REFERENCE DATA
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION
8.1 Power supply
8.2 Voltage supervisor
8.2.1 Without external divider on pin PORADJ
(or with TDA8024AT)
8.2.2 With an external divider on pin PORADJ (not
for the TDA8024AT)
8.2.3 Application examples
8.3 Clock circuitry
8.4 I/O transceivers
8.5 Inactive mode
8.6 Activation sequence
8.7 Active mode
8.8 Deactivation sequence
8.9 VCC generator
8.10 Fault detection
9 LIMITING VALUES
10 HANDLING
11 THERMAL CHARACTERISTICS
12 CHARACTERISTICS
13 APPLICATION INFORMATION
14 PACKAGE OUTLINES
15 SOLDERING
15.1 Introduction to soldering surface mount
packages
15.2 Reflow soldering
15.3 Wave soldering
15.4 Manual soldering
15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
16 DATA SHEET STATUS
17 DEFINITIONS
18 DISCLAIMERS
2004 July 12 3
Philips Semiconductors Product specification
IC card interface TDA8024
1 FEATURES
•IC card interface
•3 or 5 V supply for the IC (VDD and GND)
•Three specifically protected half-duplex bidirectional
buffered I/O lines to card contacts C4, C7 and C8
•DC/DC converter for VCC generation separately
powered from a 5 V ±20% supply (VDDP and PGND)
•3or5V±5% regulated card supply voltage (VCC) with
appropriate decoupling has the following capabilities:
–I
CC < 80 mA at VDDP = 4 to 6.5 V
– Handles current spikes of 40 nAs up to 20 MHz
– Controls rise and fall times
– Filtered overload detection at approximately 120 mA
•Thermal and short-circuit protection on all card contacts
•Automatic activation and deactivation sequences;
initiated by software or by hardware in the event of a
short-circuit, card take-off, overheating, VDD or VDDP
drop-out
•Enhanced ESD protection on card side (>6 kV)
•26 MHz integrated crystal oscillator
•Clock generation for cards up to 20 MHz (divided by
1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals)
with synchronous frequency changes
•Non-inverted control of RST via pin RSTIN
•ISO 7816, GSM11.11 and EMV (payment systems)
compatibility
•Supply supervisor for spike-killing during power-on and
power-off and Power-on reset (threshold fixed internally
or externally by a resistor bridge); not for TDA8024AT
•Built-in debounce on card presence contacts
•One multiplexed status signal OFF.
2 APPLICATIONS
•IC card readers for banking
•Electronic payment
•Identification
•Pay TV.
3 GENERAL DESCRIPTION
The TDA8024 is a complete and cost-efficient analog
interface for asynchronous 3 or 5 V smart cards. It can be
placed between the card and the microcontroller to
perform all supply, protection and control functions. Very
fewexternalcomponentsarerequired.TheTDA8024ATis
a direct replacement for the TDA8004AT.
More information can be obtained from the Philips Internet
site (http://www.semiconductors.philips.com) and from
“Application note AN10141”
.
4 ORDERING INFORMATION
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA8024T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1
TDA8024AT SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1
TDA8024TT TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
2004 July 12 4
Philips Semiconductors Product specification
IC card interface TDA8024
5 QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Power supplies
VDD supply voltage 2.7 −6.5 V
VDDP DC/DC converter supply
voltage VCC =5V;ICC< 80 mA 4.0 5.0 6.5 V
VCC =5V;ICC< 20 mA 3.0 −6.5 V
IDD supply current VDD = 3.3 V; fXTAL = 10 MHz
card inactive −−1.2 mA
card active; fCLK =f
XTAL;
CL=30pF −−1.5 mA
IDDP DC/DC converter supply
current VDDP =5V; f
XTAL = 10 MHz
inactive mode −−0.1 mA
active mode; fCLK =f
XTAL;
CL= 30 pF; ICC=0 −−10 mA
Card supply
VCC card supply voltage (including
ripple voltage) 5 V card
card active;
ICC<80mADC 4.75 5.0 5.25 V
card active; current pulses
Ip= 40 nAs 4.65 5.0 5.25 V
3 V card
card active;
ICC<65mADC 2.85 3.0 3.15 V
card active; current pulses
Ip= 40 nAs 2.76 3.0 3.20 V
VCC(ripple)(p-p) ripple voltage on VCC
(peak-to-peak value) fripple = 20 kHz to 200 MHz −−350 mV
ICCcard supply current VCC =0to5V −−80 mA
VCC =0to3V −−65 mA
General
tde deactivation time 50 80 100 µs
Ptot total power dissipation continuous operation;
Tamb =−25 to +85 °C−−0.56 W
Tamb ambient temperature −25 −+85 °C
2004 July 12 5
Philips Semiconductors Product specification
IC card interface TDA8024
6 BLOCK DIAGRAM
mdb051
100 nF 100 nF 100 nF
100 nF
100 nF 100 nF
I/O
TRANSCEIVER
I/O
TRANSCEIVER
I/O
TRANSCEIVER
THERMAL
PROTECTION
VCC
GENERATOR
RST
BUFFER
CLOCK
BUFFER
SEQUENCER
CLOCK
CIRCUITRY
OSCILLATOR
HORSEQ
INTERNAL OSCILLATOR
2.5 MHz
DC/DC CONVERTER
INTERNAL
REFERENCE
VOLTAGE SENSE
SUPPLY
EN2
PVCC
EN5
EN4
EN3
CLK
EN1 CLKUP
ALARM
Vref
21
VDD 6
VDDP 75
S1 S2
8
4PGND
VUP
17 VCC
16
14
RST
CGND
PRES
10
9PRES
15 CLK
13
12
11
AUX1
AUX2
I/O
22
GND
26
28
27
I/OUC
AUX2UC
AUX1UC
25
24
2
1
3
19
20
23
18
(1)
XTAL2
XTAL1
CLKDIV2
CLKDIV1
5V/3V
CMDVCC
RSTIN
OFF
TDA8024
POWER_ON
VDD
R1
R2
PORADJ
Fig.1 Block diagram.
(1) Optional external resistor bridge. If this bridge is not required pin 18 should be connected to ground; see Section 8.2.2. Pin 18 is not connected
in the TDA8024AT.
2004 July 12 6
Philips Semiconductors Product specification
IC card interface TDA8024
7 PINNING
Note
1. The noise margin on VCC will be higher with the 220 nF capacitor.
SYMBOL PIN TYPE DESCRIPTION
CLKDIV1 1 I CLK frequency selection input 1
CLKDIV2 2 I CLK frequency selection input 2
5V/3V 3 I card supply voltage selection input; VCC = 5 V (HIGH) or VCC = 3 V (LOW)
PGND 4 S DC/DC converter power supply ground
S2 5 I/O DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
VDDP 6 S DC/DC converter power supply voltage
S1 7 I/O DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 mΩ
VUP 8 I/O DC/DC converter output decoupling capacitor connection; C = 100 nF with
ESR < 100 mW must be connected between VUP and PGND
PRES 9 I card presence contact input (active LOW); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
PRES 10 I card presence contact input (active HIGH); if PRES or PRES is active, the card is
considered ‘present’ and a built-in debounce feature of 8 ms (typ.) is activated
I/O 11 I/O data line to/from card reader contact C7; integrated 11 kΩ pull-up resistor to VCC
AUX2 12 I/O data line to/from card reader contact C8; integrated 11 kΩ pull-up resistor to VCC
AUX1 13 I/O data line to/from card reader contact C4; integrated 11 kΩ pull-up resistor to VCC
CGND 14 S card signal ground
CLK 15 I/O card clock to/from card reader contact C3
RST 16 O card reset output from card reader contact C2
VCC 17 S card supply voltage to card reader contact C1; decoupled to CGND via 2 ×100 nF
or 100 + 220 nF capacitors with ESR < 100 mΩ; note 1
PORADJ 18 I Power-on reset threshold adjustment input for changing the reset threshold with
an external resistor bridge; doubles the width of the POR pulse when used; this
pin is not connected for the TDA8024AT
CMDVCC 19 I input from the host to start activation sequence (active LOW)
RSTIN 20 I card reset input from the host
VDD 21 S supply voltage
GND 22 S ground
OFF 23 O NMOS interrupt output to the host (active LOW); 20 kΩintegrated pull-up resistor
to VDD
XTAL1 24 I crystal connection or input for external clock
XTAL2 25 O crystal connection (leave open-circuit if external clock source is used)
I/OUC 26 I/O host data I/O line; integrated 11 kΩ pull-up resistor to VDD
AUX1UC 27 I/O auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD
AUX2UC 28 I/O auxiliary data line to/from the host; integrated 11 kΩ pull-up resistor to VDD
2004 July 12 7
Philips Semiconductors Product specification
IC card interface TDA8024
TDA8024T
CLKDIV1 AUX2UC
CLKDIV2 AUX1UC
5V/3V I/OUC
PGND XTAL2
S2 XTAL1
VDDP OFF
S1 GND
VUP VDD
PRES RSTIN
PRES CMDVCC
I/O PORADJ
AUX2 VCC
AUX1 RST
CGND CLK
001aab430
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Fig.2 Pin configuration TDA8024T.
TDA8024TT
CLKDIV1 AUX2UC
CLKDIV2 AUX1UC
5V/3V I/OUC
PGND XTAL2
S2 XTAL1
VDDP OFF
S1 GND
VUP VDD
PRES RSTIN
PRES CMDVCC
I/O PORADJ
AUX2 VCC
AUX1 RST
CGND CLK
001aab431
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Fig.3 Pin configuration TDA8024TT.
TDA8024AT
CLKDIV1 AUX2UC
CLKDIV2 AUX1UC
5V/3V I/OUC
PGND XTAL2
S2 XTAL1
VDDP OFF
S1 GND
VUP VDD
PRES RSTIN
PRES CMDVCC
I/O n.c.
AUX2 VCC
AUX1 RST
CGND CLK
001aab382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Fig.4 Pin configuration TDA8024AT.
2004 July 12 8
Philips Semiconductors Product specification
IC card interface TDA8024
8 FUNCTIONAL DESCRIPTION
Throughout this document it is assumed that the reader is
familiar with ISO7816 terminology.
8.1 Power supply
The supply pins for the IC are VDD and GND. VDD should
be in the range of 2.7 to 6.5 V. All signals interfacing with
the system controller are referred to VDD, therefore VDD
should also supply the system controller. All card reader
contacts remain inactive during power-on or power-off.
The internal circuits are maintained in the reset state until
VDD reaches Vth2 +V
hys2 and for the duration of the
internal Power-on reset pulse, tW (see Fig.5). When VDD
falls below Vth2, an automatic deactivation of the contacts
is performed.
A DC/DC converter is incorporated to generate the
5 or 3 V card supply voltage (VCC). The DC/DC converter
should be supplied separately by VDDP and PGND. Due to
the possibility of large transient currents, the two 100 nF
capacitors of the DC/DC converter should be located as
near as possible to the IC and have an ESR less than
100 mΩ.
The DC/DC converter functions as a voltage doubler or a
voltage follower according to the respective values of VCC
and VDDP (both have thresholds with a hysteresis of
100 mV).
The DC/DC converter function changes as follows:
•VCC = 5 V and VDDP > 5.8 V; voltage follower
•VCC = 5 V and VDDP < 5.7 V; voltage doubler
•VCC = 3 V and VDDP > 4.1 V; voltage follower
•VCC = 3 V and VDDP < 4.0 V; voltage doubler.
Supply voltages VDD and VDDP may be applied to the IC in
any sequence.
After powering the device, OFF remains LOW until
CMDVCC is set HIGH.
During power off, OFF falls LOW when VDD is below the
falling threshold voltage.
8.2 Voltage supervisor
8.2.1 WITHOUT EXTERNAL DIVIDER ON PIN PORADJ
(OR WITH TDA8024AT)
The voltage supervisor surveys the VDD supply. A defined
reset pulse of approximately 8 ms (tW) is used internally to
keep the IC inactive during power-on or power-off of the
VDD supply (see Fig.5).
As long as VDD is less than Vth2 +V
hys2, the IC remains
inactive whatever the levels on the command lines. This
statealso lasts for the durationof tWafter VDD has reached
a level higher than Vth2 +V
hys2.
When VDD falls below Vth2, a deactivation sequence of the
contacts is performed.
handbook, full pagewidth
Vth2 + Vhys2
VDD Vth2
ALARM
(internal signal)
supply dropout power-off
power-on
MDB053
twtw
Fig.5 Voltage supervisor.
2004 July 12 9
Philips Semiconductors Product specification
IC card interface TDA8024
8.2.2 WITH AN EXTERNAL DIVIDER ON PIN PORADJ (NOT
FOR THE TDA8024AT)
If an external resistor bridge is connected to pin PORADJ
(R1 and R2 in Fig.1), then the following occurs:
•The internal threshold voltage Vth2 is overridden by the
external voltage and by the hysteresis, therefore:
where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ.
•The reset pulse width tW is doubled to approximately
16 ms.
InputPORADJisbiasedinternally with a pull-down current
source of 4 µA which is removed when the voltage on
pin PORADJ exceeds 1 V. This ensures that after
detection of the external bridge by the IC during power-on,
the input current on pin PORADJ does not cause
inaccuracy of the bridge voltage.
The minimum threshold voltage should be higher than 2 V.
The maximum threshold voltage may be up to VDD.
8.2.3 APPLICATION EXAMPLES
The voltage supervisor is used as Power-on reset and as
supply dropout detection during a card session.
Supply dropout detection is to ensure that a proper
deactivationsequence is followed before the voltage istoo
low.
For the internal voltage supervisor to function, the system
microcontroller should operate down to 2.35 V to ensure a
proper deactivation sequence. If this is not possible,
external resistor values can be chosen to overcome the
problem.
8.2.3.1 Microcontroller requiring a 3.3 V
±
20% supply
For a microcontroller supplied by 3.3 V with a ±5%
regulator and with resistors R1, R2 having a ±1%
tolerance, the minimum supply voltage is 3.135 V.
VPORADJ =k×VDD, where with S1 and S2
the actual values of nominal resistors R1 and R2.
This can be shown as
0.99 ×R1 < S1 < 1.01 ×R1 and
0.99 ×R2 < S2 < 1.01 ×R2
Transposed, this becomes
If V1 = Vth(ext)(rise)(max) and V2 = Vth(ext)(fall)(min)
activation will always be possible if VPORADJ >V1
and deactivation will always be done for VPORADJ < V2.
Activation is always possible for
and deactivation is always possible for .
That is V1 = 1.31 V and V2 = 1.19 V
and
Suppose R1 + R2 = 100 kΩ, then
= 42.3 kΩand R1 = 57.7 kΩ.
Deactivation will be effective at
V2 ×(1 + 1.02 ×1.365) = 2.847 V in any case.
If the microcontroller continues to function down to 2.80 V,
the slew rate on VDD should be less than 2 V/ms to ensure
that clock CLK is correctly delivered to the card until
time t12 (see Fig.9).
8.2.3.2 Microcontroller requiring a 3.3 V
±
10% supply
For a microcontroller supplied by a 3.3 V with a ±1%
regulator and with resistors R1, R2 having a ±0.1%
tolerance, the minimum supply voltage is 3.267 V.
The same calculations as in Section 8.2.3.1 conclude:
Therefore = 40.14 kΩ and R1 = 59.86 kΩ.
Deactivation will be effective at
V2 ×(1 + 1.002 ×1.491) = 2.967 V in any case.
If the microcontroller continues to function down to 2.97 V,
the slew rate on VDD should be less than 0.20 V/ms to
ensure that clock CLK is correctly delivered to the card
until time t12 (see Fig.9).
Vth2(ext)(rise) 1R1
R2
-------
+
Vbridge Vhys(ext)
2
--------------------
+
×=
Vth2(ext)(fall) 1R1
R2
-------
+
Vbridge Vhys(ext)
2
--------------------
–
×=
kS1
S1 S2+
---------------------
=
1 0.98 R1
R2
-------
×
+10.99
1.01
-----------
R1
R2
--------1
k
---
<×+=
1
k
---11.01
0.99
-----------
R1
R2
-------
×+<1 1.02 R1
R2
-------
×
+=
VDD V1
k
-------
>
VDD V2
k
-------
<
R1
R2
------- 3.135
1.31
---------------1–
0.98×1.365=<
R2 100 kΩ
2.365
-------------------
=
R1
R2
------- 3.267
1.310
---------------1–
0.998×1.491=<
R2 100 kΩ
2.49
-------------------
=
2004 July 12 10
Philips Semiconductors Product specification
IC card interface TDA8024
8.3 Clock circuitry
The card clock signal (CLK) is derived from a clock signal
input to pin XTAL1 or from a crystal operating at up to
26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be fXTAL,1/2×fXTAL,1/4×fXTAL
or 1/8×fXTAL. Frequency selection is made via
inputs CLKDIV1 and CLKDIV2 (see Table 1).
Table 1 Clock frequency selection; note 1
Note
1. Thestatusofpins CLKDIV1andCLKDIV2mustnotbe
changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of
any state of CLK is eight periods of XTAL1.
The frequency change is synchronous, which means that
during transition no pulse is shorter than 45% of the
smallest period, and that the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the change is
effective for only eight periods of XTAL1 after the
command.
The duty factor of fXTAL depends on the signal present at
pin XTAL1.
In order to reach a 45 to 55% duty factor on pin CLK, the
input signal on pin XTAL1 should have a duty factor of
48 to 52% and transition times of less than 5% of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be
45 to 55% depending on the circuit layout and on the
crystal characteristics and frequency.
In other cases, the duty factor on pin CLK is guaranteed
between 45 and 55% of the clock period.
Thecrystaloscillatorruns as soon as the IC is powered up.
If the crystal oscillator is used, or if the clock pulse on
pin XTAL1 is permanent, the clock pulse is applied to the
cardasshownintheactivationsequences shown in Figs 7
and 8.
If the signal applied to XTAL1 is controlled by the system
microcontroller, the clock pulse will be applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
8.4 I/O transceivers
The three data lines I/O, AUX1 and AUX2 are identical.
The idle state is realized by both I/O and I/OUC lines being
pulled HIGH via a 11 kΩresistor (I/O to VCC and I/OUC to
VDD).
Pin I/O is referenced to VCC, and pin I/OUC to VDD, thus
allowing operation when VCC is not equal to VDD.
The first side of the transceiver to receive a falling edge
becomes the master. An anti-latch circuit disables the
detection of falling edges on the line of the other side,
which then becomes a slave.
After a time delay td(edge), an N transistor on the slave side
is turned on, thus transmitting the logic 0 present on the
master side.
When the master side returns to logic 1, a P transistor on
the slave side is turned on during the time delay tpu and
then both sides return to their idle states.
This active pull-up feature ensures fast LOW-to-HIGH
transitions;as shown inFig.6,itis able todelivermorethan
1 mA at an output voltage of up to 0.9VCC into an 80 pF
load. At the end of the active pull-up pulse, the output
voltage depends only on the internal pull-up resistor and
the load current.
The current to and from the card I/O lines is limited
internally to 15 mA and the maximum frequency on these
lines is 1 MHz.
CLKDIV1 CLKDIV2 fCLK
00
01
11
10
fXTAL
fXTAL
8
-------------
fXTAL
4
-------------
fXTAL
2
-------------
2004 July 12 11
Philips Semiconductors Product specification
IC card interface TDA8024
8.5 Inactive mode
After a Power-on reset, the circuit enters the inactive
mode. A minimum number of circuits are active while
waiting for the microcontroller to start a session:
•All card contacts are inactive (approximately 200 Ω to
GND)
•Pins I/OUC, AUX1UC and AUX2UC are in the
high-impedance state (11 kΩ pull-up resistor to VDD)
•Voltage generators are stopped
•XTAL oscillator is running
•Voltage supervisor is active
•The internal oscillator is running at its low frequency.
8.6 Activation sequence
Afterpower-on and afterthe internal pulsewidth delay, the
system microcontroller can check the presence of a card
using the signals OFF and CMDVCC as shown in Table 2.
Table 2 Card presence indication
If the card is in the reader (this is the case if PRES or
PRES is active), the system microcontroller can start a
card session by pulling CMDVCC LOW. The following
sequence then occurs (see Fig.6):
1. CMDVCC is pulled LOW and the internal oscillator
changes to its high frequency (t0).
2. The voltage doubler is started (between t0and t1).
3. VCC rises from 0 to 5 V (or 3 V) with a controlled slope
(t2=t
1+ 1.5 ×T) where T is 64 times the period of the
internal oscillator (approximately 25 µs).
4. I/O, AUX1 and AUX2 are enabled (t3=t
1+ 4T) (these
were pulled LOW until this moment).
5. CLKis applied tothe C3 contact of thecard reader (t4).
6. RST is enabled (t5=t
1+ 7T).
The clock may be applied to the card using the following
sequence:
1. Set RSTIN HIGH.
2. Set CMDVCC LOW.
3. Reset RSTIN LOW between t3and t5; CLK will start at
this moment.
4. RST remains LOW until t5, when RST is enabled to be
the copy of RSTIN.
5. After t5, RSTIN has no further affect on CLK; this
allows a precise count of CLK pulses before toggling
RST.
If the applied clock is not needed, then CMDVCC may be
set LOW with RSTIN LOW. In this case, CLK will start at t3
(minimum 200 ns after the transition on I/O), and after t5,
RSTIN may be set HIGH in order to obtain an Answer To
Request (ATR) from the card.
Activation should not be performed with RSTIN held
permanently HIGH.
0
(2)
(1)
6
4
2
020 40 t (ns)
Vo
(V)
12
8
4
0
Io
(mA)
60
FCE661
Fig.6 I/O, AUX1 and AUX2 output voltage and
current as functions of time during a
LOW-to-HIGH transition.
(1) Current.
(2) Voltage.
OFF CMDVCC INDICATION
HIGH HIGH card present
LOW HIGH card not present
2004 July 12 12
Philips Semiconductors Product specification
IC card interface TDA8024
handbook, full pagewidth
VUP
CMDVCC
VCC
I/O
RSTIN
CLK
I/OUC
RST
ATR
t0t2t4t5 = tact
t1
MDB054
t3
Fig.7 Activation sequence using RSTIN and CMDVCC.
handbook, full pagewidth
VUP
CMDVCC
VCC
I/O
RSTIN
CLK
I/OUC
RST
t0t2t4
t5 = tact
t1
MDB055
t3
ATR
200 ns
Fig.8 Activation sequence at t3.
2004 July 12 13
Philips Semiconductors Product specification
IC card interface TDA8024
8.7 Active mode
When the activation sequence is completed, the TDA8024
will be in its active mode. Data is exchanged between the
card and the microcontroller via the I/O lines. The
TDA8024 is designed for cards without VPP (the voltage
required to program or erase the internal non-volatile
memory).
8.8 Deactivation sequence
When a session is completed, the microcontroller sets the
CMDVCC line HIGH. The circuit then executes an
automatic deactivation sequence by counting the
sequencer back and finishing in the inactive mode (see
Fig.9):
1. RST goes LOW (t10).
2. CLK is held LOW (t12 =t
10 + 0.5 ×T) where T is 64
times the period of the internal oscillator
(approximately 25 µs).
3. I/O, AUX1 and AUX2 are pulled LOW (t13 =t
10 + T).
4. VCC starts to fall towards zero (t14 =t
10 + 1.5 ×T).
5. The deactivation sequence is complete at tde, when
VCC reaches its inactive state.
6. VUP falls to zero (t15 =t
10 + 5T) and all card contacts
becomelow-impedance to GND;I/OUC,AUX1UCand
AUX2UC remain at VDD (pulled-up via a 11 kΩ
resistor).
7. The internal oscillator returns to its lower frequency.
handbook, full pagewidth
RST
CMDVCC
CLK
I/O
VUP
VCC
t15
t14
t13
t12
MDB056
tde
t10
Fig.9 Deactivation sequence.
2004 July 12 14
Philips Semiconductors Product specification
IC card interface TDA8024
8.9 VCC generator
The VCC generator has a capacity to supply up to 80 mA
continuously at 5 V and 65 mA at 3 V.
An internal overload detector operates at approximately
120 mA. Current samples to the detector are internally
filtered, allowing spurious current pulses up to 200 mA
with a duration in the order of µs to be drawn by the card
without causing deactivation. The average current must
stay below the specified maximum current value.
For reasons of VCC voltage accuracy, a 100 nF capacitor
with an ESR < 100 mΩ should be tied to CGND near to
pin VCC, and a 100 or 220 nF capacitor (220 nF is the best
choice) with the same ESR should be tied to CGND near
card reader contact C1.
8.10 Fault detection
The following fault conditions are monitored:
•Short-circuit or high current on VCC
•Removal of a card during a transaction
•VDD dropping
•DC/DC converter operating out of the specified values
(VDDP too low or current from VUP too high)
•Overheating.
There are two different cases (see Fig.10):
•CMDVCC HIGH outside a card session. Output OFF
is LOW if a card is not in the card reader, and HIGH if a
card is in the reader. A voltage drop on the VDD supply
is detected by the supply supervisor, this generates an
internal Power-on reset pulse but does not act upon
OFF. No short-circuit or overheating is detected
because the card is not powered-up.
•CMDVCC LOW within a card session. Output OFF
goes LOW when a fault condition is detected. As soon
as this occurs, an emergency deactivation is performed
automatically (see Fig.11). When the system controller
resets CMDVCC to HIGH it may sense the OFF level
again after completing the deactivation sequence. This
distinguishes between a hardware problem or a card
extraction (OFF goes HIGH again if a card is present).
Depending on the type of card-present switch within the
connector (normally-closed or normally-open) and on the
mechanical characteristics of the switch, bouncing may
occur on the PRES signals at card insertion or withdrawal.
There is a debounce feature in the device with an 8 ms
typical duration (see Fig.10). When a card is inserted,
output OFF goes HIGH only at the end of the debounce
time.
When the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES or PRES and output OFF goes LOW.
handbook, full pagewidth
MDB059
OFF
CMDVCC
PRES
VCC
debounce
deactivation caused by
cards withdrawal deactivation caused by
short-circuit
debounce
Fig.10 Behaviour of OFF, CMDVCC, PRES and VCC.
See
“Application note AN10141”
for software decision algorithm on OFF signal.
2004 July 12 15
Philips Semiconductors Product specification
IC card interface TDA8024
handbook, full pagewidth
RST
PREST
OFF
CLK
I/O
VUP
VCC
t15
t14
t13
t12
MDB057
tde
t10
Fig.11 Emergency deactivation sequence (card extraction).
2004 July 12 16
Philips Semiconductors Product specification
IC card interface TDA8024
9 LIMITING VALUES
Notes
1. All card contacts are protected against any short-circuit with any other card contact.
2. Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.
Method 3015 (HBM; 1500 Ωand 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground.
3. In accordance with EIA/JESD22-A114-B, June 2000.
4. In accordance with EIA/JESD22-A115-A, October 1997.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see
“Handling MOS devices”
).
11 THERMAL CHARACTERISTICS
Note
1. This figure was obtained using the following PCB technology: FR, 4 layers, 0.5 mm thickness, class 5, copper
thickness 35 µm, Ni/Go plating, ground plane in internal layers
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDD supply voltage −0.3 +6.5 V
VDDP DC/DC converter supply voltage −0.3 +6.5 V
VI, VOvoltage on input and output pins pins XTAL1, XTAL2, 5V/3V, RSTIN,
AUX1UC, AUX2UC, I/OUC,
CLKDIV1, CLKDIV2, CMDVCC, OFF
and PORADJ
−0.3 +6.5 V
Vcard voltage on card pins pins PRES, PRES, I/O, RST, AUX1,
AUX2 and CLK −0.3 +6.5 V
Vnvoltage on other pins pins VUP, S1 and S2 −0.3 +6.5 V
Tj(max) maximum junction temperature −150 °C
Tstg storage temperature −55 +150 °C
Vesd electrostatic discharge voltage card contacts in typical application;
notes 1 and 2
pins I/O, RST, VCC, AUX1, AUX2,
CLK, PRES and PRES −6+6kV
all pins; note 1
human body model; notes 2 and 3 −2+2kV
machine model; note 4 −200 +200 V
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction
to ambient in free air
TDA8024T 70 K/W
TDA8024AT 70 K/W
TDA8024TT 100(1) K/W
2004 July 12 17
Philips Semiconductors Product specification
IC card interface TDA8024
12 CHARACTERISTICS
VDD = 3.3 V; VDDP =5V; T
amb =25°C; fXTAL = 10 MHz; all currents flowing into the IC are positive; see note 1; unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT
Temperature
Tamb ambient temperature −25 −+85 °C
Supplies
VDD supply voltage 2.7 −6.5 V
VDDP DC/DC converter supply
voltage VCC =5V;ICC< 80 mA 4.0 5.0 6.5 V
VCC =5V;ICC< 20 mA 3.0 −6.5 V
IDD supply current card inactive −−1.2 mA
card active; fCLK =f
XTAL;
CL=30pF −−1.5 mA
IDDP DC/DC converter supply
current inactive mode −−0.1 mA
active mode; fCLK =f
XTAL;
CL= 30 pF; ICC=0 −−10 mA
VCC =5V;ICC=80mA −−200 mA
VCC =3V;ICC=65mA −−100 mA
Vth2 falling threshold voltage on
VDD
no external resistors at
pin PORADJ; VDD level falling 2.35 2.45 2.55 V
Vhys2 hysteresis of threshold
voltage Vth2
no external resistors at
pin PORADJ 50 100 150 mV
Pin PORADJ; note 2
Vth(ext)(rise) external rising threshold
voltage on VDD
external resistor bridge at
pin PORADJ; VDD level rising 1.240 1.28 1.310 V
Vth(ext)(fall) external falling threshold
voltage on VDD
external resistor bridge at
pin PORADJ; VDD level falling 1.190 1.22 1.26 V
Vhys(ext) hysteresis of threshold
voltage Vth(ext)
external resistor bridge at
pin PORADJ 30 60 90 mV
∆Vhys(ext) hysteresis of threshold
voltage Vth(ext) variation
with temperature
external resistor bridge at
pin PORADJ −−0.25 mV/K
twwidth of internal Power-on
reset pulse no external resistors at
pin PORADJ 4 8 12 ms
external resistor bridge at
pin PORADJ 81624ms
IL(PORADJ) leakage current on
pin PORADJ VPORADJ < 0.5 V −0.1 4 10 µA
VPORADJ >1V −1−+1 µA
Ptot total power dissipation continuous operation;
Tamb =−25 to +85 °C−−0.56 W
2004 July 12 18
Philips Semiconductors Product specification
IC card interface TDA8024
DC/DC converter
fCLK clock frequency card active 2.2 −3.2 MHz
Vth(vd-vf) threshold voltage for
voltage doubler to change
to voltage follower
5 V card 5.2 5.8 6.2 V
3 V card 3.8 4.1 4.4 V
VUP(av) output voltage on pin VUP
(average value) VCC = 5 V 5.2 5.7 6.2 V
VCC =3V; V
DDP = 3.3 V 3.5 3.9 4.3 V
Card supply voltage (pin VCC); note 3
CVCC external capacitance on
pin VCC
note 4 80 −400 nF
VCC card supply voltage
(including ripple voltage) 5 V card
card inactive; ICC=0mA −0.1 0 +0.1 V
card inactive; ICC=1mA −0.1 0 +0.3 V
card active; ICC< 80 mA 4.75 5.0 5.25 V
card active; single current
pulse, Ip=−100 mA,
tp=2ms
4.65 5.0 5.25 V
card active; current pulses,
Ip= 40 nAs 4.65 5.0 5.25 V
card active; current pulses,
Ip= 40 nAs with
ICC< 200 mA, tp< 400 ns
4.65 5.0 5.25 V
3 V card
card inactive; ICC=0mA −0.1 0 +0.1 V
card inactive; ICC=1mA −0.1 0 +0.3 V
card active; ICC< 65 mA 2.85 3.0 3.15 V
card active; single current
pulse Ip=−100 mA;
tp=2ms
2.76 3.0 3.20 V
card active; current pulses,
Ip= 40 nAs 2.76 3.0 3.20 V
card active; current pulses,
Ip= 40 nAs with
ICC< 200 mA, tp< 400 ns
2.76 3.0 3.20 V
VCC(ripple)(p-p) ripple voltage on VCC
(peak to peak value) fripple = 20 kHz to 200 MHz −−350 mV
ICCcard supply current VCC =0to5V −−80 mA
VCC =0to3V −−65 mA
VCC short-circuit to GND 100 120 150 mA
SR slew rate slew up or down 0.08 0.15 0.22 V/µs
SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT
2004 July 12 19
Philips Semiconductors Product specification
IC card interface TDA8024
Crystal oscillator (pins XTAL1 and XTAL2)
CXTAL1,
CXTAL2
external capacitance on
pins XTAL1 and XTAL2 depends on type of crystal or
resonator used −−15 pF
fXTAL crystal frequency 2 −26 MHz
fXTAL1 frequency applied on
pin XTAL1 0−26 MHz
VIL LOW-level input voltage on
pin XTAL1 −0.3 −+0.3VDD V
VIH HIGH-level input voltage
on pin XTAL1 0.7VDD −VDD + 0.3 V
Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC)
td(I/O-I/OUC),
td(I/OUC-I/O)
I/O to I/OUC, I/OUC to I/O
falling edge delay −−200 ns
tpu active pull-up pulse width −−100 ns
fI/O(max) maximum frequency on
data lines −−1 MHz
Ciinput capacitance on data
lines −−10 pF
Data lines to card reader (pins I/O, AUX1 and AUX2; with integrated 11 kΩ pull-up resistors to VCC)
Vo(inactive) output voltage inactive mode
no load 0 −0.1 V
Io(inactive) =1mA −−0.3 V
Io(inactive) output current inactive mode; pin grounded −−−1mA
VOL LOW-level output voltage IOL = 1 mA 0 −0.3 V
IOL ≥15 mA VCC −0.4 −VCC V
VOH HIGH-level output voltage no DC load 0.9VCC −VCC + 0.1 V
5 and 3 V cards; IOH <−40 µA 0.75VCC −VCC + 0.1 V
IOH≥10 mA 0 −0.4 V
VIL LOW-level input voltage 0.3 −0.8 V
VIH HIGH-level input voltage 1.5 −VCC + 0.3 V
IILLOW-level input current VIL =0V −−600 µA
ILIHHIGH-level input leakage
current VIH =V
CC −−10 µA
tt(DI) data input transition time VIL(max) to VIH(min) −−1.2 µs
tt(DO) data output transition time Vo= 0 to VCC; CL≤80 pF;
10% to 90% −−0.1 µs
Rpu integrated pull-up resistor pull-up resistor to VCC 91113kΩ
Ipu current when pull-up active VOH = 0.9VCC; C = 80 pF −1−− mA
SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT
2004 July 12 20
Philips Semiconductors Product specification
IC card interface TDA8024
Data lines to microcontroller (pins I/OUC, AUX1UC and AUX2UC; with integrated 11 kΩ pull-up resistors
to VDD)
VOL LOW-level output voltage IOL = 1 mA 0 −0.3 V
VOH HIGH-level output voltage no DC load 0.9VDD −VDD + 0.1 V
5 and 3 V cards; IOH <−40 µA 0.75VDD −VDD + 0.1 V
VIL LOW-level input voltage −0.3 −+0.3VDD V
VIH HIGH-level input voltage 0.7VDD −VDD + 0.3 V
ILIHHIGH-level input leakage
current VIH =V
DD −−10 µA
ILLOW-level input current VIL =0V −−600 µA
Rpu integrated pull-up resistor pull-up resistor to VCC 91113kΩ
tt(DI) data input transition time VIL(max) to VIH(min) −−1.2 µs
tt(DO) data output transition time Vo= 0 to VDD; CL< 30 pF;
10% to 90% −−0.1 µs
Ipu current when pull-up active VOH = 0.9VDD; C = 30 pF −1−− mA
Internal oscillator
fOSC(int) frequency of internal
oscillator inactive mode 55 140 200 kHz
active mode 2.2 2.7 3.2 MHz
Reset output to card reader (pin RST)
Vo(inactive) output voltage inactive mode
no load 0 −0.1 V
Io(inactive) =1mA 0 −0.3 V
Io(inactive) output current inactive mode; pin grounded 0 −−1mA
td(RSTIN-RST) RSTIN to RST delay RST enabled −−2µs
VOL LOW-level output voltage IOL = 200 µA0−0.2 V
IOL = 20 mA (current limit) VCC −0.4 −VCC V
VOH HIGH-level output voltage IOH =−200 µA 0.9VCC −VCC V
IOH =−20 mA (current limit) 0 −0.4 V
trrise time CL= 100 pF; VCC =5or3V −−0.1 µs
tffall time CL= 100 pF; VCC =5or3V −−0.1 µs
Clock output to card reader (pin CLK)
Vo(inactive) output voltage inactive mode
no load 0 −0.1 V
Io(inactive) =1mA 0 −0.3 V
Io(inactive) output current CLK inactive; pin grounded 0 −−1mA
VOL LOW-level output voltage IOL = 200 µA0−0.3 V
IOL = 70 mA (current limit) VCC −0.4 −VCC V
VOH HIGH-level output voltage IOH =−200 µA 0.9VCC −VCC V
IOH =−70 mA (current limit) 0 −0.4 V
trrise time CL= 30 pF; note 5 −−16 ns
SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT
2004 July 12 21
Philips Semiconductors Product specification
IC card interface TDA8024
tffall time CL= 30 pF; note 5 −−16 ns
δduty factor (except for
fXTAL)CL= 30 pF; note 5 45 −55 %
SR slew rate slew up or down; CL= 30 pF 0.2 −− V/ns
Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V); note 6
VIL LOW-level input voltage −0.3 −+0.3VDD V
VIH HIGH-level input voltage 0.7VDD −VDD + 0.3 V
ILILLOW-level input leakage
current 0<V
IL <V
DD −−1µA
ILIHHIGH-level input leakage
current 0<V
IH <V
DD −−1µA
Card presence inputs (pins PRES and PRES); note 7
VIL LOW-level input voltage −0.3 −+0.3VDD V
VIH HIGH-level input voltage 0.7VDD −VDD + 0.3 V
ILILLOW-level input leakage
current 0<V
IL <V
DD −−5µA
ILIHHIGH-level input leakage
current 0<V
IH <V
DD −−5µA
Interrupt output (pin OFF; NMOS drain with integrated 20 kΩ pull-up resistor to VDD)
VOL LOW-level output voltage IOL = 2 mA 0 −0.3 V
VOH HIGH-level output voltage IOH =−15 µA 0.75VDD −− V
Rpu integrated pull-up resistor 20 kΩ pull-up resistor to VDD 16 20 24 kΩ
Protection and limitation
ICC(sd)shutdown and limitation
current pin VCC
−130 150 mA
II/O(lim) limitation current pins I/O,
AUX1 and AUX2 −15 −+15 mA
ICLK(lim) limitation current pin CLK −70 −+70 mA
IRST(lim) limitation current pin RST −20 −+20 mA
Tsd shut-down temperature −150 −°C
Timing
tact activation time see Fig.7 50 −220 µs
tde deactivation time see Fig.8 50 80 100 µs
t3start of the window for
sending CLK to the card see Fig.7 50 −130 µs
t5end of the window for
sending CLK to the card see Fig.7 140 −220 µs
tdebounce debounce time pins PRES
and PRES see Fig.10 5 8 11 ms
SYMBOL PARAMETER CONDITIONS MIN. TYP MAX. UNIT
2004 July 12 22
Philips Semiconductors Product specification
IC card interface TDA8024
Notes
1. All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is
specified as a function of VDD or VCC it means their actual value at the moment of measurement.
2. If no external bridge is used then, to avoid any disturbance, it is recommended to connect pin 18 to ground. Pin 18
is not connected in the TDA8024AT
3. To meet these specifications, pin VCC should be decoupled to CGND using two ceramic multilayer capacitors of low
ESR both with values of 100 nF, or one 100 nF and one 220 nF (see Fig.13).
4. Permitted capacitor values are 100, or 100 + 100, or 220, or 220 + 100, or 330 nF.
5. Transition time and duty factor definitions are shown in Fig.12;
6. Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 1.
7. Pin PRES is active LOW; pin PRES is active HIGH; PRES has an integrated 1.25 µA current source to GND
(PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active.
δt1
t1t2
+
---------------
=
handbook, full pagewidth
MDB058
10%
90% 90%
10%
trtf
t1t2
VOH
VOH + VOL
2
VOL
Fig.12 Definition of output and input transition times.
13 APPLICATION INFORMATION
Performance can be affected by the layout of the
application. For example, an additional cross-capacitance
of 1 pF between card reader contacts C2 and C3 or C2
and C7 can cause contact C2 to be polluted with high
frequency noise from C3 (or C7). In this case, include a
100 pF capacitor between contacts C2 and CGND.
Application recommendations:
•Ensurethereis ample ground areaaroundtheTDA8024
and the connector; place the TDA8024 very near to the
connector;decoupletheVDD andVDDP lines (these lines
are best positioned under the connector)
•The TDA8024 and the microcontroller must use the
same VDD supply. Pins CLKDIV1, CLKDIV2, RSTIN,
PRES, PRES, AUX1UC, I/OUC, AUX2UC, 5V/3V,
CMDVCC, and OFF are referred to VDD; if pin XTAL1 is
to be driven by an external clock, also refer this pin to
VDD
•Track C3 should be placed as far as possible from the
other tracks
•The track connecting CGND to C5 should be straight
(the two capacitors on C1 should be connected to this
ground track)
•Avoid ground loops between CGND, PGND and GND
•Decouple VDDP and VDD separately; if the two supplies
are the same in the application, then they should be
connected in star on the main track.
With all these layout precautions, noise should be kept to
an acceptable level and jitter on C3 should be less than
100 ps.
Reference layouts are provided in
“Application
note 10141”
, available on request.
2004 July 12 23
Philips Semiconductors Product specification
IC card interface TDA8024
handbook, full pagewidth
100 nF(1)
100 nF(1)
100 nF
(3)
(6)
(7)
AUX2UC
AUX1UC
I/OUC
XTAL2
XTAL1
OFF
GND
VDD
RSTIN
CMDVCC
PORADJ
VCC
RST
CLK
CLKDIV1
CLKDIV2
5V/3V
PGND
VDDP
S1
S2
VUP
PRES
PRES
I/O
AUX2
AUX1
CGND
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
TDA8024
C5
C6
C7
C8
C1
C2
C3
C4
CARD READ
(normally closed type)
K1
K2
+3.3 V
+3.3 V
VDD
58.1 kΩ
41.9 kΩ
3.3 V POWERED
MICROCONTROLLER
33 pF
100 nF
100 nF(4)
220 nF(5)
+5 V
10 µF
100 kΩ
MDB050
+3.3 V(2)
Fig.13 Application diagram.
(1) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm).
(2) TDA8024 and the microcontroller must use the same VDD supply.
(3) Make short, straight connections between CGND, C5 and the ground connection to the capacitor.
(4) Mount one low ESR-type 100 nF capacitor close to pin VCC.
(5) Mount one low ESR-type 100 or 220 nF capacitor close to C1 contact (less than 100 mm from it).
(6) The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by grounded tracks.
(7) Optional resistor bridge for changing the threshold of VDD. If this bridge is not required pin 18 should be connected to ground; see Section 8.2.2.
Pin 18 is not connected in the TDA8024AT.
2004 July 12 24
Philips Semiconductors Product specification
IC card interface TDA8024
14 PACKAGE OUTLINES
UNIT A
max. A
1
A
2
A
3
b
p
cD
(1)
E
(1) (1)
eH
E
LL
p
QZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 18.1
17.7 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT136-1
X
14
28
w
M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
c
L
v
M
A
e
15
1
(A )
3
A
y
0.25
075E06 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.71
0.69 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1
99-12-27
03-02-19
2004 July 12 25
Philips Semiconductors Product specification
IC card interface TDA8024
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 9.8
9.6 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.8
0.5 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT361-1 MO-153 99-12-27
03-02-19
0.25
w
M
b
p
Z
e
114
28 15
pin 1 index
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
D
y
0 2.5 5 mm
scale
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1
A
max.
1.1
2004 July 12 26
Philips Semiconductors Product specification
IC card interface TDA8024
15 SOLDERING
15.1 Introduction to soldering surface mount
packages
Thistextgives a verybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurface mount ICs,butitis not suitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboardby screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 seconds and 200 seconds
depending on heating method.
Typical reflow peak temperatures range from
215 °C to 270 °Cdepending on solderpaste material. The
top-surface temperature of the packages should
preferably be kept:
•below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
– for all BGA, HTSSON-T and SSOP-T packages
– for packages with a thickness ≥2.5 mm
– for packages with a thickness < 2.5 mm and a
volume ≥350 mm3 so called thick/large packages.
•below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
15.3 Wave soldering
Conventional single wave soldering is not recommended
forsurface mount devices(SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackages with leadsonfoursides, thefootprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 °C or 265 °C, depending
on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 seconds to 5 seconds
between 270 °C and 320 °C.
2004 July 12 27
Philips Semiconductors Product specification
IC card interface TDA8024
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. FormoredetailedinformationontheBGApackagesrefer to the
“(LF)BGAApplicationNote
”(AN01026);orderacopy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C±10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable
PLCC(5), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(5)(6) suitable
SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable
CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable not suitable
2004 July 12 28
Philips Semiconductors Product specification
IC card interface TDA8024
16 DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
17 DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at any other conditions above those given inthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentation orwarrantythat suchapplicationswillbe
suitable for the specified use without further testing or
modification.
18 DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2004 SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands R63/03/pp29 Date of release: 2004 July 12 Document order number: 9397 750 13195
