PRELIMINARY
DS-LM3S101-05 Copyright © 2006 Luminary Micro, Inc.
LM3S101 Microcontroller
DATA SHEET
2October 5, 2006
Preliminary
Legal Disclaimers and Trademark Informatio n
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LM3S101 Data Sheet
October 5, 2006 3
Preliminary
Table of Contents
Legal Disclaimers and Trademark Information.............................................................................. 2
Revis io n H is t o ry .......... .. ...... ... .. ...... ... ...... ... .. ...... ... ...... .. ... ...... .. ....... .. .. ....... .. ....... .. .. ....... ................ 14
About This Document............................................................................................................ ......... 15
Audience...........................................................................................................................................................15
About This Manua l................. ................... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... .................................15
Related Documents ..........................................................................................................................................15
Documentation Conventions.............................................................................................................................15
1. Architectural Overview....................................................................................................... 18
1.1 Product Features .................................................................................................................................18
1.2 Target Applica tio ns......... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ...... ....... ..........................20
1.3 High-Level Block Diagram ...................................................................................................................21
1.4 Functional Overview ............................................................................................................................22
1.4.1 ARM Cortex™-M3 ...............................................................................................................................22
1.4.2 Motor Control Peripherals....................................................................................................................22
1.4.3 Analog Peripherals ..............................................................................................................................22
1.4.4 Serial Communications Peripherals.....................................................................................................23
1.4.5 System Periphe rals................ ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... .................................23
1.4.6 Memory Peripherals.............................................................................................................................24
1.4.7 Additional Features..............................................................................................................................25
1.4.8 Hardware Details .................................................................................................................................25
1.5 System Block Diag ram ................ .................... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....................26
2. ARM Cortex-M3 Processor Core........................................................................................27
2.1 Block Diagram ................ ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ..........................28
2.2 Functional Description .........................................................................................................................28
2.2.1 Serial Wire and JTAG Debug ..............................................................................................................28
2.2.2 Embedded Trace Macrocell (ETM)......................................................................................................29
2.2.3 Trace Port Interface Unit (TPIU)..........................................................................................................29
2.2.4 ROM Table ..........................................................................................................................................29
2.2.5 Memory Protection Unit (MPU)............................................................................................................29
2.2.6 Nested Vectored Interrupt Controller (NVIC).......................................................................................29
3. Memory Map ........................................................................................................................ 30
4. Interrupts .............................................................................................................................32
5. JTAG Interface ....................................................................................................................35
5.1 Block Diagram ................ ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ..........................36
5.2 Functional Description .........................................................................................................................36
5.2.1 JTAG Interface Pins.............................................................................................................................37
5.2.2 JTAG TAP Controller...........................................................................................................................38
5.2.3 Shift Registers ................ ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ..............................................39
5.2.4 Operational Considerations .................................................................................................................39
5.3 Initialization and Configuration.............................................................................................................40
5.4 Register Descriptions...........................................................................................................................41
5.4.1 Instruction Register (IR).......................................................................................................................41
5.4.2 Data Registers.....................................................................................................................................43
6. Syste m C o n tr o l... .. ....... .. .. ....... .. ....... .. .. ....... .. ...... ... .. ...... ... ...... .. ... ...... ... ...... .. ... ...... .. ............45
6.1 Functional Description .........................................................................................................................45
6.1.1 Device Identification.............................................................................................................................45
Table of Contents
4October 5, 2006
Preliminary
6.1.2 Reset Control.......................................................................................................................................45
6.1.3 Power Control......................................................................................................................................48
6.1.4 Clock Control .......................................................................................................................................48
6.1.5 System Contro l .. ....... ...... ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...... ....... ..........................50
6.2 Initialization and Configuration.............................................................................................................51
6.3 Register Map .......................................................................................................................................51
6.4 Register Descriptions...........................................................................................................................52
7. Inte rn a l Me mory ....... ... ...... .. ....... .. ... ...... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... .. .. .....83
7.1 Block Diagram ................ ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ..........................83
7.2 Functional Description .........................................................................................................................83
7.2.1 SRAM Memory ............... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... .......................................83
7.2.2 Flash Memory........... ...... ....... ...... .................... ...... ....... ...... ...... ....... ...... ....... ...... ....... ..........................84
7.3 Initialization and Configuration.............................................................................................................85
7.3.1 Changing Flash Protection Bits ...........................................................................................................85
7.3.2 Flash Programmi ng ............... ...... ....... ...... ....... ................... ...... ....... ...... ....... ...... ....... ..........................86
7.4 Register Map .......................................................................................................................................86
7.5 Register Descriptions...........................................................................................................................87
8. Gener al-Purpose Input/Outputs (GPIOs)................. ........... ........... ........... ........... ........... ..97
8.1 Block Diagram ................ ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ..........................98
8.2 Functional Description .........................................................................................................................98
8.2.1 Data Register Operation......................................................................................................................99
8.2.2 Data Direction....................................................................................................................................100
8.2.3 Interrupt Operation.............................................................................................................................100
8.2.4 Mode Control .....................................................................................................................................101
8.2.5 Pad Configuration..............................................................................................................................101
8.2.6 Identification.......................................................................................................................................101
8.3 Initialization and Configuration...........................................................................................................101
8.4 Register Map .....................................................................................................................................103
8.5 Register Descriptions.........................................................................................................................104
9. General-Purpose Timers .................................................................................................. 135
9.1 Block Diagram ................ ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ........................136
9.2 Functional Description .......................................................................................................................136
9.2.1 GPTM Reset Conditio ns. ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...... ....... ...... ..................136
9.2.2 32-Bit Timer Operating Modes...........................................................................................................137
9.2.3 16-Bit Timer Operating Modes...........................................................................................................138
9.3 Initialization and Configuration...........................................................................................................142
9.3.1 32-Bit One-Shot/Periodic Timer Mode...............................................................................................142
9.3.2 32-Bit Real-Time Clock (RTC) Mode.................................................................................................143
9.3.3 16-Bit One-Shot/Periodic Timer Mode...............................................................................................143
9.3.4 16-Bit Input Edge Count Mode ..........................................................................................................143
9.3.5 16-Bit Input Edge Timing Mode .........................................................................................................144
9.3.6 16-Bit PWM Mode..............................................................................................................................144
9.4 Register Map .....................................................................................................................................145
9.5 Register Descriptions.........................................................................................................................146
10. Watchdog Timer................................................................................................................167
10.1 Block Diagram ................ ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ........................167
10.2 Functional Description .......................................................................................................................168
10.3 Initialization and Configuration...........................................................................................................168
10.4 Register Map .....................................................................................................................................168
LM3S101 Data Sheet
October 5, 2006 5
Preliminary
10.5 Register Descriptions.........................................................................................................................169
11. Universal Asynchronous Receiver/Tra nsmi tter (UART).............................................. ..190
11.1 Block Diagram ................ ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ........................191
11.2 Functional Description .......................................................................................................................191
11.2.1 Transmit/Receive Logic .....................................................................................................................191
11.2.2 Baud-Rate Generation.......................................................................................................................192
11.2.3 Data Transmission.............................................................................................................................193
11.2.4 FIFO Operation..................................................................................................................................193
11.2.5 Interrupts............................................................................................................................................193
11.2.6 Loopback Operation ..........................................................................................................................194
11.3 Initialization and Configuration...........................................................................................................194
11.4 Register Map .....................................................................................................................................195
11.5 Register Descriptions.........................................................................................................................196
12. Synchronous Serial Interface (SSI)........... .. ........... .................... ........... ........... ........... ....226
12.1 Block Diagram ................ ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ........................226
12.2 Functional Description .......................................................................................................................227
12.2.1 Bit Rate Generation ...........................................................................................................................227
12.2.2 FIFO Operation..................................................................................................................................227
12.2.3 Interrupts............................................................................................................................................227
12.2.4 Frame Formats ............... .................... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ........................228
12.3 Initialization and Configuration...........................................................................................................235
12.4 Register Map .....................................................................................................................................236
12.5 Register Descriptions.........................................................................................................................237
13. A n a lo g Co mp a ra t o r s ... ...... .. ....... .. ... ...... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... .. .. ... 261
13.1 Block Diagram ................ ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ........................261
13.2 Functional Description .......................................................................................................................261
13.2.1 Internal Reference Programming.......................................................................................................263
13.3 Initialization and Configuration...........................................................................................................264
13.4 Register Map .....................................................................................................................................265
13.5 Register Descriptions.........................................................................................................................265
14. P in D ia g r a m...... ...... .. ... ...... .. ....... .. ... ...... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... ....... 273
15. Signal Tables..................................................................................................................... 274
16. O p e ra t in g C h a ra cteristics..... .. .. ....... .. ....... .. .. ....... .. ...... ... .. ...... ... ...... ... .. ...... ... ...... .. ... ...... . 28 1
17. Electrical Characteristics................................................................................................. 282
17.1 DC Characteristics.............................................................................................................................282
17.1.1 Maximum Ratings..............................................................................................................................282
17.1.2 Recommended DC Operating Conditions .........................................................................................282
17.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics..................................................................283
17.1.4 Power Specifications .........................................................................................................................284
17.1.5 Flash Memory Characteri stic s ............ ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ..................284
17.2 AC Characteristic s.......... ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...... ....... ........................285
17.2.1 Load Conditions.................................................................................................................................285
17.2.2 Clocks................................................................................................................................................285
17.2.3 Analog Comparator............................................................................................................................286
17.2.4 Synchronous Serial Interface (SSI) ...................................................................................................287
17.2.5 JTAG and Boundary Scan.................................................................................................................289
17.2.6 General-Purpose I/O..........................................................................................................................291
17.2.7 Reset .................................................................................................................................................291
Table of Contents
6October 5, 2006
Preliminary
18. Package Information.........................................................................................................294
Appendix A. Serial Flash Loader................................................................................................. 295
A.1 Interfaces...........................................................................................................................................295
A.1.1 UART.................................................................................................................................................295
A.1.2 SSI.....................................................................................................................................................295
A.2 Packet Handli ng..................... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ........................295
A.2.1 Packet Format ................ ....... ...... ....... ...... ....... ................... ...... ....... ...... ....... ...... ....... ........................296
A.2.2 Sending Pack ets....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ...... ....... ........................296
A.2.3 Receiving Pack ets .......... ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...... ....... ........................296
A.3 Commands ........................................................................................................................................296
A.3.1 COMMAND_PING (0x20)..................................................................................................................297
A.3.2 COMMAND_GET_STATUS (0x23)...................................................................................................297
A.3.3 COMMAND_DOWNLOAD (0x21)......................................................................................................297
A.3.4 COMMAND_ SEND_DA TA (0x2 4)...... ...... ....... ...... ....... ...... ...... ....... ................... ....... ...... ....... ...... .....297
A.3.5 COMMAND_RUN (0x22)...................................................................................................................298
A.3.6 COMMAND_RESET (0x25)...............................................................................................................298
Ordering and Contact Information.............................................................................................. 299
Ordering Information.......................................................................................................................................299
Development Ki t . ................... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ............................................299
Company Information .....................................................................................................................................299
Support Info rmati on ........ ....... ...... ....... ...... ....... ................... ....... ...... ...... ....... ...... ....... ...... ...............................300
LM3S101 Data Sheet
October 5, 2006 7
Preliminary
List of Figures
Figure 1-1. Stellaris High-Level Block Diagram ...........................................................................................21
Figure 1-2. LM3S101 Controller System-Level Block Diagram ...................................................................26
Figure 2-1. CPU Block Diagram .......... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....................28
Figure 2-2. TPIU Block Diagram..................................................................................................................29
Figure 5-1. JTAG Module Block Diagram....................................................................................................36
Figure 5-2. Test Access Port State Machine ...............................................................................................39
Figure 5-3. IDCODE Register Format..........................................................................................................43
Figure 5-4. BYPASS Register Format .........................................................................................................43
Figure 5-5. Boundary Scan Register Format...............................................................................................44
Figure 6-1. External Circuitry to Extend Reset.............................................................................................46
Figure 6-2. Main Clock Tree ........................................................................................................................49
Figure 7-1. Flash Block Diagram ......... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....................83
Figure 8-1. GPIO Module Block Diagram ....................................................................................................98
Figure 8-2. GPIO Port Block Diagram..........................................................................................................99
Figure 8-3. GPIODATA Write Example......................................................................................................100
Figure 8-4. GPIODATA Read Example .....................................................................................................100
Figure 9-1. GPTM Module Block Diagram.. ...... ....... ...... ....... ...... ...... .................... ...... ....... ...... ....... ...........136
Figure 9-2. 16-Bit Input Edge Count Mode Example.................................................................................140
Figure 9-3. 16-Bit Input Edge Time Mode Example...................................................................................141
Figure 9-4. 16-Bit PWM Mode Example ....................................................................................................142
Figure 10-1. WDT Module Block Diagram...................................................................................................167
Figure 11-1. UART Module Block Diagram..................................................................................................191
Figure 11-2. UART Character Frame...........................................................................................................192
Figure 12-1. SSI Module Block Diagram......................................................................................................226
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer)..........................................................228
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) .................................................229
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0..........................................230
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0..................................230
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1...........................................................231
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0...............................231
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0.......................232
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1...........................................................232
Figure 12-10. MICROWIRE Frame Format (Single Frame)...........................................................................233
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ...............................................................234
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................235
Figure 13-1. Analog Comparator Module Block Diagram............................................................................261
Figure 13-2. Structure of Comparator Unit...................................................................................................262
Figure 13-3. Comparator Inte rnal Refere nce Structure ... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... .....263
Figure 14-1. Pin Connection Diagram..........................................................................................................273
Figure 17-1. Load Conditions.......................................................................................................................285
Figure 17-2. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement................287
Figure 17-3. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer...................... ...........288
Figure 17-4. SSI Timing for SPI Frame Format (FRF=00), with SPH=1......................................................288
Figure 17-5. JTAG Test Clock Input Timing.................................................................................................290
Figure 17-6. JTAG Test Access Port (TAP) Timing.....................................................................................290
Figure 17-7. JTAG TRST Timing.................................................................................................................290
List of Figures
8October 5, 2006
Preliminary
Figure 17-8. External Reset Timing (RST)...................................................................................................292
Figure 17-9. Power-On Reset Timing..........................................................................................................292
Figure 17-10. Brown-Out Reset Timing.........................................................................................................292
Figure 17-11. Software Reset Timing................... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ..................292
Figure 17-12. Watchdog Reset Timing..........................................................................................................293
Figure 17-13. LDO Reset Timing...................................................................................................................293
Figure 18-1. 28-Pin SOIC Package .............................................................................................................294
LM3S101 Data Sheet
October 5, 2006 9
Preliminary
List of Tables
Table 0-1. Documentation Conventions .....................................................................................................15
Table 3-1. Memory Map..............................................................................................................................30
Table 4-1. Exception Types........................................................................................................................32
Table 4-2. Interrupts ...................................................................................................................................33
Table 5-1. JTAG Port Pins Reset State......................................................................................................37
Table 5-2. JTAG Instruction Register Commands......................................................................................41
Table 6-1. System Control Register Map....................................................................................................51
Table 6-2. VADJ to VOUT ..........................................................................................................................62
Table 6-3. PLL Mode Control......................................................................................................................73
Table 6-4. Default Crystal Field Values and PLL Programming.................................................................74
Table 7-1. Flash Protection Policy Combinations.......................................................................................85
Table 7 -2 . Flash Regi ster Map ..... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....................86
Table 8-1. GPIO Pad Configuration Examples ........................................................................................101
Table 8-2. GPIO Interrupt Configuration Example ...................................................................................102
Table 8-3. GPIO Register Map.................................................................................................................103
Table 9-1. 16-Bit Timer With Prescaler Configurations ............................................................................139
Table 9 -2 . GPTM Regist er Map................. ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ..................145
Table 1 0-1. WDT Register Map................... ...... .................... ...... ...... ....... ...... ....... ...... ....... ...... ..................168
Table 11-1. UART Register Map ................................................................................................................195
Table 12-1. SSI Register Map ....................................................................................................................236
Table 13-1. Comparator 0 Operating Modes..............................................................................................262
Table 13-2. Comparator 1 Operating Modes..............................................................................................262
Table 13-3. Internal Reference Voltage and ACREFCTL Field Values......................................................263
Table 13-4. Analog Comparator Register Map...........................................................................................265
Table 15-1. Signals by Pin Number............................................................................................................274
Table 15-2. Signals by Signal Name ..........................................................................................................276
Table 15-3. Signals by Function, Except for GPIO.....................................................................................278
Table 15-4. GPIO Pins and Alternate Functions.........................................................................................279
Table 16-1. Temperature Characteristics...................................................................................................281
Table 16-2. Thermal Characteristics...........................................................................................................281
Table 17-1. Maximum Ratings....................................................................................................................282
Table 17-2. Recommended DC Operating Conditions...............................................................................282
Table 17-3. LDO Regulator Characteristics................................................................................................283
Table 17-4. Power Specifications...............................................................................................................284
Table 1 7-5. Flash Memory Characteri stics........ ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....... ...........284
Table 17-6. Phase Locked Loop (PLL) Characteristics..............................................................................285
Table 17-7. Clock Characteristics...............................................................................................................285
Table 17-8. Analog Comparator Characteristics.........................................................................................286
Table 17-9. Analog Comparator Voltage Reference Characteristics..........................................................286
Table 17-10. SSI Characteristics..................................................................................................................287
Table 17-11. JTAG Characteristics...............................................................................................................289
Table 17-12. GPIO Characteristics...............................................................................................................291
Table 1 7-13. Res et Characteri stic s ........ ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ...............................291
List of Registers
10 October 5, 2006
Preliminary
List of Registers
Syste m Co n tr o l . .. ...... ... ...... .. ... ...... .. ....... .. ... ...... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... .. .. ....... .. ................ 45
Register 1: Device Identification 0 (DID0), offset 0x000..............................................................................53
Register 2: Device Identification 1 (DID1), offset 0x004..............................................................................54
Register 3: Device Capabilities 0 (DC0), offset 0x008.................................................................................56
Register 4: Device Capabilities 1 (DC1), offset 0x010.................................................................................57
Register 5: Device Capabilities 2 (DC2), offset 0x014.................................................................................58
Register 6: Device Capabilities 3 (DC3), offset 0x018.................................................................................59
Register 7: Device Capabilities 4 (DC4), offset 0x01C................................................................................60
Register 8: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030........................................61
Register 9: LDO Power Control (LDOPCTL), offset 0x034..........................................................................62
Register 10: Software Reset Control 0 (SRCR0), offset 0x040.....................................................................63
Register 11: Software Reset Control 1 (SRCR1), offset 0x044.....................................................................64
Register 12: Software Reset Control 2 (SRCR2), offset 0x048.....................................................................65
Register 13: Raw Interrupt Status (RIS), offset 0x050...................................................................................66
Register 14: Interrupt Mask Control (IMC), offset 0x054 ...............................................................................67
Register 15: Masked Interrupt Status and Clear (MISC), offset 0x058..........................................................69
Register 16: Reset Cause (RESC), offset 0x05C................... ...... ...... ....... ...... ....... ...... ....... ................... .......70
Register 17: Run-Mode Clock Configuration (RCC), offset 0x060.................................................................71
Register 18: XTAL to PLL Translation (PLLCFG), offset 0x064 ....................................................................75
Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100.......................................................76
Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110.....................................................76
Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120...........................................76
Register 22: Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104.......................................................77
Register 23: Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114.....................................................77
Register 24: Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124...........................................77
Register 25: Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108.......................................................79
Register 26: Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118.....................................................79
Register 27: Deep-Sleep-Mode Clock Gating Control 2 (DCGC2), offset 0x128...........................................79
Register 28: Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144..............................................80
Register 29: Clock Verification Clear (CLKVCLR), offset 0x150....................................................................81
Register 30: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160.......................................82
Inte rn a l Me mo r y.... .. ....... .. ....... .. .. ....... .. ....... .. .. ....... .. ...... ... .. ...... ... ...... .. ... ...... ... ...... .. ... .................... 83
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x1 30.............. .................... ...... .......88
Register 2: Flash Memory Protection Prog ram Enab le (FMPP E), offset 0x13 4................ ...... ....... ...... .......8 8
Register 3: USec Reload (USECRL), offse t 0x14 0............... ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... .......89
Register 4: Flash Memory Address (FMA), offset 0x000.............................................................................90
Register 5: Flash Memory Data (FMD), offset 0x004 .... ....... ...... ...... .................... ...... ....... ...... ....... ...... .......91
Register 6: Flash Memory Control (FMC), offset 0x008 ..............................................................................92
Register 7: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C...................................................94
Register 8: Flash Controller Interrupt Mask (FCIM), offset 0x010 ...............................................................95
Register 9: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014...........................96
General-Purpose Input/Outputs (GPIOs).................... ..................................................... .............97
Register 1: GPIO Data (GPIODATA), offset 0x000 ...................................................................................105
Register 2: GPIO Direction (GPIODIR), offset 0x400................................................................................106
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404.........................................................................107
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408..............................................................108
LM3S101 Data Sheet
October 5, 2006 11
Preliminary
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C.......................................................................109
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410..........................................................................110
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414..............................................................111
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418........................................................112
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C.......................................................................113
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420.................................................114
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500..............................................................115
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504..............................................................116
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508..............................................................117
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C...............................................................118
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ......................................................................119
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514..................................................................120
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518......................................................121
Register 18: GPIO Digital Input Enable (GPIODEN), offset 0x51C.............................................................122
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0...........................................123
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4...........................................124
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8...........................................125
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC...........................................126
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ...........................................127
Register 24: GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 ............................................128
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ...........................................129
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC...........................................130
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0..............................................131
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4..............................................132
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8..............................................133
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC..............................................134
General-Purpose Timers.............................................................................................................. 135
Register 1: GPTM Configuration (GPTMCFG), offset 0x000.....................................................................147
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004..................................................................148
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008..................................................................149
Register 4: GPTM Control (GPTMCTL), offset 0x00C...............................................................................150
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018....................................................................152
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..........................................................154
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020.....................................................155
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024.....................................................................156
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028......................................................157
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C......................................................158
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 .......................................................159
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .......................................................160
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038..............................................................161
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C.............................................................162
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040................................................163
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044................................................164
Register 17: GPTM TimerA (GPTMTAR), offset 0x048...............................................................................165
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ..............................................................................166
Watchdog Timer............................................................................................................................ 167
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ............................................................................170
Register 2: Watchdog Value (WDTVALUE), offset 0x004.........................................................................171
List of Registers
12 October 5, 2006
Preliminary
Register 3: Watchdog Control (WDTCTL), offset 0x008............................................................................172
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................173
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .......................................................174
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014..................................................175
Register 7: Watchdog Lock (WDTLOCK), offset 0xC00............................................................................176
Register 8: Watchdog Test (WDTTEST), offset 0x418..............................................................................177
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0.....................................178
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4.....................................179
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8.....................................180
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC....................................181
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0.....................................182
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4.....................................183
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8.....................................184
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ....................................185
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................186
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................187
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................188
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC......................................189
Universal Asynchronous Receiver/Transmitt er (UART) ................. ........... ........... .................. ..190
Register 1: UART Data (UARTDR), offset 0x000......................................................................................197
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004..............................199
Register 3: UART Flag (UARTFR), offset 0x018.......................................................................................201
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024.................................................203
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028................... ...... ....... ...... .....20 4
Register 6: UART Line Control (UARTLCRH), offset 0x02C.....................................................................205
Register 7: UART Control (UARTCTL), offset 0x030.................................................................................207
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034................................................208
Register 9: UART Interrupt Mask (UARTIM), offset 0x038........................................................................209
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................211
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ......................................................212
Register 12: UART Interrupt Clear (UARTICR), offset 0x044......................................................................213
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0..........................................214
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4..........................................215
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8..........................................216
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC.........................................217
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0..........................................218
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4..........................................219
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8..........................................220
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC.........................................221
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0.............................................222
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4.............................................223
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8.............................................224
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC............................................225
Synchronous Serial Interface (SSI)............................... .............................................................. 226
Register 1: SSI Control 0 (SSICR0), offset 0x000.....................................................................................238
Register 2: SSI Control 1 (SSICR1), offset 0x004.....................................................................................240
Register 3: SSI Data (SSIDR), offset 0x008..............................................................................................242
Register 4: SSI Status (SSISR), offset 0x00C...........................................................................................243
LM3S101 Data Sheet
October 5, 2006 13
Preliminary
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010.........................................................................244
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014................................................................................245
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018....................................................................246
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C..............................................................247
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020..............................................................................248
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0..................................................249
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4..................................................250
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8..................................................251
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC.................................................252
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0..................................................253
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4..................................................254
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8..................................................255
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC.................................................256
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0.....................................................257
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4.....................................................258
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8.....................................................259
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC....................................................260
Analo g C o mpa ra t o r s ......... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... .. .. ....... .. ....... .. .. .............. 261
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00........................................266
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04..............................................267
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08................................................268
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10............................269
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20............................................................270
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40............................................................270
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24.............................................................271
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44.............................................................271
Revision History
14 October 5, 2006
Preliminary
Revision Histor y
This table provides a summary of the document revisions.
Date Revision Description
March 27, 2006 00 Initial public release of LM3S101 and LM3S102 data sheets.
March 30, 2006 01 Second release of LM3S101 and LM3S102 data sheets. Includes the following
changes:
• Added timing data.
May 2006 02 Third release of LM3S101 and LM3S102 data sheets. Includes the following
changes:
• Added Ini tial iz ati on and Conf igu rati on sec ti on to Syst em C ontr ol cha pte r
• Renamed boot oscillator to internal oscillator
• Corrected reset value of DC1 in System Control Register Map (was correct on
register reference page)
• Corrected description of bits to set to enable PWM mode in timer
• Corrected WDTICR register offset (was correct in Register Map but not on
register reference page)
• Added Watchdog Test (WDTTEST) register
• Changed some bit and register names for consistency with DriverLib:
- Changed USESYS bit in RCC register to USESYSDIV
- Changed name of Capture bit fields in GPTMIMR, GPTMRIS, GPTMMIS,
and GPTMICR registers from C1bitname and C2bitname to CAbitname and
CBbitname
• Fixed minor style and edit issues
July 2006 03 Fourth release of LM3S101 and LM3S102 data sheets. Includes the following
changes:
• Added initialization and configuration content into PWM, Comparators, and
JTAG ch apters.
• Clarified that peripheral clock must be set before enabling peripherals in
“Initialization and Configuration” sect ions.
September 2006 04 Fifth release of LM3S101 data sheet. Includes the following changes:
• Updated the clocking examples in the I2C chapter.
• Added “5-V-tolerant” description for GPIOs to feature list, GPIO chapter, and
Electric al ch apter.
• Added maximum values for 20 MHz and 25 MHz parts to Table 9-1, “16-Bit
Timer With Prescaler Configurations” in the Timers chapter.
• Made the following changes in the System Control chapter:
- Updated field descriptions in the Run-Mode Clock Config uration
(RCC) register.
- Updated the internal oscillator clock speed.
- Added the Deep-Sleep Clock Configuration (DSLPCFG) register.
- Added bus fault information to the clock gating registers.
October 2006 05 Sixth release of LM3S101 data sheet. Includes the following changes:
• Added Serial Flash Loader usage information.
LM3S101 Data Sheet
October 5, 2006 15
Preliminary
About This Document
This data sheet provides reference information for the LM3S101 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation
CD or from the Luminary Micro web site at www.luminarymicro.com:
ARM® Cortex™-M3 Technical Reference Manual
CoreSight™ Design Kit Technical Reference Manual
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 0-1.
Table 0-1. Documentation Conventions
Notation Meaning
General Register Notation
REGISTER APB registers are indicated in uppercase bold. For example,
PBORCTL is the Po wer-On and Brown-Ou t Reset Cont rol registe r . I f
a register name cont a ins a lowerc ase n, it rep resent s mo re than one
register. For example, SRCRn represents any (or all) of the three
Software Reset Control registers: SRCR0, SRCR1, and SRCR2.
bit A single bit in a register.
bit field Two or more consec utive and related bits.
offs et 0xnnn A hexadecimal increment to a register’s address, relative to that
module’s base addres s as specified in Table 3-1, "Memory Map , " o n
page 30.
About This Document
16 October 5, 2006
Preliminary
Register NRegisters are numbered consecutively throughout the document to
aid in referencing them. The register number has no meaning to
software.
reserved Register bits marked reserved are reserv ed for future use. Reserved
bits return an indeterminate value, and should never be changed.
Only write a reserved bit with its current value.
yy:xx The range of register bits inclusive from xx to yy . For example, 31:15
means bits 15 through 31 in that register.
Register Bit/Field Types This value in the register bit diagram indicates whether software
running on the controller can change the value of the bit field.
RO Software can read this field. Always write the chip reset value.
R/W Software can read or write this field.
R/W1C Softwa re ca n read or write this field. A write of a 0 to a W1C bit does
not affect the bit value in the register. A write of a 1 clears the value
of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits
where the read operation provides the interrupt status and the write
of the r ead va lue cl ears o nly th e inte rrupt s bein g re ported at the t ime
the register was read.
W1C Software can write this field. A write of a 0 to a W1C bit does not
affect the bit value in the register. A write of a 1 clears the value of
the bit in the register; the remaining bits remain unchanged. A read
of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an
interrupt register.
WO Only a write by software is valid; a read of the register returns no
meaningful data.
Register Bit/Field Reset Va lue This value in the register bit diagram shows the bit/field value after
any reset, unless noted.
0 Bit cleared to 0 on chip reset.
1 Bit set to 1 on chip reset.
– Nondeterministic.
Pin/Signal Notation
[ ] Pin alternate function; a pin defaults to the signal without the
brackets.
pin Refers to the physical connection on the package.
signal Refers to the electrical signal encoding of a pin.
Table 0-1. Documentation Conventions
Notation Meaning
LM3S101 Data Sheet
October 5, 2006 17
Preliminary
assert a signal Change the value of the signal from the logi cally False state to the
logically True state. For active High signals, the asserted signal
value is 1 (High); for active Low signals, the asserted signal value is
0 (Low). The active polarity (High or Low) is defined by the signal
name (see SIGNAL and SIGNAL below).
deassert a signal Change the value of the signal from the logi cally True state to the
logically False state.
SIGNAL Signal names are in uppercase and in the Courier font. An overbar
on a signal nam e in dic ates that it is active Low. To assert SIGNAL is
to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL Signal names are in uppercase and in the Courier font. An active
High signal has no overbar. To assert SIGNAL is to drive it High; to
deassert SIGNAL is to drive it Low.
Numbers
X An uppercase X indicates any of several values is allowed, where X
can be any leg al pattern. For ex ample, a binary va lue of 0X00 can be
either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on.
0x Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is
the hexadecimal number FF. Binary numbers are indicated with a b
suffix, for example, 1011b. Decimal numbers are written without a
prefix or suffix.
Table 0-1. Documentation Conventions
Notation Meaning
Architectural Overview
18 October 5, 2006
Preliminary
1 Arch ite ctural Overview
The Luminary Micro Stellaris™ family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The LM3S101 controller in the Stellaris family offers the advantages of ARM’s widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user
community. Additionally, the controller uses ARM’s Thumb®-compatible Thumb-2 instruction set to
reduce memory requirements and, thereby, cost.
Luminary Micro offers a complete solution to get to market quickly, with a customer development
board, white papers and application notes, and a strong support, sales, and distributor network.
1.1 Product Features
The LM3S101 microcontroller includes the following product features:
32-Bit RISC Perfo rmanc e
–32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
–Thumb®-compatible Thumb-2-only instruction set processor core for high code density
–20-MHz operation
–Hardware-division and single-cycle-multiplication
–Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
–14 interrupts with eight priority levels
–Unaligned data access, enabling data to be efficiently packed into memory
–Atomic bit manipulation (bit-banding) delivers maximum memory utilization and
streamlined peripheral control
Internal Memory
–8 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined a nd managed flash-protection block
–2 KB single-cycle SRAM
General-Purpose Timers
–Two timers, each of which can be configured as a single 32-bit timer or as two 16-bit timers
–32-bit Timer modes:
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enab led stalling in periodic and one-shot mode when the controller asserts the
CPU H alt flag d uring debug
–16-bit Timer modes:
LM3S101 Data Sheet
October 5, 2006 19
Preliminary
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
–16-bit Input Capture modes:
• Input edge count capture
• Input edge time capture
–16-bit PWM mode:
• Simple PWM mode with software-programmable output inversion of the PWM signal
ARM FiRM-compliant Watchdog Timer
–32-bit down counter with a programmable load register
–Separate watchdog clock with an enable
–Programmable interrupt generation logic with interrupt masking
–Lock register protection from runaway software
–Reset genera tio n logic with an enable / disa ble
–User-enabled stalling when the controller asserts the CPU Halt flag during debug
Synchronous Serial Interface (SSI)
–Master or slave operation
–Programmable clock bit rate and prescale
–Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
–Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
–Programmable data frame size from 4 to 16 bits
–Internal loopback test mode for diagnostic/debug testing
UART
–Fully programmable 16C550-type UART
–Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt
service loading
–Programmable baud-rate generator with fractional divider
–Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
–FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
–Standard asynchronous communication bits for start, stop, and parity
–False-start-bit detection
–Line-break generation and detection
Analog Comparators
–Two independent integrated analog comparators
–Configurable for output to drive an output pin or generate an interrupt
Architectural Overview
20 October 5, 2006
Preliminary
–Compare external pin input to external pin input or to internal programmable voltage
reference
GPIOs
–2 to 18 GPIOs, depending on configuration
–5-V-tolerant input/outputs
–Programmable interrupt generation as either edge-triggered or level-sensitive
–Bit masking in both read and write operations through address lines
–Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open d rain enables
• Digital input enables
Power
–On-chip Low Drop-Out (LDO) voltage regulator , with programmable output user-adjustable
from 2.25 V to 2.75 V
–Low-power options on controller: Sleep and Deep-sleep modes
–Low-power options for peripherals: sof tware controls shutdown of individual peripherals
–User-enabled LDO unregulated voltage detection and automatic reset
–3.3-V supply brownout detection and reporting via interrupt or reset
Flexible Reset Sources
–Power-on reset (POR)
–Reset pin asse rt ion
–Brown-out (BOR) detector alerts to system power drops
–Software reset
–Watchdog timer reset
–Internal low drop-out (LDO) regulator output goes unregulated
Additional Features
–Six re se t sour c es
–Programmable clock source control
–Clock gating to individual peripherals for power savings
–IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
–Debug access via JTAG and Serial Wire interfaces
–Full JTAG boundary scan
Industrial -ran ge 28- pin RoHS- c omp liant SO IC packag e
1.2 Target Applications
Factory automation and control
LM3S101 Data Sheet
October 5, 2006 21
Preliminary
Industrial control power devices
Building and home automation
1.3 High-Level Block Diagram
Figure 1-1. Stellaris High-Level Block Diagram
DCode bus
APB Bridge SRAM
ICode bus
ARM Cortex-M3
Flash
(including Nested
Vectored Interrupt
Controller (NVIC))
Memory
Peripherals
LMI JTAG
Test Access Port
(TAP)
Controller
System
Control
& Clocks
Universal
Asynchronous
Receiver/
Transmitter
(UART)
Synchronous
Serial
Interface
(SSI)
General-Purpose
Timers
LM3S101
General-Purpose
Input/Outputs
(GPIOs)
System
Peripherals
Serial
Communications
Peripherals
Analog
Comparators
Analog
Peripherals
Watchdog
Timer
Peripheral Bus
Architectural Overview
22 October 5, 2006
Preliminary
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S101 microcontroller. The
chapter number in parenthesis indicates where that feature is discussed in detail. Ordering and
support information can be found in “Ordering and Contact Information” on page 299.
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (Section 2 on page 27)
All members of the Stellaris product family, including the LM3S101 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core
for a high-performance, low-cost platform that meets the needs of minimal memory
implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
Section 2, “ARM Cortex-M3 Processor Core,” on page 27 provides an overview of the ARM core;
the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 Nested V ectored Interrupt Controller (NVIC)
The LM3S101 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stor ed to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed
without the overhead of state saving and restoration. Software can set eight priority levels on 7
exceptions (system handlers) and 14 interrupts.
Section 4, “Interrupts,” on page 32 provides an overview of the NVIC controller and the interrupt
map. Exce ptions and interrupts are detailed in the AR M® Cortex ™-M3 Techn ic al Refe renc e
Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S101 controller features Pulse Width Modulation (PWM)
outputs.
1.4.2.1 PWM (“16-Bit PWM Mode” on page 144)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power
supplie s a nd moto r contr ol .
On the LM3S101, PWM motion control functionality can be achieved through the motion control
features of the general-purpose timers (using the CCP pins).
The General-Purpose Timer Module’s CCP (Capture Compare PWM) pins are software
programmable to support a simple PWM mode with a software-programmable output inversion of
the PWM signal.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S101 controller offers two analog comparators.
1.4.3.1 Analog Comparators (Section 13 on page 261)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
LM3S101 Data Sheet
October 5, 2006 23
Preliminary
The LM3S101 controller provides two independent integrated analog comparators that can be
configured to drive an output or generate an interrupt.
A comparator can compare a test voltage against any one of these voltages:
An individual external reference voltage
A shared single external reference voltage
A shared inte rn al refer enc e vol tage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to
start capturing a sample sequence. The interrupt generation logic is separate.
1.4.4 Serial Communications Peripherals
The LM3S101 controller supports both asynchronous and synchronous serial communications
with one fully programmable 16C550-type UART and SSI serial communications.
1.4.4.1 UART (Section 1 1 on page 190)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S101 controller includes one fully programmable 16C550-type UART that supports data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
registe r co mpatibl e.)
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are
asserted and are unmasked.
1.4.4.2 SSI (Section 12 on page 226)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The Stellaris SSI module provides the functionality for synchronous serial communications with
peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI
synchronous serial interface frame formats. The size of the data frame is also configurable, and
can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module’s input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (Section 8 on page 97)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
Architectural Overview
24 October 5, 2006
Preliminary
The Stellaris GPIO module is composed of three physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-T ime Microcontrollers specification) and supports 2 to 18 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see Table 15-4 on
page 279 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 T wo Programmable Timers (Section 9 on page 135)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris General-Purpose Timer Module (GPTM) contains two GPTM blocks. Each GPTM
block provides two 16-bit timer/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock
(RTC).
When configured in 32-bit mode, a timer can run as a one-shot timer, periodic timer, or Real-Time
Clock (RTC). When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (Section 10 on page 167)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first
time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has
been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
1.4.6 Memory Peripherals
The Stellaris controllers offer both SRAM and Flash memory.
1.4.6.1 SRAM (Section 7.2.1 on page 83)
The LM3S101 static random access memory (SRAM) controller supports 2 KB SRAM. The
internal SRAM of the Stellaris devices is located at address 0x20000000 of the device memory
map. To reduce the numb er of time consuming read-modify-write (RMW) operation s, ARM has
introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled
processor, certain regions in the memory map (SRAM and peripheral space) can use address
aliases to access individual bits in a single, atomic operation.
1.4.6.2 Flash (Section 7.2.2 on page 84)
The LM3S101 Flash controller supports 8 KB of flash memory. The flash is organized as a set of
1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of
code protection. Read-only blocks cannot be erased or programmed, protecting the contents of
those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can
LM3S101 Data Sheet
October 5, 2006 25
Preliminary
only be read by the controller instruction fetch mechanism, protecting the contents of those blocks
from being read by either the controller or by a debugger.
1.4.7 Additional Features
1.4.7.1 Memory Map (Section 3 on page 30)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S101 controller can be found on page 30. Register addresses are given as a hexadecimal
increment, relative to the module’s base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.7.2 JT AG T AP Controller (Section 5 on page 35)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The LMI JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is
implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions
sele ct t he ARM TDO output while LMI JTAG instructions select the LMI TDO outputs. Th e
multiplexer is controlled by the LMI JTAG controller, which has comprehensive programming for
the ARM, LMI, and unimplemented JTAG instructions.
1.4.7.3 System Control and Clocks (Section 6 on page 45)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
Section 14, “Pin Diagram,” on page 273
Section 15, “Signal Tables,” on page 274
Section 16, “Operating Characteristics,” on page 281
Section 17, “Electrical Characteristics,” on page 282
Section 18, “Package Information,” on page 294
Architectural Overview
26 October 5, 2006
Preliminary
1.5 System Block Diagram
Figure 1-2. L M 3S1 01 Contr ol ler Sys tem- Level Block Diagram
Flash
SRAM
APB Bridge
ICode
DCode
GND
VDD_3.3V
LDO VDD_2.5V
LDO
System
Control
& Clocks
OSC0
OSC1
RST
PLL
Watchdog
Timer
POR
BOR
IOSC
Debug
ARM Cortex-M3
NVIC
CM3Core
Bus
Peripheral Bus
UART0
GPIO Port B
PA1/U0Tx
PA0/U0Rx
GPIO Port A
SSI
PA3/SSIFss
PA2/SSIClk
PA5/SSITx
PA4/SSIRx
GPIO Port C
JTAG
SWD/SWO
PC1/TMS/SWDIO
PC0/TCK/SWCLK
PC3/TDO/SWO
PC2/TDI
PB1/32KHz
PB0/CCP0
PB3
PB2
PB5/C0o/C1-
PB4/C0-
PB6/C0+
GP Timer1
GP Timer0
PB7/TRST
Analog
Comparators
(2 KB)
(8 KB)
(20 MHz)
LM3S101LM3S101
LM3S101 Data Sheet
October 5, 2006 27
Preliminary
2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
Compact core.
Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.
Exceptional interrupt handling, by implementing the register manipulations required for
handling an interrupt in hardware.
Full-featured debug solution with a:
–Serial Wire JTAG Debug Port (SWJ-DP)
–Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
–Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
–Instrumentation Trace Macrocell (ITM) for support of printf style debugging
–Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit
computing to cost-sensitive embedded microcontroller applications, such as factory automation
and control, indu str i al con trol powe r devic es , and b uil di ng and hom e autom ati on.
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3
Technical Reference Manual. For information on SWJ-DP, see the CoreSight™ Design Kit
Technical Reference Manual.
ARM Cortex-M3 Processor Core
28 October 5, 2006
Preliminary
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
2.2 Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of
an ARM Cortex-M3 in detail. However, these features differ based on the
implementation. This section describes the Stellaris im plementation.
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1. As noted in
the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible
in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1 Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM
CoreSight™-compliant Serial Wire JT AG Debug Port (SWJ-DP) interface. This means Chapter 12,
“Debug Port,” of the ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris
devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
P rivat e Pe ri phe ral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace M ac rocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
P at c h and
Breakpoint
Ad v. High-
Pe r f. Bu s
Access Port
Nested
Vectored
Interrupt
Controller
S e ri al Wire JTAG
D e bug P ort
Bus
Matrix
A dv. Peri ph eral
Bus I-co de bus
D-code bus
System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
LM3S101 Data Sheet
October 5, 2006 29
Preliminary
2.2. 2 E mbedded Trace Macroc ell (E TM)
ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2. This is
similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual,
however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
2.2.4 ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
2.2.5 Memory Protection Unit (MPU)
The LM3S101 controller does not include the memory protection unit (MPU) of the ARM Cortex-
M3.
2.2.6 Nested Vectored Interrupt Controller (NVIC)
2.2.6.1 Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of
interrupts and interrupt priorities. The LM3S101 microcontroller supports 14 interrupts with eight
priority levels.
2.2.6.2 SysTick Calibration V alue Registers
The SysTick Calibration Value register is not implemented.
ATB
Interface Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
Memory Map
30 October 5, 2006
Preliminary
3Memory Map
The memory map for the LM3S101 is provided in Table 3-1. In this manual, register addresses are
given as a hexadecimal increment, relative to the module’s base address as shown in the memory
map. See al so Ch apte r 4, “ Memor y Ma p” in t he ARM® Cortex™-M3 Technical Reference Manual.
Table 3-1. Memory Map (Sheet 1 of 2)
Start End Description For details on
registers, see ...
Memory
0x00000000 0x00001FFF On-chip flash page 87
0x00002000 0x1FFFFFFF Reserveda
0x20000000 0x200003FF Bit-banded on-chip SRAM -
0x20000400 0x200FFFFF Reserveda-
0x22000000 0x2200FFFF Bit-band alias of 0x 20000000 through 0x200003FF -
0x22010000 0x23FFFFFF Reserveda-
FiRM Peripherals
0x40000000 0x40000FFF Watchdog timer page 169
0x4000 1000 0x40003FFF Reserved for three ad ditional watchdog tim ers (per FiRM
specification)a-
0x40004000 0x40004FFF GPIO Port A page 104
0x40005000 0x40005FFF GPIO Port B page 104
0x40006000 0x40006FFF GPIO Port C page 104
0x40007000 0x40007FFF Reserved for additional GPIO port (per FiRM
specification)a-
0x40008000 0x40008FFF SSI page 237
0x40009000 0x4000BFFF Reserved for three additional SSIs (per FiRM
specification)a-
0x4000C000 0x4000CFFF UART0 page 196
0x4000D000 0x4000FFFF Reserved for addi tional UART (per FiRM specification)a-
0x40010000 0x4001FFFF Reserved for future FiRM peripheralsa-
Peripherals
0x40020000 0x40023FFF Reserveda-
0x40024000 0x40027FFF Reserveda-
0x40028000 0x4002BFFF Reserveda-
0x4002C000 0x4002FFFF Reserveda-
LM3S101 Data Sheet
October 5, 2006 31
Preliminary
0x40030000 0x40030FFF Timer0 page 146
0x40031000 0x40031FFF Timer1 page 146
0x40032000 0x40037FFF Reserveda-
0x40038000 0x4003BFFF Reserveda-
0x4003C000 0x4003CFFF Analog comparators page 265
0x4003D000 0x400FCFFF Reserveda-
0x400FD000 0x400FDFFF Flash control page 87
0x400FE000 0x400FFFFF System control page 52
0x40100000 0x41FFFFFF Reserveda-
0x42000000 0x43FFFFFF Bit-band alias of 0x40000000 through 0x 400FFFFF -
0x44000000 0xDFFFFFFF Reserveda-
Private Periph er al Bus
0xE0000000 0xE0000FFF Instrumentation Trace Macrocell (ITM) ARM® Cortex™-M3
Technical Reference
Manual
0xE0001000 0xE0001FFF Data Watchpoint and Trace (DWT)
0xE0002000 0xE0002FFF Flash Patch and Breakpoint (FPB)
0xE0003000 0xE000DFFF Reserveda
0xE000E000 0xE000EFFF Nested Vectored Interrupt Controller (NVIC)
0xE000F000 0xE003FFFF Reserveda
0xE0040000 0xE0040FFF Trace Port Interface Unit (TPIU)
0xE0041000 0xE0041FFF Reserveda-
0xE0042000 0xE00FFFFF Reserveda-
0xE0100000 0xFFFFFFFF Reserved for vendor peripheralsa-
a. All reserved space returns a bus fault when read or written.
Table 3-1. Memory Map (Sheet 2 of 2)
Start End Description For details on
registers, see ...
Interrupts
32 October 5, 2006
Preliminary
4Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions. All exceptions are handled in Handler Mode. The processor state is
automatically stored to the stack on an exception, and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving,
which enables efficient interrupt entry. The processor supports tail-chaining, which enables
back-to-back interrupts to be performed without the overhead of state saving and restoration.
Table 4-1 lists all the exceptions. Software can set eight priority levels on seven of these
exceptions (system handlers) as well as on 14 interrupts (listed in Table 4-2). Priorities on the
system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled
through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority
registers. You can also group priorities by splitting priority levels into pre-emption priorities and
subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and
a Hard Fault. Note that 0 is the default priority for all the settable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower the
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Table 4-1. Exception Types
Exception Type Position PriorityaDescription
-0-S t ack top is loa ded from first e ntry of v ector t abl e on
reset.
Reset 1 -3 (highest) Invoked on power up and warm reset. On first
instruction, drops to lowest priority (and then is
called the base level of activation). This is
asynchronous.
Non-Maskable
Interrupt (NMI) 2-2 Cannot be stopped or preempted by any exception
but reset. This is asynchronous.
An NMI is only producible by software, using the
NVIC Interrupt Control State register.
Hard Fault 3 -1 All classes of Fault, when the fault cannot activate
due to priority or the configurable fault handler has
been disabled. This is synchronous.
Memory
Management 4 settable MPU mismatch, including access violation and no
match. This is synchronous.
The priority of this exception can be changed.
Bus Fault 5 settable Pre-fetch fault, memory access fault, and other
address/m emory relat ed fau lts . This is sync hronou s
when precise and asynchronous when imprecise.
You can enable or disable this fault.
LM3S101 Data Sheet
October 5, 2006 33
Preliminary
Usage Fault 6 sett abl e Usage fault , such as und efined instru ct ion ex ecuted
or illegal state transition attempt. This is
synchronous.
-7-10 -Reserved.
SVCall 11 settable System service call with SVC instruction. This is
synchronous.
Debug Monitor 12 settable Debug monitor (when not halting). This is
synchronous, but only active when enabled. It does
not activate if lower priority than the cu rrent
activation.
-13 -Reserved.
PendSV 14 settable Pendable request for system service. This is
asynchronous and only pended by software.
SysTick 15 settable System tick timer has fired. This is asynchronous.
Interrupts 16 and
above sett able Asserted fro m outs ide the ARM Cortex-M 3 core and
fed through the NVIC (prioritized). These are all
asynchronous. Table 4-2 lists the interrupts on the
LM3S101 controller.
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Interrupt
(Bit in Interrupt Registers) Description
0 GPIO Port A
1 GPIO Port B
2 GPIO Port C
3-4 Reserved
5UART0
6 Reserved
7 SSI
8-17 Reserved
18 Watchdog timer
19 Timer0a
20 Timer0b
21 Timer1a
22 Timer1b
Table 4-1. Exception Types (Continued)
Exception Type Position PriorityaDescription
Interrupts
34 October 5, 2006
Preliminary
23-24 Reserved
25 Analog Comparator 0
26 Analog Comparator 1
27 Reserved
28 System Control
29 Flash Control
30-31 Reserved
Table 4-2. Interrupts (Continued)
Interrupt
(Bit in Interrupt Registers) Description
LM3S101 Data Sheet
October 5, 2006 35
Preliminary
5 JTAG Int erface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial
interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data
Registers (DR) can be used to test the interconnections of assembled printed circuit boards and
obtain manufacturing information on the components. The JTAG Port also provides a means of
accessing and controlling design-for-test features such as I/O pin observation and control, scan
testing, and debugging.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The LMI JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is
implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions
sele ct t he ARM TDO output while LMI JTAG instructions select the LMI TDO outputs. Th e
multiplexer is controlled by the LMI JTAG controller, which has comprehensive programming for
the ARM, LMI, and unimplemented JTAG instructions.
The JTAG module has the following features:
IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
Four-bit Instruction Register (IR) chain for storing JTAG instructions
IEEE standard instructions:
–BYPASS instruction
–IDCODE instruction
–SAMPLE/PRELOAD instruction
–EXTEST instruction
–INTEST instruction
ARM additional instructions:
–APACC instruction
–DPACC instruction
–ABORT instruction
Integrated ARM Serial Wire Debug (SWD)
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
JTAG Interface
36 October 5, 2006
Preliminary
5.1 Block Diagram
Figure 5-1. JTAG Module Block Diagram
5.2 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1. The JTAG module is
composed of the Test Access Port (TAP) controller and serial shift chains with parallel update
registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS
inputs. The current state of the TAP controller depends on the current value of TRST and the
sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines
when the serial shift chains capture new data, shift data from TDI towards TDO, and update the
parallel load registers. The current state of the TAP controller also determines whether the
Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register
(IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel
load register determines which DR chain is captured, shifted, or updated during the sequencing of
the TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-2 on page 41 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 289 for JTAG timing diagrams.
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TRST
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
LM3S101 Data Sheet
October 5, 2006 37
Preliminary
5.2.1 JTAG Interf ace Pins
The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and
their associated reset state are given in Table 5-1. Detailed information on each pin follows.
5.2.1.1 T est Reset Input (TRST)
The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG
TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to
the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller
enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default
instruction, IDCODE.
By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the
pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains
enabled on PB7/TRST; otherwise JTAG communication could be lost.
5.2.1.2 T est Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks. In addition, it ensures that multiple JTAG TAP
controllers that are daisy-chained together can synchronously communicate serial test data
between components. During normal operation, TCK is driven by a free-running clock with a
nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of
time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in
the JTAG Instruction and Data Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no
clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down
resistors can be turned off to save internal power as long as the TCK pin is constantly being driven
by an external source.
5.2.1.3 T est Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is
entered. Bec au se the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1
expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can
be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state
machine can be seen in its entirety in Figure 5-2 on page 39.
Table 5-1. JTAG Port Pins Reset State
Pin Name Data
Direction Internal
Pull-Up Internal
Pull-Down Drive
Strength Drive Value
TRST Input Enabled Disabled N/A N/A
TCK Input Enabled Disabled N/A N/A
TMS Input Enabled Disabled N/A N/A
TDI Input Enabled Disabled N/A N/A
TDO Output Enabled Disabled 2-mA driver High-Z
JTAG Interface
38 October 5, 2006
Preliminary
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the
pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains
enabled on PC1/TMS; otherwise JTAG communication could be lost.
5.2.1.4 T est Dat a Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on
the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the
falling edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the
pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains
enabled on PC2/TDI; otherwise JTAG communication could be lost.
5.2.1.5 T est Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is
placed in an inactive drive state when not actively shifting out data. Because TDO can be
connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard
1149.1 expects the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the
pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up
and pull-down resistors can be turned off to save internal power if a High-Z output value is
acceptable during certain TAP controller states.
5.2.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2 on page 39. The TAP controller
state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR)
or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module
to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed
information on the function of the TAP controller and the operations that occur in each state,
please refer to IEEE Standard 1149.1.
LM3S101 Data Sheet
October 5, 2006 39
Preliminary
Figure 5-2. Test Access Port State Machine
5.2.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial
shift register chain samples specific information during the TAP controller’s CAPTURE states and
allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the
sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift
registe r on TDI. This new data is stored in the parallel load register during the TAP controller’s
UPDATE states. Each of the shift registers is discussed in detail in “Shift Registers” on page 39.
5.2.4 Operational Considerations
There are certain operational considerations when using the JTAG module. Because the JTAG
pins can be programmed to be GPIOs, board configuration and reset conditions on these pins
must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes requires clarification.
5.2.4.1 GPIO Functionality
When the controller is reset with either a POR or RST, the JTAG port pins default to their JTAG
configurations. The default configuration includes enabling the pull-up resistors (setting GPIOPUR
Test Logic
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
111
11
1
11
11
11
11
1100
00
00
00
00
00
00
0
0
JTAG Interface
40 October 5, 2006
Preliminary
to 1 for PB7 and PC[3:0]) and enabling the alternate hardware function (setting GPIOAFSEL to 1
for PB7 and PC[3:0]) on the JTAG pins.
It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and
PC[3:0]in the GPIOAFSEL register. If the user does not require the JTAG port for debugging or
board-level testing, this provides five more GPIOs for use in the design.
Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external
pull-down resistors connected to both of them at the same time. If both pins are pulled Low during
reset, the controller has unpredictable behavior. If this happens, remove one or both of the
pull-down resistors, and apply RST or power-cycle the part
In addition, it is possible to create a software s equence that prevents the debugger from connecting
to the Stellaris microcontroller. If the program code loaded into flash immediately changes the
JTAG pins to their GPIO functionality, the debugger does not have enough time to connect and
halt the controller before the JTAG pin functionality switches. This locks the debugger out of the
part. This can be avoided with a software routine that restores JTAG fu nctionality using an
external trigger.
5.2.4.2 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the
SWD session begins.
The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP
controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR,
Run Test Idle, Select DR, Select IR, Capture IR, Exit1 IR, Update IR, Run Test Idle, Select DR,
Select IR, and Test-Logic-Reset states.
Stepping through the JTAG TAP Instruction Register (IR) load sequences of the TAP state
machine twice without shifting in a new instruction enables the SWD interface and disables the
JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where
the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low
probability of this sequence occuring during normal operation of the TAP controller, it should not
affect normal performance of the JTAG interface.
5.3 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JT AG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the
user application changes these pins to their GPIO function, they must be configured back to their
JTAG functionality before JTAG communication can be restored. This is done by enabling the five
JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register.
LM3S101 Data Sheet
October 5, 2006 41
Preliminary
5.4 Register Descriptions
There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The
registers within the JTAG controller are all accessed serially through the TAP Controller. The
registers can be broken down into two main categories: Instruction Registers and Data Registers.
5.4.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register
connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct
states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the
chain and updated, they are interpreted as the current instruction. The decode of the Instruction
Register bits is shown in Table 5-2. A detailed explanation of each instruction, along with its
associated Data Register, follows.
5.4.1.1 EXTEST Instruction
The EXTEST instruction does not have an associated Data Register chain. The EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction
Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and
output enables are used to drive the GPIO pads rather than the signals coming from the core. This
allows tests to be developed that drive known values out of the controller, which can be used to
verify connectivity.
5.4.1.2 INTEST Instruction
The INTEST instruction does not have an associated Data Register chain. The INTEST instruction
uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/
PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the
preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. This allows
Table 5-2. JTAG Instruction Register Commands
IR[3:0] Instruction Description
0000 EXTEST Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
0001 INTEST Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
0010 SAMPLE / PRELOAD Captu res the c urren t I/O val ue s an d sh if t s the sam pl ed v alu es out of the
Boundary Scan Chain while new preload data is shifted in.
1000 ABORT Shifts data into the ARM Debug Port Abort Register.
1010 DPACC Shifts data into and out of the ARM DP Access Register.
1011 APACC Shifts data into and out of the ARM AC Access Register.
1110 IDCODE Loads manufacturing information defined by the IEEE Standard 1149.1
into the IDCODE chain and shifts it out.
1111 BYPASS Connects TDI to TDO through a single Shift Register chain.
All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always
connected to TDO.
JTAG Interface
42 October 5, 2006
Preliminary
tests to be developed that drive known values into the controller, which can be used for testing. It
is important to note that although the RST input pin is on the Boundary Scan Data Register chain,
it is only observable.
5.4.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and
preloads new test data. Each GPIO pad has an associated input, output, and output enable signal.
When the TAP controller enters the Capture DR state during this instruction, the input, output, and
output-enable signals to each of the GPIO pads are captured. These samples are serially shifted
out of TDO while the TAP controller is in the Shift DR state and can be used for observation or
comparison in variou s tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the
Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register
from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is
saved in the parallel load registers when the TAP controller enters the Update DR state. This
update of the parallel load register preloads data into the Boundary Scan Data Register that is
associated with each input, output, and output enable. This preloaded data can be used with the
EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary
Scan Data Register” on page 43 for more information.
5.4.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or
initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 44 for
more information.
5.4.1.5 DP ACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. Please see “DPACC
Data Register” on page 44 for more information.
5.4.1.6 AP ACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
Please se e “APACC Data Register” on page 44 for more information .
5.4.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure their input and output data streams. IDCODE is the default instruction that is loaded into
the JTAG Instruction Register when a power-on- reset (POR) is asserted, TRST is asserted, or the
Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 43 for more
information.
LM3S101 Data Sheet
October 5, 2006 43
Preliminary
5.4.1.8 BYP ASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO
ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test
efficiency by allowing components that are not needed for a specific test to be bypassed in the
JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data
Register” on page 43 for more information.
5.4. 2 Dat a Re gist ers
The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary
Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is
discussed in the following sections.
5.4.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE S t andard 1149.1 is shown in
Figure 5-3. The standard requires that every JTAG-compliant device implement either the
IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This allows auto configuration test tools to determine which instruction is the default
instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly, and
program development and debug. To facilitate the use of auto-configuration debug tools, the
IDCODE instruction outputs a value of 0x1BA00477. This value indicates an ARM Cortex-M3,
Version 1 processor. This allows the debuggers to automatically configure themselves to work
correctly with the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
5.4.2.2 BYP ASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4. The standard requires that every JTAG-compliant device implement either the
BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This allows auto configuration test tools to determine which instruction is the default
instruction.
Figure 5-4. BYPASS Register Format
5.4.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5. Each GPIO pin, in a
counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data
Register. Each GPIO pin has three associated digital signals that are included in the chain. These
1Version Part Number Manufacturer ID
011112272831 TDOTDI
0
0TDOTDI
JTAG Interface
44 October 5, 2006
Preliminary
signals are input, output, and output enable, and are arranged in that order as can be seen in the
figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because
the reset pin is always an input, only the input signal is included in the Data Register chain.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the
chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture
DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan
chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use
with the EXTEST and INTEST instructions. These instructions either force data out of the
controller, with the EXTEST instruction, or into the controller, with the INTEST instruction.
Figure 5-5. Boundary Scan Register Format
For detailed information on the order of the input, output, and output enable bits for each of the
GPIO ports, please refer to the Stellaris Family Boundary Scan Description Language (BSDL)
files, downloadable from www.luminarymicro.com.
5.4.2.4 AP ACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.5 DP ACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.4.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
OTDO
TDI O
I
NE
U
T
O
O
I
NE
U
TO
O
I
NE
U
TO
O
I
NE
U
T
I
N
... ...
RST
GPIO PB 6 GPIO m GPIO m+1 GPIO n
LM3S101 Data Sheet
October 5, 2006 45
Preliminary
6 System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
6.1 Functional Description
The System Control module provides the following capabilities:
Device identification, see page 45
Local control, such as reset (see page 45), power (see page 48) and clock control (see
page 48)
System control (Run, Sleep, and Deep-Sleep modes), see page 50
6.1.1 Device Identification
Seven read-only registers provide software with information on the microcontroller, such as
version, part number, SRAM size, Flash size, and other features. See the DID0, DID1 and
DC0-DC4 registers starting on page 53.
6.1.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.1.2.1 Reset Sources
The controller has six sources of reset:
1. External reset input pin (RST) assertion, see page 45.
2. Power-on reset (POR), see page 46.
3. Internal brown-out (BOR) detector, see page 46.
4. Software-initiated reset (with the software reset registers), see page 47.
5. A watchdog timer reset condition violation, see page 47.
6. Internal low drop-out (LDO) regulator output, see page 48.
After a reset, the Reset Cause (RESC) register (see page 70) is set with the reset cause. The bits
in this register are sticky and maintain their state across multiple reset sequences, except when an
external reset is the cause, and then all the other bits in the RESC register are cleared.
Note: The main oscillator is used for external resets and power-on resets; the internal oscillator
is used during the internal process by internal reset and clock verification circuitry.
6.1.2.2 RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals
except the JTAG TAP controller (see “JT AG Interface” on page 35). The external reset sequence is
as follows:
1. The external reset pin (RST) is asserted and then de-asserted.
2. After RST is de-assserted, the main crystal oscillator must be allowed to settle and there is an
internal main oscillator counter that takes from 15-30 ms to account for this. During this time,
internal reset to the rest of the controller is held active.
System Control
46 October 5, 2006
Preliminary
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The external reset timing is shown in Figure 17-8 on page 292.
6.1.2.3 Power-On Reset (POR)
The Power-On Reset (POR) circuitry detects a rise in power-supply voltage and generates an
on-chip reset pulse. To use the on-chip circuitry, the RST input needs a pull-up resistor (1K to
10K Ω).
The device must be operating within the specified operating parameters at the point when the
on-chip power-on reset pulse is complete. The specified operating parameters include supply
voltage, frequency, temperature, and so on. If the operating conditions are not met at the point of
POR end, the Stellaris controller does not operate correctly. In this case, the reset must be
extended using external circuitry. The RST input may be used with the circuit as shown in
Figure 6-1.
Figure 6-1. External Circuitry to Extend Reset
The R1 and C1 components define the power-on delay . The R2 resistor mitigates any leakage from
the RST input. The diode discharges C1 rapidly when the power supply is turned off.
The Power-On Reset sequence is as follows:
1. The controller waits for the later of external reset (RST) or internal POR to go inactive.
2. After the resets are inactive, the main crystal oscillator must be allowed to settle and there is
an internal main oscillator counter that takes from 15-30 ms to account for this. During this
time, internal reset to the rest of the controller is held active.
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The internal POR is only active on the initial power-up of the controller. The Power-On Reset
timing is shown in Figure 17-9 on page 292.
6.1.2.4 Brown-Out Reset (BOR)
A dr op in the i npu t vo lta ge re sul tin g in t he asse rtio n of t he i nte rna l bro wn- out de te cto r can b e us ed
to reset the controller. This is initially disabled and may be enabled by software.
The system provides a brown-out detection circuit that triggers if VDD drops below VBTH. The
circuit is provided to guard against improper operation of logic and peripherals that operate off VDD
and not the LDO voltage. If a brown-out condition is detected, the system may generate a
controller interrupt or a system reset. The BOR circuit has a digital filter that protects against
noise-related detection. This feature may be optionally enabled.
R1
C1 R2 RST
Stellaris
D1
LM3S101 Data Sheet
October 5, 2006 47
Preliminary
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register (see page 61). The BORIOR bit in the PBORCTL register must be set for a brown-out to
trigger a reset. The brown-out reset sequence is as follows:
1. When VDD drops below VBTH, an internal BOR condition is set.
2. If the BORWT bit in the PBORCTL register is set, the BOR condition is resampled sometime
later (specified by BORTIM) to determine if the original condition was caused by noise. If the
BOR condition is not met the second time, then no action is taken.
3. If the BOR condition exists, an internal reset is asserted.
4. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
5. The internal BOR signal is released after 500 μs to prevent another BOR condition from being
set before software has a chance to investigate the original cause.
The internal Brown-Out Reset timing is shown in Figure 17-10 on page 292.
6.1.2.5 Software Reset
Each peripheral can be reset by software. There are three registers that control this function (see
the SRCRn registers, starting on page 63). If the bit position corresponding to a peripheral is set,
the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the
clock gating control for peripherals and on-chip functions (see “System Control” on page 50).
Writing a bit lane with a value of 1 initiates a reset of the corresponding unit. Note that all reset
signals for all clocks of the specified unit are asserted as a result of a software-initiated reset.
The entire system can be reset by software also. Setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset in initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The software-initiated system reset timing is shown in Figure 17-11 on page 292.
6.1.2.6 W atchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its se con d time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register (see page 170), and the timer resumes counting down from that value.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The
watchdog timer reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
System Control
48 October 5, 2006
Preliminary
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The watchdog reset timing is shown in Figure 17-12 on page 293.
6.1.2.7 Low Drop-Out
A reset can be made when the internal low drop-out (LDO) regulator output goes unregulated. This
is initially disabled and may be enabled by software. LDO is controlled with the LDO Power
Control (LDOPCTL) register (see page 62). The LDO reset sequence is as follows:
1. LDO goes unregulated and the LDOARST bit in the LDOARST register is set.
2. An internal reset is asserted.
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The LDO reset timing is shown in Figure 17-13 on page 293.
6.1.3 Power Control
The LDO regulator permits the adjustment of the on-chip output voltage (VOUT). The output may
be adjusted in 50 mV increments between the range of 2.25 V through 2.75 V. The adjustment is
made through the VADJ field of the LDO Power Control (LDOPCTL) register (see page 62).
6.1.4 C lock Control
System control determines the clocking and control of clocks in this part.
6.1.4.1 Fundament al Clock Sources
There are two fundamental clock sources for use in the device:
The main oscillator, driven from either an external crystal or a single-ended source. As a
crystal, the main oscillator source is specified to run from 1-8 MHz. However , when the crystal
is being used as the PLL source, it must be from 3.579545–8.192 MHz to meet PLL
requirements. As a single-ended source, the range is from DC to the specified speed of the
device.
The internal oscillator, which is an on-chip free running clock. The internal oscillator is
specified to run at 12 MHz ± 50%. It can be used to clock the system, but the tolerance of
frequency range must be met.
The internal system clock may be driven by either of the above two reference sources as well as
the internal PLL, provided that the PLL input is connected to a clock source that meets its AC
requirements.
Nearly all of the control for the clocks is provided by the Run-Mode Clock Configuration (RCC)
registe r (see page 71).
Figure 6-2 shows the logic for the main clock tree. The peripheral blocks are driven by the System
Clock signal and can be programmatically enabled/disabled.
LM3S101 Data Sheet
October 5, 2006 49
Preliminary
Figure 6-2. Main Clock Tree
6.1.4.2 PLL Frequency Configuration
The user does not have direct control over the PLL frequency , but is required to match the external
crystal used to an internal PLL-Crystal table. This table is used to create the best fit for PLL
parameters to the crystal chosen. Not all crystals result in the PLL operating at exactly 200 MHz,
though the freque nc y is within ±1%. The result of the lookup is kept in the XTAL to PLL
Translation (PLLCTL) register (see page 75).
Table 6-4 on page 74 describes the available crystal choices and default programming of the
PLLCTL register. The crystal number is written into the XTAL field of the Run-Mode Clock
Configuration (RCC) register (see page 71). Any time the XTAL field changes, a read of the
internal table is performed to get the correct value. Table 6-4 on page 74 describes the available
crystal choices and default programming values.
6.1.4.3 PLL Modes
The PLL has two modes of operation: Normal and Power-Down
Normal: The PLL multiplies the input clock reference and drives the output.
Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the
output.
The modes are programmed using the RCC register fields as shown in Table 6-4 on page 74.
6.1.4.4 PLL Operation
If the PLL configuration is changed, the PLL output is not stable for a period of time (PLL
TREADY=0.5 ms) and during this time, the PLL is not usable as a clock reference.
The PLL is changed by one of the following:
Change to the XTAL value in the RCC register (see page 71)—writes of the same value do not
cause a relock.
Change in the PLL from Pow er -D own to Normal mod e.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is
set to 0x1200 (that is, ~600 μs at a 8.192-MHz external oscillator clock). Hardware is provided to
keep the PLL from being used as a system clock until the TREADY condition is met after one of the
Main
Osc
1-8 MHz
Internal
Osc
15 MHz ÷4
OSCSRCa
OSC1
OSC2
PLL
(200 MHz
output )
BYPASSa
SYSDIVa
USESYSDIVa
System Clock
OENa
XTALa
PWRDNa
a. These are bit fields within the Run-Mode Clock Configuration (RCC) register.
System Control
50 October 5, 2006
Preliminary
two changes above. It is the user's responsibility to have a stable clock source (like the main
oscillator) before the RCC register is switched to use the PLL.
6.1.4.5 Clock Verification Timers
There are three identical clock verification circuits that can be enabled though software. The circuit
checks the faster clock by a slower clock using timers:
The main oscillator checks the PLL.
The main oscillator checks the internal oscillator.
The internal oscillator divided by 64 checks the main oscillator.
If the verification timer function is enabled and a failure is detected, the main clock tree is
immediately switched to a working clock and an interrupt is generated to the controller. Software
can then determine the course of action to take. The actual failure indication and clock switching
does not clear without a write to the CLKVCLR register, an external reset, or a POR reset. The
clock verification timers are controlled by the PLLVER, IOSCVER, and MOSCVER bits in the RCC
registe r (see page 71).
6.1.5 System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registe rs c o ntro l th e cl oc k g ati ng
logic for each peripheral or block in the system while the controller is in Run, Sleep, and
Deep-Sle ep mode, respec tively. The DC1, DC2 and DC4 registers act as a write mask for the
RCGCn, SCGCn, and DCGCn regist ers.
In Run mode, the controller is actively executing code. In Sleep mode, the clocking of the device is
unchanged but the controller no longer executes code (and is no longer clocked). In Deep-Sleep
mode, the clocking of the device may change (depending on the Run mode clock configuration)
and the controller no longer executes code (and is no longer clocked). An interrupt returns the
device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code. Each mode is described in more detail in this section.
6.1.5.1 Run Mode
Run mode provides normal operation of the processor and all of the peripherals that are currently
enabled by the RCGCn registers. The system clock can be any of the available clock sources
includi ng the PLL .
6.1.5.2 Sleep Mode
In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked.
Peripherals are clocked that are enabled in the SCGCn register when Auto Clock Gating is
enabled (see RCC register on page 71) or the RCGCn register when the Auto Clock Gating is
disabled. The System Clock has the same source and frequency as that during Run mode.
6.1.5.3 Deep-Sleep Mode
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when Auto Clock Gating is enabled (see RCC
register) or the RCGCn register when the Auto Clock Gating is disabled. The system clock source
is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if
one is enabled (see page 80). When the DSLPCLKCFG register is used, the internal oscillator is
powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the
time of the WFI instruction, hardware powers the PLL down and overrides the SYSDIV field of the
active RCC register to be /16 or /64 respectively. When the Deep-Sleep exit event occurs,
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that were stopped during the Deep-Sleep duration.
LM3S101 Data Sheet
October 5, 2006 51
Preliminary
6.2 Initialization and Configuration
The PLL is configured using direct register writes to the Run-Mode Clock Configuration (RCC)
register. The steps required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN and OE
bits in RCC. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN and OE bits powers and enables the PLL and its
output.
3. Sele ct th e de si red sys t em d iv id e r (SYSDIV) and set the USESYS bit in RCC. The SYSDIV field
determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt S tatus (RIS) register.
If the PLL doesn’t lock, the con fig ur ation is inva li d.
5. Enable use of the PLL by clearing the BYPASS bit in RCC.
Important: If the BYPASS bit is clea red before the PLL locks, it is possible to render the device
unusable.
6.3 Register Map
Table 6-1 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400FE000.
Table 6-1. System Control Register Map (Sheet 1 of 2)
Offset Name Reset Type Description See
page
Device Identification and Capabilities
0x000 DID0 - RO Device identification 0 53
0x004 DID1 - RO Device identification 1 54
0x008 DC0 0x00070003 RO Device capabilities 0 56
0x010 DC1 0x00000009 RO Device capabilities 1 57
0x014 DC2 0x03030011 RO Device capabilities 2 58
0x018 DC3 0x810003C0 RO Device Capabilities 3 59
0x01C DC4 0x00000007 RO Device Capabilities 4 60
Local Control
System Control
52 October 5, 2006
Preliminary
6.4 Register Descriptions
The remainder of this section lists and describes the System Control registers, in numerical order
by address offset.
0x030 PBORCTL 0x00007FFD R/W Power-On and Brown-Out Reset Control 61
0x034 LDOPCTL 0x00000000 R/W LDO Power Control 62
0x040 SRCR0 0x00000000 R/W Software Reset Control 0 63
0x044 SRCR1 0x00000000 R/W Software Reset Control 1 64
0x048 SRCR2 0x00000000 R/W Software Reset Control 2 65
0x050 RIS 0x00000000 RO Raw Interrupt Status 66
0x054 IMC 0x00000000 R/W Interrupt Mask Control 67
0x058 MISC 0x00000000 R/W1C Masked Interrupt Status and Clear 69
0x05 C RESC - R/W Reset C ause 70
0x060 RCC 0x07803AC0 R/W Run-Mode Clock Configuration 71
0x064 PLLCFG - RO XTAL to PLL translation 75
System Control
0x100 RCGC0 0x00000001 R/W Run-Mode Clock Gating Control 0 76
0x104 RCGC1 0x00000000 R/W Run-Mode Clock Gating Control 1 77
0x108 RCGC2 0x00000000 R/W Run-Mode Clock Gating Control 2 79
0x110 SCGC0 0x00000001 R/W Sleep-Mode Clock Gating Control 0 76
0x114 SCGC1 0x00000000 R/W Sleep-Mode Clock Gating Control 1 77
0x118 SCGC2 0x00000000 R/W Sleep-Mode Clock Gating Control 2 79
0x120 DCGC0 0x00000001 R/W Deep-Sleep-Mode Clock Gating Control 0 76
0x124 DCGC1 0x00000000 R/W Deep-Sleep-Mode Clock Gating Control 1 77
0x128 DCGC2 0x00000000 R/W Deep-Sleep-Mode Clock Gating Control 2 79
0X144 DSLPCLKCFG 0x07800000 R/W Deep-Sleep Clock Configuration 80
0x150 CLKVCL R 0x00000 000 R/ W Clock verifi cat ion clear 81
0x160 LDOARST 0x00000000 R/W Allow unregulated LDO to re set the part 82
Table 6-1. System Control Register Map (Sheet 2 of 2)
Offset Name Reset Type Description See
page
LM3S101 Data Sheet
October 5, 2006 53
Preliminary
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the device.
Bit/Field Name Type Reset Description
31 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
30:28 VER RO 0 This field defines the version of the DID0 register format:
0=Register version for the Stellaris microcontrollers
27:16 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
15:8 MAJO R RO - Thi s fie ld speci fies t he ma jor rev ision nu mber o f the devi ce.
The major r evisi on num ber is indicated i n the part number
as a letter (A for first revision, B for second, and so on).
This field is encoded as follows:
0: Revisi on A (initi al dev ice)
1: Revi si on B (firs t revision)
and so on.
7:0 MINOR RO - T his field speci fies t he minor revisi on nu mber o f the devi ce.
This field is num eri c and is enc od ed as fol low s :
0: No changes. Major revision was most recent update.
1: One interc on nec t change made since la st m ajor revi si on
update.
2: T wo interconnec t changes mad e since la st major rev ision
update.
and so on.
RO
0
Device Identification 0 (DID0)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
-
Reset
Type ---------------
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reservedreserved
MINOR
VER
MAJOR
System Control
54 October 5, 2006
Preliminary
Register 2: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, and package type.
Bit/Field Name Type Reset Description
31:28 VER RO 0x0 This field defines the version of the DID1 register format:
0=Register version for the Stellaris microcontrollers
27:24 FAM RO 0x0 Family
This field provides the family identification of the device
within the Luminary Micro product portfolio.
The 0x0 value indicates the Stellaris family of
microcontrollers.
23:16 PART NO RO 0x01 Part Number
This field provides the pa rt number of the device within the
family.
The 0x01 value indicates the LM3S101 microcontroller.
15:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:5 TEMP RO see table Temperature Range
This field specifies the temperature rating of the device.
This field is encoded as follows:
4:3 PKG RO 0x0 This fie ld s pe ci fie s t he package typ e. A value of 0 indi ca tes
a 28-pin SOIC package.
2 RoHS RO 1 RoHS-Compliance
A 1 in this bit specifies the device is RoHS-compliant.
reserved
RO
0
Device Identification 1 (DID1)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 0000000- - - 001- -
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
QUAL
VER
PKG
TEMP
PARTNOFAM
RoHS
TEMP Description
000 Commercial temperature range (0°C to
70°C)
001 Industrial temperature range (-40°C to
85°C)
010-111 Reserved
LM3S101 Data Sheet
October 5, 2006 55
Preliminary
1:0 QUAL RO see table This field specifies the qualification status of the device.
This field is encoded as follows:
Bit/Field Name Type Reset Description
QUAL Description
00 En gineering Sample (unqualif ied )
01 Pi lot Production (unqualif ied )
10 Fully Qualified
11 Reserved
System Control
56 October 5, 2006
Preliminary
Register 3: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Bit/Field Name Type Reset Description
31:16 SRAMSZ RO 0x0007 Indicates the size of the on-chip SRAM. A value of 0x0007
indicates 2 KB of SRAM.
15:0 FLSHSZ RO 0x0003 Indicates the size of the on-chip flash memory. A value of
0x03 indicates 8 KB of Flash.
RO
0
Device Capabilities Register 0 (DC0)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000111
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000011
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
SRAMSZ
FLSHSZ
LM3S101 Data Sheet
October 5, 2006 57
Preliminary
Register 4: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
15:12 MINSYSDIV RO 0x09 The reset value is hardware-dependent. A value of 0x09
specifies a 20-MHz CPU clock with a PLL divider of 10.
See the RCC register (page 71) for how to change the
system clock divisor using the SYSDIV bit.
11:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7 MPU RO 0 This bit indi cates whether the Memory Protection Unit
(MPU) in the Corte x-M3 is avail able. A 0 in this b it indica tes
the MPU is not available; a 1 indicates the MPU is
available.
See the ARM® Cortex™-M3 Technical Reference Manual
for details on the MPU.
6:5 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
4 PLL RO 1 A 1 in this bit indicates the presence of an implemented
PLL in the device.
3WDT
aRO 1 A 1 in this bit indicates a watchdog timer on the device.
2SWO
aRO 1 A 1 in this bit indicates the presence of the ARM Serial Wire
Output (SWO) trace port capabilities.
1SWD
aRO 1 A 1 in this bit indicates the presence of the ARM Serial Wire
Debug (SWD) capabilities.
0JTAG
a
a. These bits mask the Run-Mode Clock Gatin g C ontrol 0 (RCGC 0 ) register (see page 113), Sleep-Mode Clock Gating Control 0
(SCGC0) register (see page 113), and Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 113). Bits that are
not noted are passed as 0.
RO 1 A 1 in this bit indicates the presence of a JTAG port.
RO
0
Device Capabilities 1 (DC1)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
1
Reset
Type 001000000011111
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
PLL
reserved
MINSYSDIV WDT JTAGSWDSWOMPU reservedreserved
System Control
58 October 5, 2006
Preliminary
Register 5: Device Capabilities 2 (DC2), offset 0x014
This register is predefined by the part and can be used to verify features.
Bit/Field Name Type Reset Description
31:26 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
25 COMP1 RO 1 A 1 in this bit indicates the presence of analog
comparator 1.
24 COMP0 RO 1 A 1 in this bit indicates the presence of analog
comparator 0.
23:18 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
17 GPTM1 RO 1 A 1 in this bit indicates the presence of General-Purpose
Timer module 1.
16 GPTM0 RO 1 A 1 in this bit indicates the presence of General-Purpose
Timer module 0.
15:5 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
4 SSI RO 1 A 1 in this bit indicates the presence of the SSI module.
3:1 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
0 UART0 RO 1 A 1 in this bit indicates the presence of the UART0 module.
reserved
reserved reserved
reserved
RO
0
Device Capabilities 2 (DC2)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000001100000011
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00 0000000010001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
SSI
COMP1 COMP0 GPTM1 GPTM0
UART0
LM3S101 Data Sheet
October 5, 2006 59
Preliminary
Register 6: Device Capabilities 3 (DC3), offset 0x018
This register is predefined by the part and can be used to verify features.
Bit/Field Name Type Reset Description
31 32KHz RO 1 A 1 in this bit indicates the presence of a 32.768-KHz input
pin.
30:25 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
24 CCP0 RO 1 A 1 in this bit indicates the presence of the Capture/
Compare/PWM pin 0.
23:10 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
9 C1- RO 1 A 1 in this bit indicates the presence of the C1- pin.
8 C0o RO 1 A 1 in this bit indicates the presence of the C0o pin.
7 C0+ RO 1 A 1 in this bit indicates the presence of the C0+ pin.
6 C0- RO 1 A 1 in this bit indicates the presence of the C0- pin.
5:0 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
reserved reserved
reserved
RO
1
Device Capabilities 3 (DC3)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000100000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000001111000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
32KHz
C1- C0o C0+ C0-
CCP0 reserved
System Control
60 October 5, 2006
Preliminary
Register 7: Device Capabilities 4 (DC4), offset 0x01C
This register is predefined by the part and can be used to verify features.
Bit/Field Name Type Reset Description
31:3 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
2 PORTC RO 1 A 1 in this bit indicates the presence of GPIO Port C.
1 PORTB RO 1 A 1 in this bit indicates the presence of GPIO Port B.
0 PORTA RO 1 A 1 in this bit indicates the presence of GPIO Port A.
RO
0
Device Capabilities 4 (DC4)
Offset 0x01C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000111
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
PORTC PORTB PORTA
reserved
reserved
LM3S101 Data Sheet
October 5, 2006 61
Preliminary
Register 8: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
15:2 BORTIM R/W 0x1FFF This field specifies the number of internal oscillator clocks
delayed before the BOR outp ut is res am ple d if the BORWT
bit is set.
The width of this field is derived by the tBOR width of 500 μs
and the internal oscillator (IOSC) frequency of 15 MHz ±
50%. At +50%, the counter value has to exceed 10,000.
1 BORIOR R/W 0 BOR Interrupt or Reset
This bit controls how a BOR event is signaled to the
controller . If set, a reset is signa led . Otherwise, an interru pt
is signaled.
0 BORWT R/W 1 BOR Wait and Check for Noise
This bit speci fies the respon se to a brow n-ou t sign al
assertion. If BORWT is set to 1, the controller waits BORTIM
IOSC periods before resampling the BOR output, and if
asserted , it sig nals a BOR co ndi tion in terrupt o r reset. If the
BOR resample is deasserted, the cause of the initial
assertion was likely noise and the interrupt or reset is
suppr essed. I f BORWT is 0, BOR asse rtions do not resamp le
the output and any condition is reported immediately if
enabled.
RO
0
Power-On and Brown-Out Reset Control (PBORCTL)
Offset 0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
R/W
0
Reset
Type 111111111111101
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
BORTIM BORIOR BORWT
System Control
62 October 5, 2006
Preliminary
Register 9: LDO Power Control (LDOPCTL), offset 0x034
The VADJ field in this register adjusts the on-chip output voltage (VOUT).
Bit/Field Name Type Reset Description
31:6 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
5:0 VADJ R/W 0x0 This field sets the on-ch ip output vol tag e. The prog ramming
values for the VADJ field are provided in Table 6-2.
Table 6-2. VADJ to VOUT
VADJ Value VOUT (V) VADJ Va lue VOUT (V) VADJ Value VOUT (V)
0x1B 2.75 0x1F 2.55 0x03 2.35
0x1C 2.70 0x00 2.50 0x04 2.30
0x1D 2.65 0x01 2.45 0x05 2.25
0x1E 2.60 0x02 2.40 0x06-0x3F Reserved
RO
0
LDO Power Control (LDOPCTL)
Offset 0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
reserved
reserved VADJ
LM3S101 Data Sheet
October 5, 2006 63
Preliminary
Register 10: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register (see
page 57).
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
3 WDT R/W 0 Reset control for the Watchdog unit.
2:0 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
reserved
RO
0
Software Reset Control 0 (SRCR0)
Offset 0x040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO R/W RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W RO RO RO
reserved
WDT reserved
System Control
64 October 5, 2006
Preliminary
Register 11: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register (see
page 58).
Bit/Field Name Type Reset Description
31:26 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
25 COMP1 R/W 0 Reset control for analog comparator 1.
24 COMP0 R/W 0 Reset control for analog comparator 0.
23:18 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
17 GPTM1 R/W 0 Reset control for General-Purpose Timer module 1.
16 GPTM0 R/W 0 Reset control for General-Purpose Timer module 0.
15:5 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
4 SSI R/W 0 Reset control for the SSI units.
3:1 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
0 UART0 R/W 0 Reset control for the UART0 module.
reserved
reserved reserved
reserved
RO
0
Software Reset Control 1 (SRCR1)
Offset 0x044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO R/W R/W RO RO RO RO RO RO R/W R/W
RO
0
Reset
Type 00 0000000000000
RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
SSI
COMP1 COMP0 GPTM1 GPTM0
UART0
LM3S101 Data Sheet
October 5, 2006 65
Preliminary
Register 12: Software Reset Control 2 (SRCR2), offset 0x048
Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register (see
page 60).
Bit/Field Name Type Reset Description
31:3 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
2 PORTC R/W 0 Reset control for GPIO Port C.
1 PORTB R/W 0 Reset control for GPIO Port B.
0 PORTA R/W 0 Reset control for GPIO Port A.
RO
0
Software Reset Control (SRCR2)
Offset 0x048
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
PORTC PORTB PORTA
reserved
reserved
System Control
66 October 5, 2006
Preliminary
Register 13: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
Bit/Field Name Type Reset Description
31:7 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
6 PLLLRIS RO 0 PLL Lock Raw Interrupt Status
This bit is set when the PLL TREADY Timer asserts .
5 CLRIS RO 0 Current Limit Raw Interrupt Status
This bit is set if the LDO’s CLE output asserts.
4 IOFRIS RO 0 Internal Oscillator Fault Raw Interrupt Status
This bit is set if an internal oscillator fault is detected.
3 MOFRIS RO 0 Main Oscillator Fault Raw Interrupt Status
This bit is set if a main oscillator fault is detected.
2 LDORIS RO 0 LDO Power Unregulated Raw Interrupt Status
This bit is set if a LDO voltage is unregulated.
1 BORRIS RO 0 Brown-Out Reset Raw Interrupt Status
This bit is the raw in terrupt status for any brown-out
conditions. If set, a brown-out condition was detected. An
interrupt is reported if the BORIM bit in the IMC register is
set and the BORIOR bit in the PBORCTL register is clea red.
0 PLLFRIS RO 0 PLL Fault Raw Interrupt Status
This bit is set if a PLL fault is detected (stops oscillating).
RO
0
Raw Interrupt Status (RIS)
Offset 0x050
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PLLLRISreserved CLRIS IOFRIS MOFRIS LDORIS BORRIS PLLFRIS
LM3S101 Data Sheet
October 5, 2006 67
Preliminary
Register 14: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
Bit/Field Name Type Reset Description
31:7 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
6 PLLLIM R/W 0 PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is
promoted to a controller interrupt. If set, an interrupt is
generated if PLLLRIS in RIS is set; otherwise, an interrupt
is not generated.
5 CLIM R/W 0 Current Limit Interrupt Mask
This bit specifies whether a current limit detection is
promoted to a controller interrupt. If set, an interrupt is
generated if CLRIS is set; otherwise, an interrupt is not
generated.
4 IOFIM R/W 0 Internal Oscillator Fault Interrupt Mask
This bit specifies whether an internal oscillator fault
detection is promoted to a controller interrupt. If set, an
interrupt is generated if IOFRIS is set; otherwise, an
interrupt is not generated.
3 MOFIM R/W 0 Main Oscillator Fault Interrupt Mask
This bi t spe cifies whe ther a main oscil lator f ault d etectio n is
promoted to a controller interrupt. If set, an interrupt is
generated if MOFRIS is set; otherwise, an interrupt is not
generated.
2 LDOIM R/W 0 LDO Power Unregulated Interrupt Mask
This bit specifies whether an LDO unregulated power
situation is promoted to a controller interrupt. If set, an
interrupt is generated if LDORIS is set; otherwise, an
interrupt is not generated.
RO
0
Interrupt Mask Control (IMC)
Offset 0x054
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
reserved
PLLLIMreserved CLIM IOFIM MOFIM LDOIM BORIM PLLFIM
System Control
68 October 5, 2006
Preliminary
1 BORIM R/W 0 Brown-Out Reset Interrupt Mask
This bit specifies whether a brown-out condition is
promoted to a controller interrupt. If set, an interrupt is
generated if BORRIS is set; otherwise, an interrupt is not
generated.
0 PLLFIM R/W 0 PLL Fault Interrupt Mask
This bit sp ecifie s whet her a PLL fault det ection is promot ed
to a controller interrupt. If set, an interrupt is generated if
PLLFRIS is set; otherwise, an interrupt is not generated.
Bit/Field Name Type Reset Description
LM3S101 Data Sheet
October 5, 2006 69
Preliminary
Register 15: Masked Interrupt Status and Clear (MISC), offset 0x058
Central location for system control result of RIS AND IMC to generate an interrupt to the controller.
All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS
registe r (see page 66).
Bit/Field Name Type Reset Description
31:7 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
6 PLLLMIS R/W1C 0 PLL Lock Masked Interrupt Status
This bit is set when the PLL TREADY timer asserts. The
interrupt is cleared by writing a 1 to this bit.
5 CLMIS R/W1C 0 Current Limit Masked Interrupt Status
This bit is set if the LDO’s CLE output asserts. The interrupt
is cleared by writing a 1 to this bit.
4 IOFMIS R/W1C 0 Internal Oscillator Fault Masked Interrupt Status
This bit is set if an internal oscillator fault is detected. The
interrupt is cleared by writing a 1 to this bit.
3 MOFMIS R/W1C 0 Main Oscillator Fault Masked Interrupt Status
This bit is set if a main oscillator fault is detected. The
interrupt is cleared by writing a 1 to this bit.
2 LDOMIS R/W1C 0 LDO Power Unregula ted Ma sk ed Inte rrup t Statu s
This bit is set if LDO power is unregulated. The interrupt is
cleared by writing a 1 to this bit.
1 BORMIS R/W1C 0 Brown-Out Reset Masked Interrupt Status
This bit is the masked interrupt status for any brown-out
conditions. If set, a brown-out condition was detected. An
interrupt is reported if the BORIM bit in the IMC register is
set and the BORIOR bit in t he PBORCTL registe r is cl eared.
The interrupt is cleared by writing a 1 to this bit.
0 PLLFMIS R/W1C 0 PLL Fault Masked Interrupt Status
This bit is set if a PLL fault is detected (stops oscillating).
The interrupt is cleared by writing a 1 to this bit.
RO
0
Masked Interrupt Status and Clear (MISC)
Offset 0x058
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
reserved
PLLLMISreserved CLMIS IOFMIS MOFMIS LDOMIS BORMISPLLFMIS
System Control
70 October 5, 2006
Preliminary
Register 16: Reset Cause (RESC), offset 0x05C
This field specifies the cause of the reset event to software. The reset value is determined by the
cause of the reset. When an external reset is the cause (EXT is set), all other reset bits are
cleared. However, if the reset is due to any other cause, the remaining bits are sticky, allowing
software to see all causes.
Bit/Field Name Type Reset Description
31:6 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
5 LDO R/W - When se t to 1, LDO pow er OK lo st is the cause of the reset
event.
4 SW R/W - When set to 1, a software reset is the cause of the reset
event.
3 WDT R/W - When set to 1, a watchdog reset is the cause of the reset
event.
2 BOR R/W - When set to 1, a brown-out reset is the cause of the reset
event.
1 POR R/W - When set to 1, a power-on reset is the cause of the reset
event.
0 EXT R/W - When set to 1, an external reset (RST assertion) is the
cause of the reset event.
reserved
RO
0
Reset Cause (RESC)
Offset 0x05C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000- - - - - -
RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
reserved
WDT BOR POR EXTSWLDO
LM3S101 Data Sheet
October 5, 2006 71
Preliminary
Register 17: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
Bit/Field Name Type Reset Description
31:28 Reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
27 ACG R/W 0 Auto Clock Gating
This bit s pecifies w hether the sys tem uses the Sleep-Mode
Clock Gating Control (SCGCn) registers (see page 76)
and Deep-Sleep-Mode Clock Gating Control (DCGCn)
registers (see page 76) if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or
DCGCn registers are used to cont rol the cl ock s distri bute d
to the peripherals when the controller is in a sleep mode.
Otherwise, the Run-Mode Clock Gating Control (RCGCn)
registers (see page 76) are used when the controller enters
a sleep mode.
The RCGCn registers are always used to control the clocks
in Run mode.
This allows peripherals to consume less power when the
controller is in a sleep mode and the peripheral is unused.
RO
0
Run-Mode Clock Configuration (RCC)
Offset 0x060
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000011110000000
RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO
RO
0
Reset
Type 011101011000000
RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
BYPASS OSCSRCPLLVER
SYSDIV
reserved PWRDN IOSCDIS
reserved ACG USESYSDIV
OEN XTAL IOSCVER MOSCVER MOSCDIS
System Control
72 October 5, 2006
Preliminary
26:23 SYSDIV R/W 0xF System Clock Divisor
S pecifi es which divi sor is used to generate th e system cl ock
from the PLL output (200 MHz).
When reading the Run-Mode Cloc k Config uration (RCC)
register (see page 71), the SYSDIV value is MINSYSDIV if
a lower divider was requested and the PLL is being used.
This lower value is allowed to divide a non-PLL source.
22 USESYSDIV R/W 0 Use the system clock divider as the source for the system
clock. The system clock divider is forced to be used when
the PLL is selected as the source.
21:14 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
13 PWRDN R/W 1 PLL Power Down
This bit connects to the PLL PWRDN input. The reset value
of 1 powers down the PLL. S ee Table 6-4 on page 74 for
PLL mode cont rol .
12 OEN R/W 1 PLL Output Enable
This bit specifies whether the PLL output driver is enabled.
If cleared, the driver transmits the PLL clock to the output.
Otherwi se, t he PLL clo ck d oes n ot os cill ate ou ts ide th e PLL
module.
Note: Both PWRDN and OEN must be cleared to run the
PLL.
11 BYPASS R/W 1 PLL Bypass
Choose s w het her th e sy ste m cl oc k is deri ved from th e PLL
output or the OSC source. If set, the clock that drives the
system is th e OSC source. Otherwise, the clock that drives
the system is the PLL output clock divided by the system
divider.
Bit/Field Name Type Reset Description
Binary
Value Divisor
(BYPASS=1) Frequency
(BYPASS=0)
0000-
1000 reserved reserved
1001 /10 20 MHz
1010 /11 18.18 MHz
1011 /12 16.67 MHz
1100 /13 15.38 MHz
1101 /14 14.29 MHz
1110 /15 13.33 MHz
1111 /16 12.5 MHz (default)
LM3S101 Data Sheet
October 5, 2006 73
Preliminary
10 PLLVER R/W 0 PLL V erific ati on
This bit controls the PLL verification timer function. If set,
the verification timer is enabled and an interrupt is
generated if the PLL becomes inoperative. Otherwise, the
verification timer is not enabled.
9:6 XTAL R/W 0xB This field specifies the crystal value attached to the main
oscilla tor . The enc oding for this f ield is provided in Table 6-4
on page 74.
Oscilla tor-R e lat ed Bits
5:4 OSCSRC R/W 0x0 Picks among the four input sources for the OSC. The
values are:
3 IOSCVER R/W 0 This bit controls the internal oscillator verification timer
function. If set, the verification timer is enabled and an
interrupt is generated if the timer becomes inoperative.
Otherwise, the verification timer is not enabled.
2 MOSCVER R/W 0 This bit controls the main oscillator verification timer
function. If set, the verification timer is enabled and an
interrupt is generated if the timer becomes inoperative.
Otherwise, the verification timer is not enabled.
1 IOSCDIS R/W 0 Internal Oscillator Disable
0: Internal oscillator is enabled.
1: Internal oscillator is disabled.
0 MOSCDIS R/W 0 Main Os ci ll ator D is abl e
0: Main oscillator is enabled.
1: Main oscillator is disabled.
Table 6-3. PLL Mode Control
PWRDN OEN Mode
1 X Power down
00Normal
Bit/Field Name Type Reset Description
Value Input Source
00 Main os cil la tor (defa ult)
01 I nternal oscillator
10 Internal oscillator / 4 (this is necessary if used
as input to PLL)
11 reserved
System Control
74 October 5, 2006
Preliminary
Table 6-4. Default Crystal Field Values and PLL Programming
Crystal Number
(XTAL Binary Value) Crystal Frequency (MHz)
0000-0011 reserved
0100 3.579545 MHz
0101 3.6864 MHz
0110 4 MHz
0111 4.096 MHz
1000 4.9152 MHz
1001 5 MHz
1010 5.12 MHz
1011 6 MHz (reset value)
1100 6.144 MHz
1101 7.3728 MHz
1110 8 MHz
1111 8.192 MHz
LM3S101 Data Sheet
October 5, 2006 75
Preliminary
Register 18: XTAL to PLL Translation (PLLCFG), off set 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) re gister (see page 71).
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
15:14 OD RO - This f ield s pecif ies th e valu e supp lied t o the PL L’s O D inpu t.
13:5 F RO - This field specifies the value supplied to the PLL’s F input.
4:0 R RO - This field specifies the value supplied to the PLL’s R input.
RO
0
XTAL to PLL Translation (PLLCFG)
Offset 0x064
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
-
Reset
Type ---------------
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
RFOD
System Control
76 October 5, 2006
Preliminary
Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100
Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110
Register 21: Deep-Sleep-Mode Cloc k Gating Control 0 (DCGC0), offset 0x120
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will
generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that
all functional units are disabled. It is the responsibility of software to enable the ports necessary for
the application. Note that these registers may contain more bits than there are interfaces,
functions, or units to control. This is to assure reasonable code compatibility with other family and
future parts.
RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and
DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 71) specifies that the system uses sleep modes.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
3 WDT R/W 0 This bit controls the clock gating for the WDT module. If
set, the u nit receives a cl ock and func tions. Otherwi se, the
unit is unclocked and disabled .a
a. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
2 SWO R/W 0 This bit controls the clock gating for the SWO module. If
set, the u nit receives a cl ock and func tions. Otherwi se, the
unit is unclocked and disabled .a
1 SWD R /W 0 This bit controls the clock gating for the SWD module. If
set, the u nit receives a cl ock and func tions. Otherwi se, the
unit is unclocked and disabled .a
0 JTAG R/W 1 This bit controls the clock gating for the JTAG module.
The reset s tate for th is bit is 1. At res et, the unit receives a
clock and functions. Setting this bit to 0 leaves the unit
unclocked and disabled.a
RO
0
Run-Mode, Sleep-Mode and Deep-Sleep-Mode Clock Gating Control 0 (RCGC0, SCGC0, and DCGC0)
Offset 0x100, 0x110, 0x120
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000001
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
reserved
WDT JTAGSWDSWOreserved
LM3S101 Data Sheet
October 5, 2006 77
Preliminary
Register 22: Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104
Register 23: Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114
Register 24: Deep-Sleep-Mode Cloc k Gating Control 1 (DCGC1), offset 0x124
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will
generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that
all functional units are disabled. It is the responsibility of software to enable the ports necessary for
the application. Note that these registers may contain more bits than there are interfaces,
functions, or units to control. This is to assure reasonable code compatibility with other family and
future parts.
RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and
DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 71) specifies that the system uses sleep modes.
Bit/Field Name Type Reset Description
31:26 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
25 COMP1 R/W 0 This bit controls the clock gating for the Comparator 1
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.a
24 COMP0 R/W 0 This bit controls the clock gating for the Comparator 0
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.a
23:18 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
17 GPTM1 R/W 0 This bit controls the clock gating for the General Purpose
Timer 1 module. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled.a
16 GPTM0 R/W 0 This bit controls the clock gating for the General Purpose
Timer 0 module. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled.a
reserved
reserved reserved
reserved
RO
0
Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 1 (RCGC1, SCGC1, and DCGC1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO R/W R/W RO RO RO RO RO RO R/W R/W
RO
0
Reset
Type 00 0000000000000
RO RO RO RO RO RO RO RO RO RO R/W RO RO RO R/W
SSI
COMP1 COMP0 GPTM1 GPTM0
UART0
Offset 0x104, 0x114, and 0x124
System Control
78 October 5, 2006
Preliminary
15:5 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
4 SSI R/W 0 This bit controls the clock gating for the SSI module. If set,
the unit receives a clock and functions. Otherwise, the unit
is unclocke d and disabl ed.a
3:1 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
0 UART0 R/W 0 This bit controls the clock gating for the UART0 module. If
set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled.a
a. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
Bit/Field Name Type Reset Description
LM3S101 Data Sheet
October 5, 2006 79
Preliminary
Register 25: Run-Mode Clock Gating Control 2 (RCGC2), offset 0x108
Register 26: Sleep-Mode Clock Gating Control 2 (SCGC2), offset 0x118
Register 27: Deep-Sleep-Mode Cloc k Gating Control 2 (DCGC2), offset 0x128
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will
generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that
all functional units are disabled. It is the responsibility of software to enable the ports necessary for
the application. Note that these registers may contain more bits than there are interfaces,
functions, or units to control. This is to assure reasonable code compatibility with other family and
future parts.
RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and
DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 71) specifies that the system uses sleep modes.
Bit/Field Name Type Reset Description
31:3 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
2 PORTC R/W 0 This bit controls the clock gating for the GPIO Port C
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.a
a. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
1 PORTB R/W 0 This bit controls the clock gating for the GPIO Port B
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.a
0 PORTA R/W 0 This bit controls the clock gating for the GPIO Port A
module. If set, the unit receives a clock and functions.
Otherwise, the unit is unclocked and disabled.a
RO
0
Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 2 (RCGC2, SCGC2, and DCGC2)
Offset 0x108, 0x118, and 0x128
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
PORTC PORTB PORTA
reserved
reserved
System Control
80 October 5, 2006
Preliminary
Register 28: Deep-Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register is used to automatically switch from the main oscillator to the internal oscillator when
entering Deep-Sleep mode. The system clock source is the main oscillator by default. When this
register is set, the internal oscillator is powered up and the main oscillator is powered down. When
the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and
frequency it had at the onset of Deep-Sleep mode.
Bit/Field Name Type Reset Description
31:1 Reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
0 IOSC R/W 0 This field allows an override of the main oscillator when
Deep-Sl eep mode is running. W hen set, th is field forces the
internal oscillator to be the clock source during Deep-Sleep
mode. O therwise, th e main os cillator re mains as the default
system cloc k source.
RO
0
Deep-Sleep Clock Configuration (DSLPCLKCFG)
Offset 0x144
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
IOSC
reserved
reserved
LM3S101 Data Sheet
October 5, 2006 81
Preliminary
Register 29: Clock Verification Clear (CLKVCLR), offset 0x150
This register is provided a s a means of clearing the clock verification circuits by software. Since
the clock verification circuits force a known good clock to control the process, the controller is
allowed the opportunity to solve the problem and clear the verification fault. This register clears all
clock verification faults. To clear a clock verification fault, the VERCLR bit must be set and then
cleared by software. This bit is not self-clearing.
Bit/Field Name Type Reset Description
31:1 Reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
0 VERCLR R/W 0 Clear clock verification faults.
RO
0
Clock Verification Clear (CLKVCLR)
Offset 0x150
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
VERCLR
reserved
reserved
System Control
82 October 5, 2006
Preliminary
Register 30: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160
This register is provided as a means of allowing the LDO to reset the part if the voltage goes
unregulated. Use this register to choose whether to automatically reset the part if the LDO goes
unregulated, based on the design tolerance for LDO fluctuation.
Bit/Field Name Type Reset Description
31:1 Reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
0 LDOARST R/W 0 Set to 1 to allow unregulated LDO output to reset the part.
RO
0
Allow Unregulated LDO to Reset the Part (LDOARST)
Offset 0x160
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
LDOARST
reserved
reserved
LM3S101 Data Sheet
October 5, 2006 83
Preliminary
7Internal Memory
The LM3S101 microcontroller comes with 2 KB of bit-banded SRAM and 8 KB of flash memory.
The flash controller provides a user-friendly interface, making flash programming a simple task.
Flash protection can be applied to the flash memory on a 2-KB block basis.
7.1 Block Diagram
Figure 7-1. Flash Block Diagram
7.2 Functional Description
This section describes the functionality of both memories.
7.2.1 SRAM Me mory
The internal SRAM of the Stellaris devices is located at address 0x20000000 of the device
memory map. To reduce the number of time consuming read-modify-write (RMW) operations,
ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a
bit-band-enabled processor , certain regions in the memory map (SRAM and peripheral space) can
use address aliases to access individual bits in a single, atomic operation.
Flash Co n tro l
FMA
FCMISC
FCIM
FCRIS
FMC
FMD
Fl ash Ti m i ng
USECRL
Fl ash P rotecti on
FMPRE
FMPPE
Flash A rray
SRAM Array
Bridge
Cortex-M3 ICode
DCode
System Bus
APB
Internal Memory
84 October 5, 2006
Preliminary
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x20001000 is to be modified, the bit-band alias is calculated as:
0x22000000 + (0x1000 * 32) + (3 * 4) = 0x2202000C
With the alias address calculated, an instruction performing a read/write to address 0x2202000C
allows direct access to only bit 3 of the byte at address 0x20001000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
7.2.2 Flash Memory
The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of
2-KB blocks that can be individually protected. The blocks can be marked as read-only or
execute-only, providing different levels of code protection. Read-only blocks cannot be erased or
programmed, protecting the contents of those blocks from being modified. Execute-only blocks
cannot be erased or programmed, and can only be read by the controller instruction fetch
mechanism, protecting the contents of those blocks from being read by either the controller or by a
debugger.
7.2.2.1 Flash Memory Timing
The timing for the flash is automatically handled by the flash controller. However, in order to do so,
it must know the clock rate of the system in order to time its internal signals properly. The number
of clock cycles per microsecond must be provided to the flash controller for it to accomplish this
timing. It is software's responsibility to keep the flash controller updated with this information via
the USec Reload (USECRL) register (see page 89).
On reset, USECRL is loaded with a value that configures the flash timing so that it works with the
selected crystal value. If software changes the system operating frequency, the new operating
frequency must be loaded into USECRL before any flash modifications are attempted. For
example, if the device is operating at a speed of 20 MHz, a value of 0x13 must be written to the
USECRL register.
7.2.2.2 Flash Memory Protection
The user is provided two forms of flash protection per 2-KB flash blocks in two 32-bit wide
registers. The protection policy for each form is controlled by individual bits (per policy per block) in
the FMPPE and FMPRE registers (see page 88).
Flash Memory Protection Program Enable (FMPPE): If set, the block may be programmed
(written) or erased. If cleared, the block may not be changed.
Flash Memory Protection Read Enable (FMPRE): If set, the block may be executed or read
by software or debuggers. If cleared, the block may only be executed. The contents of the
memory block are prohibited from being accessed as data and traversing the DCode bus.
LM3S101 Data Sheet
October 5, 2006 85
Preliminary
The policies may be combined as shown in Table 7-1.
An access that attempts to program or erase a PE-protected block is prohibited. A controller
interrupt may be optionally generated (by setting the AMASK bit in the FIM register) to alert
software developers of poorly behaving software during the development and debug phases.
An access that attempts to read an RE-protected block is prohibited. Such accesses return data
filled with all 0s. A controller interrupt may be optionally generated to alert software developers of
poorly behaving software during the development and debug phases.
The factory settings for the FMPRE and FMPPE registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. The changes are not permanent until the register is
committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0
and not committed, it may be restored by executing a power-on reset sequence.
7.2.2.3 Flash Memory Programming
Writing the flash memory requires that the code be executed out of SRAM to avoid corrupting or
interrupting the bus timing. Flash pages can be erased on a page basis (1 KB in size), or by
performing a mass erase of the entire flash.
All erase and program operations are performed using the Flash Memory Address (FMA), Flash
Memory Data (FMD) and Flash Memory Control (FMC) registers. See section 7.3 for examples.
7.3 Initialization and Configuration
This section shows examples for using the flash controller to perform various operations on the
contents of the flash memory.
7.3.1 C hanging Flas h Protection Bits
As discussed in Section 7.2.2.2, changes to the protection bits must be committed before they
take effect. The sequence to change and commit a bit in software is as follows:
1. The Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection
Program Enable (FMPPE) registers are written, changing the intended bit(s). The action of
these changes can be tested by software while in this state.
2. The Flash Memory Address (FMA) register (see page 90) bit 0 is set to 1 if the FMPPE
register is to be committed; otherwise, a 0 commits the FMPRE register.
3. The Flash Memory Control (FMC) r egister (see page 92) is written with the COMT bit set. This
initiates a write sequence and commits the changes.
Table 7-1. Flash Protection Policy Combinations
FMPPE FMPRE Protection
0 0 Execute-only protection. The block may only be executed and may not be
written or erased. This mode is used to protect code.
1 0 The block ma y b e wr itt en, e r as ed o r ex ecu t ed , but not re ad. This combinatio n
is unlikely to be used.
0 1 Read-only protection. The block m ay be read or executed but may not be
written o r erased. Thi s mode is used to lock th e block fro m further mo dificatio n
while allowing any read or execute ac cess.
1 1 No protection. The block may be written, erased, executed or read.
Internal Memory
86 October 5, 2006
Preliminary
7.3.2 Flash Programming
The Stellaris devices provide a user-friendly interface for flash programming. All erase/program
operations are handled via three registers: FMA, FMD and FMC.
The flash is programmed using the following sequence:
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the flash write key and the WRITE bit (a value of 0xA4420001) to the FMC register.
4. Poll the FMC register until the WRITE bit is cleared.
To perform an erase of a 1-KB page:
1. Write the page address to the FMA register.
2. Write the flash write key and the ERASE bit (a value of 0xA4420002) to the FMC register.
3. Poll the FMC register until the ERASE bit is cleared.
To perform a mass erase of the flash:
1. Write the flash write key and the MERASE bit (a value of 0xA4420004) to the FMC register.
2. Poll the FMC register until the MERASE bit is cleared.
7.4 Register Map
Table 7-2 lists the Flash memory and control registers. The offset listed is a hexadecimal
increment to the register’s address, relative to the Flash control base address of 0x400FD000,
except for FMPRE and FMPPE, which are relative to the System Control base address of
0x400FE000.
Table 7-2. Flash Register Map
Offset Name Reset Type Description See
page
0x130a
a. Relative to System Control base address of 0x400FE000.
FMPRE 0x0F R/W0 Flash memory read protect 88
0x134aFM PPE 0x0F R/W0 Flash memory progra m prot ect 88
0X140aUSECRL 0x13 R/W USec reload 89
0x000 FMA 0x0 000 0000 R/W Flash memory addre ss 90
0x004 FMD 0x0 000 00 00 R/W Flash me mo ry data 91
0x008 FMC 0x0 000 00 00 R/W Flash me mo ry con trol 92
0x00C FCRIS 0x00000000 RO Flash controller raw interrupt status 94
0x010 FCIM 0x00000000 R/W Flash controller interrupt mask 95
0x014 FCMISC 0x00000000 R/W1C Flash controller masked interrupt status and clear 96
LM3S101 Data Sheet
October 5, 2006 87
Preliminary
7.5 Register Descriptions
The remainder of this section lists and describes the Flash Memory registers, in numerical order
by address offset.
Internal Memory
88 October 5, 2006
Preliminary
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130
Register 2: Flash Memory Protection Program Enable (FMPPE), offset 0x134
Note: Offset is relative to System Control base address of 0x400FE000
These registers store the read-only (FMPRE) and execute-only (FMPPE) protection bits for each
2 KB flash block. This register is loaded during the power-on reset sequence.
The factory settings for the FMPRE and FMPPE registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. However, this register is R/W0; the user can only
change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1).
The changes are not permanent until the register is committed (saved), at which point the bit
change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by
executing a power-on reset sequence.
For additional information, see “Flash Memory Protection” on page 84.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Re served bits retu rn an indeterminate value, and
should never be changed.
3:0 Block3-
Block0 R/W0 0x0F Enable 2-KB flash blocks to be written or erased
(FMPPE register), or executed or read (FMPRE
register). The policies may be combined as shown
in Table 7-1 on page 85.
reserved
reserved
RO RO RO RO RO RO RO RO RO RO RO RO
RO RO RO RO RO RO R/W0 R/W0 R/W0 R/W0RO RO
RO RO RO RO
0000000000000000
00000000
RO RO RO RO
00001111
Block0Block1Block2Block3
Flash Memory Protection Read Enable and Program Enable (FMPRE and FMPPE)
Offset 0x130 and 0x134
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
Reset
Type
LM3S101 Data Sheet
October 5, 2006 89
Preliminary
Register 3: USec Reload (USECRL), offset 0x140
Note: Offset is relative to System Control base address of 0x400FE000
This register is provided as a means of creating a 1 μs tick divider reload value for the flash
controller. The internal flash has specific minimum and maximum requirements on the length of
time the high voltage write pulse can be applied. It is required that this register contain the
operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is
required to change this value if the clocking conditions are changed for a flash erase/program
operation.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 USEC R/W 0x13 MHz -1 of the controller clock when the flash is being
erased or pr ogra mmed .
USEC should be set to 0x13 (19 MHz) whenever the flash is
being erased or programmed.
RO
0
Usec Reload (USECRL)
Offset 0x140
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000010011
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
USEC
reserved
reserved
Internal Memory
90 October 5, 2006
Preliminary
Register 4: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and
specifies which page is erased. Note that the alignment requirements must be met by software or
the results of the operation are unpredictable.
Bit/Field Name Type Reset Description
31:13 reserved RO 0x0 Reserved bits return an indeterminate value, and should
never be changed.
12:0 OFFSET R/W 0x0 Address offset in flash where operation is performed.
reserved
RO
0
Flash Memory Address (FMA)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
OFFSET
LM3S101 Data Sheet
October 5, 2006 91
Preliminary
Register 5: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during the erase cycles.
Bit/Field Name Type Reset Description
31:0 DATA R/W 0x0 Data value for write operation.
0
Flash Memory Data (FMD)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
R/W
0
Reset
Type 000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DATA
DATA
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Internal Memory
92 October 5, 2006
Preliminary
Register 6: Flash Memory Control (FMC), offset 0x008
When this register is written, the flash controller initiates the appropriate access cycle for the
location specified by the Flash Memory Address (FMA) register (see page 90). If the access is a
write access, the data contained in the Flash Memory Data (FMD) register (see page 91) is
written.
This is the final register written and initiates the memory operation. There are four control bits in
the lower byte of this register that, when set, initiate the memory operation. The most used of
these register bits are the ERASE and WRITE bits.
It is a programming error to write multiple control bits and the results of such an operation are
unpredictable.
Bit/Field Name Type Reset Description
31:16 WRKEY WO 0x0 This fi eld contai ns a write key, which is used to minimi ze the
inciden ce of accidental flash writes. The va lue 0xA442 must
be written into this field for a write to occur. Writes to the
FMC register without this WRKEY value are ignored. A
read of this field returns the value 0.
15:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
3 COMT R/W 0 Commit (write) of register value to nonvolatile storage. A
write of 0 has no effect on the state of this bit.
If read, the st ate of the previous commit acc ess is prov ided.
If the previous commit access is complete, a 0 is returned;
otherwise, if the commit access is not complete, a 1 is
returned.
This can ta ke up to 50 μs.
2 MERASE R/W 0 Mass erase flash memory
If this bit is set, the flash main memory of the device is all
erased. A write of 0 has no effect on the state of this bit.
If read, the state of the previous mass erase access is
provided. If the previous mass erase access is complete, a
0 is returned; ot herwi se , if the pre vi ous ma ss eras e acc es s
is not complete, a 1 is returned.
This can t a ke up to 250 ms .
reserved
WO
0
Flash Memory Control (FMC)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
COMT
WRKEY
MERASE ERASE WRITE
LM3S101 Data Sheet
October 5, 2006 93
Preliminary
1 ERASE R/W 0 Erase a page of flash memory
If this b it is s et, the page of flash m ain m em ory as s pec if ied
by the co ntents of FMA is erased. A write of 0 has no effect
on the state of this bit.
If read, th e state of the previous er ase acce ss is p rovided. I f
the previous erase access is complete, a 0 is returned;
otherwis e, if the pre vious erase ac cess is not comp le te, a 1
is returned.
This can ta ke up to 25 ms.
0 WRITE R/W 0 Write a word into flash memory
If this bit is set, the data stored in FMD is written into the
location as specified by the contents of FMA. A write of 0
has no effect on the state of this bit.
If read, the state of the previous write update is provi ded . If
the previous write access is complete, a 0 is returned;
otherwise, if the write access is not complete, a 1 is
returned.
This can ta ke up to 50 μs.
Bit/Field Name Type Reset Description
Internal Memory
94 October 5, 2006
Preliminary
Register 7: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only
signaled if the corresponding FCIM register bit is set.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
1 PRIS RO 0 Programming Raw Interrupt Status
This bit indicates the current state of the prog ramming
cycle. If set, the prog ram ming cy cl e com ple ted ; if cleared,
the programming cycle has not completed. Programming
cycles are either write or erase actions generated through
the Flash Memory Control (FMC) register bi ts (see
page 92).
0 ARIS RO 0 Access Raw Interrupt Status
This bit indicates if the flash was improperly accessed. If
set, the program tried to access the flash counter to the
policy as set in the Flash Memory Protection Read
Enable (FMPRE) and Flash Memory Prote ction Program
Enable (FMPPE) registers (see page 88). Otherwise, no
access has tried to improperly access the flash.
reserved
RO
0
Flash Controller Raw Interrupt Status (FCRIS)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00000000000000 0
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
ARIS
reserved
PRIS
LM3S101 Data Sheet
October 5, 2006 95
Preliminary
Register 8: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
1 PMASK R/W 0 Programming Interrupt Mask
This bit control s the repo rtin g of the progra mm in g raw
interrupt status to the controller. If set, a
programming-generated interrupt is promoted to the
controlle r. Otherwise, inte rrup t s are recorde d but
suppressed from the controller.
0 AMASK R/W 0 Access Interrupt Mask
This bit controls the reporting of the access raw interrupt
statu s to the c ontroller. If set, an a ccess-generate d interrup t
is promoted to the controller. Otherwise, interrupts are
recorded but suppressed from the controller.
reserved
RO
0
Flash Controller Interrupt Mask (FCIM)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
AMASK
reserved
PMASK
Internal Memory
96 October 5, 2006
Preliminary
Register 9: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear
the interrupt reporting.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
1 PMISC R/W1C 0 Programming Mask ed Inte rrupt Statu s and Clea r
This bit indicates whether an interrupt was sign aled
because a programming cycle completed and was not
masked. This bit is cleared by writing a 1. The PRIS bit in
the FCRIS register (see page 94) is also cleared when the
PMISC bit is cleared.
0 AMISC R/W1C 0 Access Masked Inte rrupt Status and Clea r
This bit indicates whether an interrupt was sign aled
because an improper access was attempted and was not
masked. This bit is cleared by writing a 1. The ARIS bit in
the FCRIS register is also cleared when the AMISC bit is
cleared.
reserved
RO
0
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C
AMISC
reserved
PMISC
LM3S101 Data Sheet
October 5, 2006 97
Preliminary
8 General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of three physical GPIO blocks, each corresponding to an
individual GPIO port (Port A, Port B, and Port C). The GPIO module is FiRM-compliant and
supports 2 to 18 programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
Programmable control for GPIO interrupts:
–Interrupt generation masking
–Edge-triggered on rising, falling, or both
–Level-sensitive on High or Low values
5-V-tolerant input/outputs
Bit masking in both read and write operations through address lines
Programmable control for GPIO pad configuration:
–Weak pull-up or pull-down resistors
–2-mA, 4-mA, and 8-mA pad drive
–Slew rate control for the 8-mA drive
–Open drain enables
–Digital input enables
General-Purpose Input/Outp uts (GPIOs)
98 October 5, 2006
Preliminary
8.1 Block Diagram
Figure 8-1. GPIO Module Block Diagram
8.2 Functional Description
Important: All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the
exception of the five JTAG pins (PB7 and PC[3:0]. The JTAG pins default to their
JTAG func tionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR) or an
external reset (RST) puts both groups of pins back to their default state.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-2).
The LM3S101 microcontroller contains three ports and thus three of these physical GPIO blocks.
UART0
SSI
Analog
Comparators
TRST
JTAG
Timer 0CCP0
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
GPIO Port AGPIO Port BGPIO Port C
U0Tx
SSIFss
SSIRx
SSITx
Timer 1
TMS/SWDIO
TDI
TDO/SWO
C0-
C0o/C1-
C0+
32KHz
TCK/SWCLK
SSIClk
U0Rx
LM3S101 Data Sheet
October 5, 2006 99
Preliminary
Figure 8-2. GPIO Port Block Diagram
8.2. 1 D ata Registe r Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 105) by using bits [9:2] of the address bus as a mask.
This allows software drivers to modify individual GPIO pins in a single instruction, without affecting
the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write
operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA
register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set to 1, the value of the
GPIODATA register is altered. If it is cleared to 0, it is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in
Figure 8-3, where u is data unchanged by the write.
GPIOIBE
GPIOIS
GPIOIM
GPIOIEV
GPIOMIS
GPIORIS
GPIOICR
Interrupt
Control
GPIODR4R
GPIODR2R
GPIOSLR
GPIODR8R
GPIOPDR
GPIOPUR
GPIODEN
GPIOODR
I/O Pad
Control
GPIOAFSEL
Function
Selection
GPIODIR
GPIODATA
I/O
Data
M
U
X
M
U
X
D
E
M
U
X
I/O
Pad
Alternate Input
Alternate Output
Alternate Output Enable
Interrupt
GPIO Input
GPIO Output
GPIO Output Enable
Pad Input
Pad Output
Pad Output Enable
Package I/O Pin
GPIOPeriphID0
Identification Registers
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
General-Purpose Input/Outp uts (GPIOs)
100 Octo ber 5, 2006
Preliminary
Figure 8-3. GPIODATA Write Example
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual
value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-4.
Figure 8-4. GPIODATA Read Example
8.2. 2 Data Direction
The GPIO Direction (GPIODIR) register (see page 106) is used to configure each individual pin
as an input or output.
8.2.3 Inte rrupt Operatio n
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external
source holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
GPIO Interrupt Sense (GPIOIS) register (see page 107)
GPIO Interrupt Both Edges (GPIOIBE) register (see page 108)
GPIO Interrupt Event (GPIOIEV) register (see page 109)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 110).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS)
registers (see pages 111 and 112). As the name implies, the GPIOMIS register only shows
interrupt conditions that are allowed to be passed to the controller . The GPIORIS register indicates
that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the
controller.
0xEB
GPIODATA
0x098
111 001 11
u 1u u 0u 1 u
17 06 45 3 2
ADDR[9:2] 978 6 4
5321 0
0 10 0 10 1 0 00
Returned Value 0 10 1 00 0 0
7 56 4 23 1 0
ADDR[9:2] 978 6 4
53210
1 1
GPIODATA 110 1 1 0
0x0C4 010 1 00 0 1 00
LM3S101 Data Sheet
October 5, 2006 101
Preliminary
Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) regis te r (see
page 113).
When programming interrupts, the interrupts should be masked (GPIOIM set to 0). Writing any
value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious
interrupt if the corresponding bits are enabled.
8.2.4 Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is
enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 114), the pin
state is controlled by its alternate function (that is, the peripheral). Software control corresponds to
GPIO mode, where the GPIODATA register is used to read/write the corresponding pins.
8.2.5 Pad Configuration
The pad configuration registers allow for GPIO pad configuration by software based on the
application requirements. The pad configuration registers include the GPIODR2R, GPIODR4R,
GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers.
8.2.6 Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers
as well as the GPIOPCellID0-GPIOPCellID3 registers.
8.3 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting PORTA, PORTB, and PORTC in
the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) default to general-purpose input mode
(GPIODIR and GPIOAFSEL both set to 0). Table 8-1 shows all possible configurations of the
GPIO pads and the control register settings required to achieve them. Table 8-2 shows how a
rising edge interrupt would be configured for pin 2 of a GPIO port.
Table 8-1. GPIO Pad Configuration Examples
Configuration
Register Bit Valuea
GPIOAFSEL
GPIODIR
GPIOODR
GPIODEN
GPIOPUR
GPIOPDR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
Digital Input (GPIO) 0001??XXXX
Digital Output (GPIO) 0101??????
Open Drain Input (GPIO) 0011XXXXXX
Open Drain Output (GPIO) 0111XX????
Digital Input (Timer CCP) 1X01??XXXX
Digital Output (Timer PWM) 1X01??????
Digital Input/Output (SSI) 1X01??????
General-Purpose Input/Outp uts (GPIOs)
102 Octo ber 5, 2006
Preliminary
Digital Input/Output (UART) 1X01??????
Analog Input (Comparator) 000000XXXX
Digital Output (Comparator) 1X01??????
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 8-2. GPIO Interrupt Configuration Example
Register Desired Interrupt
Event Trigger
Pin 2 Bit Va luea
7 6 5 4 3 2 1 0
GPIOIS 0=edge
1=level XXXXX0XX
GPIOIBE 0=single ed ge
1=both edges XXXXX0XX
GPIOIEV 0=Low level, or
negative edge
1=High level, or
positive edge
XXXXX1XX
GPIOIM 0=masked
1=not masked 00000100
a. X=Ignored (don’t care bit)
Table 8-1. GPIO Pad Configuration Examples (Continued)
Configuration
Register Bit Valuea
GPIOAFSEL
GPIODIR
GPIOODR
GPIODEN
GPIOPUR
GPIOPDR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
LM3S101 Data Sheet
October 5, 2006 103
Preliminary
8.4 Register Map
Table 8-2 lists the GPIO registers. The offset listed is a hexadecimal increment to the register’s
address, relative to that GPIO port’s base address:
GPIO Port A: 0x40004000
GPIO Port B: 0x40005000
GPIO Port C: 0x40006000
Important: The GPIO reg isters in this chapter are duplicated in each GPIO block, how ever,
depending on the block, all eight b its may not be co nnected to a GPIO pad (see
Figure 8-1 on page 98). In those cases, writing to those unconne cted bits has no
effect and reading th ose unconnected bits returns no meaningf ul data.
Table 8-3. GPIO Register Map
Offset Name Reset Type Description See
page
0x000 GPIODATA 0x00000000 R/W Data 105
0x400 GPIODIR 0x00000000 R/W Data direction 106
0x404 GPIOIS 0x00000000 R/W Interrupt sense 107
0x408 GPIOIBE 0x00000000 R/W Interrupt both edges 108
0x40C GPIOIEV 0x00000000 R/W Interrupt event 109
0x410 GPIOIM 0x00000000 R/W Interrupt mask enable 110
0x414 GPIORIS 0x00000000 RO Raw interrupt status 111
0x418 GPIOMIS 0x00000000 RO Masked interrupt status 112
0x41C GPIOICR 0x00000000 W1C Interrupt clear 113
0x420 GPIOAFSEL see noteaR/W Alternate functi on sel ec t 114
0x500 GPIODR2R 0x000000FF R/W 2-mA drive select 115
0x504 GPIODR4R 0x00000000 R/W 4-mA drive select 116
0x508 GPIODR8R 0x00000000 R/W 8-mA drive select 117
0x50C GPIOODR 0x00000000 R/W Open drain select 118
0x510 GPIOPUR 0x000000FF R/W Pull-up select 119
0x514 GPIOPDR 0x00000000 R/W Pull-down select 120
0x518 GPIOSLR 0x00000000 R/W Slew rate control select 121
0x51C GPIODEN 0x000000FF R/W Digital input enable 122
0xFD0 GPIOPeriphID4 0x00000000 RO Peripheral identification 4 123
0xFD4 GPIOPeriphID5 0x00000000 RO Peripheral identification 5 124
0xFD8 GPIOPeriphID6 0x00000000 RO Peripheral identification 6 125
General-Purpose Input/Outp uts (GPIOs)
104 Octo ber 5, 2006
Preliminary
8.5 Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by
address offset.
0xFDC GPIOPeriphID7 0x00000000 RO Peripheral identification 7 126
0xFE0 GPIOPeriphID0 0x00000061 RO Peripheral identification 0 127
0xFE4 GPIOPeriphID1 0x00000000 RO Peripheral identification 1 128
0xFE8 GPIOPeriphID2 0x00000018 RO Peripheral identification 2 129
0xFEC GPIOPeriphID3 0x00000001 RO Peripheral identification 3 130
0xFF0 G PIOP Cel lID 0 0x0 000 00 0D RO GPIO PrimeCell ide nti fic ati on 0 131
0xFF4 G PIOP Cel lID1 0x0 000 00F 0 RO GPIO PrimeCe ll ide nti fic ati on 1 132
0xFF8 G PIOP Cel lID2 0x0000000 5 RO GPIO PrimeCell identific ati on 2 133
0xFFC GPIOP Cel lID 3 0x0000 00B 1 RO GPIO PrimeCell identi fic ati on 3 134
a. The default reset value for the GPIOAFSEL register is 0x00000000 for all GPIO pins, with the exception of the five JTAG pins
(PB7 and PC[3:0]. These five pins default to JTA G functionality. Because of this, the default reset value of GPIOAFSEL for
GPIO Port B is 0x00000080 while the default reset value of GPIOAFSEL for Port C is 0x0000000F.
Table 8-3. GPIO Register Map (Continued)
Offset Name Reset Type Description See
page
LM3S101 Data Sheet
October 5, 2006 105
Preliminary
Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) registe r (see page 106).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived
from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask
cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask
cause the corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be chang ed.
7:0 DATA R/W 0 GPIO Data
This register is virtually mapped to 256 locations in the address
space. To facilitate the reading and writing of data to these
registers by ind ependent driver s, the data read from and the dat a
written to the registers are masked by the eight address lines
ipaddr[9:2]. Reads from this register return its current
state. Writes to this register only affect bits that are not masked
by ipaddr[9:2] and are configured as outputs. See “Data
Register Operation” on page 99 for examples of reads and
writes.
reserved
RO
0
GPIO Data (GPIODATA)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
DATA
General-Purpose Input/Outp uts (GPIOs)
106 Octo ber 5, 2006
Preliminary
Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Bit s set to 1 in the GPIODIR register configure
the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are
cleared by a reset, meaning all GPIO pins are inputs by default.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 DIR R/W 0x00 GPIO Data Direction
0: Pins are inputs.
1: Pins are outputs.
reserved
RO
0
GPIO Direction (GPIODIR)
Offset 0x400
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
DIR
LM3S101 Data Sheet
October 5, 2006 107
Preliminary
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the
corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits
are cleared by a reset.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 IS R/W 0x00 GPIO Interrupt Sense
0: Edge on corresponding pin is detected (edge-sensitive).
1: Level on corresponding pin is detected (level-sensitive).
reserved
RO
0
GPIO Interrupt Sense (GPIOIS)
Offset 0x404
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
IS
General-Purpose Input/Outp uts (GPIOs)
108 Octo ber 5, 2006
Preliminary
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register is the interrupt both-edges register . When the corresponding bit in the GPIO
Interrupt Sense (GPIOIS) register (see page 107) is set to detect edges, bits set to High in
GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the
corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 109). Clearing a bit
configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 IBE R/W 0x00 GPIO Interrupt Both Edges
0: Interrupt g eneration is con trolled by the GPIO Interrupt Event
(GPIOIEV) register (see page 142).
1: Both edges on the corres pon din g pin trig ger an inte rrup t .
Note: Single edge is determined by the corresponding bit in
GPIOIEV.
reserved
RO
0
GPIO Interrupt Both Edges (GPIOIBE)
Offset 0x408
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
IBE
LM3S101 Data Sheet
October 5, 2006 109
Preliminary
Register 5: GPIO Inte rrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the
corresponding pin to detect rising edges or high levels, depending on the corresponding bit value
in the GPIO Interrupt Sense (GPIOIS) register (see page 107). Clearing a bit configures the pin to
detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are
cleared by a reset.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 IEV R/W 0x00 GPIO Interrupt Event
0: Falling edge or Low levels on corresponding pins trigger
interrupts.
1: Rising edge or High levels on corresponding pins trigger
interrupts.
reserved
RO
0
GPIO Interrupt Event (GPIOIEV)
Offset 0x40C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
IEV
General-Purpose Input/Outp uts (GPIOs)
110 Octo ber 5, 2006
Preliminary
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the
corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing
a bit disables interrupt triggering on that pin. All bits are cleared by a reset.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 IME R/W 0x00 GPIO Interrupt Mask Enable
0: Corresponding pin interrupt is masked.
1: Corresponding pin interrupt is not masked.
reserved
RO
0
GPIO Interrupt Mask (GPIOIM)
Offset 0x410
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
IME
LM3S101 Data Sheet
October 5, 2006 111
Preliminary
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the
status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the
requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt
Mask (GPIOIM) register (see page 110). Bits read as zero indicate that corresponding input pins
have not initiated an interrupt. All bits are cleared by a reset.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 RIS RO 0x00 GPIO Interrupt Raw Status
Reflect the status of interrupt trigger condition detection on pins
(raw, prior to masking).
0: Corresponding pin interrupt requirements not met.
1: Correspo ndi ng pin interru pt has me t requirements.
reserved
RO
0
GPIO Raw Interrupt Status (GPIORIS)
Offset 0x414
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
RIS
General-Purpose Input/Outp uts (GPIOs)
112 Octo ber 5, 2006
Preliminary
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect
the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has
been generated, or the interrupt is masked.
GPIOMIS is the state of the interrupt after masking.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 MIS RO 0x00 GPIO Masked Inte rrup t Status
Masked value of interrupt due to corresponding pin.
0: Corresponding GPIO line interrupt not active.
1: Corresponding GPIO line asserting interrupt.
reserved
RO
0
GPIO Masked Interrupt Status (GPIOMIS)
Offset 0x418
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
MIS
LM3S101 Data Sheet
October 5, 2006 113
Preliminary
Register 9: GPIO Interrupt Clear (GPIOICR), o ffset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 IC W1C 0x00 GPIO Interrupt Clear
0: Corresponding interrupt is unaffec ted .
1: Correspondi ng interrupt is cleared.
reserved
RO
0
GPIO Interrupt Clear (GPIOICR)
Offset 0x41C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C
reserved
IC
General-Purpose Input/Outp uts (GPIOs)
114 Octo ber 5, 2006
Preliminary
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register
selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset,
therefore no GPIO line is set to hardware control by default.
Caution – All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the
exception of the five JTAG pins (PB7 and PC[3:0]). The JTAG pins default to their JTAG
functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR) or an external reset (RST)
puts both groups of pins back to their default state.
If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down
resistors connected to both of them at the same time. If both pins are pulled Low during reset, the
controller has unpredictable behavior. If this happens, remove one or both of the pull-down
resistors, and apply RST or power-cycle the part.
In addition, it is possible to create a software s equence that prevents the debugger from connecting
to the Stellaris microcontroller. If the program code loaded into flash immediately changes the
JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and
halt the controller before the JTAG pin functionality switches. This m ay lock the debugger out of
the part. This can be avoided with a software routine that restores JTAG functionality based on an
external or software trigger.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 AFSEL R/W see note GPIO Alternate Function Select
0: Software control of corresponding GPIO line (GPIO mode).
1: Hardware control of corresponding GPIO line (alternate
hardware function).
Note: The default reset value for the GPIOAFSEL register is
0x00 for all GPIO pins, with the exception of the five
JTAG pins (PB7 and PC[3:0]). These five pins
default to JTAG functionality. Because of this, the
default reset value of GPIOAFSEL for GPIO Port B is
0x80 while the default reset value of GPIOAFSEL for
Port C is 0x0F.
reserved
RO
0
GPIO Alternate Function Select (GPIOAFSEL)
Offset 0x420
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 0000000- - - - - - - -
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
AFSEL
LM3S101 Data Sheet
October 5, 2006 115
Preliminary
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the
port to be individually configured without affecting the other pads. When writing a DRV2 bit for a
GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the
GPIODR8R register are automatically cleared by hardware.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 DRV2 R/W 0xFF Output Pad 2-mA Drive Enable
A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the
corresponding 2-mA enable bit. The change is effective on the
second clock cycle after the write.
reserved
RO
0
GPIO 2-mA Drive Select (GPIODR2R)
Offset 0x500
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000011111111
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
DRV2
General-Purpose Input/Outp uts (GPIOs)
116 Octo ber 5, 2006
Preliminary
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the
port to be individually configured without affecting the other pads. When writing the DRV4 bit for a
GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the
GPIODR8R register are automatically cleared by hardware.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 DRV4 R/W 0x00 Output Pad 4-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the
corresponding 4-mA enable bit. The change is effective on the
second clock cycle after the write.
reserved
RO
0
GPIO 4-mA Drive Select (GPIODR4R)
Offset 0x504
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
DRV4
LM3S101 Data Sheet
October 5, 2006 117
Preliminary
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the
port to be individually configured without affecting the other pads. When writing the DRV8 bit for a
GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the
GPIODR4R register are automatically cleared by hardware.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 DRV8 R/W 0x00 Output Pad 8-mA Drive Enable
A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the
corresponding 8-mA enable bit. The change is effective on the
second clock cycle after the write.
reserved
RO
0
GPIO 8-mA Drive Select (GPIODR8R)
Offset 0x508
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
DRV8
General-Purpose Input/Outp uts (GPIOs)
118 Octo ber 5, 2006
Preliminary
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 122). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R,
GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts
as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open
drain output when set to 1.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 ODE R/W 0x00 Output Pad Open Drain Enable
0: Open drai n conf igu r ati on is dis ab led .
1: Open drai n conf igu r ati on is ena ble d.
reserved
RO
0
GPIO Open Drain Select (GPIOODR)
Offset 0x50C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
ODE
LM3S101 Data Sheet
October 5, 2006 119
Preliminary
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak
pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears
the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 120).
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 PUE R/W 0xFF Pad Weak Pull-Up Enable
A write of 1 to GPIOPDR[n] clears the corresponding
GPIOPUR[n] enables. The change is effective on the second
clock cycle after the write.
reserved
RO
0
GPIO Pull-Up Select (GPIOPUR)
Offset 0x510
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000011111111
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
PUE
General-Purpose Input/Outp uts (GPIOs)
120 Octo ber 5, 2006
Preliminary
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak
pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically
clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 119).
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 PDE R/W 0x00 Pad Weak Pull-Down Enable
A write of 1 to GPIOPUR[n] clears the corresponding
GPIOPDR[n] enables. The change is effective on the second
clock cycle after the write.
reserved
RO
0
GPIO Pull-Down Select (GPIOPDR)
Offset 0x514
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
PDE
LM3S101 Data Sheet
October 5, 2006 121
Preliminary
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 117).
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 SRL R/W 0 Slew Rate Limit Enable (8-mA drive only)
0: Slew rate control disa ble d.
1: Slew rate control enabl ed.
reserved
RO
0
GPIO Slew Rate Control Select (GPIOSLR)
Offset 0x518
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
SRL
General-Purpose Input/Outp uts (GPIOs)
122 Octo ber 5, 2006
Preliminary
Register 18: GPIO Digital Input Enable (GPIODEN), offset 0x51C
The GPIODEN register is the digital input enable register. By default, all GPIO signals are
configured as digital inputs at reset. The only time that a pin should not be configured as a digital
input is when the GPIO pin is configured to be one of the analog input signals for the analog
comparators.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 DEN R/W 0xFF Digital-Input Enable
0: Digit al inp ut dis abl ed
1: Digital input enabled
reserved
RO
0
GPIO Digital Input Enable (GPIODEN)
Offset 0x51C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000011111111
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
DEN
LM3S101 Data Sheet
October 5, 2006 123
Preliminary
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit
register, used by software to identify the peripheral.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0]
reserved
RO
0
GPIO Peripheral Identification 4 (GPIOPeriphID4)
Offset 0xFD0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID4
General-Purpose Input/Outp uts (GPIOs)
124 Octo ber 5, 2006
Preliminary
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit
register, used by software to identify the peripheral.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8]
reserved
RO
0
GPIO Peripheral Identification 5 (GPIOPeriphID5)
Offset 0xFD4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID5
LM3S101 Data Sheet
October 5, 2006 125
Preliminary
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit
register, used by software to identify the peripheral.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16]
reserved
RO
0
GPIO Peripheral Identification 6 (GPIOPeriphID6)
Offset 0xFD8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID6
General-Purpose Input/Outp uts (GPIOs)
126 Octo ber 5, 2006
Preliminary
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit
register, used by software to identify the peripheral.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24]
reserved
RO
0
GPIO Peripheral Identification 7 (GPIOPeriphID7)
Offset 0xFDC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID7
LM3S101 Data Sheet
October 5, 2006 127
Preliminary
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit
register, used by software to identify the peripheral.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 PID0 RO 0x61 GPIO Peripher al ID Regi st er[7: 0]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
GPIO Peripheral Identification 0 (GPIOPeriphID0)
Offset 0xFE0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000001100001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID0
General-Purpose Input/Outp uts (GPIOs)
128 Octo ber 5, 2006
Preliminary
Register 24: GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit
register, used by software to identify the peripheral.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 PID1 RO 0x00 GPIO Peripher al ID Regi st er[15 :8]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
GPIO Peripheral Identification 1 (GPIOPeriphID1)
Offset 0xFE4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID1
LM3S101 Data Sheet
October 5, 2006 129
Preliminary
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit
register, used by software to identify the peripheral.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 PID2 RO 0x18 GPIO Peripher al ID Regi st er[23 :16]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
GPIO Peripheral Identification 2 (GPIOPeriphID2)
Offset 0xFE8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000011000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID2
General-Purpose Input/Outp uts (GPIOs)
130 Octo ber 5, 2006
Preliminary
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit
register, used by software to identify the peripheral.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 PID3 RO 0x01 GPIO Peripher al ID Regi st er[31 :24]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
GPIO Peripheral Identification 3 (GPIOPeriphID3)
Offset 0xFEC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID3
LM3S101 Data Sheet
October 5, 2006 131
Preliminary
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 re gister s are four 8-bit
wide registers, that can conceptually be treated as one 32-bit register. The register is used as a
standard cross-peripheral identification system.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 CID0 RO 0x0D GPIO PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
GPIO Primecell Identification 0 (GPIOPCellID0)
Offset 0xFF0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000001101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID0
General-Purpose Input/Outp uts (GPIOs)
132 Octo ber 5, 2006
Preliminary
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 re gister s are four 8-bit
wide registers, that can conceptually be treated as one 32-bit register. The register is used as a
standard cross-peripheral identification system.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 CID1 RO 0xF0 GPIO PrimeCell ID Registe r [15 :8]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
GPIO Primecell Identification 1 (GPIOPCellID1)
Offset 0xFF4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000011110000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID1
LM3S101 Data Sheet
October 5, 2006 133
Preliminary
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 re gister s are four 8-bit
wide registers, that can conceptually be treated as one 32-bit register. The register is used as a
standard cross-peripheral identification system.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 CID2 RO 0x05 GPIO PrimeCell ID Regi ste r[23 :16]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
GPIO Primecell Identification 2 (GPIOPCellID2)
Offset 0xFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID2
General-Purpose Input/Outp uts (GPIOs)
134 Octo ber 5, 2006
Preliminary
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 re gister s are four 8-bit
wide registers, that can conceptually be treated as one 32-bit register. The register is used as a
standard cross-peripheral identification system.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 CID3 RO 0xB1 GPIO PrimeCell ID Registe r[31 :24]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
GPIO Primecell Identification 3 (GPIOPCellID3)
Offset 0xFFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000010110001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID3
LM3S101 Data Sheet
October 5, 2006 135
Preliminary
9 General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
The LM3S101 controller General-Purpose Timer Module (GPTM) contains two GPTM blocks
(Timer0 and Timer1). Each GPTM block provides two 16-bit timer/counters (referred to as TimerA
and TimerB) that can be configured to operate independently as timers or event counters, or
configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
The following modes are supported:
32-bit Timer modes:
–Programmable one-shot timer
–Programmable periodic timer
–Real-Time Clock using 32.768-KHz input clock
–Software-controlled event stalling (excluding RTC mode)
16-bit Timer modes:
–General-purpose timer function with an 8-bit prescaler
–Programmable one-shot timer
–Programmable periodic timer
–Software-controlled event stalling
16-bit Input Capture modes:
–Input edge count capture
–Input edge time capture
16-bit PWM mode:
–Simple PWM mode with software-programmable output inversion of the PWM signal
General-Purpose Timers
136 Octo ber 5, 2006
Preliminary
9.1 Block Diagram
Figure 9-1. GPTM Module Block Diagram
9.2 Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two
16-bit load/initialization registers and their associated control functions. The exact functionality of
each GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCF G) register (see
page 147), the GPTM TimerA Mode (GPTMTAMR) register (see page 148), and the GPTM
TimerB Mode (GPTMTBMR) register (see page 149). When in one of the 32-bit modes, the timer
can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its
two 16-bit timers configured in any combination of the 16-bit modes.
9.2.1 GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all
control registers are cleared and in their default states. Counters TimerA and TimerB are initialized
to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 157) and the GPTM TimerB Interval Load (GPTMTBILR)
register (see page 158). The prescale counters are initialized to 0x00: the GPTM TimerA
Prescale (GP T MTAPR) register (see page 161) and the GPTM TimerB Prescale (GPTMTBPR)
registe r (see page 162).
TA Com parator
TB Com parator
GPTMTBR
GPTMAR
Clo ck / Edg e
Detect
RTC Divider
Clo ck / Edg e
Detect
TimerA
Interrupt
TimerB
Interrupt
System
Clock
0x000 0 (Dow n Counter M odes )
0x 0 000 (D o wn Counte r Mo des )
32KHz
CCP1
En
En
Ti m erA C o ntrol
GPTMTAPMR
GPTMTAILR
GPTMTAMATCHR
GPTMTAPR
GPTMTAMR
Ti m erB C o ntrol
GPTMTBPMR
GPTMTBILR
GPTMTBMATCHR
GPTMTBPR
GPTMTBMR
Interrupt / Config
GPTMCFG
GPTMRIS
GPTMICR
GPTMMIS
GPTMIMR
GPTMCTL
LM3S101 Data Sheet
October 5, 2006 137
Preliminary
9.2.2 32-Bit Timer Operating Modes
Note: Both the odd- and even-numbered CCP pins are used for 16-bit mode. Only the
even-numbered CCP pins are used for 32-bit mode.
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and
their configuration.
The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1
(RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain
GPTM registers are concatenated to form pseudo 32-bit registers. These registers include:
GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 157
GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 158
GPTM TimerA (GPTMTAR) register [15:0], see page 165
GPTM TimerB (GPTMTBR) register [15:0], see page 166
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write acce ss
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]. Likewise, a read access to GPTMTAR returns the
value: GPTMTBR[15:0]:GPTMTAR[15:0].
9.2.2.1 32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR)
register (see page 148), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR)
register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 150), the
timer begins counting down from its preloaded value. Once the 0x00000000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the ne x t c ycl e. I f co nfigured t o
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and output triggers when it
reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt
Status (GPTMRIS) register (see page 154), and holds it until it is cleared by writing the GPTM
Interrupt Clear (GPTMICR) register (see page 156). If the time-out interrupt is enabled in the
GPTM Interrupt M ask (GPTIMR) register (see page 152), the GPTM also sets the TATOMIS bit in
the GPTM Masked Interrupt Status (GPTMISR) register (see page 155).
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the
0x00000000 state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE
bit in GPTMCTL.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the
new value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal
is deasserted.
9.2.2.2 32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x00000001. All subsequent load values must be written to the GPTM
TimerA Match (GPTMTAMATCHR) register (see page 159) by the controller.
General-Purpose Timers
138 Octo ber 5, 2006
Preliminary
The 32KHZ pin is dedicated to the 32-bit RTC function, and the input clock is 32.768 KHz.
When software writes the TAEN bit in GPTMCTL, the counter starts counting up from its preloaded
value of 0x00000001. When the current count value matches the preloaded value in
GPTMTAMATCHR, it rolls over to a value of 0x00000000 and continues counting until either a
hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the
GPTM asse rts t he RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM
also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are
cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bit s in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
9.2.3 16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 147). This section describes each of the GPTM 16-bit modes of
operation. Timer A and Timer B have identical modes, so a single description is given using an n
to reference both.
9.2.3.1 16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with
an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The
selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale
(GPTMTnPR) regis ter.
When software writes the TnEN bit in the GPTMCTL register , the timer begins counting down from
its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from
GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer
stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer,
it continues coun tin g.
In addition to reloading the count value, the timer generates interrupts and output triggers when it
reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it
until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR,
the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt.
The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000
state, and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the
GPTMCTL register, and can trigger SoC-level events.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the
new value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal
is deasserted.
The following example shows a variety of configurations for a 16-bit free running timer while using
the prescaler. All values assume a 20-MHz clock with Tc=20 ns (clock period).
LM3S101 Data Sheet
October 5, 2006 139
Preliminary
9.2.3.2 16-Bit Input Edge Count Mode
In Edge Count mode, the timer is configured as a down-counter capable of capturing three types
of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit
of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined
by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match
(GPTMTnMATCHR) register is configured so that the difference between the value in the
GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events th at
must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register , the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event
count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in
the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then
reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the
TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are
ignored until TnEN is re-enabled by software.
Figure 9-2 shows how input edge count mode works. In this case, the timer start value is set to
GPTMnILR=0x000A and the match value is set to GPTMnMATCHR=0x0006 so that four edge
events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit af te r
the current count matches the value in the GPTMnMR register.
Table 9-1. 16-Bit Timer With Prescaler Configurations
Prescale #Clock (TC)aMax Time Units
00000000 1 3.2768 mS
00000001 2 6.554 mS
00000010 3 9.8302 mS
------------ --
11111100 254 832.3073 mS
11111110 255 835.584 mS
11111111 256 838.8608 mS
a. TC is the clock period.
General-Purpose Timers
140 Octo ber 5, 2006
Preliminary
Figure 9-2. 16-Bit Input Edge Count Mode Example
9.2.3.3 16-Bit Input Edge Time Mode
In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value
loaded in the GPTMTnILR register (or 0x FFFF at reset). This mode allows for event capture of
both rising and falling edges. The timer is placed into Edge Ti me mode by setting the TnCMR bit in
the GPTMTnMR register, and the type of event that the timer captures is determined by the
TnEVENT fi elds of the GPTMCTL regis t e r.
When software writes the TnEN bit in the GPTMCTL reg ister, the timer is enabled for event
capture. When the selected input event is detected, the current Tn counter value is captured in the
GPTMTnR register and is available to be read by the controller. The GPTM then asserts the
CnERIS bit (and the CnEMIS bit, if the inter rupt is not mask ed).
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR regis t e r.
Figure 9-3 shows how input edge timing mode works. In the diagram, it is assumed that the start
value of the timer i s the de fault va lue of 0 xFFFF, and the tim er i s co nfigured to cap ture ris ing edge
events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
0x000A
0x0006
0x0007
0x0008
0x0009
Input S ig nal
Timer stops,
flags
asserted
Timer reload
on next cycle Ignored Ignored
Count
LM3S101 Data Sheet
October 5, 2006 141
Preliminary
Figure 9-3. 16-Bit Input Edge Time Mode Example
9.2.3.4 16-Bit PWM Mode
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled
with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TNCMR bit to 0x0, and the TnMR
field to 0x2.
PWM mode can take advantage of the 8-bit prescaler by using the GPTM Timern Prescale
Regist er (GPTMTnPR) and the GPTM Timern Prescale Match Register (GPTMTnPMR). This
effectively extends the range of the timer to 24 bits.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by
software clear i ng the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted
in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timern
Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM
signal by se tting the TnPWML bit in the GPTMCTL register.
Figure 9-4 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle
assuming a 50-MHz input clock and TnPWML=0 (duty cycle would be 33% for the TnPWML=1
configur at ion ). For this exa mpl e, the start value is GPTMnIRL=0 xC3 50 and the match val ue is
GPTMnMR=0x411A.
GPTMTnR=Y
Input S ig nal
Time
Count
GPTMTnR=X GPTMTnR=Z
Z
X
Y
0xFFFF
General-Purpose Timers
142 Octo ber 5, 2006
Preliminary
Figure 9-4. 16-Bit PWM Mode Example
9.3 Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the GPTM0 and
GPTM1 bits in the RCGC1 register.
This section shows module initialization and configuration examples for each of the supported
timer modes.
9.3.1 32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Writ e the GPTM Configuration Register (GPTMCFG) with a value of 0x0.
3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Load the start value into the GPTM TimerA Inte rval Load Register (GPTMTAILR).
5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register
(GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if
enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the
GPTM Interrupt Cle ar Register (GPTMICR).
Output
Signal
Time
Count
GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR
0xC350
0x411A
TnP WML = 0
TnP WML = 1
TnEN set
LM3S101 Data Sheet
October 5, 2006 143
Preliminary
In One-Shot mode, the timer stops counting after step 7. To re-enable the timer, repeat the
sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.2 32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on its 32KHz pin. To enable
the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Writ e the GPTM Configuration Register (GPTMCFG) with a value of 0x1.
3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR).
4. Set/clea r the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register
(GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x00000000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
9.3.3 16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Writ e the GPTM Configuration Register (GPTMCFG) with a value of 0x4.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register
(GPTMTnPR).
5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register
(GPTMIMR).
7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if
enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the
GPTM Interrupt Cle ar Register (GPTMICR).
In One-Shot mode, the timer stops counting after step 8. To re-enable the timer, repeat the
sequence. A timer configured in Periodic mode does not stop counting after it times out.
9.3.4 16-Bit Input Edge Count Mode
A timer is configured to Input Edge Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Writ e the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
General-Purpose Timers
144 Octo ber 5, 2006
Preliminary
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the
GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register.
7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge
events.
9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if
enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the
GPTM Interrupt Clear (GPTMICR) register.
In Input Edge Count Mode, the timer stops after the desired number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat steps 4-9.
9.3.5 16-Bit Input Edge Tim ing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Writ e the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start
counting.
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if
enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the
GPTM Interrupt Clear (GPTMICR) register. The time at which the event happened can be
obtained by reading the GPTM Timern (GPTMTnR) regis t er.
In Input Edge T iming mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
9.3.6 16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Writ e the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TNCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT
field of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
LM3S101 Data Sheet
October 5, 2006 145
Preliminary
7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR)
registe r and the GPTM Timern Prescale Match (GPTMTnPMR) register.
8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change
takes effect at the next cycle after the write.
9.4 Register Map
Table 9-1 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s
address, relative to that timer’s base address:
Timer0: 0x40030000
Timer1: 0x40031000
Table 9-2. GPTM Register Map
Offset Name Reset Type Description See
page
0x000 GPTMCFG 0x00000000 R/W Configuration 147
0x004 GPTMTAMR 0 x00000000 R/W TimerA mode 148
0x008 GPTMTBMR 0x00000000 R/W TimerB mode 149
0x00C GPTMCTL 0x00000000 R/W Control 150
0x018 GPTMIMR 0x00000000 R/W Interrupt mask 152
0x01C GPTMRIS 0x00000000 RO Interrupt status 154
0x020 GPTMMIS 0x00000000 RO Masked interrupt status 155
0x024 GPTMICR 0x00000000 W1C Interrupt clear 156
0x028 GPTMTAILR 0x0000FFFFa
0xFFFFFFFF R/W TimerA interval load 157
0x02C GPTMTBILR 0x0000FFFF R/W TimerB interval load 158
0x030 GPTMTAMATCHR 0x0000FFFFa
0xFFFFFFFF R/W TimerA match 159
0x034 GPTMTBMATCHR 0x0000FFFF R/W TimerB match 160
0x038 GPTMTAPR 0x00000000 R/W TimerA prescale 161
0x03C GPTMTBPR 0x00000000 R/W TimerB prescale 162
0x040 GPTMTAPMR 0x00000000 R/W TimerA prescale match 163
0x044 GPTMTBPMR 0x00000000 R/W TimerB prescale match 164
General-Purpose Timers
146 Octo ber 5, 2006
Preliminary
9.5 Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by
address offset.
0x048 GPTMTAR 0x0000FFFFa
0xFFFFFFFF RO TimerA 165
0x04C GPTMTBR 0x0000FFFF RO TimerB 166
a. The default reset value for the GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers is 0x0000FFFF when in 16-bit mode
and 0xFFFFFFFF when in 32-bit mode.
Table 9-2. GPTM Register Map (Continued)
Offset Name Reset Type Description See
page
LM3S101 Data Sheet
October 5, 2006 147
Preliminary
Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this
register determines whether the GPTM is in 32- or 16-bit mode.
Bit/Field Name Type Reset Description
31:3 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
2:0 GPTMCFG R/W 0 GPTM Configuratio n
0x0: 32-bit timer configuration.
0x1: 32-bit real-time clock (RTC) counter configuration.
0x2: Reserved.
0x3: Reserved.
0x4-0x7: 16-bit timer configuration, function is controlled by bits
1:0 of GPTMTAMR and GPTMTBMR.
reserved
RO
0
GPTM Configuration (GPTMCFG)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
reserved
GPTMCFG
General-Purpose Timers
148 Octo ber 5, 2006
Preliminary
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to
0x2.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 TAAMS R/W 0 GPTM TimerA Alternate Mode Select
0: Capture mode is enabled.
1: PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TACMR
bit and set the TAMR field to 0x2.
2 TACMR R/W 0 GPTM Time rA Capture Mode
0: Edge-Coun t mode.
1: Edge-Time mode.
1:0 TAMR R /W 0 GPTM Time rA Mode
0x0: Reserved.
0x1: One-Shot Timer mode.
0x2: Periodic Timer mode.
0x3: Capture mode.
The Timer mode is based on the timer configuratio n defined by
bits 2:0 in the GPTMCFG register (16-or 32-bit).
In 16-bit timer configuration, TAMR controls the 16-bit timer
modes for TimerA.
In 32-bit timer configuration, this register controls the mode and
the cont ents of GPTMTBMR are ignored.
reserved
RO
0
GPTM TimerA Mode (GPTMTAMR)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
reserved
TAMR
TAAMS TACMR
LM3S101 Data Sheet
October 5, 2006 149
Preliminary
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to
0x2.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
3 TBAMS R/W 0 GPTM TimerB Alternate Mode Select
0: Capture mode is enabled.
1: PWM mode is enabled.
Note: To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
2 TBCMR R/W 0 GPTM TimerB Capt ure Mode
0: Edge-Coun t mode.
1: Edge-Time mode.
1:0 TBMR R/W 0 GPTM TimerB Mode
0x0: Reserved.
0x1: One-Shot Timer mode.
0x2: Periodic Timer mode.
0x3: Capture mode.
The timer mode is based on the timer configuration defined by
bits 2:0 in the GPTMCFG register.
In 16-bit timer configuration, these bits control the 16-bit timer
modes for TimerB.
In 32-bit timer configuration, this register’s contents are ignored
and GPTMTAMR is used.
reserved
RO
0
GPTM TimerB Mode (GPTMTBMR)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
reserved
TBMR
TBAMS TBCMR
General-Purpose Timers
150 Octo ber 5, 2006
Preliminary
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger.
Bit/Field Name Type Reset Description
31:15 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
14 TBPWML R/W 0 GPTM TimerB PWM Output Level
0: Output is unaffected.
1: Output is inverted.
13 TBOTE R/W 0 GPTM TimerB Output Trigger Enable
0: The output TimerB trigger is disabled.
1: The output TimerB trigger is enabled.
12 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
11:10 TBEVENT R/W 0 GPTM TimerB Event Mode
00: Positive edge.
01: Negative edge.
10: Reserved.
11: Both edges.
9 TBSTALL R/W 0 GPTM TimerB Stall Enable
0: TimerB stalling is disabled.
1: TimerB stalling is enabled.
8 TBEN R/W 0 GPTM TimerB Enable
0: TimerB is disabled.
1: TimerB is ena bl ed and begin s co unti ng or the capture log ic is
enabled bas ed on the GPTMCFG register.
7 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
res
RO
0
GPTM Control (GPTMCTL)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W
TBPWML
reserved
res TBEVENT
resTBOTE TBSTALL TBEN TAPWML TAEVENT
TAOTE TASTALL TAEN
RTCEN
LM3S101 Data Sheet
October 5, 2006 151
Preliminary
6 TAPWML R/W 0 GPTM TimerA PWM Output Level
0: Output is unaffected.
1: Output is inverted.
5 TAOTE R/W 0 GPTM TimerA Output Trigger Enable
0: The output TimerA trigger is disabled.
1: The output TimerA trigger is enabled.
4 RTCEN R/W 0 GPTM RTC Enable
0: RTC counting is disabled.
1: RTC counting is enabled.
3:2 TAEVENT R/W 0 GPTM Ti merA Event Mode
00: Positive edge.
01: Negative edge.
10: Reserved.
11: Both edges.
1 TASTALL R/W 0 GPTM TimerA Stall Enable
0: TimerA stalling is disabled.
1: TimerA stalling is enabled.
0 TAEN R/W 0 GPTM TimerA Enable
0: TimerA is disabled.
1: TimerA is ena bl ed and begin s co unti ng or the capture log ic is
enabled bas ed on the GPTMCFG register.
Bit/Field Name Type Reset Description
General-Purpose Timers
152 Octo ber 5, 2006
Preliminary
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1
enables the interrupt, while writing a 0 disables it.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 CBEIM R/W 0 GPTM CaptureB Event Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
9 CBMIM R/W 0 GPTM CaptureB Match Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
8 TBTOI M R/W 0 GPTM TimerB Time-Ou t Interrupt M ask
0: Interrupt is disabled.
1: Interrupt is enabled.
7:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 RTCIM R/W 0 GPTM RTC Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
2 CAEIM R/W 0 GPTM CaptureA Event Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
reserved
RO
0
GPTM Interrupt Mask (GPTMIMR)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W
CBEIM
reserved
CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM
LM3S101 Data Sheet
October 5, 2006 153
Preliminary
1 CAMIM R/W 0 GPTM CaptureA Match Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
0 TATOIM R/W 0 GPTM TimerA Time-Out Interrupt Mask
0: Interrupt is disabled.
1: Interrupt is enabled.
Bit/Field Name Type Reset Description
General-Purpose Timers
154 Octo ber 5, 2006
Preliminary
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR r egister. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 CBERIS RO 0 GPTM CaptureB Event Raw Interrupt
This is the CaptureB Event interrupt status prior to masking.
9 CBMRIS RO 0 GPTM CaptureB Match Raw Interrupt
This is the CaptureB Match interrupt status prior to masking.
8 TBTORIS RO 0 GPTM TimerB Time-Out Raw Interrupt
This is the TimerB time-out interrupt status prior to masking.
7:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 RTCRIS RO 0 GPTM RTC Raw Interrupt
This is the RTC Event interrupt status prior to masking.
2 CAERIS RO 0 GPTM CaptureA Event Raw Interrupt
This is the CaptureA Event interrupt status prior to masking.
1 CAMRIS RO 0 GPTM CaptureA Match Raw Interrupt
This is the CaptureA Match interrupt status prior to masking.
0 TATORIS RO 0 GPTM TimerA Time-Out Raw Interrupt
This the TimerA time-out interrupt status prior to masking.
reserved
RO
0
GPTM Raw Interrupt Status (GPTMRIS)
Offset 0x01C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
CBERIS
reserved
CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS
LM3S101 Data Sheet
October 5, 2006 155
Preliminary
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 CBEMIS RO 0 GPTM CaptureB Event Masked Interrupt
This is the Capture B even t interrupt status after masking.
9 CBMMI S RO 0 GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
8 TBTOMIS RO 0 GPTM TimerB Time-Out Masked Inte rrupt
This is the TimerB time-out interrupt status after masking.
7:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 RTC M IS RO 0 GPTM RTC Masked Inte rrupt
This is the RTC event interrupt status after masking.
2 CAEMIS RO 0 GPTM CaptureA Even t Masked Interrupt
This is the Capture A even t interrupt status after masking.
1 CAMMI S RO 0 GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
0 TATOMIS RO 0 GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
reserved
RO
0
GPTM Masked Interrupt Status (GPTMMIS)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
CBEMIS
reserved
CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS
General-Purpose Timers
156 Octo ber 5, 2006
Preliminary
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 CBECINT W1C 0 GPTM CaptureB Event Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
9 CBMCINT W1C 0 GPTM CaptureB Match Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
8 TBTOCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
7:4 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
3 RTCCINT W1C 0 GPTM RTC Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
2 CAECINT W1C 0 GPTM Captu reA Event Interrupt Clear
0: The interrupt is unaffected.
1: The interrupt is clea red .
1 CAMCINT W1C 0 GPTM CaptureA Match Raw Interrupt
This is the CaptureA match interrupt status after masking.
0 TATOCINT W1C 0 GPTM TimerA Time-Out Raw Interrupt
0: The interrupt is unaffected.
1: The interrupt is clea red .
reserved
RO
0
GPTM Interrupt Clear (GPTMICR)
Offset 0x024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00000 0000000000
RO RO RO W1C W1C W1C W1C RO RO RO RO W1C W1C W1C W1C
CBECINT RTCCINT
reserved
CBMCINT TBTOCINT reserved CAECINT CAMCINTTATOCINT
LM3S101 Data Sheet
October 5, 2006 157
Preliminary
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028
This register is used to load the starting count value into the timer. When GPTM is configured to
one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond
to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.
Bit/Field Name Type Reset Description
31:16 TAILRH R/W 0xFFFF
(32-bit
mode)
0x0000
(16-bit
mode)
GPTM TimerA Interval Load Register High
When configured for 32-bit mode via the GPTMCFG register,
the GPTM TimerB Interval Lo ad (GPTMTBILR) re gister l oads
this value on a write. A read returns the current value of
GPTMTBILR.
In 16-bit mode, this field read s as 0 and d oes not hav e an ef fect
on the state of GPTMTBILR.
15:0 TAILRL R/W 0xFFFF GPTM TimerA Interval Load Register Low
For both 16- and 32-bit modes, writing this field loads the
counter for TimerA. A read returns the current value of
GPTMTAILR.
TAILRL
R/W
1/0
GPTM TimerA Interval Load (GPTMTAILR)
Offset 0x028
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W
1
Reset
Type
111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TAILRH
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
General-Purpose Timers
158 Octo ber 5, 2006
Preliminary
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C
This register is used to load the starting count value into TimerB. When the GPTM is configured to
a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
15:0 TBILRL R/W 0xFFFF GPTM Ti merB Interval Load Register
When the GPTM is not configured as a 32-bit timer, a write to
this field updates GPTMTBILR. In 32-bit mode, writes are
ignored, and reads return the current value of GPTMTBILR.
TBILRL
RO
0
GPTM TimerB Interval Load (GPTMTBILR)
Offset 0x02C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
R/W
1
Reset
Type 111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
LM3S101 Data Sheet
October 5, 2006 159
Preliminary
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count
modes.
Bit/Field Name Type Reset Description
31:16 TAMRH R/W 0xFFFF
(32-bit
mode)
0x0000
(16-bit
mode)
GP TM TimerA Match Regi ste r High
When configured for 32-bit Real -Time C lock (RTC) mode via
the GPTMCFG register, this value is compared to the upper
half of GPTMTAR, to determine match events.
In 16-bit mode, this field read s as 0 and d oes not hav e an ef fect
on the state of GPTMTBMATCHR.
15:0 TAMRL R/W 0xFFFF GP TM TimerA Match Registe r Low
When configured for 32-bit Real -Time C lock (RTC) mode via
the GPTMCFG register, this value is compa red to the lo wer half
of GPTMTAR, to determine match events.
When configured for PWM mode, this value along with
GPTMTAILR, determines the duty cycle of the output PWM
signal.
When configured for Edge Count mode, this value along with
GPTMTAILR, determines how many edge events are counted.
The total number of edge events counted is equal to the value
in GPTMTAILR minus this value.
R/W
Offset 0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
Type
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TAMRH
GPTM TimerA Match (GPTMTAMATCHR)
TAMRL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W
1
Reset
Type
111111111111111
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
General-Purpose Timers
160 Octo ber 5, 2006
Preliminary
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034
This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count
modes.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
15:0 TBMRL R/W 0xFFFF GP TM TimerB Match Registe r Low
When configured for PWM mode, this value along with
GPTMTBILR, determines the duty cycle of the output PWM
signal.
When configured for Edge Count mode, this value along with
GPTMTBILR, determines ho w ma ny e dge ev ent s are counted.
The total number of edge events counted is equal to the value
in GPTMTBILR minus this value.
TBMRL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W
0
Reset
Type 000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
GPTM TimerB Match (GPTMTBMATCHR)
RO
0
Offset 0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
LM3S101 Data Sheet
October 5, 2006 161
Preliminary
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038
This register allows software to extend the range of the 16-bit timers.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminat e value, and should never
be changed.
7:0 TAPSR R/W 0 GPTM T im erA Prescale
The register loads this value on a write. A read returns the
current value of the register.
Refer to Table 9-1 on page 139 for more details and an
example.
reserved
RO
0
GPTM TimerA Prescale (GPTMTAPR)
Offset 0x038
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
TAPSR
General-Purpose Timers
162 Octo ber 5, 2006
Preliminary
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C
This register allows software to extend the range of the 16-bit timers.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminat e value, and should never
be changed.
7:0 TBPSR R/W 0 GPTM TimerB Prescale
The register loads this value on a write. A read returns the
current value of this register.
Refer to Table 9-1 on page 139 for more details and an
example.
reserved
RO
0
GPTM TimerB Prescale (GPTMTBPR)
Offset 0x03C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
TBPSR
LM3S101 Data Sheet
October 5, 2006 163
Preliminary
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040
This register effectively extends the range of GPTMTAMATCHR to 24 bits.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminat e value, and should never
be changed.
7:0 TAPSMR R/W 0 GPTM TimerA Prescale Match
This valu e is us ed alon gside GPTMTAMATCHR to detect timer
match events while using a prescaler.
reserved
RO
0
GPTM TimerA Prescale Match (GPTMTAPMR)
Offset 0x040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
TAPSMR
General-Purpose Timers
164 Octo ber 5, 2006
Preliminary
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044
This register effectively extends the range of GPTMTBMATCHR to 24 bits.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminat e value, and should never
be changed.
7:0 TBPSMR R/W 0 GPTM TimerB Prescale Match
This value is used along side GPTMTBMATCHR to dete ct tim er
match events while using a prescaler.
reserved
RO
0
GPTM TimerB Prescale Match (GPTMTBPMR)
Offset 0x044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
TBPSMR
LM3S101 Data Sheet
October 5, 2006 165
Preliminary
Register 17: GPTM TimerA (GPTMTAR), offset 0x048
This register shows the current value of the TimerA counter in all cases except for Input Edge
Count mode. When in this mode, this register contains the time at which the last edge event took
place.
Bit/Field Name Type Reset Description
31:16 TARH RO 0xFFFF
(32-bit
mode)
0x0000
(16-bit
mode)
GPTM TimerA Register High
If the GPTMCFG i s in a 32-bit mode, T ime rB value is read. If the
GPTMCFG is in a 16-bit mode, this is read as zero.
15:0 TAR L RO 0xFFFF GPTM TimerA Register Low
A read returns the current value of the GPTM TimerA Count
Register, except in Inpu t Edge Count mode, w hen it retu rns the
timestamp from the last edge event.
TARL
RO
1/0
GPTM TimerA (GPTMTAR)
Offset 0x048
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
1
Reset
Type
111111111111111
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
TARH
1/0 = 1 if timer is configured in 32-bit mode; 0 if timer is configured in 16-bit mode.
General-Purpose Timers
166 Octo ber 5, 2006
Preliminary
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C
This register shows the current value of the TimerB counter in all cases except for Input Edge
Count mode. When in this mode, this register contains the time at which the last edge event took
place.
Bit/Field Name Type Reset Description
31:16 re served RO 0 Reserved bits return an in dete rminate value, and sh ould never
be changed.
15:0 TBRL RO 0xFFFF GPTM TimerB
A read returns the current value of the GPTM TimerB Count
Register, except in Inpu t Edge Count mode, w hen it retu rns the
timestamp from the last edge event.
TBRL
RO
0
GPTM TimerB (GPTMTBR)
Offset 0x04C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
1
Reset
Type 111111111111111
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
LM3S101 Data Sheet
October 5, 2006 167
Preliminary
10 Watchdog Timer
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way.
The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, a locking register, and user-enabled stalling.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first
time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has
been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
10.1 Block Diagram
Figure 10-1. WDT Module Block Diagram
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
WDTLOAD
WDTVALUE
Comparator
32-Bit Do wn
Counter
0x00000000
Interrupt
System Clock
Identification Registers
WDTPCellID0 WDTPeriphID0 WDTPeriphID4
WDTPCellID1 WDTPeriphID1 WDTPeriphID5
WDTPCellID2 WDTPeriphID2 WDTPeriphID6
WDTPCellID3 WDTPeriphID3 WDTPeriphID7
Watchdog Timer
168 Octo ber 5, 2006
Preliminary
10.2 Functional Description
The Watchdog Timer module consists of a 32-bit down counter, a programmable load register,
interrupt generation logic, and a locking register. Once the Watchdog Timer has been configured,
the W atc hdog Timer Lock (WDTLOCK) re gist er i s writ ten, wh ich prev en ts the ti mer conf igu rat ion
from being inadve r tentl y altered by so ftware.
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
After the first time-out event, the 32-bit counter is re-loaded with the value of the W atchdog T imer
Load (WDTLOAD) register, and the timer resumes counting down from that value.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and
counting resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared
by writing to the Watchdog Interrupt Clear (WDTICR) regis t er.
The Watchdog module interrupt and reset generation can be enabled or disabled as required.
When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and
not its last state.
10.3 Initialization and Configuration
To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register.
The Watchdog Timer is configured using the following sequence:
1. Load the WDTLOAD register with the desired timer load value.
2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL
register.
3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control
register.
If software requires that all of the watchdog registers are locked, the Watchdog Timer module can
be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer,
write a value of 0x1ACCE551.
10.4 Register Map
Table 10-1 lists the Watchdog registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the Watchdog Timer base address of 0x40000000.
Table 10-1. WDT Register Map
Offset Name Reset Type Description See
page
0x000 WDTLOAD 0xFFFFFFFF R/W Load 170
0x004 WDTVALUE 0xFFFFFFFF RO Current value 171
0x008 WDTCTL 0x00000000 R/W Control 172
LM3S101 Data Sheet
October 5, 2006 169
Preliminary
10.5 Register Descriptions
The remainder of this section lists and describes the WDT registers, in numerical order by address
offset.
0x00 C WD TICR - WO Interr upt cl ear 173
0x010 WDTRIS 0x00000000 RO Raw interrupt status 174
0x014 WDTMIS 0x00000000 RO Masked interrupt status 175
0x418 WDTTEST 0x00000000 R/W Watchdog stall enable 177
0xC00 WDTLOCK 0x00000000 R/W Lock 176
0xFD0 WDTPeriphID4 0x00000000 RO Peripheral identi fic ati on 4 178
0xFD4 WDTPeriphID5 0x00000000 RO Peripheral identi fic ati on 5 179
0xFD8 WDTPeriphID6 0x00000000 RO Peripheral identi fic ati on 6 180
0xFDC WDTPeriphID7 0x00000000 RO Peripheral identi fic ati on 7 181
0xFE0 WDTPeriphID0 0x00000005 RO Peripheral identi fic ati on 0 182
0xFE4 WDTPeriphID1 0x00000018 RO Peripheral identi fic ati on 1 183
0xFE8 WDTPeriphID2 0x00000018 RO Peripheral identi fic ati on 2 184
0xFEC W DTPerip hID 3 0x00000001 RO Peripheral identific ati on 3 185
0xFF0 WDTPCellID0 0x0000000D RO PrimeCell identification 0 186
0xFF4 WDTPCellID1 0x000000F0 RO PrimeCell identification 1 187
0xFF8 WDTPCellID2 0x00000005 RO PrimeCell identification 2 188
0xFFC WDTPCellID3 0x000000B1 RO PrimeCell identification 3 189
Table 10-1. WDT Register Map (Continued)
Offset Name Reset Type Description See
page
Watchdog Timer
170 Octo ber 5, 2006
Preliminary
Register 1: Watchdog Load (WDTLOAD), offset 0x000
This register is the 32-bit interval value used by the 32-bit counter . When this register is written, the
value is immediately loaded and the counter restarts counting down from the new value. If the
WDTLOAD register is loaded with 0x00000000, an interrupt is immediately generated.
Bit/Field Name Type Reset Description
31:0 WDTLoad R/W 0xFFFFFFFF Watchdog Load Value
WDTLoad
R/W
1
Watchdog Load (WDTLOAD)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W
1
Reset
Type 111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
WDTLoad
LM3S101 Data Sheet
October 5, 2006 171
Preliminary
Register 2: Watchdog Value (WDTVALUE), offset 0x004
This register contains the current count value of the timer.
Bit/Field Name Type Reset Description
31:0 WDTValue RO 0xFFFFFFFF Watchdog Value
Current value of the 32-bit down counter.
WDTValue
RO
1
Watchdog Value (WDTVALUE)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 111111111111111
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
1
Reset
Type 111111111111111
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
WDTValue
Watchdog Timer
172 Octo ber 5, 2006
Preliminary
Register 3: Watchdog Control (WDTCTL), offset 0x008
This register is the watchdog control register. The watchdog timer can be configured to generate a
reset signal (upon second time-out) or an interrupt on time-out.
When the watchdog interrupt has been enabled, all subsequent writes to the control register are
ignored. The only mechanism that can re-enable writes is a hardware reset.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
1 RESEN R/W 0 Watchdog Reset Enable
0: Disabled.
1: Enable the Watchdog module reset output.
0 INTEN R/W 0 Watchdog Interrupt Enable
0: Interrupt event disabled (once this bit is set, it can only
be cleared by a hardware reset)
1: Interrupt event enabled. Once enabled, all writes are
ignored.
reserved
RO
0
Watchdog Control (WDTCTL)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W
INTEN
reserved
RESEN
LM3S101 Data Sheet
October 5, 2006 173
Preliminary
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C
This register is the interrupt clear register. A write of any value to this register clears the W atchdog
interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is
indeterminate.
Bit/Field Name Type Reset Description
31:0 WDTIntClr WO - Watchdog Interrupt Clear
WDTIntClr
WO
-
Watchdog Interrupt Clear (WDTICR)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type ---------------
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
WO
-
Reset
Type ---------------
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
WDTIntClr
Watchdog Timer
174 Octo ber 5, 2006
Preliminary
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010
This register is the raw interrupt status register. W atchdog interrupt events can be monitored via
this register if the controller interrupt is masked.
Bit/Field Name Type Reset Description
31:1 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
0 WDTRIS RO 0 Watchdog Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of
WDTINTR.
reserved
RO
0
Watchdog Raw Interrupt Status (WDTRIS)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
WDTRIS
reserved
LM3S101 Data Sheet
October 5, 2006 175
Preliminary
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014
This register is the masked interrupt status register. The value of this register is the logical AND of
the raw interrupt bit and the Watchdog interrupt enable bit.
Bit/Field Name Type Reset Description
31:1 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
0 WDTMIS RO 0 Watchdog Masked Interrupt Status
Gives the masked interrupt state (after masking) of the
WDTINTR interrupt.
reserved
RO
0
Watchdog Masked Interrupt Status (WDTMIS)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
WDTMIS
reserved
Watchdog Timer
176 Octo ber 5, 2006
Preliminary
Register 7: Watchdog Lock (WDTLOCK), offset 0xC00
W ritin g 0x1A CCE5 51 to the WDTLOCK register enables write access to all other registers. Writing
any other value to the WDTLOCK register re-enables the locked state for register writes to all the
other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit
value written. Therefore, when write accesses are disabled, reading the WDTLOCK register
returns 0x00000001 (when locked; otherwise, the returned value is 0x00000000 (unlocked)).
Bit/Field Name Type Reset Description
31:0 WDTLock R/W 0x0000 Watchdog Lock
A write of the value 0x1ACCE551 unlocks the watchdog
registers for write access. A write of any other value
reapplies the lock, preventing any register updates.
A read of this register returns the following values:
Locked: 0x00000001
Unlocked: 0x00000000
WDTLock
R/W
0
Watchdog Lock (WDTLOCK)
Offset 0xC00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W
0
Reset
Type 000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
WDTLock
LM3S101 Data Sheet
October 5, 2006 177
Preliminary
Register 8: Watchdog Test (WDTTEST), offset 0x418
This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag
during debug.
Bit/Field Name Type Reset Description
31:9 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
8 STALL R/W 0 Watchdog Stall Enable
When set to 1, if the Stellaris microcontroller is stopped
with a debugger , th e watchdog timer stop s counti ng. Once
the microcontroller is restarted, the watchdog timer
resumes cou nting.
7:0 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
RO
0
Watchdog Test (WDTTEST)
Offset 0x418
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO
STALL
reserved
reserved reserved
Watchdog Timer
178 Octo ber 5, 2006
Preliminary
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0]
reserved
RO
0
Watchdog Peripheral Identification 4 (WDTPeriphID4)
Offset 0xFD0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID4
LM3S101 Data Sheet
October 5, 2006 179
Preliminary
Register 10: Watchdog Peripher al Identification 5 (WDTPeriphID5), offset 0xFD4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8]
reserved
RO
0
Watchdog Peripheral Identification 5 (WDTPeriphID5)
Offset 0xFD4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID5
Watchdog Timer
180 Octo ber 5, 2006
Preliminary
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16]
reserved
RO
0
Watchdog Peripheral Identification 6 (WDTPeriphID6)
Offset 0xFD8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID6
LM3S101 Data Sheet
October 5, 2006 181
Preliminary
Register 12: Watchdog Peripher al Identification 7 (WDTPeriphID7), offset 0xFDC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24]
reserved
RO
0
Watchdog Peripheral Identification 7 (WDTPeriphID7)
Offset 0xFDC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID7
Watchdog Timer
182 Octo ber 5, 2006
Preliminary
Register 13: Watchdog Peripher al Identification 0 (WDTPeriphID0), offset 0xFE0
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0]
reserved
RO
0
Watchdog Peripheral Identification 0 (WDTPeriphID0)
Offset 0xFE0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID0
LM3S101 Data Sheet
October 5, 2006 183
Preliminary
Register 14: Watchdog Peripher al Identification 1 (WDTPeriphID1), offset 0xFE4
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8]
reserved
RO
0
Watchdog Peripheral Identification 1 (WDTPeriphID1)
Offset 0xFE4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000011000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID1
Watchdog Timer
184 Octo ber 5, 2006
Preliminary
Register 15: Watchdog Peripher al Identification 2 (WDTPeriphID2), offset 0xFE8
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16]
reserved
RO
0
Watchdog Peripheral Identification 2 (WDTPeriphID2)
Offset 0xFE8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000011000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID2
LM3S101 Data Sheet
October 5, 2006 185
Preliminary
Register 16: Watchdog Peripher al Identification 3 (WDTPeriphID3), offset 0xFEC
The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24]
reserved
RO
0
Watchdog Peripheral Identification 3 (WDTPeriphID3)
Offset 0xFEC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID3
Watchdog Timer
186 Octo ber 5, 2006
Preliminary
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0]
reserved
RO
0
Watchdog Primecell Identification 0 (WDTPCellID0)
Offset 0xFF0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000001101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID0
LM3S101 Data Sheet
October 5, 2006 187
Preliminary
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8]
reserved
RO
0
Watchdog Primecell Identification 1 (WDTPCellID1)
Offset 0xFF4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000011110000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID1
Watchdog Timer
188 Octo ber 5, 2006
Preliminary
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16]
reserved
RO
0
Watchdog Primecell Identification 2 (WDTPCellID2)
Offset 0xFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID2
LM3S101 Data Sheet
October 5, 2006 189
Preliminary
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC
The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24]
reserved
RO
0
Watchdog Primecell Identification 3 (WDTPCellID3)
Offset 0xFFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000010110001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID3
Universal Asynchronous Receiver/Transmitter (UART)
190 Octo ber 5, 2006
Preliminary
11 Universal Asynchronous Receiver/Transmitter
(UART)
The Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable,
16C550-type serial interface characteristics. The LM3S101 controller is equipped with one UART
module.
The UART has the following features:
Separate transmit and receive FIFOs
Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Programmable baud-rate generator allowing rates up to 460.8 Kbps
Standard asynchronous communication bits for start, stop and parity
False start bit detect ion
Line-break generation and detection
Fully programmable serial interface characteristics:
–5, 6, 7, or 8 data bits
–Even, odd, stick, or no-parity bit generation/detection
–1 or 2 stop bit generation
LM3S101 Data Sheet
October 5, 2006 191
Preliminary
11.1 Block Diagram
Figure 11-1. UART Module Block Diagram
11.2 Functional Description
The S tellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It
is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bit s of th e UART Control
(UARTCTL) register (see page 207). Transmit and receive are both enabled out of reset. Before
any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is
completed prior to the UART stopping.
11.2.1 Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
Receiver
Transmitter
S ystem Cl ock
Control / Status
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
Interrupt C ontrol
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
Baud Rate
Generator
UARTIBRD
UARTFBRD
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UART PeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTDR
TXFIFO
16x8
.
.
.
RXFIFO
16x8
.
.
.
Interrupt
UnTx
UnRx
Universal Asynchronous Receiver/Transmitter (UART)
192 Octo ber 5, 2006
Preliminary
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the
control registers. See Figure 11-2 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid
start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are
also performed, and their status accompanies the data that is written to the receive FIFO.
Figure 11-2. UART Character Frame
11.2.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) reg is t er
(see page 203) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate
Divisor (UARTFBRD) register (see page 204). The baud-rate divisor (BRD) has the following
relationship to th e system clock (where BRDI is the integer part of the BRD and BRDF is the
fractional part, separated by a decimal place.):
BRD = BRDI + BRDF = SysClk / (16 * Baud Rate)
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD
register) can be calculated by taking the fractional part of the baud-rate divisor , multiplying it by 64,
and adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for
error detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 205), the
UARTIBRD and UARTFBRD registers form an internal 30-bit register . This internal register is only
updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate
divisor must be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
UARTIBRD write, UARTFBRD write, and UARTLCRH write
UARTFBRD write, UARTIBRD write, and UARTLCRH write
UARTIBRD write and UARTLCRH write
UARTFBRD write and UARTLCRH write
105-8 data bits
LSB MSB
Paritybit
if enabled
1-2
stop bits
UnTX
n
Start
LM3S101 Data Sheet
October 5, 2006 193
Preliminary
11.2.3 Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit
FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters
indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in
the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 201) is asserted
as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains
asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is
empty, and the last character has been transmitted from the shift register, including the stop bits.
The UART can indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the U0Rx is continuously 1) and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 (described in “Transmit/Receive Logic” on page 191).
The start bit is valid if U0Rx is still low on the eighth cycle of Baud16, otherwise a false start bit is
detected and it is ignored. S t art bit errors can be viewed in the UART Receive St atus (UARTRSR)
register (see page 199). If the start bit was valid, successive data bits are sampled on every 16th
cycle of Baud16 (that is, one bit period later) according to the programmed length of the data
characters. The parity bit is then checked if parity mode was enabled. Data length and parity are
defined in the UARTLCRH register.
Lastly, a valid stop bit is confirmed if U0Rx is High, otherwise a framing error has occurred. When
a full word is received, the data is stored in the receive FIFO, with any error bits associated with
that word.
11.2.4 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 197). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit
data in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 205).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 201) and the
UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun
conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE and RXFF bi t s)
and the UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt
FIFO Level Select (UARTIFLS) register (see page 208). Both FIFOs can be individually
configured to trigger interrupts at different levels. Available configurations include 1/8, 1/4, 1/2, 3/4
and 7/8. For example, if the 1/4 option is selected for the receive FIFO, the UART generates a
receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger
an inter rupt at the 1/2 mark.
11.2.5 Interrupts
The UART can generate interrupts when the following conditions are observed:
Overrun Error
Break Er r or
Parity Error
Framing Error
Universal Asynchronous Receiver/Transmitter (UART)
194 Octo ber 5, 2006
Preliminary
Receive Timeout
Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met)
Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
UART can only generate a single interrupt request to the controller at any given time. Software can
service multiple interrupt events in a single interrupt service routine by reading the UART Masked
Interrupt Status (UARTMIS) register (see page 212).
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt
Mask (UARTIM) register (see page 209) by setting the corresponding IM bit to 1. If interrupts are
not used, the raw interrupt status is always visible via the UART Raw Interrupt St atus (UARTRIS)
registe r (see page 211 ).
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the
corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 213).
11.2.6 Loopback Operation
The UART can be placed into an internal loopback mode for diagnostic or debug work. This is
accomplished by setting the LBE bit in the UARTCTL register (see page 207). In loopback mode,
data transmitted on U0Tx is received on the U0Rx input.
11.3 Initialization and Configuration
To use the UART, the peripheral clock must be enabled by setting the UART0 bit in the RCGC1
register.
This section discusses the steps that are required for using a UART module. For this example, the
system clock is assumed to be 20 MHz and the desired UART configuration is:
115 200 bau d rate
Data length of 8 bits
One stop bit
No parity
FIFOs disabled
No interrupts
The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the
UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the
equation described in “Baud-Rate Generation” on page 192, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 203) should be set to 10.
The value to be loaded into the UARTFBRD register (see page 204) is calculated by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following
order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
LM3S101 Data Sheet
October 5, 2006 195
Preliminary
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x00000060).
5. Enable the UART by setting the UARTEN bit in the UARTCTL register.
11.4 Register Map
Table 11-1 lists the UART registers. The offset listed is a hexadecimal increment to the register’s
address, relative to that UART’s base address:
UART0: 0x4000C00 0
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 207)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 11-1. UART Register Map
Offset Name Reset Type Description See
page
0x000 UARTDR 0x00000000 R/W Data 197
0x004 UARTRSR
UARTECR
0x00000000 R/W Receive Status (read)
Error Clear (write)
199
0x018 UARTFR 0x00000090 RO Flag Register (read only) 201
0x024 UARTIBRD 0x00000000 R/W Integer Baud-Rate Divisor 203
0x028 UART FBRD 0x0000 000 0 R/W Fractional Baud-Rate Diviso r 204
0x02 C UARTLCRH 0x000000 00 R /W Line Control Register, High by te 205
0x030 UARTCTL 0x00000300 R/W Control Register 207
0x034 UARTIFLS 0x00000012 R/W Interrupt FIFO Level Select 208
0x038 UARTIM 0x00000000 R/W Interrupt Mask 209
0x03C UART RIS 0x0000000F RO Raw Interrupt Status 211
0x040 UARTMIS 0x00000000 RO Masked Interrupt Status 212
0x044 UARTICR 0x00000000 W1C Interrupt Clear 213
0xFD0 UARTPeriphID4 0x00000000 RO Peripheral identification 4 214
0xFD4 UARTPeriphID5 0x00000000 RO Peripheral identification 5 215
0xFD8 UARTPeriphID6 0x00000000 RO Peripheral identification 6 216
0xFDC UARTPeriphID7 0x 00000000 RO Peripheral identification 7 217
0xFE0 UARTPeriphID0 0x00000011 RO Peripheral identification 0 218
0xFE4 UARTPeriphID1 0x00000000 RO Peripheral identification 1 219
0xFE8 UARTPeriphID2 0x00000018 RO Peripheral identification 2 220
0xFEC UARTPeriphID3 0x00000001 RO Peripheral identification 3 221
Universal Asynchronous Receiver/Transmitter (UART)
196 Octo ber 5, 2006
Preliminary
11.5 Register Descriptions
The remainder of this section lists and describes the UART registers, in numerical order by
address offset.
0xFF0 UARTPCellID0 0x0000000D RO PrimeCell identification 0 222
0xFF4 UARTPCellID1 0x000000F0 RO PrimeCell identification 1 223
0xFF8 UARTPCellID2 0x00000005 RO PrimeCell identification 2 224
0xFFC UARTPCellID3 0x000000B1 RO PrimeCell identification 3 225
Table 11-1. UART Register Map (Continued)
Offset Name Reset Type Description See
page
LM3S101 Data Sheet
October 5, 2006 197
Preliminary
Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit
FIFO). A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The
received data can be retrieved by reading this register.
Bit/Field Name Type Reset Description
31:12 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
11 OE RO 0 UART Overrun Error
1=New data was received when the FIFO was full, resulting in
data loss.
0=There has been no data loss due to a FIFO overrun.
10 BE RO 0 UART Break Error
This bit is se t to 1 w h en a break condition is de tec ted, indicating
that the receive data input was he ld Low for longer than a full-
word transmission time (defined as start, data, parity, and stop
bits).
In FIFO mode, this error is associated with the character at the
top of the FIFO. When a break occurs, only one 0 character is
loaded in to the FIFO. The next character is only enabled after
the received data input goes to a 1 (marking state) and the next
valid st art bit is receiv ed .
9 PE RO 0 UART Parity Error
This bit is set to 1 when the parity of the received data character
does not match the parity defined by bits 2 and 7 of the
UARTLCRH register.
In FIFO mode, this error is associated with the character at the
top of the FIFO.
reserved
RO
0
UART Data (UARTDR)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
FE
reserved
DATA
PEBE
OE
Universal Asynchronous Receiver/Transmitter (UART)
198 Octo ber 5, 2006
Preliminary
8 FE RO 0 UART Framing Error
This bit is set to 1 when the received character does not have a
valid stop bit (a valid stop bit is 1).
7:0 DATA R/W 0 When written, the data that is to be transmitted via the UART.
When read, the data that was received by the UART.
Bit/Field Name Type Reset Description
LM3S101 Data Sheet
October 5, 2006 199
Preliminary
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR regist er, re ceive s tat us c an als o be re ad fr om th e UARTRSR register . If
the status is read from this register , then the status information corresponds to the entry read from
UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when
an overrun cond iti on occur s.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors.
All the bits are cleared to 0 on reset.
Bit/Field Name Type Reset Description
Read-Only Re ceive Status (UARTRSR) R egi ster
31:4 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed. The UARTRSR register cannot be written.
3 OE RO 0 UART Overrun Error
When this bi t is set to 1, dat a is received and the FIFO is al ready
full. This bit is cleared to 0 by a write to UARTECR.
The FIFO contents remain valid since no further data is written
when the FIFO is full, only the contents of the shift register are
overwritten. The CPU must now read the data in order to empty
the FIFO.
reserved
WO
0
UART Error Clear (UARTECR): Write
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
WO
0
Reset
Type 000000000000000
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
reserved
DATA
reserved
RO
0
UART Receive Status (UARTRSR): Read
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
OE BE PE FE
Universal Asynchronous Receiver/Transmitter (UART)
200 Octo ber 5, 2006
Preliminary
2 BE RO 0 UART Break Error
This bit is se t to 1 w h en a break condition is de tec ted, indicating
that the rece ived data input was held Low for longer than a full-
word transmission time (defined as start, data, parity, and stop
bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the
top of the FIFO. When a break occurs, only one 0 character is
loaded in to the FIFO. The next character is only enabled after
the receive data input goes to a 1 (marking state) and the next
valid st art bit is receiv ed .
1 PE RO 0 UART Parity Error
This bit is set to 1 when the parity of the received data character
does not match the parity defined by bits 2 and 7 of the
UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
0 FE RO 0 UART Framing Error
This bit is set to 1 when the received character does not have a
valid stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the
top of the FIFO.
Write-Only Error Clear (UARTECR) Register
31:8 reserved WO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 DATA WO 0 A write to this register of any data clears the framing, parity,
break and overrun flags.
Bit/Field Name Type Reset Description
LM3S101 Data Sheet
October 5, 2006 201
Preliminary
Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7 TXFE RO 1 UART Transmit FIFO Empty
The meani ng of this bit depends on the st ate of the FEN bit in the
UARTLCRH register.
If the FI FO is dis abled (FEN is 0), t his b it is set when t he tran smit
holding register is empty.
If the FIFO is e nabled (FEN is 1), this bit is set when th e transm it
FIFO is empty.
6 RXFF RO 0 UART Receive FIFO Full
The meani ng of this bit depends on the st ate of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding
register is full.
If the FIFO is enabled, this bit is set when the receive FIFO is
full.
5 TXFF RO 0 UART Transmit FIFO Full
The meani ng of this bit depends on the st ate of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding
register is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is
full.
reserved
RO
0
UART Flag (UARTFR)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000010010000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
TXFE RXFF TXFF RXFE BUSY reserved
Universal Asynchronous Receiver/Transmitter (UART)
202 Octo ber 5, 2006
Preliminary
4 RXFE RO 1 UART Receive FIFO Empty
The meani ng of this bit depends on the st ate of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding
registe r is empty.
If the FIFO is enabled, this bit is set when the receive FIFO is
empty.
3 BUSY RO 0 UART Busy
When this bit is 1, the UART is busy transmitting data. This bit
remains set until the complete byte, including all stop bits, has
been sent from the shift register.
This bit is se t as soon as the transmi t FIFO bec omes non-e mpty
(regardless of whether UART is enabled).
2:0 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
Bit/Field Name Type Reset Description
LM3S101 Data Sheet
October 5, 2006 203
Preliminary
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024
The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared
on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the
UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not
take effect until transmission/reception of the current character is complete. Any changes to the
baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate
Generation” on page 192 for configuration details.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor
RO
0
UART Integer Baud-Rate Divisor
Offset 0x024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
R/W
0
Reset
Type 000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
DIVINT
Universal Asynchronous Receiver/Transmitter (UART)
204 Octo ber 5, 2006
Preliminary
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028
The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are
cleared on reset. When changing the UARTFBRD register , the new value does not take effect until
transmission/reception of the current character is complete. Any changes to the baud-rate divisor
must be f oll owed by a w rit e to th e UARTLCRH register . See “Baud-Rate Generation” on page 192
for configuration details.
Bit/Field Name Type Reset Description
31:6 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
5:0 DIVFRAC R/W 0 x00 Fractional Baud-Rate Divisor
reserved
RO
0
UART
Fractional Baud-Rate Divisor (UARTFBRD)
Offset 0x028
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
reserved
DIVFRAC
LM3S101 Data Sheet
October 5, 2006 205
Preliminary
Register 6: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7 SPS R/W 0 UART Stick Parity Select
When bits 1, 2 and 7 of UARTLCRH are set, the parity bit is
transmitt ed an d chec ked a s a 0. W hen b it s 1 and 7 a re set a nd 2
is cleared, the parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
6:5 WLEN R/W 0 UART Word Length
The bits ind ic ate the number of data bi t s tra ns mitted or receiv ed
in a frame as follows:
0x3: 8 bits
0x2: 7 bits
0x1: 6 bits
0x0: 5 bits (default)
4 FEN R/W 0 UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are
enabled (FIFO mode).
When cleared to 0, FIFOs are disabled (Character mode). The
FIFOs become 1-byte-deep holding registers.
3 STP2 R/W 0 UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a
frame. The receive logic does not check for two stop bits being
received.
reserved
RO
0
UART Line Control (UARTLCRH)
Offset 0x02C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
SPS
reserved
WLEN FEN STP2 EPS PEN BRK
Universal Asynchronous Receiver/Transmitter (UART)
206 Octo ber 5, 2006
Preliminary
2 EPS R/W 0 UART Even Parity Select
If this bit is set to 1, even parity generation and checking is
performed during transmission and reception, which checks for
an even number of 1s in data and parity bits.
When clea red to 0, then odd parity is performed, whi ch checks
for an odd number of 1s.
This bit has no effect when parity is disabled by the PEN bit.
1 PEN R/W 0 UART Parity Enable
If this bit is set to 1, parity checking and generation is enabled;
otherwise, parity is disabled and no parity bit is added to the data
frame.
0 BRK R/W 0 UART Send Break
If this bit is se t to 1, a Low level is continuall y output on the UnTX
output, after completing transmission of the current character.
For the proper execution of the break command, the software
must set this bit for at least two frames (character periods). For
normal use, this bit must be cleared to 0.
Bit/Field Name Type Reset Description
LM3S101 Data Sheet
October 5, 2006 207
Preliminary
Register 7: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are
written. If the UART is disabled during a transmit or receive operation, the current transaction is
completed prior to the UART stopping.
Bit/Field Name Type Reset Description
31:10 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
9 RXE R/W 1 UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled.
When the UART is disabled in the middle of a receive, it
completes the current character before stopping.
8 TXE R/W 1 UART Transmit Enable
If this bit is s et to 1, the tran sm it se cti on of the UAR T i s en abl ed.
When the UART is disabled in the middle of a transmission, it
completes the current character before stopping.
7 LBE R/W 0 UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
6:1 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
0 UARTEN R/W 0 UART Enable
If this bit is set to 1, the UART is enabled. When the UART is
disabled in the middle of transmission or reception, it completes
the current character before stopping.
RO
0
UART Control (UARTCR)
Offset 0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000001100000000
RO RO RO RO RO R/W R/W R/W RO RO RO RO RO RO R/W
reserved
reserved
RXE TXE LBE UARTEN
reserved
Universal Asynchronous Receiver/Transmitter (UART)
208 Octo ber 5, 2006
Preliminary
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to
define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receivin g the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an
interrupt at the half-way mark.
Bit/Field Name Type Reset Description
31:6 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
5:3 RXIFLSEL R/W 0X2 UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
000: RX FIFO ≥ 1/8 full
001: RX FIFO ≥ 1/4 full
010: RX FIFO ≥ 1/2 full (default)
011: RX FIFO ≥ 3/4 full
100: RX FIFO ≥ 7/8 full
101-111: Reserved
2:0 TXIFLSEL R/W 0X2 UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
000: TX FIFO ≤ 1/8 full
001: TX FIFO ≤ 1/4 full
010: TX FIFO ≤ 1/2 full (default)
011: TX FIFO ≤ 3/4 full
100: TX FIFO ≤ 7/8 full
101-111: Reserved
reserved
RO
0
UART Interrupt FIFO Level Select (UARTIFLS)
Offset 0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000010010
RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
reserved
TXIFLSEL
RXIFLSEL
LM3S101 Data Sheet
October 5, 2006 209
Preliminary
Register 9 : UART Interrupt Mask (UARTIM), offset 0x038
The UARTIM register is the interrupt mask set/clear register.
On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to
a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a
0 prevents the raw interrupt signal from being sent to the interrupt controller.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 OEIM R/W 0 UART Overrun Error Interrupt Mask
On a read, the current mask for the OEIM interrupt is returned.
Setting this bit to 1 promotes the OEIM interrupt to the interrupt
controller.
9 BEIM R/W 0 UART Break Error Interrupt Mask
On a read, the current mask for the BEIM interrupt is returned.
Setting this bit to 1 promotes the BEIM interrupt to the interrupt
controller.
8 PEIM R/W 0 UART Parity Error Interrupt Mask
On a read, the current mask for the PEIM interrupt is returned.
Setting this bit to 1 promotes the PEIM interrupt to the interrupt
controller.
7 FEIM R/W 0 UART Framing Error Interrupt Mask
On a read, the current mask for the FEIM interrupt is returned.
Setting this bit to 1 promotes the FEIM interrupt to the interrupt
controller.
6 RTIM R/W 0 UART Receive Time-Out Interrupt Mask
On a read, the current mask for the RTIM interrupt is returned.
Setting this bit to 1 promotes the RTIM interrupt to the interrupt
controller.
reserved
RO
0
UART Interrupt Mask (UARTIM)
Offset 0x038
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00000000000 0000
RO RO RO RO R/W R/W R/W R/W R/W R/W R/W RO RO RO RO
OEIM
reserved
BEIM PEIM FEIM RTIM TXIM RXIM reserved
Universal Asynchronous Receiver/Transmitter (UART)
210 Octo ber 5, 2006
Preliminary
5 TXIM R/W 0 UART Transmit Interrupt Mask
On a read, the current mask for the TXIM interrupt is returned.
Setting this bit to 1 promotes the TXIM interrupt to the interrupt
controller.
4 RXIM R/W 0 UART Receive Interrupt Mask
On a read, the current mask for the RXIM interrupt is returned.
Setting this bit to 1 promotes the RXIM interrupt to the interrupt
controller.
3:0 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
Bit/Field Name Type Reset Description
LM3S101 Data Sheet
October 5, 2006 211
Preliminary
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register . On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 OERIS RO 0 UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
9 BERIS RO 0 UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
8 PERIS RO 0 UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
7 FERIS RO 0 UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
5 TXRIS RO 0 UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
4 RXRIS RO 0 UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
3:0 reserved RO 0xF This reserved bit is read-only and has a reset value of 0xF.
reserved
RO
0
UART Raw Interrupt Status (UARTRIS)
Offset 0x03C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000001111
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
OERIS
reserved
BERIS PERIS FERIS RTRIS TXRIS RXRIS reserved
Universal Asynchronous Receiver/Transmitter (UART)
212 Octo ber 5, 2006
Preliminary
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 OEMIS RO 0 UART Overrun Error Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
9 BEMIS RO 0 UART Break Error Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
8 PEMIS RO 0 UART Parity Error Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
7 FEMIS RO 0 UART Framing Error Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
5 TXMIS RO 0 UART Transmit Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
4 RXMIS RO 0 UART Receive Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
3:0 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
reserved
RO
0
UART Masked Interrupt Status (UARTMIS)
Offset 0x040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
OEMIS
reserved
BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS reserved
LM3S101 Data Sheet
October 5, 2006 213
Preliminary
Register 12: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 OEIC W1C 0 Overrun Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
9 BEIC W1C 0 Break Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
8 PEIC W1C 0 Parity Error Interrupt Clea r
0: No effect on the interrupt.
1: Clears interrupt.
7 FEIC W1C 0 Framing Error Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
6 RTIC W1C 0 Receive Time-Out Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
5 TXIC W1C 0 Transmit Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
4 RXIC W1C 0 Receive Interrupt Clear
0: No effect on the interrupt.
1: Clears interrupt.
3:0 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
reserved
RO
0
UART Interrupt Clear (UARTICR)
Offset 0x044
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO W1C W1C W1C W1C W1C W1C W1C RO RO RO RO
OEIC
reserved
BEIC PEIC FEIC RTIC TXIC RXIC reserved
Universal Asynchronous Receiver/Transmitter (UART)
214 Octo ber 5, 2006
Preliminary
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID4 RO 0x00 UART Peripheral ID Register[7:0]
reserved
RO
0
UART Peripheral Identification 4 (UARTPeriphID4)
Offset 0xFD0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID4
LM3S101 Data Sheet
October 5, 2006 215
Preliminary
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID5 RO 0x00 UART Peripheral ID Register[15:8]
reserved
RO
0
UART Peripheral Identification 5 (UARTPeriphID5)
Offset 0xFD4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID5
Universal Asynchronous Receiver/Transmitter (UART)
216 Octo ber 5, 2006
Preliminary
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID6 RO 0x00 UART Peripheral ID Register[23:16]
reserved
RO
0
UART Peripheral Identification 6 (UARTPeriphID6)
Offset 0xFD8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID6
LM3S101 Data Sheet
October 5, 2006 217
Preliminary
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID7 RO 0x00 UART Peripheral ID Register[31:24]
reserved
RO
0
UART Peripheral Identification 7 (UARTPeriphID7)
Offset 0xFDC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID7
Universal Asynchronous Receiver/Transmitter (UART)
218 Octo ber 5, 2006
Preliminary
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7:0 PID0 RO 0 x11 UART Peripheral ID Register[7:0]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
UART Peripheral Identification 0 (UARTPeriphID0)
Offset 0xFE0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000010001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID0
LM3S101 Data Sheet
October 5, 2006 219
Preliminary
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7:0 PID1 RO 0x00 UART Peripheral ID Register[15:8]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
UART Peripheral Identification 1 (UARTPeriphID1)
Offset 0xFE4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID1
Universal Asynchronous Receiver/Transmitter (UART)
220 Octo ber 5, 2006
Preliminary
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7:0 PID2 RO 0x18 UART Peripheral ID Register[23:16]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
UART Peripheral Identification 2 (UARTPeriphID2)
Offset 0xFE8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000011000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID2
LM3S101 Data Sheet
October 5, 2006 221
Preliminary
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC
The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7:0 PID3 RO 0x01 UART Peripheral ID Register[31:24]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
UART Peripheral Identification 3 (UARTPeriphID3)
Offset 0xFEC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID3
Universal Asynchronous Receiver/Transmitter (UART)
222 Octo ber 5, 2006
Preliminary
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7:0 CID0 RO 0x0D UART PrimeCell ID Register[7:0]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
UART Primecell Identification 0 (UARTPCellID0)
Offset 0xFF0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000001101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID0
LM3S101 Data Sheet
October 5, 2006 223
Preliminary
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7:0 CID1 RO 0xF0 UART PrimeCell ID Register[15:8]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
UART Primecell Identification 1 (UARTPCellID1)
Offset 0xFF4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000011110000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID1
Universal Asynchronous Receiver/Transmitter (UART)
224 Octo ber 5, 2006
Preliminary
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7:0 CID2 RO 0x05 UART PrimeCell ID Register[23:16]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
UART Primecell Identification 2 (UARTPCellID2)
Offset 0xFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID2
LM3S101 Data Sheet
October 5, 2006 225
Preliminary
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bi ts return an indeterminate value, and should never
be changed.
7:0 CID3 RO 0xB1 UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
UART Primecell Identification 3 (UARTPCellID3)
Offset 0xFFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000010110001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID3
Synchronous Serial Interface (SSI)
226 Octo ber 5, 2006
Preliminary
12 Synchronous Serial Interface (SSI)
The Stellaris Synchronous Serial Interface (SSI) is a master or slave interface for synchronous
serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or
Texas Instrume nts sync hr on ous serial interfaces.
The Stellaris SSI has the following features:
Master or slave operation
Programmable clock bit rate and prescale
Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
Programmable data frame size from 4 to 16 bits
Internal loopback test mode for diagnostic/debug testing
12.1 Block Diagram
Figure 12-1. SSI Module Block Diagram
Transmit/
Rec eive
Logic
Clock
Prescaler
SSICPSR
C ontrol / Status
SSICR0
SSICR1
SSISR
Interrupt Control
SSIIM
SSIMIS
SSIRIS
SSIICR
SSIDR
TxFIFO
8 x 16
.
.
.
RxFIFO
8 x 16
.
.
.
System Clock
SSITx
SSIRx
SSIClk
SSIFss
Interrupt
Identification Regi sters
SSIPCellID0 SSIPeriphID0 SSIPeriphID4
SSIPCellID1 SSIPeriphID1 SSIPeriphID5
SSIPCellID2 SSIPeriphID2 SSIPeriphID6
SSIPCellID3 SSIPeriphID3 SSIPeriphID7
LM3S101 Data Sheet
October 5, 2006 227
Preliminary
12.2 Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The
CPU accesses data, control, and status information. The transmit and receive paths are buffered
with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both
transmit and receive modes.
12.2.1 Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 1.5 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the 20-MHz input clock. The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 244). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see
page 238).
The frequency of the output clock SSIClk is defined by:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note that although the SSIClk transmit clock can theoretically be 10 MHz, the module may not be
able to operate at that speed. For transmit operations, the system clock must be at least two times
faster than the SSIClk. For receive operations, the system clock must be at least 12 times faster
than the SSIClk.
See “Electrical Characteristics” on page 282 to view SSI timing parameters.
12.2.2 FIFO Operation
12.2.2.1 T ransmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 242), and data is
stored in the FIFO until it is read out by the transmission logic.
When configured as a master or a slave, parallel data is written into the transmit FIFO prior to
serial conversion and transmission to the attached slave or master, respectively, through the
SSITx pin.
12.2.2.2 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer.
Received data from the serial interface is stored in the buffer until read out by the CPU, which
accesses the read FIFO by reading the SSIDR register.
When configured as a master or slave, serial data received through the SSIRx pin is registered
prior to parallel loading into the attached slave or master receive FIFO, respectively.
12.2.3 Interrupts
The SSI can generate interrupts when the following conditions are observed:
Transmit FIFO service
Receive FIFO service
Receive FIFO time-out
Receive FIFO overrun
Synchronous Serial Interface (SSI)
228 Octo ber 5, 2006
Preliminary
All of the interrupt events are ORed together before being sent to the interrupt controller, so the
SSI can only generate a single interrupt request to the controller at any given time. You can mask
each of the four individual maskable interrupts by setting the appropriate bits in the S SI Interrupt
Mask (SSIIM) register (see page 245). Setting the appropriate mask bit to 1 enables the interrupt.
Provision of the individual outputs, as well as a combined interrupt output, allows use of either a
global interrupt service routine, or modular device drivers to handle interrupts. The transmit and
receive dynamic dataflow interrupts have been separated from the status interrupts so that data
can be read or written in response to the FIFO trigger levels. The status of the individual interrupt
sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt
Status (SSIMIS) registers (see page 246 and page 247, respectively).
12.2.4 Frame Formats
Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. There are three basic frame types that can be selected:
Texas Instrume nts sync hr on ous serial
Freescale SPI
MICROWIRE
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk
transitions at the programmed frequency only during active transmission or reception of data. The
idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive
FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss) pin is active Low,
and is asserted (pulled down) during the entire transmission of the frame.
For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial
clock period starting at its rising edge, prior to the transmission of each frame. For this frame
format, both the SSI and the off-chip slave device drive their output data on the rising edge of
SSIClk, and latch data from the other device on the falling edge.
Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a
special master-slave messaging technique, which operates at half-duplex. In this mode, when a
frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no
incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes
it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent,
responds with the requested data. The returned data can be 4 to 16 bits in length, making the total
frame length anywhere from 13 to 25 bits.
12.2.4.1 T exas Instruments Synchronous Serial Frame Format
Figure 12-2 shows the Texas Instruments synchronous serial frame format for a single transmitted
frame.
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer)
SSIClk
4to16bits
SSIFss
SSITx/SSIRx MSB LSB
LM3S101 Data Sheet
October 5, 2006 229
Preliminary
In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated
whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is
pulsed High for one SSIClk period. The value to be transmitted is also transferred from the
transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk,
the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the
received data is shifted onto the SSIRx pin by the off-chip serial slave device.
Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on
the falling edge of each SSIClk. The received data is transferred from the serial shifter to the
receive FIFO on the first rising edge of SSIClk after the LSB has been latched.
Figure 12-3 shows the Texas Instruments synchronous serial frame format when back-to-back
frames are transmitted.
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer)
12.2.4.2 Freescale SPI Frame Format
The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave
select. The main feature of the Freescale SPI format is that the inactive state and phase of the
SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control
register.
SPO Clock Polarity Bit
When the SPO clock polarity control bit is Low, it produces a steady state Low value on the
SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when
data is not being transferred.
SPH Phase Control Bit
The SPH phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted by either allowing or not allowing a clock
transition before the first data capture edge. When the SPH phase control bit is Low, data is
captured on the first clock edge transition. If the SPH bit is High, data is captured on the second
clock edge transition.
12.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and
SPH=0 are shown in Figure 12-4 and Figure 12-5.
MSB
LSB
4to16bits
SSIClk
SSIFss
SSITx/SSIRx
Synchronous Serial Interface (SSI)
230 Octo ber 5, 2006
Preliminary
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
In this configuration, during idle periods:
SSIClk is forced Low
SSIFss is forced High
The transmit data line SSITx is arbi trar il y force d Low
When the SSI is configured as a master, it enables the SSIClk pad
When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled
onto the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later , valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further
half SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be
pulsed High between each data word transfer. This is because the slave select pin freezes the
data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero.
Therefore, the master device must raise the SSIFss pin of the slave device between each data
transfer to enable the serial peripheral data write. On completion of the continuous transfer, the
SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured.
12.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in
Figure 12-6, which covers both single and continuous transfers.
4to16bits
SSIClk
SSIFss
SSIRx Q
SSITx MSB
MSB
LSB
LSB
SSIClk
SSIFss
SSIRx LSB
SSITx MSB LSB
4to16bits
LSB MSB
MSB
MSB
LSB
LM3S101 Data Sheet
October 5, 2006 231
Preliminary
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1
In this configuration, during idle periods:
SSIClk is forced Low
SSIFss is forced High
The transmit data line SSITx is arbi trar il y force d Low
When the SSI is configured as a master, it enables the SSIClk pa d
When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx outp ut is ena ble d.
After a further one half SSIClk period, both master and slave valid data is enabled onto their
respective transmission lines. At the same time, the SSIClk is enabled with a rising edge
transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk
signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is
returned to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data
words and termination is the same as that of the single word transfer.
12.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 12-7 and Figure 12-8.
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
4to16bits
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
QMSB
LSB
LSB
4to16bits
SSIClk
SSIFss
SSIRx
SSITx
QMSB
MSB LSB
LSB
Synchronous Serial Interface (SSI)
232 Octo ber 5, 2006
Preliminary
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0
In this configuration, during idle periods:
SSIClk is forced High
SSIFss is forced High
The transmit data line SSITx is arbi trar il y force d Low
When the SSI is configured as a master, it enables the SSIClk pa d
When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low, which causes slave data to be
immediately transferred onto the SSIRx line of the master. The master SSITx output pad is
enabled.
One half period later, valid master data is transferred to the SSITx line. Now that both the master
and slave data have been set, the SSIClk master clock pin becomes Low after one further half
SSIClk period. This means that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be
pulsed High between each data word transfer. This is because the slave select pin freezes the
data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero.
Therefore, the master device must raise the SSIFss pin of the slave device between each data
transfer to enable the serial peripheral data write. On completion of the continuous transfer, the
SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured.
12.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in
Figure 12-9, which covers both single and continuous transfers.
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1
Note: Q is undefined in Figure 12-9.
SSIClk
SSIFss
SSITx/SSIRx MSB LSB
4to16bits
LSB MSB
4to16bits
SSIClk
SSIFss
SSIRx
SSITx
Q Q
MSB
MSB
LSB
LSB
LM3S101 Data Sheet
October 5, 2006 233
Preliminary
In this configuration, during idle periods:
SSIClk is forced High
SSIFss is forced High
The transmit data line SSITx is arbi trar il y force d Low
When the SSI is configured as a master, it enables the SSIClk pa d
When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low . The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their
respective trans mi ssion line s. At the same time, SSIClk is enabled with a falling edge transition.
Data is then captured on the rising edges and propagated on the falling edges of the SSIClk
signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described
above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data
words and termination is the same as that of the single word transfer.
12.2.4.7 MICROWIRE Frame Format
Figure 12-10 shows the MICROWIRE frame format, again for a single frame. Figure 12-11 shows
the same format when back-to-back frames are transmitted.
Figure 12-10. MICROWIRE Frame Format (Single Frame)
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead
of full-duplex, using a master-slave message passing technique. Each serial transmission begins
with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the
off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control
message has been sent, responds with the required data. The returned data is 4 to 16 bits in
length, making the total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
SSIClk is forced Low
SSIFss is forced High
The transmit data line SSITx is arbi trar il y force d Low
SSIClk
SSIFss
LSBMSB
SSIRx
4to16bits
output data
0
SSITx MSB LSB
8-bit control
Synchronous Serial Interface (SSI)
234 Octo ber 5, 2006
Preliminary
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of
SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to
the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out
onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx
pin remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of
each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a
one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is
driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the
rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled
High one clock period after the last bit has been latched in the receive serial shifter, which causes
the data to be transferred to the receive FIFO.
Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk
after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High.
For continuous transfers, data transmission begins and ends in the same manner as a single
transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data
occurs back-to-back. The control byte of the next frame follows directly after the LSB of the
received data from the current frame. Each of the received values is transferred from the receive
shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI.
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer)
In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of
SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that
the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of
SSIClk.
Figure 12-12 illustrates these setup and hold time requirements. With respect to the SSIClk rising
edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a
setup of at least two times the period of SSIClk on which the SSI operates. With respect to the
SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk
period.
8-bit control
SSIClk
SSIFss
LSBMSB
SSIRx
4to16bits
output data
0
SSITx MSB LSBLSB
MSB
LM3S101 Data Sheet
October 5, 2006 235
Preliminary
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
12.3 Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x00000000.
b. For slave mode (output enabled), set the SSICR1 register to 0x00000004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Writ e the SSICR0 register with the following configuration:
–Serial clock rate (SCR)
–Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
–The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
–The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
Master operation
Freescale SPI mode (SPO=1, SPH=1)
1 Mbps bit rate
8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) ' 1x106 = 20x106 / (CPSDVSR * (1 +
SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Writ e the SSICR1 register with a value of 0x00000000.
SSIClk
SSIFss
SSIRx
First RX data to be
sam
p
led b
y
SSI slave
tSetup =(2*tSSIClk )
tHold=tSSIClk
Synchronous Serial Interface (SSI)
236 Octo ber 5, 2006
Preliminary
3. Writ e the SSICPSR register with a value of 0x00000002.
4. Writ e the SSICR0 register with a value of 0x000009C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
12.4 Register Map
Table 12-1 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s
address, relative to the SSI base address of 0x40008000.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the
control registers are reprogrammed.
Table 12-1. SSI Register Map
Offset Name Reset Type Description See
page
0x000 SSICR0 0x00000000 RW Control 0 238
0x004 SSICR1 0x00000000 RW Control 1 240
0x008 SSIDR 0x00000000 RW Data 242
0x00C SSISR 0x00000003 RO Status 243
0x010 SSICPSR 0x00000000 RW Clock prescale 244
0x014 SSIIM 0x00000000 RW Interrupt mask 245
0x018 SSIRIS 0x0000000 8 RO Raw interrupt statu s 246
0x01C SSIMIS 0x00000000 RO Masked interrupt status 247
0x020 SSIICR 0x00000000 W1C Interrupt clear 248
0xFD0 SSIPeriphID4 0x00000000 RO Peripheral identification 4 249
0xFD4 SSIPeriphID5 0x00000000 RO Peripheral identification 5 250
0xFD8 SSIPeriphID6 0x00000000 RO Peripheral identification 6 251
0xFDC SSIPeriphID7 0x00000000 RO Peripheral identification 7 252
0xFE0 SSIPeriphID0 0x00000022 RO Peripheral identification 0 253
0xFE4 SSIPeriphID1 0x00000000 RO Peripheral identification 1 254
0xFE8 SSIPeriphID2 0x00000018 RO Peripheral identification 2 255
0xFEC SSIPeriphID3 0x00000001 RO Peripheral identification 3 256
0xFF0 SSIPCellID0 0x0000000D RO PrimeCell identification 0 257
0xFF4 SSIPCellID1 0x000000F0 RO PrimeCell identification 1 258
0xFF8 SSIPCellID2 0x00000005 RO PrimeCell identification 2 259
0xFFC SSIPCellID3 0x000000B1 RO PrimeCell identification 3 260
LM3S101 Data Sheet
October 5, 2006 237
Preliminary
12.5 Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
Synchronous Serial Interface (SSI)
238 Octo ber 5, 2006
Preliminary
Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate and data size are configured in this
register.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
15:8 SCR R/W 0 SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit
rate of the SSI. The bit rate is:
BR= FSSICLK/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even valu e from 2-254 pro grammed in the
SSICPSR register, and SCR is a value from 0-255.
7 SPH R/W 0 SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data
and allows it to change state. It has the most impact on the first
bit transmitted by either allowing or not allowing a clock
transition before the first data capture edge.
When the SPH bit is 0, data is captured on the first clock edge
transitio n. If SPH is 1, data is capt ured on the sec ond c loc k ed ge
transition.
6 SPO R/W 0 SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on
the SSIClk pin. If SPO is 1, a steady state High value is placed
on the SSIClk pin when data is not being transferred.
RO
0
SSI Control 0 (SSICR0)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
R/W
0
Reset
Type 000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
FRF DSSSCR SPO
SPH
LM3S101 Data Sheet
October 5, 2006 239
Preliminary
5:4 FRF R/W 0 SSI Frame Format Select.
The FRF values are defined as follows:
3:0 DSS R/W 0 SSI Data Size Select
The DSS values are defined as follows:
Bit/Field Name Type Reset Description
FRF Value Frame Format
00 Freescale SPI Frame Format
01 Texas Instruments Synchronous
Serial Frame Format
10 MICROWIRE Frame Format
11 Reserved
DSS Value Data Size
0000-0010 Reserved
0011 4-bit data
0100 5-bit data
0101 6-bit data
0110 7-bit data
0111 8-bit data
1000 9-bit data
1001 10-bit data
1010 11-bit data
1011 12-bit data
1100 13-bit data
1101 14-bit data
1110 15-bit da ta
1111 16-bit data
Synchronous Serial Interface (SSI)
240 Octo ber 5, 2006
Preliminary
Register 2: SSI Control 1 (SSICR1), offset 0x004
SSICR1 is control register 1 and contains bit fields that control various functions within the SSI
module. Master and slave mode functionality is controlled by this register.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
3 SOD R/W 0 SSI Slave Mode Output Disable
This bit is relevant only in the Slave mode (MS=1). In
multiple-slave systems, it is possible for the SSI master to
broadcast a message to all slaves in the system while
ensuring tha t only one slave drives data o nto the s eri al output
line. In such systems, the TXD lines from mult iple slaves
could be tied together. To operate in such a system, the SOD
bit can be configured so that the SSI slave does not drive the
SSITx pin.
0: SSI can drive SSITx output in Slave Output mode.
1: SSI must not drive the SSITx output in Slave mode.
2 MS R/W 0 SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified
only when SSI is disabled (SSE=0).
0: Device configured as a master.
1: Device configured as a slave.
reserved
RO
0
SSI Control 1 (SSCR1)
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
reserved
LBM
SSEMS
SOD
LM3S101 Data Sheet
October 5, 2006 241
Preliminary
1 SSE R/W 0 SSI Synchronous Serial Port Enable
Setting this bit enables SSI operation.
0: SSI operation disabled.
1: SSI operation enabled.
Note: This bit must be set to 0 before any control registers
are reprogramm ed .
0 LBM R/W 0 SSI Loopback Mode
Setting this bit enables Loopback Test mode.
0: Normal serial port ope rati on enabled.
1: Output of the transmit serial shift register is connected
internally to the input of the receive serial shift register.
Bit/Field Name Type Reset Description
Synchronous Serial Interface (SSI)
242 Octo ber 5, 2006
Preliminary
Regist er 3: SSI Data (SSIDR), offset 0x008
SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO
(pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI
receive logic from the incoming data frame, they are placed into the entry in the receive FIFO
(pointed to by the current FIFO write pointer).
When SSIDR is written to, the entry in the transmit FIFO (poin te d to by th e w ri t e p oi n te r ) is wr it te n
to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is
loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the
programmed bit rate.
When a data size of less than 16 bits is selected, the user must right-justify data written to the
transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is
automatically right-justified in the receive buffer.
When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is
eight bits (the most significant byte is ignored). The receive data size is controlled by the
programmer . The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the
SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the
SSI.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
15:0 DATA R/W 0 SSI Receive/Transmit Data
A read operation reads the receive FIFO. A write operation
writes the transmit FIFO.
Software must right-justify data when the SSI is programmed
for a data size that is less than 16 bits. Unused bits at the top
are ignored by the transmit logic. The receive logic
automatically right-justifies the data.
DATA
RO
0
SSI Data (SSIDR)
Offset 0x008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
R/W
0
Reset
Type 000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
LM3S101 Data Sheet
October 5, 2006 243
Preliminary
Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy
status.
Bit/Field Name Type Reset Description
31:5 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
4 BSY RO 0 SSI Busy Bit
0: SSI is idle.
1: SSI is cur rently tr ansmitting a nd/or recei ving a fram e, or the
transmit FIFO is not empty.
3 RFF RO 0 SSI Receive FIFO Full
0: Receive FIFO is not full.
1: Receive FIFO is full.
2 RNE RO 0 SSI Receive FIFO Not Empty
0: Receive FIFO is empty.
1: Receive FIFO is not empty.
1 T NF RO 1 SSI Transmit FIFO Not Full
0: Transmit FIFO is full.
1: Transmit FIFO is not full.
0 TFE R0 1 SSI Transmit FIFO Empty
0: Transmit FIFO is not empty.
1: Transmit FIFO is empty.
reserved
RO
0
SSI Status (SSISR)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000011
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
TFE
TNFRNE
RFFBSY
Synchronous Serial Interface (SSI)
244 Octo ber 5, 2006
Preliminary
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
7:0 CPSDVSR R/W 0 SSI Clock Prescale Divisor
This valu e must be an eve n numbe r from 2 to 25 4, depen ding
on the frequency of SSIClk. The LSB always returns 0 on
reads.
reserved
RO
0
SSI Clock Prescale (SSICPSR)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
CPSDVSR
LM3S101 Data Sheet
October 5, 2006 245
Preliminary
Regist er 6: SSI Interrupt Mask (SSIIM), offset 0x 014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the
corresponding mask.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
3 TXIM R/W 0 SSI Transmit FIFO Interrupt Mask
0: TX FIFO half-full or less condition interrupt is masked.
1: TX FIFO half-full or less condition interrupt is not masked.
2 RXIM R/W 0 SSI Receive FIFO Interrupt Mask
0: RX FIFO half-full or more condition interrupt is masked.
1: RX FIFO half-full or more condition interrupt is not masked.
1 RTIM R/W 0 SSI Receive Time-Out Interrupt Mask
0: RX FIFO time-out interrupt is masked.
1: RX FIFO time-out interrupt is not masked.
0 RORIM R/W 0 SSI Receive Overrun Interrupt Mask
0: RX FIFO overrun interrupt is masked.
1: RX FIFO overrun interrupt is not masked.
reserved
RO
0
SSI Interrupt Mask (SSIIM)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
reserved
RORIM
RTIMRXIM
TXIM
Synchronous Serial Interface (SSI)
246 Octo ber 5, 2006
Preliminary
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
3 TXRIS RO 1 SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status
Indicates that the re ceive FIFO is half full or more, when set.
1 RTRIS RO 0 SSI Receive Time-Ou t Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
0 RORRIS RO 0 SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
reserved
RO
0
SSI Raw Interrupt Status (SSIRIS)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000001000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
RORRIS
RTRISRXRIS
TXRIS
LM3S101 Data Sheet
October 5, 2006 247
Preliminary
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
3 TXMIS RO 0 SSI Transmit FIFO Masked Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status
Indicates that the re ceive FIFO is half full or more, when set.
1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status
Indicates that the receive time-out has occurred, when set.
0 RORMIS RO 0 SSI Receive Overrun Masked Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
reserved
RO
0
SSI Masked Interrupt Status (SSIMIS)
Offset 0x01C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
RORMIS
RTMISRXMIS
TXMIS
Synchronous Serial Interface (SSI)
248 Octo ber 5, 2006
Preliminary
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
1 RTIC W1C 0 SSI Receive Time-Out Interrupt Clear
0: No effect on interrupt.
1: Clears interrupt.
0 RORIC W1C 0 SSI Receive Overrun Interrupt Clear
0: No effect on interrupt.
1: Clears interrupt.
reserved
RO
0
SSI Interrupt Clear (SSIICR)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C
reserved
RORIC
RTIC
LM3S101 Data Sheet
October 5, 2006 249
Preliminary
Register 10: SSI Peripheral Id entification 4 (SSIPeriphID4), offset 0xFD0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID4 RO 0x00 SSI Peripheral ID Register[7:0]
reserved
RO
0
SSI Peripheral Identification 4 (SSIPeriphID4)
Offset 0xFD0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID4
Synchronous Serial Interface (SSI)
250 Octo ber 5, 2006
Preliminary
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID5 RO 0x00 SSI Peripheral ID Register[15:8]
reserved
RO
0
SSI Peripheral Identification 5 (SSIPeriphID5)
Offset 0xFD4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID5
LM3S101 Data Sheet
October 5, 2006 251
Preliminary
Register 12: SSI Peripheral Id entification 6 (SSIPeriphID6), offset 0xFD8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID6 RO 0x00 SSI Peripheral ID Register[23:16]
reserved
RO
0
SSI Peripheral Identification 6 (SSIPeriphID6)
Offset 0xFD8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID6
Synchronous Serial Interface (SSI)
252 Octo ber 5, 2006
Preliminary
Register 13: SSI Peripheral Id entification 7 (SSIPeriphID7), offset 0xFDC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
7:0 PID7 RO 0x00 SSI Peripheral ID Register[31:24]
reserved
RO
0
SSI Peripheral Identification 7 (SSIPeriphID7)
Offset 0xFDC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID7
LM3S101 Data Sheet
October 5, 2006 253
Preliminary
Register 14: SSI Peripheral Id entification 0 (SSIPeriphID0), offset 0xFE0
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
7:0 PID0 RO 0x22 SSI Peripheral ID Register[7:0]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
SSI Peripheral Identification 0 (SSIPeriphID0)
Offset 0xFEO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000100010
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID0
Synchronous Serial Interface (SSI)
254 Octo ber 5, 2006
Preliminary
Register 15: SSI Peripheral Id entification 1 (SSIPeriphID1), offset 0xFE4
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
7:0 PID1 RO 0x00 SSI Peripheral ID Register [15:8]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
SSI Peripheral Identification 1 (SSIPeriphID1)
Offset 0xFE4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID1
LM3S101 Data Sheet
October 5, 2006 255
Preliminary
Register 16: SSI Peripheral Id entification 2 (SSIPeriphID2), offset 0xFE8
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
7:0 PID2 RO 0x18 SSI Peripheral ID Register [23:16]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
SSI Peripheral Identification 2 (SSIPeriphID2)
Offset 0xFE8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000011000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID2
Synchronous Serial Interface (SSI)
256 Octo ber 5, 2006
Preliminary
Register 17: SSI Peripheral Id entification 3 (SSIPeriphID3), offset 0xFEC
The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
7:0 PID3 RO 0x01 SSI Peripheral ID Register [31:24]
Can be used by software to identify the presence of this
peripheral.
reserved
RO
0
SSI Peripheral Identification 3 (SSIPeriphID3)
Offset 0xFEC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
PID3
LM3S101 Data Sheet
October 5, 2006 257
Preliminary
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
7:0 CID0 RO 0x0D SSI PrimeCell ID Register [7 :0]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
SSI Primecell Identification 0 (SSIPCellID0)
Offset 0xFF0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000001101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID0
Synchronous Serial Interface (SSI)
258 Octo ber 5, 2006
Preliminary
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
7:0 CID1 RO 0xF0 SSI PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
SSI Primecell Identification 1 (SSIPCellID1)
Offset 0xFF4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000011110000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID1
LM3S101 Data Sheet
October 5, 2006 259
Preliminary
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
7:0 CID2 RO 0x05 SSI PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
SSI Primecell Identification 2 (SSIPCellID2)
Offset 0xFF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000000000101
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID2
Synchronous Serial Interface (SSI)
260 Octo ber 5, 2006
Preliminary
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC
The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset
value.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
7:0 CID3 RO 0xB1 SS I PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
SSI Primecell Identification 3 (SSIPCellID3)
Offset 0xFFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 000000010110001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID3
LM3S101 Data Sheet
October 5, 2006 261
Preliminary
13 Analog Comparators
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S101 controller provides two independent integrated analog comparators that can be
configured to drive an output1 or generate an interrupt.
A comparator can compare a test voltage against any one of these voltages:
An individual external reference voltage
A shared single external reference voltage
A shared inte rn al refer enc e vol tage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to
start capturing a sample sequence. The interrupt generation logic is separate.
13.1 Block Diagram
Figure 13-1. Analog Comparator Module Block Diagram
13.2 Functional Description
Important: It is recommended that the Digital-Input enable (the GPIODEN bit in th e GPIO
module) for the anal og input pin be disabled to preven t excessive cur rent draw fr om
the I/ O pads .
The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
1.Not all comparators ha ve the o ption to d rive an o utput pin. See Ta ble 13-1 and Tab le 13-2 for more
information.
interrupt
C1-
<none> output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 1
ACSTAT1
ACCTL1
<none>
Voltage
Ref
ACREFCTL
output
+ve input (alternate)
+ve input
interrupt
-ve input
reference input
Comparator 0
ACSTAT0
ACCTL0
C0+
internal
bus
interrupt
C0-
C0o
Analog Comparators
262 Octo ber 5, 2006
Preliminary
As shown in Figure 13-2, the input source for VIN- is an external input. In addition to an external
input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference.
Figure 13-2. Structure of Comparator Unit
A comparator is configured through two status/control registers (ACCTL and ACSTAT). The
internal reference is configured through one control register (ACREFCTL). Interrupt status and
control is configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating
modes of the comparators are shown in Table 13-1 and Table 13-2.
Typically, the comparator output is used internally to generate controller interrupts. It may also be
used to drive an external pin.
Important: Certain register bit values must be set before using the analog comparators. The
proper pad configuration f or the comparator input and output pins are described in
Table 8-1 on page 101.
Table 13-1. Comparator 0 Operating Modes
ACCNTL0 Comparator 0
ASRCP VIN- VIN+ Output Interrupt
00 C0- C0+ C0o/C1- yes
01 C0- C0+ C0o/C1- yes
10 C0- Vref C0o/C1- yes
11 C0- reserved C0o/C1- yes
Table 13-2. Comparator 1 Operating Modes
ACCNTL1 Comparator 1
ASRCP VIN- VIN+ Output Interrupt
00 C0o/C1-an/a n/a yes
01 C0o/C1- C0+ n/a yes
10 C0o/C1- Vref n/a yes
output
-ve input
+ve input
interrupt
internal
bus
+ve input (alternate)
reference input
ACSTAT
ACCTL
IntGen
2
1
0
CINV
LM3S101 Data Sheet
October 5, 2006 263
Preliminary
13.2.1 Internal Reference Programming
The structure of the internal reference is shown in Figure 13-3. This is controlled by a single
configuration register (ACREFCTL). Table 13-3 shows the programming options to develop
specific internal reference values, to compare an external voltage against a particular voltage
generated internally.
Figure 13-3. Comparator Internal Reference Structure
11 C0o/C1- reserved n/a yes
a. C0o and C1- signals share a single pin and may only be used as one or the other.
Table 13-3. Internal Reference Voltage and ACREFCTL Field Values
ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
EN=0 RNG=X 0 V (GND) for any value of VREF; however, it is recommended that
RNG=1 and VREF=0 for the least noisy ground reference.
Table 13-2. Comparator 1 Operating Modes
ACCNTL1 Comparator 1
ASRCP VIN- VIN+ Output Interrupt
8R R R 8R
RR •••
••• 0
Decoder
115 14
AVDD
EN
internal
reference
VREF
RNG
Analog Comparators
264 Octo ber 5, 2006
Preliminary
13.3 Initialization and Configuration
The following example shows how to configure analog comparator to read back its output value
from an internal re gister.
1. Enable the analog comparator 0 clock by writing a value of 0x00100000 to the RCGC1 register
in the System Control module.
2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input.
3. Configure the internal voltage refer ence to 1.65 V by writing t he ACREFCTL register with the
value 0x0000030C.
4. Configure comparator 0 to use the internal voltage reference and to not output a value on the
C0O pin by writing the ACCTL0 register with the value of 0x0000040C.
5. Delay for some time.
6. Read the comparator output value by reading the ACSTAT0 register’s OVAL value.
Change the level of the signa l input on C0- to see the OVAL value change.
EN=1 RNG=0 Total resistance in ladder is 32 R.
The range of internal reference in this mode is 0.825–2.37 V.
RNG=1 Total resistance in ladder is 24 R.
The range of internal reference for this mode is 0.0–2.0625 V.
Table 13-3. Internal Reference Voltage and ACREFCTL Field Values (Continued)
ACREFCTL Register Output Reference Voltage Based on VREF Field Value
EN Bit Value RNG Bit Value
VREF AVDD RVREF
RT
----------------×=
VREF AVDD VREF 8+()
32
-----------------------------×=
VREF 0.825 0.103 VREF⋅+=
VREF AVDD RVREF
RT
----------------×=
VREF AVDD VREF()
24
--------------------×=
VREF 0.1375 VREF⋅=
LM3S101 Data Sheet
October 5, 2006 265
Preliminary
13.4 Register Map
Table 13-4 lists the comparator registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the Analog Comparator base address of 0x4003C000.
13.5 Register Descriptions
The remainder of this section lists and describes the Analog Comparator registers, in numerical
order by address offset.
Table 13-4. Analog Comparator Register Map
Offset Name Reset Type Description See
page
0x00 ACMIS 0x00000000 RO Interrupt status 266
0X04 ACRIS 0x0 000 000 0 RO Raw interrupt statu s 267
0X08 ACINTEN 0x00000000 R/W Interrupt enable 268
0x10 ACREFCTL 0x00000000 R/W Reference voltage control 269
0x20 ACSTAT0 0x00000000 RO Comparator 0 status 270
0x40 ACSTAT1 0x00000000 RO Comparator 1 status 270
0x24 ACCTL0 0x00000000 RW Comparator 0 control 271
0x44 ACCTL1 0x00000000 RW Comparator 1 control 271
Analog Comparators
266 Octo ber 5, 2006
Preliminary
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00
This register provides a summary of the interrupt status (masked) of the comparators.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should never
be chang ed.
1 IN1 RO 0 Comparator 1 Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
0 IN0 RO 0 Comparator 0 Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
reserved
RO
0
Analog Comparator Masked Interrupt Status (ACMIS)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
0
IN0
RO
0
IN1
RO
0
LM3S101 Data Sheet
October 5, 2006 267
Preliminary
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04
This register provides a summary of the interrupt status (raw) of the comparators.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should never
be chang ed.
1 IN1 RO 0 When set, indicates that an interrupt has been generated by
comparator 1.
0 IN0 RO 0 When set, indicates that an interrupt has been generated by
comparator 0.
reserved
RO
0
Analog Comparator Raw Interrupt Status (ACRIS)
Offset 0x04
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
0
IN0
RO
0
IN1
RO
0
Analog Comparators
268 Octo ber 5, 2006
Preliminary
Register 3: Analog Comparat or Interrupt Enabl e (ACINTEN), offset 0x08
This register provides the interrupt enable for the comparators.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should never
be chang ed.
1 IN1 R/W 0 When set, enab les the c ontroll er inte rrupt fr om the c ompa rato r 1
output.
0 IN0 R/W 0 When set, enab les the c ontroll er inte rrupt fr om the c ompa rato r 0
output.
reserved
RO
0
Analog Comparator Interrupt Enable (ACINTEN)
Offset 0x08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
0
IN0
R/W
0
IN1
R/W
0
LM3S101 Data Sheet
October 5, 2006 269
Preliminary
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10
This register specifies whether the resistor ladder is powered on as well as the range and tap.
Bit/Field Name Type Reset Description
31:10 reserved RO 0 Res erved bits return an indeterminate value, and should
never be changed.
9 EN R/W 0 The EN bit specifies whether the resistor ladder is powered
on. If 0, the resistor ladder is unpowered. If 1, the resistor
ladder is connected to the analog VDD.
This bit is reset to 0 so that the internal referenc e consumes
the least amount of power if not used and programmed.
8 RNG R/W 0 The RNG bit specifies the range of the resistor ladder. If 0, the
resistor ladder has a total resistance of 32 R. If 1, the resistor
ladder has a total resistance of 24 R.
7:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
3:0 VREF R/W 0 The VREF bit field specifies the resistor ladder tap that is
passed through an analog multiplexer. The voltage
corresponding to the tap position is the internal reference
volt age availab le for comp arison. See Table 13-3 on p age 263
for some output r eference voltage exam ples.
reserved
RO
0
Analog Comparator Reference Voltage Control (ACREFCTL)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
0
RNG
R/W
0
EN
R/W
0R/W
0
R/W
0
R/W
0
R/W
0
VREF
Analog Comparators
270 Octo ber 5, 2006
Preliminary
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40
These registers specify the current output value of that comparator.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
1 OVAL RO 0 The OVAL bit specifies the current output value of the
comparator.
0 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
reserved
RO
0
Analog Comparator Status 0 (ACSTAT0)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
0
RO
0
OVAL
RO
00
reserved
LM3S101 Data Sheet
October 5, 2006 271
Preliminary
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44
These registers configure that comparator’s input and output.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
10:9 ASRCP R/W 0 The ASRCP field specifies the source of input voltage to the
VIN+ terminal of the comparator. The encodings for this field
are as fol l ows:
8:5 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
4 ISLVAL R/W 0 The ISLVAL bit specifies the sense value of the input that
generates an interrupt if in Level Sense mode. If 0, an
interrupt is generated if the comparator output is Low.
Otherwise, an interrupt is generated if the comparator output
is High.
3:2 ISEN R/W 0 The ISEN field specifie s the sen se of the comparator output
that generates an interrupt. The sense condi tio nin g is as
follows:
reserved
RO
0
Analog Comparator Control 0 (ACCTL0)
Offset 0x024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type 000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type 00000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
0
RO
0
RO
0
R/W
0
R/W
0
ASRCP
RO
0
RO
0
ISLVAL
R/W
0R/W
0
R/W
0
ISEN
RO
0
CINV
R/W
0
reservedreserved
ASRCP Function
00 Pin value
01 Pin value of C0+
10 Internal vo lt ag e reference
11 Reserved
ISEN Function
00 Level sens e, see ISLVAL
01 Falling edge
10 Rising edge
11 Either edge
Analog Comparators
272 Octo ber 5, 2006
Preliminary
1 CINV R/W 0 The CINV bit conditionally inverts the output of the
comparator . If 0, the output of the comparator is unchanged. If
1, the output of the comparator is inverted prior to being
processed by hardware.
0 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
Bit/Field Name Type Reset Description
LM3S101 Data Sheet
October 5, 2006 273
Preliminary
14 Pin Diagram
Figure 14-1 shows the pin diagram and pin-to-signal-name mapping.
Figure 14-1. Pin Connection Diagram
27 PC1/TMS/SWDIO
28 PC0/TCK/SWCLK
4
PB4/C0- 25 PC3/TDO/SWO
26 PC2/TDI
6
LDO
7
VDD
8
GND 21 GND
22 VDD
9
OSC0
10
OSC1 19 PB0/CCP0
20 PB1/32KHz
11
PA0/U0Rx
12
PA1/U0Tx 17 VDD
18 GND
13
PA2/SSIClk
14
PA3/SSIFss 15 PA4/SSIRx
16 PA5/SSITx
1
PB7/TRST
5
RST
2
PB6/C0+
3
PB5/C0o/C1-
23 PB2
24 PB3
LM3S101
Signal Tabl es
274 Octo ber 5, 2006
Preliminary
15 Signal Tables
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register (see page 114).
Important: All multiplexed pins are GPIOs by d efault, with the exception of the five JTAG pins
(PB7 and PC[3:0]) which default to the JTAG functionality.
Table 15-1 shows the pin-to-signal-name mapping, including functional characteristics of the
signals. Table 15-2 lists the signals in alphabetical order by signal name. Table 15-3 groups the
signals by functionality, except for GPIOs. Table 15-4 lists the GPIO pins and their alternate
functionality.
Table 15-1. Signals by Pin Number (Sheet 1 of 2)
Pin
Number Signal Name Pin
Type Buffer
Type Description
1 PB7 I/O TTL GPIO port B bit 7.
TRST I TTL JTAG TAP reset input.
2 PB6 I/O TTL GPIO port B bit 6.
C0+ I Analog Analog comparator 0 positive reference input.
3 PB5 I/O TTL GPIO port B bit 5.
C0o O TTL Analog comparator 0 output.
C1– I Analog Analog comparator 1 negative reference input.
4 PB4 I/O TTL GPIO port B bit 4.
C0– I Analog Analog comparator 0 negative reference input.
5RST I TTL System reset input.
6 LDO - Power The low dro p-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 μF or greater.
7 VDD - Power Positive supply for logic and I/O pins.
8 GND - Power Ground reference for logic and I/O pins.
9 OSC0 I Analog Oscillator crystal input or an external clock reference input.
10 OSC1 O Analog Oscillator crystal output.
11 PA0 I/O TTL GPIO port A bit 0.
U0Rx I TTL UART0 receive data input.
12 PA1 I/O TTL GPIO port A bit 1.
U0Tx O TTL UART0 transmit data output.
13 PA2 I/O TTL GPIO port A bit 2.
SSIClk I/O TTL SSI clock reference (input when in slave mode and output in
master mode).
LM3S101 Data Sheet
October 5, 2006 275
Preliminary
14 PA3 I/O TTL GPIO port A bit 3.
SSIFss I/O TTL SSI frame enable (input for an SSI slave device and output for an
SSI ma ste r device).
15 PA4 I/O TTL GPIO port A bit 4.
SSIRx I TTL SSI receive data input.
16 PA5 I/O TTL GPIO port A bit 5.
SSITx O TTL SSI transmit data output.
17 VDD - Power Positive supply for logic and I/O pins.
18 GND - Power Ground reference for logic and I/O pins.
19 PB0 I/O TTL GPIO port B bit 0.
CCP0 I/O TTL Timer 0 capture input, compare output, or PWM output port 0.
20 PB1 I/O TTL GPIO port B bit 1.
32KHz I TTL Timer clock reference input for real-time clock operation.
21 GND - Power Ground reference for logic and I/O pins.
22 VDD - Power Positive supply for logic and I/O pins.
23 PB2 I/O TTL GPIO port B bit 2.
24 PB3 I/O TTL GPIO port B bit 3.
25 PC3 I/O TTL GPIO port C bit 3.
TDO O TTL JTAG scan test output.
SWO O TTL Serial-wire out put.
26 PC2 I/O TTL GPIO port C bit 2.
TDI I TTL JTAG scan data input.
27 PC1 I/O TTL GPIO port C bit 1.
TMS I TTL JTAG mode select input.
SWDIO I/O TTL Serial-wire debug inp ut/o utp ut.
28 PC0 I/O TTL GPIO port C bit 0.
TCK I TTL JTAG scan clock reference input.
SWCLK I TTL Serial-wire clock reference input.
Table 15-1. Signals by Pin Number (Sheet 2 of 2)
Pin
Number Signal Name Pin
Type Buffer
Type Description
Signal Tabl es
276 Octo ber 5, 2006
Preliminary
Table 15-2. Signals by Signal Name (Sheet 1 of 2)
Signal Name Pin
Number Pin
Type Buffer
Type Description
32KHz 20 I TTL Timer clock reference input for real-time clock operation.
C0+ 2 I Analog Analog comparator 0 positive reference input.
C0– 4 I Analog Analog comparator 0 negative reference input.
C0o 3 O TTL Analog comparator 0 output.
C1– 3 I Analog Analog comparator 1 negative reference input.
CCP0 19 I/O TTL Timer 0 capture input, compare output, or PWM output port 0.
GND 8 - Power Ground reference for logic and I/O pins.
GND 18 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
LDO 6 - Power The lo w drop-out regulator output voltage. This pin requires an
external capacitor between the pin and GND of 1 μF or greater.
OSC0 9 I Analog Oscillator crystal input or an external clock reference input.
OSC1 10 O Analog Oscillator crystal output.
PA0 11 I/O TTL GPIO port A bit 0.
PA1 12 I/O TTL GPIO port A bit 1.
PA2 13 I/O TTL GPIO port A bit 2.
PA3 14 I/O TTL GPIO port A bit 3.
PA4 15 I/O TTL GPIO port A bit 4.
PA5 16 I/O TTL GPIO port A bit 5.
PB0 19 I/O TTL GPIO port B bit 0.
PB1 20 I/O TTL GPIO port B bit 1.
PB2 23 I/O TTL GPIO port B bit 2.
PB3 24 I/O TTL GPIO port B bit 3.
PB4 4 I/O TTL GPIO port B bit 4.
PB5 3 I/O TTL GPIO port B bit 5.
PB6 2 I/O TTL GPIO port B bit 6.
PB7 1 I/O TTL GPIO port B bit 7.
PC0 28 I/O TTL GPIO port C bit 0.
PC1 27 I/O TTL GPIO port C bit 1.
LM3S101 Data Sheet
October 5, 2006 277
Preliminary
PC2 26 I/O TTL GPIO port C bit 2.
PC3 25 I/O TTL GPIO port C bit 3.
RST 5 I TTL System reset input.
SSIClk 13 I/O TTL SSI clock reference (input when in slave mode and output in
master mode).
SSIFss 14 I/O TTL SSI frame enable (input for an SSI slave device and output for an
SSI ma ste r device).
SSIRx 15 I TTL SSI receive data input.
SSITx 16 O TTL SSI transmit data output.
SWCLK 28 I TTL Serial-wire clock reference input.
SWDIO 27 I/O TTL Serial-wire deb ug inp ut/o utp ut.
SWO 25 O TTL Serial-w ire out put.
TCK 2 8 I TT L JTAG scan clock reference input.
TDI 26 I TTL JTAG scan data input.
TDO 25 O TTL JTAG scan test output.
TMS 27 I TTL JTAG mode select input.
TRST 1 I TTL JTAG TAP reset input.
U0Rx 11 I TTL UART0 receive data input.
U0Tx 12 O TTL UART0 transmit data output.
VDD 7 - Power Positive supply for logic and I/O pins.
VDD 17 - Power Positive supply for logic and I/O pins.
VDD 22 - Power Positive supply for logic and I/O pins.
Table 15-2. Signals by Signal Name (Sheet 2 of 2)
Signal Name Pin
Number Pin
Type Buffer
Type Description
Signal Tabl es
278 Octo ber 5, 2006
Preliminary
Table 15-3. Signals by Function, Except for GPIO (Sheet 1 of 2)
Function Signal Name Pin
Number Pin
Type Buffer
Type Description
Analog
Comparator C0+ 2 I Analog Analog comparator 0 positive reference
input.
C0– 4 I Analog Analog comparator 0 negative reference
input.
C0o 3 O TTL Analog comparator 0 output.
C1– 3 I Analog Analog comparator 1 negative reference
input.
General-Purpose
Timers 32KHz 20 I TTL Timer clock reference input for real-time
clock operation.
CCP0 19 I/O TTL Timer 0 capture input, compare output, or
PWM output port 0.
JTAG/SWD/SWO SWCLK 2 8 I TTL Serial wire clock reference input.
SWDIO 27 I/O TTL Serial-wire deb ug inp ut/o utp ut.
SWO 25 O TTL Serial-w ire out put.
TCK 2 8 I TT L JTAG scan cl ock reference input.
TDI 26 I TTL JTAG scan data input.
TDO 25 O TTL JTAG scan test output.
TMS 27 I TTL JTAG mode select input.
TRST 1 I TTL JTAG TAP reset input.
Power GND 8 - Power Ground reference for logic and I/O pins.
GND 18 - Power Ground reference for logic and I/O pins.
GND 21 - Power Ground reference for logic and I/O pins.
LDO 6 - Power The low drop-out regulator output voltage.
This pin requires an external capacitor
between the pin and GND of 1 μF or greater.
VDD 7 - Power Positive supply for logic and I/O pins.
VDD 17 - Power Positive supply for logic and I/O pins.
VDD 22 - Power Positive supply for logic and I/O pins.
LM3S101 Data Sheet
October 5, 2006 279
Preliminary
SSI SSIClk 13 I/O TTL SSI clock reference (input when in slave
mode and output in master mode).
SSIFss 14 I/O TTL SSI frame enable (input for an SSI slave
device and output for an SSI master device).
SSIRx 15 I TTL SSI receive data input.
SSITx 16 O TTL SSI transmit data output.
System Control &
Clocks OSC0 9 I Analog Oscillator crystal input or an external clock
reference input.
OSC1 10 O Analog Oscillator crystal output.
RST 5 I TTL System reset input.
UART U0Rx 11 I TTL UART0 receive data input.
U0Tx 12 O TTL UART0 transmit data output.
Table 15-4. GPIO Pins and Alternate Functions (Sheet 1 of 2)
GPIO Pin Pin
Number Multiplexe d
Function Multiplexed
Function
PA0 11 U0Rx
PA1 12 U0Tx
PA2 13 SSIClk
PA3 14 SSIFss
PA4 15 SSIRx
PA5 16 SSITx
PB0 19 CCP0
PB1 20 32KHz
PB2 23
PB3 24
PB4 4 C0-
PB5 3 C0o C1-
PB6 2 C0+
PB7 1 TRST
PC0 28 TCK SWCLK
Table 15-3. Signals by Function, Except for GPIO (Sheet 2 of 2)
Function Signal Name Pin
Number Pin
Type Buffer
Type Description
Signal Tabl es
280 Octo ber 5, 2006
Preliminary
PC1 27 TMS SWDIO
PC2 26 TDI
PC3 25 TDO SWO
Table 15-4. GPIO Pins and Alternate Functions (Sheet 2 of 2)
GPIO Pin Pin
Number Multiplexe d
Function Multiplexed
Function
LM3S101 Data Sheet
October 5, 2006 281
Preliminary
16 Op erating Characteristics
Table 16-1. Temperature Characteristics
Characteristic Symbol Value Unit
Operati ng tem pera ture rangea
a. Maximum st orage temperat ure is 150°C.
TA-40 to +85 for industrial °C
Ta ble 16-2. Thermal Ch ara cteristics
Characteristic Symbol Value Unit
Thermal resistance (junction to ambient)a
a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator.
θJA 74 °C/W
Average junction temperatureb
b. Power dissipation is a function of temperature.
TJTA + (PAVG • θJA)°C
Maximum junct ion temperature TJMAX pendingc
c. Pending characterization completion.
°C
Electrical Characteristics
282 Octo ber 5, 2006
Preliminary
17 Electrical Characteristics
17.1 DC Characteristics
17.1.1 Maximum Ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device.
Note: The device is not guaranteed to operate properly at the maximum ratings.
Important: This devi ce contains c ircuitry to protect the i nputs against da mage due to h igh-static
voltages or electr ic fields; however, it is adv ised that normal precautions be taken to
avoid application of any voltage higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (for example, either GND or VDD).
17.1.2 Recommended DC Operating Conditions
Table 17-1. Maximum Ratings
Characteristica
a. Voltages are measured with respect to GND.
Symbol Value Unit
Supply voltage range (VDD)V
DD 0.0 to +3.6 V
Input voltage VIN -0.3 to 5.5 V
Maximum current for pins, excluding pins
operating as GPIOs I100 mA
Maximum current for GPIO pins I 100 mA
Table 17-2. Recommended DC Operating Condi tions
Parameter Parameter Name Min Nom Max Unit
VDD Supply voltage 3.0 3.3 3.6 V
VIH High-level input voltage 2.0 - 5.0 V
VIL Low-level input voltage -0.3 - 1.3 V
VSIH High-level inpu t voltage for Schottky inputs 0.8 * VDD -V
DD V
VSIL Low-level input voltage for Schottky inputs 0 - 0.2 * VDD V
VOH High-level output voltage 2.4 - - V
VOL Low-level output voltage - - 0.4 V
LM3S101 Data Sheet
October 5, 2006 283
Preliminary
17.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics
IOH High-level source current, VOH=2.4 V
2-mA Drive 2. 0 - - mA
4-mA Drive 4. 0 - - mA
8-mA Drive 8. 0 - - mA
IOL Low-level sink current, VOL=0.4 V
2-mA Drive 2. 0 - - mA
4-mA Drive 4. 0 - - mA
8-mA Drive 8. 0 - - mA
Table 17-3. LDO Regulator Characteristics
Parameter Parameter Name Min Nom Max Unit
VLDOOUT Programmable inte rnal (lo gic ) p ower s up ply
output value 2.25 - 2.75 V
Output vol t ag e acc ura cy - 2% - %
tPON Power-on time - - 100 μs
tON Time on - - 200 μs
tOFF Time off - - 100 μs
VSTEP Step programming incremental voltage - 50 - mV
CLDO External filter capacitor size for internal
power supply -1-μF
Table 17-2. Recommended DC Operating Condi tions (Continued)
Parameter Parameter Name Min Nom Max Unit
Electrical Characteristics
284 Octo ber 5, 2006
Preliminary
17.1.4 Power Specifications
The power measurements specified in Table 17-4 are run on the core processor using SRAM with
the following specifications:
VDD=3.3 V
LDO=2.5
Temperature=25°C
System Clo ck = 20 MHz (with PLL)
Code while(1){} executed from SRAM with no active peripherals
17.1.5 Flash Memory Characteristics
Table 1 7-4. Pow er Specific atio ns
Parameter Paramete r Name Min Nom Max Unit
IDD_RUN Run mode - 35apendinga
a. Pending characterization comp letion.
mA
IDD_SLEEP Sleep mode - pendingapendingaμA
IDD_DEEPSLEEP Deep-Sleep mode - pending apendingaμA
Table 17-5. Flash Memory Characteristics
Parameter Parameter Name Min Nom Max Unit
PECYC Number of guaranteed program/erase
cyclesa before failure
a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1.
10,000 - - cycles
TRET Data retention at average operating
temperature of 85°C 10 - - years
TPROG Word program time 20 - - μs
TERASE Page erase time 20 - - ms
TME Mass erase time 200 - - ms
LM3S101 Data Sheet
October 5, 2006 285
Preliminary
17.2 AC Characteristics
17.2.1 Load Conditions
Unless otherwise specified, the following conditions are true for all timing measurements. Timing
measurements are for 4-mA drive strength.
Figure 17-1. Load Conditions
17.2.2 Clocks
Table 17-6. Phase Locked Loop (PLL) Characteristics
Parameter Parameter Name Min Nom Max Unit
fREF_CRYSTAL Crystal referencea
a. The exact value is determined by the crystal value programmed into the XTAL field of the Run- Mode C l oc k
Configuration (RCC) register (see page 71).
3.579545 - 8.192 MHz
fREF_EXT External cl ock refere ncea3.579545 - 8.192 MHz
fPLL PLL frequencyb
b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register.
- 200 - MHz
TREADY PLL lock time - - 0.5 ms
Table 17-7. Clock Characteristics
Parameter Parameter Name Min Nom Max Unit
fIOSC Internal oscillat or
frequency 71522MHz
fMOSC Main oscillator frequency 1 - 8 MHz
tMOSC_PER Main oscillator period 125 - 1000 ns
fREF_CRYSTAL_BYPASS Cryst al refere nce usin g the
main oscillator (PLL in
BYPASS mode)
1-8MHz
fREF_EXT_BYPASS External clock refere nce
(PLL in BYPASS mode) 0-20MHz
fSYSTEM_CLOCK System clock 0 - 20 MHz
C
L
= 5 0 pF
GND
pin
Electrical Characteristics
286 Octo ber 5, 2006
Preliminary
17.2.3 Analog Comparat or
Table 17-8. Analog Comparator Characteris tics
Parameter Parameter Name Min Nom Max Unit
VOS Input offset voltage - ± 10 ± 25 mV
VCM Input common mode voltage range 0 - VDD-1.5 V
CMRR Comm on mo de rejection ratio 50 - - dB
TRT Response time - - 1 μs
TMC Comparator mode change to Output Valid - - 10 μs
Table 17-9. Analog Comparator Voltage Reference Characteristics
Parameter Parameter Name Min Nom Max Unit
RHR Resoluti on hig h range - VDD/32 - LSB
RLR Resoluti on low rang e - VDD/24 - LSB
AHR Absolute accuracy high range - - ± 1/2 LSB
ALR Absolute accuracy low range - - ± 1/4 LSB
LM3S101 Data Sheet
October 5, 2006 287
Preliminary
17.2.4 Synchronous Serial Interface (SSI)
Figure 17-2. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement
Table 17-10. SSI Characteristics
Parameter
No. Parameter Parameter Name Min Nom Max Unit
S1 tCLK_PER SSIClk cycle time 2 - 65024 syst em
clocks
S2 tCLK_HIGH SSIClk high time - 1/2 - tCLK_PER
S3 tCLK_LOW SSIClk low time - 1/2 - tCLK_PER
S4 tCLKRF SSIClk rise/fall time - 7.4 26 ns
S5 tDMD Data from master valid delay time 0 - 20 ns
S6 tDMS Data from master setup time 20 - - ns
S7 tDMH Data from master hold time 40 - - ns
S8 tDSS Data from slave setup time 20 - - ns
S9 tDSH Data from slave hold time 40 - - ns
SSIClk
SSIFss
SSITx
SSIRx MSB LSB
S2
S3
S1
S4
4 to 16 bits
Electrical Characteristics
288 Octo ber 5, 2006
Preliminary
Figure 17-3. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer
Figure 17-4. SSI Timing for SPI Frame Format (FRF=00), with SPH=1
0
SSIClk
SSIFss
SSITx
SSIRx
MSB LSB
MSB LSB
S2
S3
S1
8-bit control
4 to 16 bits output data
SSIClk
(SPO=1)
SSITx
(master)
SSIRx
(slave) LSB
SSIClk
(SPO=0)
S2
S1
S4
SSIFss
LSB
S3
MSB
S5
S6 S7
S9S8
MSB
LM3S101 Data Sheet
October 5, 2006 289
Preliminary
17.2. 5 JTAG and Bo undary Scan
Table 17-11. JTAG Characteristics
Parameter
No. Parameter Parameter Name Min Nom Max Unit
J1 fTCK TCK operational clock frequency 0 - 10 MHz
J2 tTCK TCK operational clock period 100 - - ns
J3 tTCK_LOW TCK cloc k Low time - ½ tTCK -ns
J4 tTCK_HIGH TCK clock High time - ½ tTCK -ns
J5 tTCK_R TCK rise time 0 - 10 ns
J6 tTCK_F TCK fall time 0 - 10 ns
J7 tTMS_SU TMS setup time to TCK rise 20 - - ns
J8 tTMS_HLD TMS hold time from TCK rise 20 - - ns
J9 tTDI_SU TDI setup time to TCK rise 25 - - ns
J10 tTDI_HLD TDI hold time from TCK rise 25 - - ns
J11
tTDO_ZDV
TCK fall to
Data Valid
from High -Z
2-mA drive - 23 35 ns
4-mA drive 15 26 ns
8-mA drive 14 25 ns
8-mA drive wi th sle w rat e contr ol 18 29 ns
J12
tTDO_DV
TCK fall to
Data Valid
from Data
Valid
2-mA drive - 21 35 ns
4-mA drive 14 25 ns
8-mA drive 13 24 ns
8-mA drive wi th sle w rat e contr ol 18 28 ns
J13
tTDO_DVZ
TCK fall to
High -Z from
Data Valid
2-mA drive - 9 11 ns
4-mA drive 7 9 ns
8-mA drive 6 8 ns
8-mA drive wi th sle w rat e contr ol 7 9 ns
J14 tTRST TRST assertio n time 100 - - n s
J15 tTRST_SU TRST setup time to TCK rise 10 - - ns
Electrical Characteristics
290 Octo ber 5, 2006
Preliminary
Figure 17-5. JTAG Test Clock Input Timing
Figure 17-6. JTAG Test Access Port (TAP) Timing
Figure 17-7. JTAG TRST Timing
TCK
J6 J5
J3 J4
J2
TDO Out put Vali d
TCK
TDO Out put V alid
J12
TDO
TDI
TMS
T D I I nput V al i d TDI I nput V al id
J13
J9 J10
TMS Input Valid
J9 J10
TM S I nput V al id
J11
J7 J8J8J7
TCK
J14 J15
TRST
LM3S101 Data Sheet
October 5, 2006 291
Preliminary
17.2.6 General-Purpose I/O
17.2.7 Reset
Table 17-12. GPIO Characteristicsa
a. All GPIOs are 5 V-tolerant.
Parameter Parameter Name Condition Min Nom Max Unit
tGPIOR GPO Rise Time
(from 20% to 80%
of VDD)
2-mA drive - 17 26 ns
4-mA drive 9 13 ns
8-mA drive 6 9 ns
8-mA drive with slew rate control 10 12 ns
tGPIOF GPO Fall T ime
(from 80% to 20%
of VDD)
2-mA drive - 17 25 ns
4-mA drive 8 12 ns
8-mA drive 6 10 ns
8-mA drive with slew rate control 11 13 ns
Table 17-13. Reset Characteristics
Parameter
No. Parameter Parameter Name Min Nom Max Unit
R1 VTH Reset threshold - 2.0 - V
R2 VBTH Brown-Out threshold 2.85 2.9 2.95 V
R3 TPOR Power-O n Re se t time out - 10 - ms
R4 TBOR Brown-Out timeout - 500 - μs
R5 TIRPOR Internal reset timeout after POR 15 - 30 ms
R6 TIRBOR Internal reset timeout after BORa
a. 20 * tMOSC_PER
2.5 - 20 μs
R7 TIRHWR Internal reset timeout after hardware
reset (RST pin) 15 - 30 ms
R8 TIRSWR Internal reset timeout after
sof t ware-initiated system res et a2.5 - 20 μs
R9 TIRWDR Internal reset timeout after watchdog
reseta2.5 - 20 μs
R10 TIRLDOR Internal reset timeout after LDO reseta2.5 - 20 μs
R11 TVDDRISE Supply voltage (VDD) rise time (0V-3.3V) 100 ms
Electrical Characteristics
292 Octo ber 5, 2006
Preliminary
Figure 17-8. External Reset Timing (RST)
Figure 17-9. Power-On Reset Timing
Figure 17-10. Brown-Out Reset Timing
Figure 17-11. Software Reset Timing
RST
/Reset
(Internal)
R7
VDD
/POR
(Internal)
/Reset
(Internal)
R3
R1
R5
VDD
/BOR
(Internal)
/Reset
(Internal)
R2
R4
R6
R8
SW Re s e t
/Reset
(Internal)
LM3S101 Data Sheet
October 5, 2006 293
Preliminary
Figure 17-12. Watchdog Reset Timing
Figure 17-13. LDO Reset Timing
WDT
Reset
(Internal)
/Reset
(Internal)
R9
LDO Reset
(Internal)
/Reset
(Internal)
R10
Package Information
294 Octo ber 5, 2006
Preliminary
18 Package Information
Figure 18-1. 28-Pin SOIC Package
NOTES:
1. Dimension “D” does not include mold fl ash, protrusio ns, or gate burrs.
MOld flash, protrusions, and gate burrs shall not exceed .006”
(0.15mm) per side.
2. Dimension “E” does not include inter-lead flash or protrusions. Inter-
lead flash an d protrusion shall not exceed “.010” (0.25 mm) per side.
3. “L” is the length of terminal for soldering to a substr ate.
4. “N” is the number of terminal positions.
5. Terminal numbers are sh own for reference only.
6. The lead width “b”, as measured .014” (0.36 mm) or greater above
the seat ing plane, shall not exceed a maximum value of .024” (0.61
mm).
7. Reference drawing JE DEC MS013, Va riation AE.
SYMBOL DIMENSION IN INCH DIMENSION IN MM
MIN MAX MIN MAX
A .093 .014 2.35 2.65
A1 .004 .012 0.10 0.30
B .013 .020 0.33 0.51
C .009 .013 0.23 .032
D .696 .713 17.70 18.10
E .291 .299 7.40 7.60
e 0.50 BSC 1.27 BSC
H .394 .419 10.00 10.65
h .010 .029 0.25 0.75
L .016 .050 0.40 1.27
S .021 .031 0.533 .0787
α0°8°0°8°
LM3S101 Data Sheet
October 5, 2006 295
Preliminary
Appendix A. Serial Flash Loader
The Stellaris serial flash loader is used to download code to the flash memory of a device without
the use of a debug interface. The serial flash loader uses a simple packet interface to provide
synchronous communication with the device. The flash loader runs off the crystal and does not
enable the PLL, so its speed is determined by the crystal used. The two serial interfaces that can
be used are the UART0 and SSI interfaces. For simplicity, both the data format and
communication protocol are identical for both serial interfaces.
A.1 Interfaces
Once communication with the flash loader is established via one of the serial interfaces, that
interface is used until the flash loader is reset or new code takes over . For example, once you start
communicating using the SSI port, communications with the flash loader via the UART are
disabled until the device is reset.
A.1.1 UART
The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial
format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is
automatically detected by the flash loader and can be any valid baud rate supported by the host
and the device. The auto detection sequence requires that the baud rate should be no more than
1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the
same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device.
In order to determine the baud rate, the serial flash loader needs to determine the relationship
between its own crystal frequency and the baud rate. This is enough information for the flash
loader to configure its UART to the same baud rate as the host. This automatic baud rate detection
allows the host to use any valid baud rate that it wants to communicate with the device.
The method used to perform this automatic synchronization relies on the host sending the flash
loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can
use to calculate the ratios needed to program the UART to match the host’s baud rate. After the
host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader
returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not
received after at least twice the time required to transfer the two bytes, the host can resend
another pattern of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader
acknowledges that it has received a synchronization pattern correctly. For example, the time to
wait for data back from the flash loader should be calculated as at least 2*(20(bits/sync)/baud rate
(bits/sec)). For a baud rate of 115200, this time is 2*(20/115200) or 0.35ms.
A.1.2 SSI
The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications,
with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See the section
on SSI formats for more details on this transfer protocol. Like the UART, this interface has
hardware requirements that limit the maximum speed that the SSI clock can run. This allows the
SSI clock to be at most 1/12 the crystal frequency of the board running the flash loader. Since the
host device is the master, the SSI on the flash loader device does not need to determine the clock
as it is provided dir ec tl y by the host.
A.2 Packet Handling
All communications, with the exception of the UART auto-baud, are done via defined packets that
are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same
296 Octo ber 5, 2006
Preliminary
format for receiving and sending packets, including the method used to acknowledge successful or
unsuccessful reception of a packet.
A.2.1 Packet Format
All packets sent and received from the device use the following byte-packed format.
struct
{
unsigned char ucSize;
unsigned char ucCheckSum;
unsigned char Data[];
};
ucSize – The first byte received holds the total size of the transfer including the size and checksum
bytes.
ucChecksum – This holds a simple checksum of the bytes in the data buffer only. The algorithm is
Data[0]+Data[1]+…+ Data[ucSize-3].
Data – This is the raw data intended for the device, which is formatted in some form of command
interface. There should be ucSize – 2 bytes of data provided in this buffer to or from the device.
A.2.2 Sending Packets
The actual bytes of the packet can be sent individually or all at once, the only limitation is that
commands that cause flash memory access should limit the download sizes to prevent losing
bytes during flash programming. This limitation is discussed further in the commands that interact
with the flash.
Once the packet has been formatted correctly by the host, it should be sent out over the UART or
SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data
returned from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33)
byte from the device indicating the packet was received successfully (ACK) or unsuccessfully
(NAK). This does not indicate that the actual contents of the command issued in the data portion of
the packet were valid, just that the packet was received correctly.
A.2.3 Receiving Packets
The flash loader sends a packet of data in the same format that it receives a packet. The flash
loader may transfer leading zero data before the first actual byte of data is sent out. The first
non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the
data itself. There is no break in the data after the first non-zero byte is sent from the flash loader.
Once the device communicating with the flash loader receives all the bytes, it must either ACK or
NAK the packet to indicate that the transmission was successful. The appropriate response after
sending a NAK to the flash loader is to resend the command that failed and request the data again.
If needed, the host may send leading zeros before sending down the ACK/NAK signal to the flash
loader, as the flash loader only accepts the first non-zero data as a valid response. This zero
padding is needed by the SSI interface in order to receive data to or from the flash loader.
A.3 Commands
The next section defines the list of commands that can be sent to the flash loader. The first byte of
the data should always be one of the defined commands, followed by data or parameters as
determined by the command that is sent.
LM3S101 Data Sheet
October 5, 2006 297
Preliminary
A.3.1 COMMA ND_ PING (0 x2 0)
This command simply accepts the command and sets the global status to success. The format of
the packet is as follows:
Byte[0] = 0x03;
Byte[1] = checksum(Byte[2]);
Byte[2] = COMMAND_PING;
The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of
one byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return
status, the receipt of an ACK can be interpreted as a successful ping to the flash loader.
A.3.2 COMMAND_GET _STATUS (0x 23)
This command returns the status of the last command that was issued. Typically, this command
should be sent after every command to ensure that the previous command was successful or to
properly respond to a failure. The command requires one byte in the data of the packet and should
be followed by reading a packet with one byte of data that contains a status code. The last step is
to ACK or NAK the received data so the flash loader knows that the data has been read.
Byte[0] = 0x03
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_GET_STATUS
A.3.3 COMMAND _DOWNLOAD (0x21)
This command is sent to the flash loader to indicate where to store data and how many bytes will
be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two
32-bit values that are both transferred MSB first. The first 32-bit value is the address to start
programming data into, while the second is the 32-bit size of the data that will be sent. This
command also triggers an erase of the full area to be programmed so this command takes longer
than other commands. This results in a longer time to receive the ACK/NAK back from the board.
This command should be followed by a COMMAND_GET_STATUS to ensure that the Program
Address and Program size are valid for the device running the flash loader.
The format of the packet to send this command is a follows:
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_DOWNLOAD
Byte[3] = Program Address [31:24]
Byte[4] = Program Address [23:16]
Byte[5] = Program Address [15:8]
Byte[6] = Program Address [7:0]
Byte[7] = Program Size [31:24]
Byte[8] = Program Size [23:16]
Byte[9] = Program Size [15:8]
Byte[10] = Program Size [7:0]
A.3.4 COMMAND_SEND_DATA (0x24)
This comman d shou ld onl y foll ow a COMMAND_DOWN LOAD command or another
COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands
298 Octo ber 5, 2006
Preliminary
automatically increment address and continue programming from the previous location. The caller
should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program
successfully and not overflow input buffers of the serial interfaces. The command terminates
programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has
been received. Each time this function is called it should be followed by a
COMMAND_GET_STATUS to ensure that the data was successfully programmed into the flash. If
the flash loader sends a NAK to this command, the flash loader does not increment the current
address to allow retransmission of the previous data.
Byte[0] = 11
Byte[1] = checksum(Bytes[2:10])
Byte[2] = COMMAND_SEND_DATA
Byte[3] = Data[0]
Byte[4] = Data[1]
Byte[5] = Data[2]
Byte[6] = Data[3]
Byte[7] = Data[4]
Byte[8] = Data[5]
Byte[9] = Data[6]
Byte[10] = Data[7]
A.3.5 COMMAND _RUN (0x22)
This command is used to tell the flash loader to execute from the address passed as the parameter
in this command. This command consists of a single 32-bit value that is interpreted as the address
to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK
signal back to the host device before actually executing the code at the given address. This allows
the host to know that the command was received successfully and the code is now running.
Byte[0] = 7
Byte[1] = checksum(Bytes[2:6])
Byte[2] = COMMAND_RUN
Byte[3] = Execute Address[31:24]
Byte[4] = Execute Address[23:16]
Byte[5] = Execute Address[15:8]
Byte[6] = Execute Address[7:0]
A.3.6 COMMAND_RESET (0x25)
This command is used to tell the flash loader device to reset. This is useful when downloading a
new image that overwrote the flash loader and wants to start from a full reset. Unlike the
COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and
set up for the new code. It can also be used to reset the flash loader if a critical error occurs and
the host device wants to restart communication with the flash loader.
Byte[0] = 3
Byte[1] = checksum(Byte[2])
Byte[2] = COMMAND_RESET
The flash loader responds with an ACK signal back to the host device before actually executing the
software reset to the device running the flash loader. This allows the host to know that the
command was received successfully and the part will be reset.
LM3S101 Data Sheet
October 5, 2006 299
Preliminary
Orde ring and Contact Information
Ordering Information
Development Kit
The Luminary Micro Stellaris™ Family Development Kit
provides the hardware and software tools that engineers
need to begin development quickly. Ask your Luminary Micro
distributor for part number DK-LM3S101. See the Luminary
Micro website for the latest tools available.
Company Information
Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3 based microcontrollers for use in embedded
applications within the industrial, commercial, and consumer markets. Luminary Micro is ARM's lead partner in
the implementation of the Cortex-M3 core. Please contact us if you are interested in obtaining further
information about our company or our products.
Luminary Micro, Inc.
2499 South Capital of Texas Hwy, Suite A-100
Austin, TX 78746
Main: +1-5 12-27 9- 880 0
Fax: +1-512-279-8879
http://www.luminarymicro.com
sales@luminarymicro.com
Order Number
Features
Flash (KB )
SRAM (KB)
GPIOsa
a. Minimum is number of pins dedicated to GPIO; additional pins are available if certain peripherals are not used. See data sheet for
details.
Timersb
b. One timer available as RTC.
ADC
UART(s)
SSI
I2C
Analog
Comparator(s)
PWMc
c. PWM motion control functionality can be achieved through dedicated motion control hardware (using the PWM pins) or through
the motion control features of the general-purpose timers (using the CCP pins). See data sheet for details.
QEI
Operating
Temperatured
d. I=Industrial (–40 to 85°C).
Packagee
e. RN=28-pin RoHS-compliant SOIC.
Speed (Clock
Frequency in MHz)
Samp les Per Se c o nd
# of 10-Bit Channels
PWM Pins
CCP Pi ns
LM3S101-IRN20 822
to
18 2--1√-2-1-IRN20
LM3S101-IRN20(T)f
f. T=Tape and Reel.
Tools to
begin
development
quickly
300 Octo ber 5, 2006
Preliminary
Support Information
For support on Luminary Micro products, contact:
support@luminarymicro.com
+1-512-279-8800, ext. 3
