LM3S101 Data Sheet
October 5, 2006 11
Preliminary
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C.......................................................................109
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410..........................................................................110
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414..............................................................111
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418........................................................112
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C.......................................................................113
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420.................................................114
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500..............................................................115
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504..............................................................116
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508..............................................................117
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C...............................................................118
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ......................................................................119
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514..................................................................120
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518......................................................121
Register 18: GPIO Digital Input Enable (GPIODEN), offset 0x51C.............................................................122
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0...........................................123
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4...........................................124
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8...........................................125
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC...........................................126
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ...........................................127
Register 24: GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 ............................................128
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ...........................................129
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC...........................................130
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0..............................................131
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4..............................................132
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8..............................................133
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC..............................................134
General-Purpose Timers.............................................................................................................. 135
Register 1: GPTM Configuration (GPTMCFG), offset 0x000.....................................................................147
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004..................................................................148
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008..................................................................149
Register 4: GPTM Control (GPTMCTL), offset 0x00C...............................................................................150
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018....................................................................152
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..........................................................154
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020.....................................................155
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024.....................................................................156
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028......................................................157
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C......................................................158
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 .......................................................159
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .......................................................160
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038..............................................................161
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C.............................................................162
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040................................................163
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044................................................164
Register 17: GPTM TimerA (GPTMTAR), offset 0x048...............................................................................165
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ..............................................................................166
Watchdog Timer............................................................................................................................ 167
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ............................................................................170
Register 2: Watchdog Value (WDTVALUE), offset 0x004.........................................................................171