MT3371BSR1 - Microsemi Consumer Medical Product Group

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

• Wide dynamic range (50 dB) DTMF Receiver

• Call progress (CP) detection via cadence

indication

• 4-bit synchronous serial data output

• Software controlled guard time for MT3x70B

• Internal guard time circuitry for MT3x71B

• Powerdown option (MT317xB & MT337xB)

• 4.194304 MHz crystal or ceramic resonator

(MT337xB and MT327xB)

• External clock input (MT317xB)

• Guarantees non-detection of spurious tones

Applications

• Integrated telephone answering machine

• End-to-end signalling

•Fax Machines

February 2007

Ordering Information

MT3170/71BE 8 Pin PDIP Tubes

MT3270/71BE 8 Pin PDIP Tubes

MT3370/71BS 18 Pin SOIC Tubes

MT3370/71BN 20 Pin SSOP Tubes

MT3370/71BSR 18 Pin SOIC Tape & Reel

MT3371BNR 20 Pin SSOP Tape & Reel

MT3270/71BE1 8 Pin PDIP* Tubes

MT3171BE1 8 Pin PDIP* Tubes

MT3170BE1 8 Pin PDIP** Tubes

MT3370/BN1 20 Pin SSOP* Tubes

MT3370/71BS1 18 Pin SOIC* Tubes

MT3370/71BSR1 18 Pin SOIC* Tape & Reel

*Pb Free Matte Tin

**Pb Free Tin/Silver/Copper

-40°C to 85°C

MT3170B/71B, MT3270B/71B, MT3370B/71B

Wide Dynamic Range DTMF Receiver

Data Sheet

Figure 1 - Functional Block Diagram

PWDN

VDD

VSS

INPUT

OSC2

OSC1

(CLK)

➀MT3170B/71B and MT337xB only.

➁MT3270B/71B and MT337xB only.

Voltage

Bias Circuit

AGC

Anti-

alias

Filter

High

Group

Filter

Low

Group

Filter

Steering

Circuit

Digital

Detector

Algorithm

Code

Converter

and

Latch

Digital

Guard

Time➂

Parallel to

Serial

Converter

& Latch

Mux

Energy

Detection

Oscillator

and

Clock

Circuit

To All Chip Clocks

Dial

Tone

Filter

ESt

DStD

ACK

➀

➁

➂ MT3x71B only.

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

Description

The MT3x7xB is a family of high performance DTMF receivers which decode all 16 tone pairs into a 4-bit binary

code. These devices incorporate an AGC for wide dynamic range and are suitable for end-to-end signalling. The

MT3x70B provides an early steering (ESt) logic output to indicate the detection of a DTMF signal and requires

external software guard time to validate the DTMF digit. The MT3x71B, with preset internal guard times, uses a

delay steering (DStD) logic output to indicate the detection of a valid DTMF digit. The 4-bit DTMF binary digit can be

clocked out synchronously at the serial data (SD) output. The SD pin is multiplexed with call progress detector

output. In the presence of supervisory tones, the call progress detector circuit indicates the cadence (i.e., envelope)

of the tone burst. The cadence information can then be processed by an external microcontroller to identify specific

call progress signals. The MT327xB and MT337xB can be used with a crystal or a ceramic resonator without

additional components. A power-down option is provided for the MT317xB and MT337xB.

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

337xBN 337xBS 327xB 317xB

3211INPUTDTMF/CP Input. Input signal must be AC coupled via

capacitor.

642-OSC2Oscillator Output.

7633OSC1

(CLK)

Oscillator/Clock Input. This pin can either be driven by:

1) an external digital clock with defined input logic levels.

OSC2 should be left open.

2) connecting a crystal or ceramic resonator between

OSC1 and OSC2 pins.

8944V

SS Ground. (0V)

13 11 5 5 SD Serial Data/Call Progress Output. This pin serves the dual

function of being the serial data output when clock pulses are

applied after validation of DTMF signal, and also indicates

the cadence of call progress input. As DTMF signal lies in

the same frequency band as call progress signal, this pin

may toggle for DTMF input. The SD pin is at logic low in

powerdown state.

VDD

ESt/DStD

ACK

INPUT

PWDN

OSC2

OSC1

VSS

INPUT

PWDN

CLK

VSS

VDD

ACK

INPUT

OSC2

OSC1

VSS

VDD

ESt/

ACK

MT3170B/71B MT3270B/71B MT3370BS/71BS

8 PIN PLASTIC DIP 18 PIN PLASTIC SOIC

10 11

INPUT

PWDN

OSC1

OSC2

VSS

20 PIN SSOP

VDD

ACK

ESt/DStD

DStD

ESt/

DStD

MT3370BN/71BN

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

Change Summary

The following table summarizes the changes from the August 2006 issue.

14 13 6 6 ACK Acknowledge Pulse Input. After ESt or DStD is high,

applying a sequence of four pulses on this pin will then shift

out four bits on the SD pin, representing the decoded DTMF

digit. The rising edge of the first clock is used to latch the 4-

bit data prior to shifting. This pin is pulled down internally.

The idle state of the ACK signal should be low.

16 15 7 7 ESt

(MT3x70B)

DStD

(MT3x71B)

Early Steering Output. A logic high on ESt indicates that a

DTMF signal is present. ESt is at logic low in powerdown

state.

Delayed Steering Output. A logic high on DStD indicates

that a valid DTMF digit has been detected. DStD is at logic

low in powerdown state.

18 18 8 8 VDD Positive Power Supply (5 V Typ.) Performance of the

device can be optimized by minimizing noise on the supply

rails. Decoupling capacitors across VDD and VSS are

therefore recommended.

1,2,5,9,

10,11,12,

15,17,19,20

1,5,7,8,

10, 12,

14,16,

--NCNo Connection. Pin is unconnected internally.

43-2PWDNPower Down Input. A logic high on this pin will power down

the device to reduce power consumption. This pin is pulled

down internally and can be left open if not used. ACK pin

should be at logic ’0’ to power down device.

Summary of MT3x70/71B Product Family

Device

Type 8 Pin 18 Pin 20 Pin PWDN 2 Pin

OSC

Ext

CLK ESt DStD

MT3170B √√√√

MT3171B √√√√

MT3270B √ √√√

MT3271B √√√√

MT3370B √√√√√√

MT3371B √√√√√ √

Page Item Description

2 Figure 2 Added ordering codes to Pin Connection diagram.

2 “Pin Description“ Added 20 pin description to the table.

Pin Description

Pin # Name Description

337xBN 337xBS 327xB 317xB

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

Functional Description

The MT3x7xBs are high performance and low power consumption DTMF receivers. These devices provide wide

dynamic range DTMF detection and a serial decoded data output. These devices also incorporate an energy

detection circuit. An input voiceband signal is applied to the devices via a series decoupling capacitor. Following the

unity gain buffering, the signal enters the AGC circuit followed by an anti-aliasing filter. The bandlimited output is

routed to a dial tone filter stage and to the input of the energy detection circuit. A bandsplit filter is then used to

separate the input DTMF signal into high and low group tones. The high group and low group tones are then

verified and decoded by the internal frequency counting and DTMF detection circuitry. Following the detection

stage, the valid DTMF digit is translated to a 4-bit binary code (via an internal look-up ROM). Data bits can then be

shifted out serially by applying external clock pulses.

Automatic Gain Control (AGC) Circuit

As the device operates on a single power supply, the input signal is biased internally at approximately VDD/2. With

large input signal amplitude (between 0 and approximately -30 dBm for each tone of the composite signal), the

AGC is activated to prevent the input signal from being clipped. At low input level, the AGC remains inactive and the

input signal is passed directly to the hardware DTMF detection algorithm and to the energy detection circuit.

Filter and Decoder Section

The signal entering the DTMF detection circuitry is filtered by a notch filter at 350 and 440 Hz for dial tone rejection.

The composite dual-tone signal is further split into its individual high and low frequency components by two 6th

order switched capacitor bandpass filters. The high group and low group tones are then smoothed by separate

output filters and squared by high gain limiting comparators. The resulting squarewave signals are applied to a

digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For

MT3x70B, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high,

indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt

pin to go low. For MT3x71B, an internal delayed steering counter validates the early steering signal after a

predetermined guard time which requires no external components. The delayed steering (DStD) will go high only

when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal

due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD

output will go low only after this validation period.

Energy Detection

The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists

of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal

comparator (-35 dBm), the energy detector produces an energy present indication on the SD output. The integrator

ensures the SD output will remain at high even though the input signal is changing. When the input signal is

removed, the SD output will go low following the integrator decay time. Short decay time enables the signal

envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for

specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause

the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification.

As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected

at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse

applied at the ACK pin.

Serial Data (SD) Output

When a valid DTMF signal burst is present, ESt or DStD will go high. The application of four clock pulses on the

ACK pin will provide a 4-bit serial binary code representing the decoded DTMF digit on the SD pin output. The rising

edge of the first pulse applied on the ACK pin latches and shifts the least significant bit of the decoded digit on the

SD pin. The next three pulses on ACK pin will shift the remaining latched bits in a serial format (see Figure 5). If less

than four pulses are applied to the ACK pin, new data cannot be latched even though ESt/DStD can be valid. Clock

pulses should be applied to clock out any remaining data bits to resume normal operation. Any transitions in excess

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

of four pulses will be ignored until the next rising edge of the ESt/DStD. ACK should idle at logic low. The 4-bit

binary representing all 16 standard DTMF digits are shown in Table 1.

0= LOGIC LOW, 1= LOGIC HIGH

Table 1 - Serial Decode Bit Table

Note: b0=LSB of decoded DTMF digit and shifted out first.

Powerdown Mode (MT317xB/337xB)

The MT317xB/337xB devices offer a powerdown function to preserve power consumption when the device is not in

use. A logic high can be applied at the PWDN pin to place the device in powerdown mode. The ACK pin should be

kept at logic low to avoid undefined ESt/DStD and SD outputs (see Table 2).

Table 2 - Powerdown Mode

+ =enters powerdown mode on the rising edge.

FLOW FHIGH DIGIT b3b2b1b0

697 1209 1 0 0 0 1

697 1336 2 0 0 1 0

697 1477 3 0 0 1 1

770 1209 4 0 1 0 0

770 1336 5 0 1 0 1

770 1477 6 0 1 1 0

852 1209 7 0 1 1 1

852 1336 8 1 0 0 0

852 1477 9 1 0 0 1

941 1336 0 1 0 1 0

941 1209 * 1 0 1 1

941 1477 # 1 1 0 0

697 1633 A 1 1 0 1

770 1633 B 1 1 1 0

852 1633 C 1 1 1 1

941 1633 D 0 0 0 0

ACK (input) PWDN (input) ESt/DStD (output) SD (output) MT317xB/337xB

status

low low Refer to Fig. 4 for

timing waveforms

Refer to Fig. 4 for

timing waveforms

normal operation

low high+low low powerdown mode

high low low undefined undefined

high high undefined undefined undefined

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

Table 3 - Call Progress Tones

Table 4 - Recommended Resonator and Crystal Specifications

Note: Qm=quality factor of RLC model, i.e., 1/2P¶R1C1.

Resonator and Crystal Electric Equivalent Circuit

Oscillator

The MT327xB/337xB can be used in both external clock or two pin oscillator mode. In two pin oscillator mode, the

oscillator circuit is completed by connecting either a 4.194304 MHz crystal or ceramic resonator across OSC1 and

OSC2 pins. Specifications of the ceramic resonator and crystal are tabulated in Table 4. It is also possible to

configure a number of these devices employing only a single oscillator crystal. The OSC2 output of the first device

in the chain is connected to the OSC1 input of the next device. Subsequent devices are connected similarly. The

oscillator circuit can also be driven by an 4.194304 MHz external clock applied on pin OSC 1. The OSC2 pin should

be left open.

For MT317xB devices, the CLK input is driven directly by an 4.194304 MHz external digital clock.

Frequency 1 (Hz) Frequency 2 (Hz) On/Off Description

350 440 continuous North American Dial Tones

425 --- continuous European Dial Tones

400 --- continuous Far East Dial Tones

480 620 0.5s/0.5s North American Line Busy

440 --- 0.5s/0.5s Japanese Line Busy

480 620 0.25s/0.25s North American Reorder Tones

440 480 2.0s/4.0s North American Audible Ringing

480 620 0.25s/0.25s North American Reorder Tones

Parameter Unit Resonator Crystal

R1 Ohms 6.580 150

L1 mH 0.359 95.355

C1 pF 4.441 15.1E-03

C0 pF 34.890 12.0

Qm - 1.299E+03 101.2E+ 03

∆f%±0.2% ±0.01%

R1 = Equivalent resistor.

L1 = Equivalent inductance.

C1 = Equivalent compliance.

C0 = Capacitance between electrode.

L1 C1 R1

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

Applications

The circuit shown in Figure 3 illustrates the use of a MT327xB in a typical receiver application. It requires only a

coupling capacitor (C1) and a crystal or ceramic resonator (X1) to complete the circuit.

The MT3x70B is designed for user who wishes to tailor the guard time for specific applications. When a DTMF

signal is present, the ESt pin will go high. An external microcontroller monitors ESt in real time for a period of time

set by the user. A guard time algorithm must be implemented such that DTMF signals not meeting the timing

requirements are rejected. The MT3x71B uses an internal counter to provide a preset DTMF validation period. It

requires no external components. The DStD output high indicates that a valid DTMF digit has been detected.

The 4.194304 MHz frequency has a secondary advantage in some applications where a real time clock is required.

A 22-bit counter will count 4,194,304 cycles to provide a one second time base.

Figure 3 - Application Circuit for MT327xB

DTMF/CP Input

INPUT

OSC2

OSC1

VSS

VDD

ESt/DStD

ACK

VDD

COMPONENTS LIST:

C1 = 0.1 µF ± 10 %

X1 = Crystal or Resonator (4.194304 MHz)

To microprocessor or

microcontroller

MT327xB

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Absolute Maximum Ratings† - Voltages are with respect to VSS=0V unless otherwise stated.

Parameter Symbol Min. Max. Units

1 DC Power Supply Voltage VDD-VSS 6V

2 Voltage on any pin (other than supply) VI/O -0.3 6.3 V

3 Current at any pin (other than supply) II/O 10 mA

4 Storage temperature TS-65 150 °C

5 Package power dissipation PD500 mW

Recommended Operating Conditions - Voltages are with respect to VSS=0V unless otherwise stated

Parameter Sym. Min. Typ.‡Max. Units Test Conditions

1 Positive Power Supply VDD 4.75 5.0 5.25 V

2 Oscillator Clock Frequency fOSC 4.194304 MHz

3 Oscillator Frequency Tolerance ∆fOSC ±0.1 %

4 Operating Temperature Td-40 25 85 °C

DC Electrical Characteristics - Voltages are with respect to VDD=5V±5%,VSS=0V, and temperature -40 to 85°C, unless otherwise

stated.

Characteristics Sym. Min. Typ.‡Max. Units Test Conditions

1 Operating supply current IDD 38mA

2 Standby supply current IDDQ 30 100 µA PWDN=5V, ACK=0V

ESt/DStD = SD = 0V

3a Input logic 1 VIH 4.0 V

3b Input logic 1

(for OSC1 input only)

VIH 3.5 V MT327xB/MT337xB

4a Input logic 0 VIL 1.0 V

4b Input logic 0

(for OSC1 input only)

VIL 1.5 V MT327xB/MT337xB

5 Input impedance (pin 1) RIN 50 kW

6 Pull-down Current

(PWDN, ACK pins)

IPD 25 mA with internal pull-down

resistor of approx. 200 kΩ.

PWDN/ACK = 5V

7 Output high (source)

current

IOH 0.4 4.0 mA VOUT=VDD-0.4V

8 Output low (sink) current IOL 1.0 9.0 mA VOUT=VSS+0.4V

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

AC Electrical Characteristics - voltages are with respect to VDD=5V±5%, VSS=0V and temperature -40 to +85°C unless otherwise

stated.

Characteristics Sym. Min. Typ.‡Max. Units Test Conditions*

1 Valid input signal level

(each tone of composite signal)

-50

2.45

775

dBm

mVRMS

1,2,3,5,6,12

2 Positive twist accept 8 dB 1,2,3,4,11,12,15

3 Negative twist accept 8 dB 1,2,3,4,11,12,15

4 Frequency deviation accept ±1.5%± 2Hz 1,2,3,5,12

5 Frequency deviation reject ±3.5%1,2,3,5,12,15

6 Third tone tolerance -16 dB 1,2,3,4,5,12

7 Noise tolerance -12 dB 7,9,12

8 Dial tone tolerance +15 dB 8,10,12

9 Supervisory tones detect level

(Total power)

-35 dBm 16

10 Supervisory tones reject level -50 dBm 16

11 Energy detector attack time tSA 1.0 6.5 ms 16

12 Energy detector decay time tSD 325ms16

13a

13b

Powerdown time

Powerup time

IDDQ ≤ 100µA

MT3170B/3370B

MT3171B/3371B

Note 14

14 Tone present detect time (ESt

logic output)

tDP 3 13 20 ms MT3x70B

15 Tone absent detect time (ESt

logic output)

tDA 3 15 ms MT3x70B

16 Tone duration accept

(DStD logic output)

tREC 40 ms MT3x71B

17 Tone duration reject

(DStD logic output)

tREC 20 ms MT3x71B

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing

* Test Conditions 1. dBm refers to a reference power of 1 mW delivered into a 600 ohms load.

2. Data sequence consists of all DTMF digits.

3. Tone on = 40 ms, tone off = 40 ms.

4. Signal condition consists of nominal DTMF frequencies.

5. Both tones in composite signal have an equal amplitude.

6. Tone pair is deviated by ±1.5%± 2 Hz.

7. Bandwidth limited (0-3 kHz) Gaussian noise.

8. Precise dial tone frequencies are 350 Hz and 440 Hz (± 2%).

9. Referenced to lowest level frequency component in DTMF signal.

10. Referenced to the minimum valid accept level.

11. Both tones must be within valid input signal range.

12. External guard time for MT3x70B = 20 ms.

13. Timing parameters are measured with 70pF load at SD output.

14. Time duration between PWDN pin changes from ‘1‘ to ‘0‘ and ESt/DStD becomes active.

15. Guaranteed by design and characterization. Not subject to production testing.

16. Value measured with an applied tone of 450 Hz.

18 Interdigit pause accept (DStD

logic output)

tID 40 ms MT3x71B

19 Interdigit pause reject (DStD

logic output)

tDO 20 ms MT3x71B

20 Data shift rate 40-60% duty cycle fACK 1.0 3.0 MHz 13,15

21 Propagation delay

(ACK to Data Bit)

tPAD 100 140 ns 1MHz fACK,

13,15

22 Data hold time (ACK to SD) tDH 30 50 ns 13,15

AC Electrical Characteristics - voltages are with respect to VDD=5V±5%, VSS=0V and temperature -40 to +85°C unless otherwise

stated.

Characteristics Sym. Min. Typ.‡Max. Units Test Conditions*

MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet

Zarlink Semiconductor Inc.

Figure 4 - Timing Diagram

Figure 5 - ACK to SD Timing

INPUT

ESt

(MT3x70B)

DStD

(MT3x71B)

ACK

DTMF

Tone #n

tDP

tREC tDO

DTMF

Tone #n + 1

DTMF

Tone

#n + 1

Input

Signal

tDA

tREC tID

LSB MSB

b0b1b2b3b0b1b2b3

tSA tSD

Input

Signal

Envelope

LSB MSB

tDO

tID

- maximum allowable dropout during valid DTMF signals. (MT3x7xB).

tREC

tDA

tDP

tSA

tSD

- minimum time between valid DTMF signals (MT3x71B).

- maximum DTMF signal duration not detected as valid (MT3x7xB).

- minimum DTMF signal duration required for valid recognition (MT3x71B).

- time to detect the absence of valid DTMF signals (MT3x70B).

- time to detect the presence of valid DTMF signals (MT3x70B).

- supervisory tone integrator attack time (MT3x7xB).

- supervisory tone integrator decay time (MT3x7xB).

ESt/DStD

ACK

VIH

VIL

VIH

VIL

1/fACK

tPAD tDH

b0b1b2b3

MSB

DTMF Energy

Detect

LSB

DTMF Energy

Detect

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