HSP9501JC-32 - Intersil Corporation

FN2786.5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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HSP9501

Programmable Data Buffer

The HSP9501 is a 10-Bit wide programmab le data buffer

designed for use in high speed digital systems. Two different

modes of operation can be selected through the use of the

MODSEL input. In the delay mode, a programmable data

pipeline is created which can provide 2 to 1281 clock cycles

of delay between the input and output data. In the data

recirculate mode, the output data path is internally routed

back to the input to provide a programmable circular buffer.

The length of the buffer or amount of delay is programmed

through the use of the 11-bit Length Control Input Port (LC0-

10) and the Length Control Enable (LCEN). An 11-bit value

is applied to the LC0-10 inputs, LCEN is asserted, an d the

next selected clock edge loads the new count value into the

Length Control Register. The delay path of the HSP9501

consists of two registers with a programmable delay RAM

between them, therefore, the value programmed into the

Length Control Register is the desired length - 2. The range

of values which can be programmed into the Length Control

overall range of progra mmable delays from 2 to 1281.

Clock select logic is provided to allow the use of a positive or

negative edge system clock as the CLK input to the

HSP9501. The active edge of the CLK input is controlled

through the use of the CLKSEL input. All synchronous timing

(i.e., data setup, hold, and output delays) are relative to the

clock edge selected by CLKSEL. An additional clock enable

input (CLKEN) provides a means of disabling the internal

clock and holding the existing contents temporarily. All

outputs of the HSP9501 are three-state outputs to allow

direct interfacing to system or multi-use buses.

The HSP9501 is recommended for digital video pro ce ssing

or any applications which require a programmable delay or

circular data buffer.

Features

• DC to 32MHz Operating Frequency

• Programmable Buffer Length from 2 to 1281 Words

• Supports Data Words to 10 Bits

• Clock Select Logic for Positive or Negative Edge

System Clocks

• Data Recirculate or Delay Modes of Operation

• Expandable Data Word Width or Buffer Length

• Three-State Outputs

• TTL Compatible Inputs/Outputs

• Low Power CMOS

Applications

• Sample Rate Conversion

• Data Time Compression/Expansion

• Software Controlled Data Alignment

• Programmable Serial Data Shifting

• Audio/Speech Data Processing Video/Image Processing

Video/Image Processing

• 1-H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples:

- High Resolu tion Monitor Delay Line

- Comb Filter Designs

- Progressive Scanning Display

- TV Standards Conversion

- Image Processing

Ordering Information

PART NUMBER TEMP.

RANGE (°C) PACKAGE PKG.

DWG. #

HSP9501JC-32 0 to 70 44 Ld PLCC N44.65

Data Sheet August 2004

Pinout 44 LEAD PLCC

TOP VIEW

Block Diagram

CLKSEL

CLK

LC2

LC3

LC4

LC5

MODSEL

LCEN

CLK EN

DO9

LC0

LC1

LC10

LC9

LC8

LC7

LC6

DI9

4065 321444342414

18 19 20 21 22 23 24 25 26 27 28

838

DO0

DO1

DO2

DO3

DO4

GND

DO5

DO6

DO7

DO8

VCC

DI0

DI1

DI2

DI3

DI4

GND

DI5

DI6

DI7

DI8

VCC

MODSEL MUX

CLOCK

GENERATOR

CLKSEL

CLK

CLKEN

LC0 -10

DO0-9

DI 0 -9

LCEN

PROGRAMMABLE

DELAY RAM

0-1279 DELAYS

HSP9501

Pin Descriptions

NAME PIN NUMBER TYPE DESCRIPTION

VCC 12, 34 The +5V power supply pin. A 0.1µF capacitor between the VCC and GND pin is

recommended.

GND 13, 33 The device ground.

CLK 1 I Input Clock. This clock signal is used to control the data movement through the programmable

buffer. It is also the signal which latches the input data, length control word and mode select. Input

setup and hold times with respect to the clock must be met for proper operation.

DIO-9 27, 29-32, 35-39 IData Inputs. This 10-bit input port is used to provide the input data. When MODSEL is low, data

on the DI0-9 inputs is latched on the clock edge selected by CLKSEL.

DO0-9 7-11, 14-18 OData Outputs. This 10-bit port provides the output data from the Internal Delay Registers. Data

latched into the DI0-9 inputs will appear at the DO0 9 outputs on the Nth clock cycle, where N is

the total delay programmed.

LC0-10 20-26, 41-44 ILength Control Inputs. These inputs are used to specify the number of clock cycles of delay

between the DI0-9 inputs and the DO0-9 outputs. An integer value between 0 and 1279 is placed

on the LC0-10 inputs, and the total delay length (N) programmed is the LC0-10 value plus 2. In

order to properly load an active le ngth control word, the value must be presented to the LC0-10

inputs and LCEN must be asserted during an active clock edge selected by CLKSEL.

LCEN 6 I Length Control Enable. LCEN is used in conjunction with LC0-10 and CLK to load a new length

control word. An 11-bit value is loaded on the LC0-10 inputs, LCEN is asserted, and the next

selected clock edge will load the new count value. Since this operation is synchronous, LCEN must

meet the specified setup/hold times with respect to CLK for proper operation.

OE 19 IOutput Enable. This input controls the state of the DO0-9 output port. A low on this control line

enables the port for output. When OE is high, the output drivers are in the high impedance state.

Internal latching or transfer of data is not affected by this input.

MODSEL 40 IMode Select. This input is used to control the mode of operation of the HSP9501. A low on

MODSEL causes the device to latch new data at the DI0-9 inputs on every clock cycle, and operate

as a programmable pipeline register. When MODSEL is high, the HSP9501 is in the recirculate

mode, and will operate as a programmable length circular buffer. This control signal may be used

in a synchronous fashion during device operation, however, care must be taken to ensure the

required setup/hold times with respect to CLK are met.

CLKSEL 5 I Clock Select Control. This input is used to determine which edge of the CLK signal is used for

controlling all internal events. A low on CLKSEL selects the negative going edge, therefore, all

setup, hold, and output delay times are with respect to the negative edge of CLK. When CLKSEL

is high, the positive going edge is selected and all synchronous timing is with respect to the positive

edge of the CLK signal.

CLKEN 2 I Clock Enable. This control signal can be used to enable or disable the CLK input. When low, the

CLK input is enabled and will operate in a normal fashion. A high on CLKEN will disable the CLK

input and will “hold'' all internal operations and data. This control signal may also be used in a

synchronous fashion, however, setup and hold requirements with respect to CLK must be met for

proper device operation. This signal takes effect on the clock following the one that latches it in.

HSP9501

Functional Description

The HSP9501 is a 10-bit wide programmable length data

buffer. The length of delay is programmable from 2 to 1281

delays in single delay increments.

Data into the delay line may be selected from the data input

bus (DI0-9) or as recirculated output, depending on the state

of the mode select (MODSEL) control input.

Mode Select

The MODSEL control pin selects the source of the data

moving into the delay line. When MODSEL is low, the data

input bus (DI0-9) is the source of the data. When MODSEL

is high, the output of the HSP9501 is routed back to the input

to form a circular buffer.

The MODSEL control line is latched at the input by the CLK

signal. The edge which latches this control signal is deter-

mined by the CLKSEL control line. In either case, the

MODSEL line is latched on one edge of the CLK signal with

the following edge moving data into and through the

HSP9501. Refer to the functional timing waveforms for

specific timing references.

Clock Select Logic

The clock select logic is provided to allow the use of positive

or negative edge system clocks. The active edge of the CLK

input to the HSP9501 is controlled through the use of the

CLKSEL input.

When CLKSEL is low, the negative going edge of CLK is

used to control all internal operations. A high on CLKSEL

selects the positive going edge of CLK.

All synchronous timing (i.e., setup, hold and output

propagation delay times are relati ve to the CLK edge

selected by CLKSEL. Functional timing waveforms for each

state of CLKSEL are provided (refer to Timing Waveforms

for details).

Delay Path Control

The HSP9501 buffer length is programmable from 2 to 1281

data words in one word increments. The minimum number of

delays which can be programmed is two, consisting of the

input and Output Buffer Registers only.

The length control inputs (LC0-10) are used to set the length

of the programmable delay ram which can va ry in length

from 0 to 1279. The total length of the HSP9501 data buffer

will then be equal to the programmed value on LC0-10 plus

2. The programmed delay is established by the 11-bit integer

value of the LC0-10 inputs with LC-10 as the MSB and LC0

as the LSB.

For example,

programs a length value of 26 + 20 = 65. The total length of

the delay will be 65 + 2 or 67 delays.

Table 1 indicates several programming values. The decimal

value placed on LC0-10 must not exceed 1279. Controlled

operation with larger values is not guaranteed.

Values on LC0-10 are latched on the CLK edge selected by

the CLKSEL control line, when LCEN is active. LC0-10 and

LCEN must meet the specified setup and hold times relative

to the selected CLK edge for proper device operation.

LC10 9 8 7 6 5 4 3 2 1 LC0

0 0 0 0 1 0 0 0 0 0 1

TABLE 1. LENGTH CONTROL PROGRAMMING EXAMPLES

LC10 210 LC9

29LS8

28LC7

27LC6

26LC5

25LC4

24LC3

23LC2

22LC1

21LC0

20PROGRAMMED

LENGTH

TOTAL

LENGTH

0 0 0 0 0 0 0 0 0 0 0 0 2

0 0001110110 118 120

0 1100101000 808 810

1 0000011001 1049 1051

1 0011111111 1279 1281

HSP9501

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V

Input, Output or Voltage Applied . . . . . . . .GND -0.5V to VCC +0.5V

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . ..0°C to 70°C

Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to 5.25V

Thermal Resistance (Typical, Note 1) θJA (°C/W)

PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300°C

(PLCC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications VCC = 5.0V +5%, TA = 0°C to 70°C, Commercial

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Logical One Input Voltage VIH VCC = 5.25V 2.0 - V

Logical Zero Input Voltage VIL VCC = 4.75V -0.8 V

Output HIGH Voltage VOH IOH = -4mA VCC = 4.75V 2.4 - V

Output LOW Voltage VOL IOL = +4.0mA VCC = 4.75V -0.4 V

Input Leakage Current IIVIN = GND or VCC VCC = 5.25V -10 10 µA

Output Leakage Current IOVOUT = GND or VCC = 5.25V -10 10 µA

Standby Current ICCSB VIN = VCC or GND, VCC = 5.25V, Note 3 -500 µA

Operating Power Supply Current ICCOP f = 25MHz, VIN = VCC or GND

VCC = 5.25V, Notes 2, 3 -125 mA

Input Capacitance CIN FREQ = 1MHz, VCC = Open, All

measurements are referenced to device

GND

-10 pF

Output Capacitance CO-10 pF

AC Electrical Specifications VCC = 5.0V ±5%, TA = 0°C to +70°C, Commercia l, (Note 5)

PARAMETER SYMBOL

-32 -25

UNITS NOTESMIN MAX MIN MAX

Clock Period t CP 31 -40 -ns -

Clock Pulse Width High t PWH 12 -15 -ns -

Clock Pulse Width Low t PWL 12 - - 15 ns -

Data Input Setup Time t DS 10 -12 -ns -

Data Input Hold Time t DH 2 - 2 - ns -

Output Enable Time t ENA -20 -25 ns -

Output Disable Time t DIS -24 -25 ns Note 4

CLKEN to Clock Setup t ES 10 -12 -ns -

CLKEN to Clock Hold t EH 2 - 2 - ns -

LC0-10 Setup Time t LS 10 -13 -ns -

LC0-10 Hold Time t LH 2 - 2 - ns -

LCEN to Clock Setup t LES 10 -13 -ns -

HSP9501

Test Load Circuit

NOTE: Includes stray and jig capacitance.

LCEN to Clock Hold t LEH 2 - 2 - ns -

MODSEL Setup Time t MS 10 -13 -ns -

MODSEL Hold Time t MH 2 - 2 - ns -

Clock to Data Out TOUT -16 -22 ns -

Output Hold from Clock TOH 4 - 4 - ns -

Rise, Fall Time TRF - 6 - 6 ns Note 4

NOTES:

2. Power supply current is proportional to ope rating frequency. Typical rating for ICCOP is 5mA/MHz.

3. Output load per test load circuit with switch open and CL = 40pF.

4. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design

changes.

5. AC Testing is performed as follows: Input levels: 0V and 3.0V, timing reference levels = 1.5V, input rise and fall times driven at 1ns/V, output

load CL = 40pF.

AC Electrical Specifications VCC = 5.0V ±5%, TA = 0°C to +70°C, Commercia l, (Note 5) (Continued)

PARAMETER SYMBOL

-32 -25

UNITS NOTESMIN MAX MIN MAX

EQUIVALENT CIRCUIT

CL (NOTE)

IOH 1.5V IOL

DUT

SWITCH S1 OPEN FOR ICCSB AND ICCOP

Timing Waveforms

FIGURE 1. FUNCTIONAL TIMING (CLKSEL = LOW)

tMS tPWL

tPWH

tDH

tDS

tDIS tENA

tOUT 1.7

1.3

tMH

CLK

MODSEL

DI 0 -9

DO 0 -9 tOH

tCP

HSP9501

FIGURE 2. CLEN TIMING (CLKSEL = LOW)

FIGURE 3. OUTPUT RISE AN D FALL TIMES FIGURE 4. LENGTH CONTROL TIMING (CLKSEL = LOW)

FIGURE 5. FUNCTIONAL TIMING (CLKSEL = HIGH)

Timing Waveforms (Continued)

CLK

INTERNAL

CLOCK

CLKEN

tES TEH tES

tRF tRF

2.0V

0.8V 2.0V

0.8V

CLK

LCEN

tLES

tLS

tLEH

tLH

LC0 -10

tMS

tDH

tDS

tDIS tENA

tOUT 1.7

1.3

tMH

CLK

MODSEL

DI 0 -9

DO 0 -9

tOH

tCP

tPWL tPWH

HSP9501

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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FIGURE 6. CLKEN TIMING (CLKSEL = HIGH)

FIGURE 7. LENGTH CONTROL TIMING (CLKSEL = HIGH)

Timing Waveforms (Continued)

INTERNAL

CLOCK

CLKEN

tES tES

CLK

tEH

LCEN

tLES

tLS

tLEH

tLH

CLK

LC 0 -10

HSP9501