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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGenerates Clocks for Next Generation
Microprocessors
DUses a 14.318-MHz Crystal Input to
Generate Multiple Output Frequencies
DIncludes Spread Spectrum Clocking (SSC),
0.6% Downspread for Reduced EMI With
Theoretical EMI of 7 dB
DPower Management Control Terminals
DLow Output Skew and Jitter for Clock
Distribution
DOperates From a Single 3.3-V Supply
DGenerates the Following Clocks:
− 8 Host (Diff Pairs, 100/133 MHz)
− 1 CLK33 (3.3 V, 33.3 MHz)
− 1 REFCLK (3.3 V, 14.318 MHz)
− 2 3V48 (3.3 V, 180° Shifted Pairs, 48 MHz)
DPackaged in a 48-Pin TSSOP Package
description
The CDC950 is a differential clock synthesizer/
driver that generates HCLK/HCLK, CLK33, 3V48,
and REFCLK system clock signals to support a
computer system with next generation processors
and double data rate (DDR) memory subsystems.
All output frequencies are generated from a
14.318-MHz crystal input. A reference clock input
can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the
host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the
need for external components.
The HCLK, CLK33 clock, and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock
operation. All outputs have 3-state capability, which can be selected through control inputs SEL100/133,
3V48/SelA, and 3V48/SelB.
The outputs are either differential host clock or 3.3-V single-ended CMOS buf fers. With a logic high-level on the
PWRDWN terminal, the device operates normally. When a logical low-level input is applied, the device powers
down completely with the HOST clock at 2 × IREF, HOSTB is undriven, CLK33, 3V48, and REFCLK outputs are
in a low-level output state and 3V48B is in a high-level output state.
The host bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with the corresponding
setting for SEL100/133 control input. The CLK33 (PCI) frequency is fixed to 33 MHz.
Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up, as well as following changes to the SEL inputs. With the
use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time
starts. The CDC950 is characterized for operation from 0°C to 85°C.
Copyright 2001 − 2003, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK33
VDD3.3V
3V48/SelA
3V48/SelB
GND
VDD3.3V
HCLK(0)
HCLK(0)
GND
HCLK(1)
HCLK(1)
VDD3.3V
HCLK(2)
HCLK(2)
GND
HCLK(3)
HCLK(3)
VDD3.3V
REFCLK
SPREAD
GND
XIN
XOUT
VDD3.3V
SEL100/133
GND
AVDD3.3V
AGND
PWRDWN
VDD3.3V
HCLK(4)
HCLK(4)
GND
HCLK(5)
HCLK(5)
VDD3.3V
HCLK(6)
HCLK(6)
GND
HCLK(7)
HCLK(7)
VDD3.3V
MultSel0
MultSel1
GND
AGND
I_REF
AVDD3.3V
DGG PACKAGE
(TOP VIEW)
SCAS646B − FEBRUAR Y 2001 − REVISED OCTOBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Control
Logic
48
Xtal
Oscillator
XIN
XOUT
22
23 PLL
Sync Logic & Power Down Logic
Test
2
Latched
3
4
Spread
Logic
20
(7,10,13,16,
33,36,39,42)
(8,11,14,17
32,35,38,41)
100/133 MHz
/3
CPU
PLL /2 /2
/2
44
I_REF 26
2
Control Logic
MultSel0 30
MultSel1 29
Phase
Shift
1 CLK33
33.3 MHz
(1)
1 3V48B
48 MHz
(4)
100/133 MHz
8 HCLKs
1 REFCLK
14.318 MHz
(19)
1 3V48
(3)
48 MHz
180°
SEL100/133
SPREAD
PWRDWN
SEL100/133
8 HCLKs
3-State/Low
48-MHz
3V48/SelA
3V48/SelB
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
3V48/SelA,
3V48/SelB 3, 4 I/O 48-MHz 180° shifted pair clocks for USB use
Logic select pins. Selects the mode of operation, see Table 1 for details.
AGND 27, 45 PAnalog ground
AVDD3.3V 25, 46 PPower. Analog power supply
CLK33 1 O 33-MHz reference clock for PCI use, host clock divided by 3 or by 4
GND 5, 9, 15,
21, 28, 34,
40, 47
P Ground
HCLK 7, 10, 13,
16, 33, 36,
39, 42 OCPU and host clock outputs [7:0]. These eight differential CPU clock pairs run at 100/133 MHz. The VOH
swing amplitude is configured by MultSel0, MultSel1 pins. See Table 5 and Intel’s CK00 document for
details.
HCLK 8, 11, 14,
17, 32, 35,
38, 41 OCPU and host clock outputs [7:0]. These eight differential CPU clock pairs run at 100/133 MHz. The VOH
swing amplitude is configured by MultSel0, MultSel1 pins. See Table 5 and Intel’s CK00 document for
details.
I_REF 26 I Current reference. This pin establishes the reference current for host clock parts. See Table 5 and Intel’s
CK00 document for details.
MultSel0 30 I See Table 5 and Intel’s CK00 document for details.
MultSel1 29 I See Table 5 and Intel’s CK00 document for details.
PWRDWN 44 I Power-down input. 3.3-V LVTTL compatible, asynchronous input that requests the device to enter the
power-down mode. See Table 2 for details.
REFCLK 19 O 14.138-MHz reference clock output: 3.3 V copy of the 14.318-MHz reference clock.
SEL100/133 48 I Active low LVTTL level logic select. SEL100/133 is used for enabling 100/133 MHz. Low = 100 MHz, high
= 133 MHz
SPREAD 20 U Spread spectrum enable. 3.3-V LVTTL compatible, input that enables the spread spectrum mode when
held low. See Table 4 for details.
VDD3.3V 2, 6, 12,
18, 24, 31,
37, 43
PPower. Power supply
XIN 22 I Crystal connection or an external reference frequency input. Connect to either a 14.138-MHz crystal or
an external reference signal.
XOUT 23 O Crystal connection. An output connection for an external 14.318-MHz crystal. If using an external
reference, this pin must be left unconnected.
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4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
Table 1. Select Functions
INPUTS OUTPUTS
FUNCTION
SEL100/133 SelA SelB HCLK, HCLK CLK33 3V48, 3V48 REFCLK
FUNCTION
0 0 0 100 MHz 33 MHz 48 MHz 14.318 MHz Active 100 MHz
0 0 1 100 MHz 33 MHz L, H 14.318 MHz 100 MHz mode; PLL48 powerdown
0 1 0 105 MHz 35 MHz 48 MHz 14.318 MHz 100 MHz mode 5% overclocking
0 1 1 Hi-Z Hi-Z Hi-Z Hi-Z All 3-state outputs
1 0 0 133 MHz 33 MHz 48 MHz 14.318 MHz Active 133 MHz
1 0 1 127 MHz 31.7 MHz 48 MHz 14.318 MHz 133 MHz mode −5% underclocking
1 1 0 133 MHz 33 MHz 48 MHz 14.318 MHz Test mode
1 1 1 TCLK/2 TCLK/8 TCLK/2 TCLK Test mode (PLL bypass)
Table 2. Enable Functions
INPUT OUTPUTS
PWRDWN HCLK HCLK CLK33 3V48 3V48 REFCLK
02 × IREF Hi-Z L L H L
1 On On On On On On
Table 3. Output Buffer Specifications
BUFFER NAME VDD RANGE
(V) IMPEDANCE
(Ω)BUFFER TYPE
3V48, REFCLK 3.135 − 3.465 20−60 TYPE 3
CLK33 3.135 − 3.465 12−55 TYPE 5
HCLK/HCLK 3.135 − 3.465 TYPE X1
Table 4. Spread Spectrum Functions
INPUT
OUTPUTS
SPREAD
OUTPUTS
0Spread spectrum clocking active, −0.6% at HCLK/HCLK, CLK33
1Spread spectrum clocking inactive
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Function Tables (Continued)
Table 5. Host/HOST Output Buffer Specifications
INPUT
BOARD TARGET
REFERENCE R,
OUTPUT CURRENT
VOH at Z
MultSel0 MultSel1
BOARD TARGET
TRACE/TERM Z
REFERENCE R,
IREF = VDD/(3 Rr)
OUTPUT CURRENT
IOH
V
OH
at Z
0 0 60 ΩRr = 475 1%, I_REF = 2.32 mA 5 × IREF 0.71 V at 60 Ω
0 0 50 ΩRr = 475 1%, I_REF = 2.32 mA 5 × IREF 0.59 V at 50 Ω
0 1 60 ΩRr = 475 1%, I_REF = 2.32 mA 6 × IREF 0.85 V at 60 Ω
0 1 50 ΩRr = 475 1%, I_REF = 2.32 mA 6 × IREF 0.71 V at 50 Ω
1 0 60 ΩRr = 475 1%, I_REF = 2.32 mA 4 × IREF 0.56 V at 60 Ω
1 0 50 ΩRr = 475 1%, I_REF = 2.32 mA 4 × IREF 0.47 V at 50 Ω
1 1 60 ΩRr = 475 1%, I_REF = 2.32 mA 7 × IREF 0.99 V at 60 Ω
1 1 50 ΩRr = 475 1%, I_REF = 2.32 mA 7 × IREF 0.82 V at 50 Ω
0 0 30 (dc equivalent) Rr = 221 1%, I_REF = 5 mA 5 × IREF 0.75 V at 30 Ω
0 0 25 (dc equivalent) Rr = 221 1%, I_REF = 5 mA 5 × IREF 0.62 V at 25 Ω
0 1 30 (dc equivalent) Rr = 221 1%, I_REF = 5 mA 6 × IREF 0.90 V at 30 Ω
0 1 25 (dc equivalent) Rr = 221 1%, I_REF = 5 mA 6 × IREF 0.75 V at 25 Ω
1 0 30 (dc equivalent) Rr = 221 1%, I_REF = 5 mA 4 × IREF 0.60 V at 30 Ω
1 0 25 (dc equivalent) Rr = 221 1%, I_REF = 5 mA 4 × IREF 0.5 V at 25 Ω
1 1 30 (dc equivalent) Rr = 221 1%, I_REF = 5 mA 7 × IREF 1.05 V at 30 Ω
1 1 25 (dc equivalent) Rr = 221 1%, I_REF = 5 mA 7 × IREF 0.84 V at 25 Ω
NOTE: The entries in boldface are the primary system configurations of interest. The outputs should be optimized for these configurations.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD −0.5 V to 4.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) –0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO 2 × rated IOL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK:(V
I < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI > VDD) 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK:(V
O < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VO > VDD) 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2) 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3) 1070 mW. . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA –0°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for the through-hole packages,
which use a trace length of zero.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
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DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR†
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
DGG 1400 mW 11.2 mW/°C900 mW 730 mW
†This is the inverse of the traditional junction-to-case thermal resistance (RθJA) and uses a
board-mounted device at 89°C/W
recommended operating conditions (see Note 4)
MIN NOM‡MAX UNIT
Supply voltages, VDD, AVDD 3.135 3.3 3.465
High-level input voltage, VIH 2
V
Low-level input voltage, VIL 0.8 V
Input voltage, VI−0.3 VDD + 0.3
HCLK/HCLK −40
High-level output current, IOH
CLK33 −18
High-level output current, IOH 3V48/SelA and 3V48/SelB −14
REFCLK −14
mA
HCLK/HCLK 0 mA
Low-level output current, IOL
CLK33 12
Low-level output current, IOL 3V48/SelA and 3V48/SelB 9
REFCLK 9
Reference frequency, f(XIN)§Test mode 14
MHz
Crystal, f(XTAL)¶Normal mode 13.8 14.318 14.8 MHz
Operating free-air temperature, TA0 85 °C
‡All nominal values are measured at their respective nominal VDD values.
§Reference frequency is a test clock driven on the XIN input during the device test mode or normal mode. In test mode, XIN can be driven externally
up to f(XIN) = 16 MHz. If XIN is driven externally, XOUT is floating.
¶This is a series fundamental crystal with fo = 14.31818 MHz
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input clamp voltage VDD = 3.135 V, II = –18 mA −1.2 V
IIH High-level input
current All inputs except
SelA, SelB VDD = 3.465 V, VI = VDD 5µA
IIL Low-level input
current All inputs except
SelA, SelB VDD = 3.465 V, VI = GND −5 µA
IOZ High-impedance
-state output
current
All outputs including
SelA, SelB VDD = 3.465 V
3V48/SelA, 3V48/SelB = H,
SEL100/133 = L,
VO = VDD or GND,
PWRDWN = H
±10 µA
IDD(Z) High-impedance-state supply current‡VDD = 3.465 V 3V48/SelA, 3V48/SelB = H,
SEL100/133 = L,
PWRDWN = H 19 25 mA
IDD(PD) SelA, SelB = L
R(ref) = 475 Ω
VDD Supply 43 47 mA
AIDD(PD) PWRDWN state supply current‡
R
(ref)
= 475
Ω
PWRDWN = L AVDD Supply 3.4 4.2 mA
IDD(D)
Dynamic supply current‡
VDD = 3.465 V,
Rref = 475 Ω
PWRDWN = H
SSC = ON/OFF
100 MHz 173 190
mA
IDD(D)
Dynamic supply current‡
DD
R
ref
= 475
Ω,
IO = 6 x Iref
SSC = ON/OFF
CL = MAX 133 MHz 183 200 mA
100 MHz and SSC off 19 24
AlDD
Analog power supply current
VDD = 3.465 V
133 MHz and SSC off 26 33
mA
AlDD Analog power supply current VDD = 3.465 V 100 MHz and SSC on 26 33 mA
133 MHz and SSC on 35 45
CIInput capacitance§VDD = 3.3 V, VI = VDD or GND 2 5
pF
C(XTAL) Crystal load capacitanceWEffective capacity between CIN and COUT 13.5 22.5
pF
†All typical values are measured at their respective nominal VDD values.
‡CL = MAX = 5 pF, RS = 33.2 Ω, Rp = 49.9 Ω at HCLK/HCLK (Type X1)
CL = MAX = 20 pF, RL = 500 Ω at 48 MHz, REF (Type 3)
CL = MAX = 30 pF, RL = 500 Ω at CLK33 (Type 5)
§These parameters are assured by design and lab characterization, not 100% production tested.
¶This is the corresponding capacitive load for the XTAL in this oscillator application (Pierce oscillator)
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
HCLK/HCLK (Type X1)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
roOutput resistance 3000 Ω
VOOutput voltage 1.2 V
IO
Output current
VDD = 3.30 V nom
All combinations of Table 5, See Note 5
−7%
l(NOM) 7%
l(NOM)
mA
IOOutput current VDD = 3.30 V, ±5% All combinations of Table 5, See Note 5 −12%
l(NOM) 12%
l(NOM)
mA
COOutput capacitance VDD = 3.30 V nom VO = VDD GND 3.5 pF
NOTE 5: I(NOM) is output current (IOH) of table 5.
3V48, 3V48REFCLK (Type 3)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH
High-level output voltage
VDD = min to max, IOH = –1 mA VDD – 0.1
VOH High-level output voltage VDD = 3.135 V, IOH = −14 mA 2.4
V
VOL
Low-level output voltage
VDD = min to max, IOL = 1 mA 0.1 V
VOL Low-level output voltage VDD = 3.135 V, IOL = 9 mA 0.18 0.4
VDD = 3.135 V, VO = 1 V −29
I
OH
High-level output current VDD = 3.3 V, VO = 1.65 V −37
IOH
High-level output current
VDD = 3.465 V, VO = 3.135 V −11 −23
mA
VDD = 3.135 V, VO = 1.95 V 29 mA
I
OL
Low-level output current VDD = 3.3 V, VO = 1.65 V 39
IOL
Low-level output current
VDD = 3.465 V, VO = 0.4 V 16 27
COOutput capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7 pF
Zo
Output impedance
High state VO = 0.5 VDD, VO/IOH 20 40 60
Ω
ZoOutput impedance Low state VO = 0.5 VDD, VO/IOL 20 40 60 Ω
†All typical values are measured at their respective nominal VDD values.
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CLK33 (Type 5)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH
High-level output voltage
VDD = min to max, IOH = –1 mA VDD – 0.1
V
OH
High-level output voltage
VDD = 3.135 V, IOH = −18 mA 2.4
V
VOL
Low-level output voltage
VDD = min to max, IOL = 1 mA 0.1 V
VOL Low-level output voltage VDD = 3.135 V, IOL = 12 mA 0.15 0.4
VDD = 3.135 V, VO = 1 V −33
I
OH
High-level output current VDD = 3.3 V, VO = 1.65 V −53
IOH
High-level output current
VDD = 3.465 V, VO = 3.135 V −16 −33
mA
VDD = 3.135 V, VO = 1.95 V 30 mA
I
OL
Low-level output current VDD = 3.3 V, VO = 1.65 V 51
IOL
Low-level output current
VDD = 3.465 V, VO = 0.4 V 21 38
COOutput capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7.5 pF
Zo
Output impedance
High state VO = 0.5 VDD, VO/IOH 12 35 55
Ω
Z
o
Output impedance
Low state VO = 0.5 VDD, VO/IOL 12 35 55 Ω
†All typical values are measured at their respective nominal VDD values.
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
V(over) Overshoot†
HCLK/HCLK 0.7-V
VOH + 200
mV
V(under) Undershoot†
HCLK/HCLK 0.7-V
amplitude VOL − 200 mV
V(over) Overshoot†
Other clocks,
GND − 0.7
V
V(under) Undershoot†
Other clocks,
CL = worst case VDD + 0.7 V
tPZL Output enable time
from low level SEL100/133 All outputs SEL100/133 ↑
Rref = 475 Ω10
tPZH Output enable time to
high level SEL100/133 All outputs SEL100/133 ↑
Rref = 475 Ω10
ns
tPHZ Output disable time
from high level SEL100/133 All outputs SEL100/133 ↓
Rref = 475 Ω10 ns
tPLZ Output disable time
from low level SEL100/133 All outputs SEL100/133 ↓
Rref = 475 Ω10
ts
Stabilization time‡
VDD All outputs After power up 0.1 ms
t
s
Stabilization time‡
PWRDWN All outputs From PWRDWN ↑0.25 ms
† These parameters are assured by design and lab characterization, not 100% production tested.
‡Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its refer ence signal. In order for
phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at XIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the
time since VDD achieves its nominal operating level (3.3 V) or PWRDWN transition from a low to a high level (2 V) until the output frequency is
stable and operating within specification.
SCAS646B − FEBRUAR Y 2001 − REVISED OCTOBER 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued)
HCLK/HCLK (Type X1), CL = 2 pF, Rref = 475 Ω, 6 x Rref
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HCLK clock period‡
f(HCLK) = 100 MHz 10 10.2
ns
HCLK clock period‡
f(HCLK) = 133 MHz 7.5 7.65 ns
Tjit(cc)
Cycle-to-cycle jitter
f(HCLK) = 100 or 133 MHz
SSC off −80 80
ps
Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz SSC on −110 110 ps
tdc Duty cycle f(HCLK) = 100 or 133 MHz,
Crossing point 45% 55%
tsk(o) HCLK bus skew f(HCLK) = 100 or 133 MHz,
Crossing point 70 ps
trRise time†
0.7-V amplitude
VO = 0.14 V to 0.56 V 175 700
ps
tfFall time†0.7-V amplitude VO = 0.14 V to 0.56 V 175 700 ps
v(cross) Cross point voltages†0.7-V amplitude f(HCLK) = 100 or 133-MHz
HCLK and HCLK 45%
VOH 55%
VOH V
† These parameters are assured by design and lab characterization, not 100% production tested.
‡The average over any 1-µs period of time is greater than the minimum specified period.
CLK33 (Type 5), CL = 30 pF, RL = 500 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PCI clock period†f(HCLK) = 100 or 133 MHz 30 30.06 30.6 ns
Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz −150 150 ps
t(dc) Duty cycle f(CLK33) = 33.3 MHz 45% 55%
trRise time VO = 0.4 V to 2.4 V 0.5 2
ns
tfFall time VO = 0.4 V to 2.4 V 0.5 2
ns
†The average over any 1-µs period of time is greater than the minimum specified period.
3V48 (Type 3), CL = 20 pF, RL = 500 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3V48 clock period f(HCLK) = 100 or 133 MHz 20.83 ns
Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz −300 300 ps
tdc Duty cycle f(3V48) = 48 MHz 45% 55%
trRise time VO = 0.4 V to 2.4 V 1 4
ns
tfFall time VO = 0.4 V to 2.4 V 1 4
ns
REF (Type 3), CL = 20 pF, RL = 500 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REF clock period f(REF) = 14.318 MHz 69.84
ns
Tjit(cc) Cycle-to-cycle jitter f(HCLK) = 100 or 133 MHz −0.5 0.5
ns
t(dc) Duty cycle f(REF) = 14.318 MHz 45% 55%
trRise time VO = 0.4 V to 2.4 V 1 4
ns
tfFall time VO = 0.4 V to 2.4 V 1 4 ns
SCAS646B − FEBRUAR Y 2001 − REVISED OCTOBER 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tw
VIH(REF)
VT(REF)
VIL(REF)
3 V
0 V
Input
CL
(see Note A)
Test Point
From Output
Under Test
LOAD CIRCUIT for tr and tfVOLTAGE WAVEFORMS
VT(REF) VT(REF) VT(REF) VT(REF)
3 V
0 V
VDD
0 V
Input
tPLH
VIH(REF)
VT(REF)
VIL(REF)
tPHL
VOH
VOL
trtf
tw(high) tw(low)
Output
tPZL
tPZH
tPLZ
tPHZ
VT(REF)
VT(REF)
VOL + 0.3 V
VOH − 0.3 V
≈3 V
VOL
VOH
≈0 V
Output Enable
(High-Level
Enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
RL = 500 Ω
RL = 500 Ω
S1 VO(REF)
OPEN
GND
CL
(see Note A)
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VO(REF)
GND
S1
LOAD CIRCUIT For tpd and tsk
NOTES: A. CL includes probe and jig capacitance. CL = 2 pF (HCLK, HCLK), CL = 20 pF (48 MHz, REF), CL = 30 pF (CLK33).
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 14.318 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
PARAMETER 3.3-V INTERFACE UNIT
VIH(REF) High-level reference voltage 2.4
VIL(REF) Low-level reference voltage 0.4
V
VT(REF) Input threshold reference voltage 1.5
V
VO(REF) Off-state reference voltage 6
Figure 1. Load Circuit and Voltage Waveforms
SCAS646B − FEBRUAR Y 2001 − REVISED OCTOBER 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
HCLK
MultSel0
MultSel1
CDC950
HCLK
TLA
TLB
R(S1) = 33 Ω
R(S1) = 33 Ω
RI(REF) = 475 Ω
R(T1) = 49.9 Ω
R(T1) = 49.9 ΩCL = 2 pF CL = 2 pF
CL Represents CBOARD and Cjig
ZTLA = ZTLB = 50 Ω
VDD
HCLK
HCLK
Figure 2. Load Circuit for HCLK Bus
spread spectrum clock (SSC) implementation for CDC950
Simultaneously switching at a fixed frequency generates a significant power peak at the selected frequency,
which in turn causes EMI disturbance to the environment. The purpose of the internal frequency modulation of
the CPU-PLL allows energy to be distributed to many different frequencies which reduces the power peak.
A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in
Figure 3.
∆
Maximum Peak
SSC
δ of f(nom) f(nom)
Non-SSC
Figure 3. Frequency Power Spectrum With and Without the Use of SSC
The modulated spectrum has its distribution (left side) associated with the single-frequency spectrum which
indicates a down-spread modulation.
The peak reduction depends on the modulation scheme and modulation profile. System performance and timing
requirements are the limiting factors for actual design implementations. The implementation was driven to keep
the average clock frequency close to its upper specification limit. The modulation amount was set to
approximately –0.6%.
To allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation signal
is limited in order to minimize SSC induced tracking skew jitter. The modulation frequency is approximately
31 kHz.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CDC950DGG ACTIVE TSSOP DGG 48 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CDC950DGGG4 ACTIVE TSSOP DGG 48 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CDC950DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
CDC950DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CDC950DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Aug-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDC950DGGR TSSOP DGG 48 2000 333.2 345.9 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Aug-2008
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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