240pin Registered DDR2 SDRAM DIMMs based on 1Gb A ver. This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 1Gb 1st ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb ver. based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply * Fully differential clock operations (CK & /CK) * * All inputs and outputs are compatible with SSTL_1.8 interface Programmable Burst Length 4 / 8 with both sequential and interleave mode * Auto refresh and self refresh supported * 8 Bank architecture * 8192 refresh cycles / 64ms * Posted CAS * Serial presence detect with EEPROM * Programmable CAS Latency 3 , 4 , 5 * DDR2 SDRAM Package: 60, 68ball FBGA * OCD (Off-Chip Driver Impedance Adjustment) * 133.35 x 30.00 mm form factor * ODT (On-Die Termination) * Lead-free Products are RoHS compliant * ORDERING INFORMATION Density Organization # of DRAMs # of ranks Parity Support HYMP112P72AP8-C4/Y5 1GB 128Mx72 9 1 O HYMP125P72AP4-C4/Y5 2GB 256Mx72 18 1 O HYMP351P72AMP4-C4/Y5 4GB 512Mx72 36 2 O HYMP112R72AP8-E3 1GB 128Mx72 9 1 X HYMP125R72AP4-E3 2GB 256Mx72 18 1 X HYMP351R72AMP4-E3 4GB 512Mx72 36 2 X Part Name This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Jul. 2007 1 1240pin Registered DDR2 SDRAM DIMMs SPEED GRADE & KEY PARAMETERS E3 (DDR2-400) C4 (DDR2-533) Y5 (DDR2-667) Unit Speed@CL3 400 400 400 Mbps Speed@CL4 533 533 533 Mbps Speed@CL5 667 - 667 Mbps CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 tCK ADDRESS TABLE Organization Ranks SDRAMs # of DRAMs # of row/bank/column Address Refresh Method 1GB 128M x 72 1 128Mb x 8 9 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms 2GB 256M x 72 1 256Mb x 4 18 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms 4GB 512M x 72 2 256Mb x 4 36 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms Rev. 0.2 / Jul. 2007 2 1240pin Registered DDR2 SDRAM DIMMs Input/Output Functional Description Symbol Type Polarity Pin Description CK0 IN Positive Edge Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CK0 IN Negative Edge Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. CKE[1:0] IN Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. S[1:0] IN Active Low Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1 ODT[1:0] IN Active High On-Die Termination signals. RAS, CAS, WE IN Active Low When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define the command being entered. Vref Supply Reference voltage for SSTL18 inputs VDDQ Supply Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. BA[2:0] IN - Selects which DDR2 SDRAM internal bank of Eight is activated. During a Bank Activate command cycle, Address input difines the row address(RA0~RA13) A[9:0],A10/AP A[13:11] IN - DQ[63:0], CB[7:0] IN - DM[8:0] IN Active High VDD,VSS Supply During a Read or Write command cycle, Address input defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data and Check Bit Input/Output pins. DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on these modules. DQS[17:0] I/O Positive Edge Positive line of the differential data strobe for input and output data DQS[17:0] I/O Negative Edge Negative line of the differential data strobe for input and output data SA[2:0] IN - These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA I/O - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. SCL IN - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDDSPD to act as a pull up on the system board. Supply Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V. RESET IN The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (the PLL will remain synchronized with the input clock) Par_In IN Parity bit for the Address and Control bus("1". Odd, "0".Even) Err_Out OUT VDDSPD TEST Rev. 0.2 / Jul. 2007 Parity error found in the Address and Control bus Used by memory bus analysis tools(unused on memory DIMMs) 3 1240pin Registered DDR2 SDRAM DIMMs PIN DESCRIPTION Pin Pin Description Pin Pin Description CK0 Clock Input,positive line ODT[1:0] CK0 Clock input,negative line VDDQ DQs Power Supply DQ0~DQ63 Data Input/Output CKE0~CKE1 Clock Enable Input On Die Termination Inputs RAS Row Address Strobe CB0~CB7 Data check bits Input/Output CAS Column Address Strobe DQS(0~8) Data strobes WE Write Enable DQS(0~8) Data strobes,negative line DM(0~8),DQS(9~17) Data Maskes/Data strobes DQS(9~17) Data strobes,negative line RFU Reserved for Future Use S0,S1 A0~A9,A11~A13 A10/AP BA0, BA1, BA2 Chip Select Input Address input Address input/Autoprecharge SDRAM Bank Address NC No Connect SCL Serial Presence Detect(SPD) Clock Input TEST Memory bus test tool(Not Connected and Not Usable on DIMMs) SDA SPD Data Input/Output VDD Core Power SA0~SA2 E2PROM Address Inputs Par_In Parity bit for the Address and Control bus Err_Out Parity error found on the Addre RESET Reset Enable CB0~CB7 VDDQ VSS VREF VDDSPD I/O Power Supply Ground Reference Power Supply Power Supply for SPD Data Strobe Inputs/Outputs PIN LOCATION 1 pin 121 pin Rev. 0.2 / Jul. 2007 Front Side Back Side 64 pin 65 pin 184 pin 185 pin 120 pin 240 pin 4 1240pin Registered DDR2 SDRAM DIMMs PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name Pin 1 VREF 41 VSS 81 DQ33 121 VSS 161 CB4 201 Name VSS 2 VSS 42 CB0 82 VSS 122 DQ4 162 CB5 202 DM4/DQS13 DQS13 3 DQ0 43 CB1 83 DQS4 123 DQ5 163 VSS 203 4 DQ1 44 VSS 84 DQS4 124 VSS 164 DM8,DQS17 204 VSS 5 VSS 45 DQS8 85 VSS 125 DM0/DQS9 165 DQS17 205 DQ38 6 DQS0 46 DQS8 86 DQ34 126 DQS9 166 VSS 206 DQ39 7 DQS0 47 VSS 87 DQ35 127 VSS 167 CB6 207 VSS 8 VSS 48 CB2 88 VSS 128 DQ6 168 CB7 208 DQ44 9 DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45 10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS 11 VSS 51 VDDQ 91 VSS 131 DQ12 171 NC,CKE1 211 DM5/DQS14 12 DQ8 52 CKE0 92 DQS5 132 DQ13 172 VDD 212 DQS14 13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15,NC 213 VSS 14 VSS 54 BA2,NC 94 VSS 134 DM1/DQS10 174 A14,NC 214 DQ46 15 DQS1 55 NC,Err_Out 95 DQ42 135 DQS10 175 VDDQ 215 DQ47 16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS 17 VSS 57 A11 97 VSS 137 RFU 177 A9 217 DQ52 18 RESET 58 A7 98 DQ48 138 RFU 178 VDD 218 DQ53 19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS 20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 RFU 21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 RFU 22 DQ11 62 VDDQ 102 NC(TEST) 142 VSS 182 A3 222 VSS 23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6/DQS15 24 DQ16 64 VDD 104 DQS6 144 DQ21 184 VDD 224 NC,DQS15 25 DQ17 105 DQS6 145 VSS 26 VSS 65 106 VSS 146 DM2/DQS11 27 DQS2 66 VSS 107 DQ50 147 DQS11 186 28 DQS2 67 VDD 108 DQ51 148 VSS 187 29 VSS 68 NC,Err_Out 109 VSS 149 DQ22 188 30 DQ18 69 VDD 110 DQ56 150 DQ23 189 31 DQ19 70 A10/AP 111 DQ57 151 VSS 32 VSS 71 BA0 112 VSS 152 DQ28 Key VSS Key 225 VSS 226 DQ54 CK0 227 DQ55 VDD 228 VSS A0 229 DQ60 VDD 230 DQ61 190 BA1 231 VSS 191 VDDQ 232 DM7/DQS16 185 CK0 33 DQ24 72 VDDQ 113 DQS7 153 DQ29 192 RAS 233 NC,DQS16 34 DQ25 73 WE 114 DQS7 154 VSS 193 S0 234 VSS 35 VSS 74 CAS 115 VSS 155 DM3/DQS12 194 VDDQ 235 DQ62 36 DQS3 75 VDDQ 116 DQ58 156 DQS12 195 ODT0 236 DQ63 37 DQS3 76 NC, S1 117 DQ59 157 VSS 196 A13,NC 237 VSS 38 VSS 77 NC, ODT1 118 VSS 158 DQ30 197 VDD 238 VDDSPD 39 DQ26 78 VDDQ 119 SDA 159 DQ31 198 VSS 239 SA0 40 DQ27 79 VSS 120 SCL 160 VSS 199 DQ36 240 SA1 80 DQ32 200 DQ37 NC= No Connect, RFU= Reserved for Future Use. Notes: 1. RESET(Pin 18) is connected to both OE of PLL and Reset of register. 2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity. 3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs) Rev. 0.2 / Jul. 2007 5 1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 1GB(128Mbx72) : HYMP112[R,P]72AP8 /R S 0 DQS4 /D Q S 4 D M 4,D Q S 13 /D Q S 13 DQS0 /D Q S 0 D M 0,D Q S 9 /D Q S 9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 NU /R D Q S /C S DQS D Q 32 DQ33 DQ34 DQ35 D Q 36 DQ37 DQ38 DQ39 D0 DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 NU /R D Q S /C S DQS D Q 40 DQ41 DQ42 DQ43 D Q 44 DQ45 DQ46 DQ47 D1 DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 NU /R D Q S /C S DQS I/O I/O I/O I/O I/O NU /R D Q S /C S DQS /D Q S DQS /D Q S DQS /D Q S D5 3 4 5 6 7 D Q 48 DQ49 DQ50 DQ51 D Q 52 DQ53 DQ54 DQ55 D2 NU /R D Q S DM RDQS I/O 0 I/O 1 I/O 2 /D Q S I/O I/O I/O I/O I/O /C S D6 3 4 5 6 7 DQS7 /D Q S 7 D M 7,D Q S 16 /D Q S 16 DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 NU /R D Q S /C S DQS D Q 56 DQ57 DQ58 DQ59 D Q 60 DQ61 DQ62 DQ63 D3 NU /R D Q S DM RDQS I/O 0 I/O 1 I/O 2 /D Q S DQS8 /D Q S8 D M 8D Q S 1 7 /D Q S 17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 /D Q S DQS6 /D Q S 6 D M 6 ,D Q S 15 /D Q S1 5 DQS0 /D Q S 0 D M 0,D Q S 9 /D Q S 12 D Q 24 D Q 25 D Q 26 D Q 27 D Q 28 D Q 29 D Q 30 D Q 31 DQS D4 3 4 5 6 7 DM RDQS I/O 0 I/O 1 I/O 2 /D Q S DQS2 /D Q S 2 D M 2,D Q S 11 /D Q S 11 D Q 16 D Q 17 D Q 18 D Q 19 D Q 20 D Q 21 D Q 22 D Q 23 I/O I/O I/O I/O I/O /C S DQS5 /D Q S 5 D M 5,D Q S 1 4 /D Q S 14 DQS1 /D Q S 1 D M 1,D Q S 10 /D Q S 1 0 DQ8 DQ9 D Q 10 D Q 11 D Q 12 D Q 13 D Q 14 D Q 15 NU /R D Q S DM RDQS I/O 0 I/O 1 I/O 2 /D Q S I/O I/O I/O I/O I/O /C S D7 3 4 5 6 7 S erial P D V D D SP D DM RDQS I/O 0 I/O 1 I/O 2 I/O I/O I/O I/O I/O 3 4 5 6 7 R E G I S T E R /C S0* B A0 to BA 2 A 0 to A 13 /R AS /C A S C KE 0 /W E NU /R D Q S /C S DQS /D Q S SCL SD A SCL W P D8 /R S0 to /C S ==> /C S: S D R AM s D 0 to D 8 A0 SA0 VDD / VDDQ A1 A2 SA 1 Serial P D SDA U0 D O -D 8 V R EF D O -D 8 V SS D O -D 8 SA 2 CK0 R BA 0 to R B A 2 ==> BA 0 to BA 2: SD R AM s D 0 to D 8 /C K 0 P L L PC K 0 to P C K 6 , P C K 8 ,P C K 9 ==> C K : S D R A M s D0 toD 8 OE /P C K 7 ==> /C K : R eg ister /P C K 0 to /P C K 6, /P C K 8, /P C K 9 ==> /C K : S D R A M s D 0 toD 8 /R A 0 to R A 13 ==> A 0 to A 13: S D R AM s D 0 to D 8 /R R AS = =>/R A S : SD R AM s D 0 to D 8 /R C AS = =>/C A S : SD R AM s D 0 to D 8 P C K 7 == > C K : R eg ister /R E S E T R C KE 0 ==> C KE : S D R A M s D 0 to D 8 /R W E ==> /W E : S D R A M s D 0 to D 8 ODT0 R O D T0 == > O D T 0: S D R A M s D 0 to D 8 /R ESE T /R S T PC K 7 N otes : 1. R e gister values are 22 O hm s. /PC K 7 * : /S 0 co nnects to D /C S and V D D conn ects to /C S R on re gister. Rev. 0.2 / Jul. 2007 6 1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 2GB(256Mbx72): HYMP125[R,P]72AP4 VSS / R S0 / D Q S0 D Q S0 / D Q S9 D Q S9 DQS / DQS /CS I/ O 0 I/O 1 D0 I/O 2 I/O3 D Q0 D Q1 D Q2 D Q3 DM D Q4 D Q5 D Q6 D Q7 / D Q S1 D Q S1 DM DQS / DQS /CS I/O 0 I/O 1 D 10 I/O 2 I/O 3 DM S e ria l P D SCL DQS / DQS /CS I/O 0 I/O 1 D1 I/O 2 I/ O3 DM D Q12 D Q13 D Q14 D Q15 W P D Q 16 D Q 17 D Q 18 D Q19 DQS / DQS /CS I/O 0 I/O 1 D2 I/O 2 I/ O3 DM DQS / DQS /CS I/O 0 I/O 1 D3 I/O 2 I/ O3 DM D Q20 D Q21 D Q22 D Q23 / D Q S3 D Q S3 DQS / DQS /CS I/O 0 I/O 1 D 11 I/O 2 I/O 3 DM DQS / DQS /CS I/O 0 I/O 1 D 12 I/O 2 I/O 3 DM DQS / DQS /CS I/O 0 I/O 1 D 13 I/O 2 I/O 3 DM DQS / DQS /CS I/O 0 I/O 1 D 14 I/O 2 I/O 3 DM DQS / DQS /CS I/O 0 I/O 1 D 15 I/O 2 I/O 3 DM DQS / DQS /CS I/O 0 I/O 1 D 16 I/O 2 I/O 3 DM DQS / DQS /CS I/O 0 I/O 1 D 17 I/O 2 I/O 3 DM U0 A0 A1 A2 SA0 SA1 SA2 SDA VDD S P D S erial PD V D D /V D D Q D O-D 17 / D Q S11 D Q S11 / D Q S2 D Q S2 SDA SCL / D Q S10 D Q S10 D Q8 D Q9 D Q10 D Q11 V REF D O-D 17 VSS D O-D 17 / D Q S12 D Q S12 D Q 24 D Q25 D Q26 D Q 27 D Q28 D Q29 D Q30 D Q31 / D Q S13 D Q S13 / D Q S0 D Q S0 D Q32 D Q33 D Q34 D Q 35 DQS / DQS /CS I/O 0 I/O 1 D4 I/O 2 I/O 3 DM DQS / DQS /CS I/O 0 I/O 1 D5 I/O 2 I/ O3 DM D Q36 D Q37 D Q38 D Q39 / D Q S5 D Q S5 / D Q S14 D Q S14 D Q 40 D Q41 D Q42 D Q 43 D Q44 D Q45 D Q46 D Q47 / D Q S15 D Q S15 / D Q S6 D Q S6 DQS / DQS /CS I/O 0 I/O 1 D6 I/O 2 I/ O3 D Q 48 D Q49 D Q50 D Q 51 DM D Q52 D Q53 D Q54 D Q55 / D Q S7 D Q S7 / D Q S16 D Q S16 D Q 56 D Q57 D Q58 D Q 59 DQS / DQS /CS I/O 0 I/O 1 D7 I/O 2 I/ O3 DM DQS / DQS /CS I/O 0 I/O 1 D8 I/O 2 I/ O3 DM D Q60 D Q61 D Q62 D Q63 / D Q S17 D Q S17 / D Q S8 D Q S8 C B0 C B1 C B2 C B3 R E G I S T E R /C S 0* B A 0 to B A 2 A 0 to A 1 3 /R A S /C A S CKE0 /W E C B4 C B5 C B6 C B7 CK0 /R S 0 to /C S = = > /C S : S D R A M s D 0 to D 1 7 ODT0 PC K 0 to P C K 6, P C K8,P C K 9 = > C K : S D R A M x D 0-D 17 P L L /C K 0 /P C K 0 to /PC K 6, /PC K 8,/P C K 9 = > /C K : S D R A M x D 0-D 17 R B A 0 to R B A 2 = = > B A 0 to B A 2 : S D R A M s D 0 to D 1 7 PC K 7 = > C K: R egiste r /R A 0 to R A 1 3 = = > A 0 to A 1 3: S D R A M s D 0 to D 17 /R R A S = = > /R A S : S D R A M s D 0 to D 1 7 /R E S E T OE /P C K 7 = > /C K : R egister /R C A S = = > /C A S : S D R A M s D 0 to D 1 7 R C K E 0 = = > C K E : S D R A M s D 0 to D 17 /R W E = => /W E : S D R A M s D 0 to D 1 7 R O D T 0 = = > O D T 0: S D R A M s D 0 to D 1 7 /R E S E T DQS / DQS /CS I/O 0 I/O 1 D9 I/O 2 I/ O 3 N o tes : 1 . R e sisto r va lue s a re 22 O h m s +/- 5% . /R S T PCK7 /P C K 7 * /S 0 co nn ects to D /C S o f R e gister1 an d /C S R o f R e gister2 . /C S R of re gister a nd D/C S o f re g ister2 co nn ects to V D D . ** /R E S E T ,P C K 7 co nn ect to bo th R eg iste rs. O the r sign als con ne ct to o ne o f tw o R e g isters. /S 1 ,C K E 1 an d O D T1 are N C . Rev. 0.2 / Jul. 2007 7 1240pin Registered DDR2 SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 4GB(512Mbx72) : HYMP351[R,P]72AMP4 VSS / RS0 / RS1 Serial PD DQ0 DQ1 DQ2 D Q3 DM / C S DQ S / DQ S DM / CS DQ S / DQ S I/O0 I/O1 D0,D 18( DD P) I/O2 I/O3 / RS0 / RS1 DM / C S DQ S / DQ S DM / CS DQ S I/O0 I/O1 D1,D 19( D DP) I/O2 I/O3 DM / C S DQ S / DQ S DM / CS DQ S / DQ S I/O0 I/O1 D2,D 20( DD P) I/O2 I/O3 DM / C S DQ S / DQ S DM / CS DQ S I/O0 I/O1 D3,D 21( D D P) I/O2 I/O3 / RS0 / RS1 DM / C S DQ S / DQ S DM / CS DQ S I/O0 I/O1 D8,D 26( DD P) I/O2 I/O3 DM / C S DQ S / DQ S I/O0 I/O1 D4,D2( I/O2 I/O3 / RS0 / RS1 DD P) SA 0 SA 1 SA2 DM / CS DQ S / DQ S D M / CS D Q S I/O0 I/O1 D 10,D 28( D D P) I/O2 I/O3 D Q20 D Q21 D Q22 DQ23 Serial PD V DD SPD V D D /V DDQ DO to D 35 V REF DO to D 35 V SS DO to D 35 DM / CS DQ S / DQ S D M / CS D Q S / D Q S I/O0 I/O1 D 11,D 29( D D P) I/O2 I/O3 D Q28 D Q29 D Q30 DQ31 DM / CS DQ S / DQ S D M / CS D Q S I/O0 I/O1 D 12,D 30( D D P) I/O2 I/O3 CB4 CB5 CB6 C B7 DM / CS DQ S / DQ S D M / CS D Q S I/O0 I/O1 D 17,D 35( D D P) I/O2 I/O3 D Q36 D Q37 D Q38 DQ39 DM / CS DQ S / DQ S D M / CS D Q S / D Q S I/O0 I/O1 D 13,D 31( DD P) I/O2 I/O3 D Q44 D Q45 D Q46 DQ47 DM / CS DQ S / DQ S D M / CS D Q S I/O0 I/O1 D 14,D 32( D D P) I/O2 I/O3 DQ S15 / D Q S15 DM / C S DQ S / DQ S DM / CS DQ S / DQ S I/O0 I/O1 D6,D 24( DD P) I/O2 I/O3 D Q52 D Q53 D Q54 DQ55 DM / CS DQ S / DQ S D M / CS D Q S / D Q S I/O0 I/O1 D 15,D 33( D DP) I/O2 I/O3 D Q S9 / D Q S9 D Q S7 / D Q S7 DQ56 DQ57 DQ58 D Q59 A2 DQ S14 / D Q S14 DM / C S DQ S / DQ S DM / CS DQ S I/O0 I/O1 D5,D 23( DD P) I/O2 I/O3 D Q S6 / D Q S6 D Q48 DQ49 DQ50 D Q51 D Q12 D Q13 D Q14 DQ15 DM / CS DQ S / DQ S D Q S5 / D Q S5 DQ40 DQ41 DQ42 D Q43 A1 DQ S13 / D Q S13 D Q S4 / D Q S4 DQ32 DQ33 DQ34 D Q35 A0 DQ S17 / D Q S17 D Q S8 / D Q S8 CB0 CB1 CB2 C B3 W P DM / CS DQ S / DQ S D M / CS D Q S / D Q S I/O0 I/O1 D9,D 27( DD P) I/O2 I/O3 DQ S12 / D Q S12 D Q S3 / D Q S3 DQ24 DQ25 DQ26 D Q27 SD A U0 DQ S11 / D Q S11 D Q S2 / D Q S2 DQ16 DQ17 DQ18 D Q19 D Q4 D Q5 D Q6 D Q7 SDA SCL D Q S10 / D Q S10 D Q S1 / D Q S1 DQ8 DQ9 DQ10 DQ11 SC L D Q S9 / D Q S9 D Q S0 / D Q S0 DM / C S DQ S / DQ S DM / CS DQ S I/O0 I/O1 D7,D 25( DD P) I/O2 I/O3 /S0* /S1* BA0 ? BA 2 A0?A13 /RAS /CAS /W E CKE0 CKE1 1:2 R E G I S T E R O DT0 O DT1 /R ESET** PCK7 ** D Q60 D Q61 D Q62 DQ63 DM / CS DQ S / DQ S D M / CS D Q S I/O0 I/O1 D9,D 34( D DP) I/O2 I/O3 /R S0 to /CS : SD RAM s D 0 ? D 17 /R S 1 to /CS : SD R AM s D 18 ? D 35 CK 0 /RBA0 ? RBA2 = > BA0 -BA2 : SDRAM s D 0-D 35 /C K0 /RA0 ? R A 12 = > A0 -A12 : SDR AM s D 0-D 35 PC K0 to PC K6, PC K 8,PCK 9 = > C K : SD R AM x D0-D 35 P L L /PC K0 to /PC K 6, /PCK 8,/PC K9 = > /CK : SDR A M x D0-D 35 /RR AS = > /R AS: SDR AM s D 0-D 35 PCK 7 = > CK : Register /RCAS = > /C AS: SDRAM s D 0-D35 /R W E = > /W E : SDR AM s D 0-D 35 /R ESET OE /PC K7 = > /C K: R egister RC KE0 = > CKE 0: SD RAM s D 0-D 17 RC KE 1 = > C KE1: SD RAM s D 18-D 35 R O DT0 = > O D T0: SDR AM s D 0-D 17 R O DT1 = > O D T1: SDR AM s D 18-D 35 / RST /PCK7** N otes: 1. R egister values are 22 O hm s +/- 5% . 2. /R S0 and /R S 1 alternate betw een the back and front sides of the D IM M * /S0 connects to D/CS0 and /S1 connects to D /C S1 on both R egisters. ** /R ESET,PC K 7 and /PC K7 connect to both R egisters. O ther signals connect to two R egisters. Rev. 0.2 / Jul. 2007 8 1240pin Registered DDR2 SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Note VDD - 1.0 V ~ 2.3 V V 1 VDDQ - 0.5 V ~ 2.3 V V 1 VIN, VOUT - 0.5 V ~ 2.3 V V 1 Storage Temperature TSTG -50 ~ +100 Storage Humidity(without condensation) HSTG 5 to 95 Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss o C 1 % 1 Notes : 1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con ditions for extended periods may affect reliablility. 3. Up to 9850 ft. OPERATING CONDITIONS Parameter Symbol Rating Units DIMM Operating temperature(ambient) TOPR 0 ~ +55 oC DIMM Barometric Pressure(operating & storage) PBAR 105 to 69 K Pascal DRAM Component Case Temperature Range TCASE 0 ~+95 o C Notes 1 2 Notes : 1. Up to 9850 ft. 2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2. DC OPERATING CONDITIONS Parameter (SSTL_1.8) Min Max Unit VDD 1.7 1.9 V VDDQ 1.7 1.9 V 1 Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V 2 EEPROM Supply Voltage VDDSPD 1.7 3.6 V Termination Voltage VTT VREF-0.04 VREF+0.04 V Power Supply Voltage Symbol Note 3 Notes : 1. VDDQ must be less than or equal to VDD. 2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc) 3. VTT of transmitting device must track VREF of receiving device. Rev. 0.2 / Jul. 2007 9 1240pin Registered DDR2 SDRAM DIMMs INPUT DC LOGIC LEVEL Parameter Symbol Min Max Unit Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V Note INPUT AC LOGIC LEVEL Parameter DDR2 400/533 Symbol DDR2 667/800 Notes Unit Min Max Min Max AC Input logic High VIH(AC) VREF + 0.250 - VREF + 0.200 - V AC Input logic Low VIL(AC) - VREF - 0.250 - VREF - 0.200 V AC INPUT TEST CONDITIONS Symbol Condition Value Units Notes 0.5 * VDDQ V 1 Input signal maximum peak to peak swing 1.0 V 1 Input signal minimum slew rate 1.0 V/ns 2, 3 VREF Input reference voltage VSWING(MAX) SLEW Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising edges and the range from VREF min to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. Start of Falling Edge Input Timing Start of Rising Edge Input Timing VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS VSWING(MAX) delta TF Falling Slew = VDDQ delta TR VREF - VIL(ac) max Rising Slew = delta TF VIH(ac) min - VREF delta TR < Figure : AC Input Test Signal Waveform > Rev. 0.2 / Jul. 2007 10 1240pin Registered DDR2 SDRAM DIMMs Differential Input AC logic Level Symbol Parameter VID (ac) ac differential input voltage VIX (ac) ac differential cross point voltage Min. Max. Units Note 0.5 VDDQ + 0.6 V 1 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - VIL(DC). VDDQ VTR Crossing point VID VIX or VOX VCP VSSQ < Differential signal levels > Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross. DIFFERENTIAL AC OUTPUT PARAMETERS Symbol VOX (ac) Parameter ac differential cross point voltage Min. Max. Units Note 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1 Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Rev. 0.2 / Jul. 2007 11 1240pin Registered DDR2 SDRAM DIMMs OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS Symbol VOTR Parameter Output Timing Measurement Reference Level SSTL_18 Units Notes 0.5 * VDDQ V 1 Notes: 1. The VDDQ of the device under test is referenced. OUTPUT DC CURRENT DRIVE Symbol Parameter IOH(dc) Output Minimum Source DC Current IOL(dc) Output Minimum Sink DC Current SSTl_18 Units Notes - 13.4 mA 1, 3, 4 13.4 mA 2, 3, 4 Notes: 1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. 2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. 3. The dc value of VREF applied to the receiving device is set to VTT 4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement. Rev. 0.2 / Jul. 2007 12 1240pin Registered DDR2 SDRAM DIMMs PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25. f=1MHz ) 1GB : HYMP112[R,P]72AP8 Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Symbol Min Max Unit CCK CI1 CI2 CI3 CIO 7 8 8 8 6 11 12 12 12 9 pF Symbol Min Max Unit CCK CI1 CI2 CI3 CIO 7 8 10 8 6 11 12 15 12 9 pF Symbol Min Max Unit CCK CI1 CI2 CI3 CIO 9.5 10.5 10.5 10.5 17 14 16 16 16 21 pF pF pF pF pF 2GB : HYMP125[R,P]72AP4 Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS pF pF pF pF 4GB : HYMP351[R,P]72AMP4 Pin CK0, CK0 CKE, ODT CS Address, RAS, CAS, WE DQ, DM, DQS, DQS pF pF pF pF Notes : 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. Rev. 0.2 / Jul. 2007 13 1240pin Registered DDR2 SDRAM DIMMs IDD SPECIFICATIONS (TCASE : 0 to 95oC) 1GB, 128M x 72 Registered DIMM : HYMP112[R,P]72AP8 Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Y5(DDR2 667@CL 5) Unit IDD0 TBD TBD TBD mA IDD1 TBD TBD TBD mA IDD2P TBD TBD TBD mA IDD2Q TBD TBD TBD mA IDD2N TBD TBD TBD mA IDD3P(F) TBD TBD TBD mA IDD3P(S) TBD TBD TBD mA IDD3N TBD TBD TBD mA IDD4R TBD TBD TBD mA IDD4W TBD TBD TBD mA IDD5B TBD TBD TBD mA IDD6 TBD TBD TBD mA IDD7 TBD TBD TBD mA note 1 Notes : 1. IDD6 current alues are guaranted up to Tcase of 85 max. 2GB, 256M x 72 Registered DIMM : HYMP125[R,P]72AP4 Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Y5(DDR2 667@CL 5) Unit IDD0 TBD TBD TBD mA IDD1 TBD TBD TBD mA IDD2P TBD TBD TBD mA IDD2Q TBD TBD TBD mA IDD2N TBD TBD TBD mA IDD3P(F) TBD TBD TBD mA IDD3P(S) TBD TBD TBD mA IDD3N TBD TBD TBD mA IDD4R TBD TBD TBD mA IDD4W TBD TBD TBD mA IDD5B TBD TBD TBD mA IDD6 TBD TBD TBD mA IDD7 TBD TBD TBD mA note 1 Notes : 1. IDD6 current alues are guaranted up to Tcase of 85 max. Rev. 0.2 / Jul. 2007 14 1240pin Registered DDR2 SDRAM DIMMs 4GB, 512M x 72 Registered DIMM : HYMP351[R,P]72AMP4 Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Y5(DDR2 667@CL 5) Unit IDD0 TBD TBD TBD mA IDD1 TBD TBD TBD mA IDD2P TBD TBD TBD mA IDD2Q TBD TBD TBD mA IDD2N TBD TBD TBD mA IDD3P(F) TBD TBD TBD mA IDD3P(S) TBD TBD TBD mA IDD3N TBD TBD TBD mA IDD4R TBD TBD TBD mA IDD4W TBD TBD TBD mA IDD5B TBD TBD TBD mA IDD6 TBD TBD TBD mA IDD7 TBD TBD TBD mA note 1 Notes : 1. IDD6 current values are guaranted up to Tcase of 85 max. Rev. 0.2 / Jul. 2007 15 1240pin Registered DDR2 SDRAM DIMMs IDD Measurement Conditions Symbol Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 mA Slow PDN Exit MRS(12) = 1 mA IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W mA IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85 max. mA IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions mA Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: Rev. 0.2 / Jul. 2007 16 1240pin Registered DDR2 SDRAM DIMMs Electrical Characteristics & AC Timings Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin Speed DDR2-667 (Y5) DDR2-533 (C4) DDR2-400 (E3) Unit Bin(CL-tRCD-tRP) 5-5-5 4-4-4 3-3-3 Parameter min min min CAS Latency 5 4 3 ns tRCD 15 15 15 ns tRP 15 15 15 ns tRC 60 60 55 ns tRAS 45 45 40 ns AC Timing Parameters by Speed Grade DDR2-400 Parameter DDR2-533 Symbol Unit Min Max Min Max Note Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps DQS-Out edge to Clock edge Skew tDQSCK -500 500 -500 450 ns Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK Clock Half Period tHP min (tCL,tCH) - min (tCL,tCH) - ns System Clock Cycle Time tCK 5000 8000 3750 8000 ps DQ and DM input setup time tDS 275 - 225 - ps 1 DQ and DM input hold time tDH 150 - 100 - ps 1 Control & Address input Pulse Width for each input tIPW 0.6 - 0.6 - tCK tDIPW 0.35 - 0.35 - tCK tHZ - tAC max - tAC max ps DQ and DM input pulse witdth for each input pulse width for each input Data-out high-impedance window from CK, /CK DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 - 300 ps tQHS - 450 - 400 ps DQ hold skew factor DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps Write command to first DQS latching transition tDQSS WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write preamble tWPRE 0.35 - 0.35 - tCK Rev. 0.2 / Jul. 2007 17 1240pin Registered DDR2 SDRAM DIMMs - continued DDR2-400 Parameter DDR2-533 Symbol Address and control input setup time Address and control input hold time Unit Min Max Min Max tIS 350 - 250 - ps tIH 475 - 375 - ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Auto-Refresh to Active/Auto-Refresh command period tRFC 127.5 - 127.5 - ns Row Active to Row Active Delay for 1KB page size tRRD 7.5 - 7.5 - ns Row Active to Row Active Delay for 2KB page size tRRD 10 - 10 - ns Four Activate Window for 1KB page size tFAW 37.5 - 37.5 - ns Four Activate Window for 2KB page size tFAW 50 - 50 - ns CAS to CAS command delay tCCD 2 2 tCK Write recovery time tWR 15 - 15 - ns Auto Precharge Write Recovery + Precharge Time tDAL tWR+tRP - tWR+tRP - tCK Write to Read Command Delay tWTR 10 - 7.5 - ns Internal read to precharge command delay tRTP 7.5 Exit self refresh to a non-read command tXSNR tRFC + 10 Exit self refresh to a read command tXSRD 200 - 200 - tCK - 2 - tCK Exit precharge power down to any non-read command Note 7.5 ns tRFC + 10 ns tXP 2 Exit active power down to read command tXARD 2 2 tCK Exit active power down to read command (Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK CKE 3 3 tCK AOND 2 2 2 2 tCK AON tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns tAONPD tAC(min)+2 2tCK+tAC(m ax)+1 tAC(min)+2 2tCK+tAC(m ax)+1 ns tAOFD 2.5 2.5 2.5 2.5 tCK tAOF tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max)+ 0.6 ns tAOFPD tAC(min)+2 2.5tCK+tA C(max)+1 tAC(min)+2 2.5tCK+tA C(max)+1 ns ODT to power down entry latency tANPD 3 ODT power down exit latency tAXPD 8 OCD drive mode output delay tOIT 0 tDelay tIS+tCK+tIH tREFI - 7.8 - 7.8 us 2 tREFI - 3.9 - 3.9 us 3 CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) Minimum time clocks remains ON after CKE asynchronously drops LOW t t t Average periodic Refresh Interval 3 tCK 8 12 0 tCK 12 tIS+tCK+tIH ns ns Note : 1. For details and notes, please refer to the relevant HYNIX component datasheet HY5PS1G[4/8]31AFP. 2. 0C TCASE 85C 3. 85C TCASE 95C Rev. 0.2 / Jul. 2007 18 1240pin Registered DDR2 SDRAM DIMMs Parameter Symbol DDR2-667 DDR2-800 min max min max Unit Note DQ output access time from CK/CK tAC -450 +450 -400 +400 ps DQS output access time from CK/CK tDQSCK -400 +400 -350 +350 ps CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK CK half period tHP min(tCL, tCH) - min(tCL, tCH) - ps Clock cycle time, CL=x tCK 3000 8000 2500 tDS 100 - 50 - ps 1 tDH 175 - 125 - ps 1 Control & Address input pulse width for each input tIPW 0.6 - 0.6 - tCK DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 - tCK Data-out high-impedance time from CK/CK tHZ - tAC max - tAC max ps DQ and DM input setup time (differential strobe) DQ and DM input hold time (differential strobe) ps DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ - 240 - 200 ps DQ hold skew factor tQHS - 340 - 300 ps DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps First DQS latching transition to associated clock edge tDQSS - 0.25 + 0.25 - 0.25 + 0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK Write postamble DQS falling edge to CK setup time tWPST 0.4 0.6 0.4 0.6 tCK Auto-Refresh to Active/Auto-Refresh command period tRFC 127.5 - 127.5 - ns Row Active to Row Active Delay for 1KB page size tRRD 7.5 - 7.5 - ns tWPRE 0.35 - 0.35 - tCK Address and control input setup time tIS 200 - 175 - ps Address and control input hold time tIH 275 - 250 - ps Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Activate to precharge command tRAS 45 70000 45 70000 ns Active to active command period for 1KB page size products tRRD 7.5 - 7.5 - ns Row Active to Row Active Delay for 2KB page size tRRD 10 - 10 - ns Four Active Window for 1KB page size products tFAW 37.5 - 35 - ns Four Activate Window for 2KB page size tFAW 50 - 50 - ns Write preamble Rev. 0.2 / Jul. 2007 19 1240pin Registered DDR2 SDRAM DIMMs - continued Parameter Symbol DDR2-667 min DDR2-800 max min max CAS to CAS command delay tCCD 2 Write recovery time tWR 15 - 15 - ns Auto precharge write recovery + precharge time tDAL WR+tRP - WR+tRP - tCK Internal write to read command delay tWTR 7.5 - 7.5 - ns Internal read to precharge command delay 2 Unit tCK tRTP 7.5 7.5 ns Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns Exit self refresh to a read command tXSRD 200 - 200 - tCK tXP 2 - 2 - tCK tXARD 2 2 tCK tXARDS 7 - AL 8 - AL tCK CKE 3 3 tCK tAOND 2 2 2 2 tCK AON tAC(min) tAC(max) +0.7 tAC(min) tAC(max) +0.7 ns AONPD tAC(min)+2 2tCK+ tAC(max)+1 tAC(min) +2 2tCK+ tAC(max)+1 ns tAOFD 2.5 2.5 2.5 2.5 tCK AOF tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max) +0.6 ns AOFPD tAC(min) +2 2.5tCK+ tAC(max)+1 tAC(min) +2 2.5tCK+ tAC(max)+1 ns ODT to power down entry latency tANPD 3 3 ODT power down exit latency tAXPD 8 8 OCD drive mode output delay tOIT 0 Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) t ODT turn-on delay t ODT turn-on ODT turn-on(Power-Down mode) t ODT turn-off delay t ODT turn-off ODT turn-off (Power-Down mode) Minimum time clocks remains ON after CKE asynchronously drops LOW Average periodic Refresh Interval t 12 0 Note tCK tCK 12 tIS+tCK +tIH ns ns tDelay tIS+tCK+tIH tREFI - 7.8 - 7.8 us 2 tREFI - 3.9 - 3.9 us 3 Notes : 1. For details and notes, please refer to the relevant HYNIX component datasheet HY5PS1G[4/8]31AFP. 2. 0C TCASE 85C 3. 85C TCASE 95C Rev. 0.2 / Jul. 2007 20 1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE 128Mx72 (1 rank) - HYMP112[R,P]72AP8 Front Side 133.35 Register 2. 7 max 4.00.1 PLL Detail-A (Front) 30.0 Detail-B 5.175 5.175 63.0 5.0 1. 27 0.10 55.0 10.0 17.80 Back 3.0 3.0 Detail of Contacts B 2.50 1.0 3.80 2.50 0.20 0.20 Detail of Contacts A 0.8 0.05 1.50 0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.2 / Jul. 2007 21 1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE 256Mx72 (1 rank) - HYMP125[R,P]72AP4 Front Side 133.35 Register 4.0 max 4.00.1 PLL Detail-A 30.0 Detail-B 5.175 5.175 63.0 5.0 1.27 0.10 55.0 Register 10.0 17.80 Back 3.0 3.0 Detail of Contacts B 2.50 1.0 3.80 2.50 0.20 0.20 Detail of Contacts A 0.8 0.05 1.50 0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.2 / Jul. 2007 22 1240pin Registered DDR2 SDRAM DIMMs PACKAGE OUTLINE 512Mx72 (2 rank) - HYMP351[R,P]72AMP4 Front Side 133.35 Register 4. 0 max 4.00.1 PLL Detail-A 30.0 Detail-B 5.175 5.175 63.0 5.0 1. 27 0.10 55.0 Register 10.0 17.80 Back 3.0 3.0 Detail of Contacts B 2.50 1.0 3.80 2.50 0.20 0.20 Detail of Contacts A 0.8 0.05 1.50 0.10 5.00 Note) All dimensions are in millimeters unless otherwise stated. Rev. 0.2 / Jul. 2007 23 1240pin Registered DDR2 SDRAM DIMMs REVISION HISTORY Revision History Date 0.1 Initial data sheet released Mar. 2006 0.2 Discarded Speed C4 for Non-parity and corrected typos Jul. 2007 Rev. 0.2 / Jul. 2007 Remark 24