Quad SPDT Switch
ADG333A
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
44 V supply maximum ratings
VSS to VDD analog signal range
Low on resistance (45 Ω max)
Low ∆RON (5 Ω max)
Low RON match (4 Ω max)
Low power dissipation
Fast switching times
tON < 175 ns
tOFF < 145 ns
Low leakage currents (5 nA max)
Low charge injection (10 pC max)
Break-before-make switching action
APPLICATIONS
Audio and video switching
Battery-powered systems
Test equipment
Communication systems
FUNCTIONAL BLOCK DIAGRAM
S1A
D1
S1B
IN1
IN2
S2B
D2
S2A S3A
D3
S3B
IN3
IN4
S4B
D2
S4A
ADG333A
SWITCHES SHOWN FOR A LOGIC 1 INPUT
01212-001
Figure 1.
GENERAL DESCRIPTION
The ADG333A is a monolithic CMOS device comprising four
independently selectable SPDT switches. It is designed on an
LC2MOS process, which provides low power dissipation yet
achieves a high switching speed and a low on resistance.
The on resistance profile is very flat over the full analog input
range, ensuring good linearity and low distortion when
switching audio signals. High switching speed also makes the
part suitable for video signal switching. CMOS construction
ensures ultralow power dissipation, making the part ideally
suited for portable, battery-powered instruments.
When they are on, each switch conducts equally well in both
directions and has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked. All switches exhibit break-before-make
switching action for use in multiplexer applications. Inherent
in the design is low charge inject
PRODUCT HIGHLIGHTS
1. Extended signal range.
The ADG333A is fabricated on an enhanced LC2MOS
process, giving an increased signal range which extends to
the supply rails.
2. Low power dissipation.
3. Low RON.
4. Single-supply operation.
For applications where the analog signal is unipolar, the
ADG333A can be operated from a single rail power supply.
The part is fully specified with a single 12 V supply.
ADG333A
Rev. A | Page 2 of 12
TABLE OF CONTENTS
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Ter mi no lo g y ...................................................................................... 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ..............................................8
Test Circ uits ..................................................................................... 10
Application Information................................................................ 11
ADG333A Supply Voltages....................................................... 11
Power Supply Sequencing ......................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
REVISION HISTORY
3/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Specifications Tables.................................................... 3
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 12
10/95—Revision 0: Initial Version
ADG333A
Rev. A | Page 3 of 12
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V, VSS = −15 V, GND = 0 V, unless otherwise noted.1
Table 1.
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
RON 20 Ω typ VD = ±10 V, IS = –1 mA
45 45 Ω max
∆RON 5 Ω max VD = ±5 V, IS = –10 mA
RON Match 4 Ω max VD = ±10 V, IS = –10 mA
LEAKAGE CURRENTS VDD = +16.5 V, VSS = –16.5 V
Source OFF Leakage IS (OFF) ±0.1 nA typ VD = ±15.5 V, VS = +15.5 V
±0.25 ±3 nA max Figure 15
Channel ON Leakage ID, IS (ON) ±0.1 nA typ VS = VD = ±15.5 V
±0.4 ±5 nA max Figure 16
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current
IINL or IINH ±0.005 µA typ VIN = 0 V or VDD
±0.5 µA max
DYNAMIC CHARACTERISTICS2
tON 90 ns typ RL= 300 Ω, CL = 35 pF;
175 ns max VS = ±10 V; Figure 17
tOFF 80 ns typ RL = 300 Ω, CL = 35 pF;
145 ns max VS = ±10 V; Figure 17
Break-Before-Make Delay, tOPEN 10 ns min RL = 300 Ω, CL= 35 pF;
V
S = +5 V; Figure 18
Charge Injection 2 pC typ VD = 0 V, RD = 0 Ω, CL= 10 nF;
10 pC max VDD = +15 V, VSS = –15 V; Figure 19
OFF Isolation 72 dB typ RL = 75 Ω, CL = 5 pF, f = 1 MHz;
V
S = 2.3 V rms; Figure 20
Channel-to-Channel Crosstalk 85 dB typ RL = 75 Ω, CL = 5 pF, f = 1 MHz;
V
S = 2.3 V rms; Figure 21
CS (OFF) 7 pF typ
CD, CS (ON) 26 pF typ
POWER REQUIREMENTS
IDD 0.05 mA typ Digital inputs = 0 V or 5 V
0.25 0.35 mA max
ISS 0.01 µA typ
1 5 µA max
VDD/VSS ±3/±20 V min/V max |VDD| = |VSS|
1 Temperature range is as follows: B version: −40°C to +85°C.
2 Guaranteed by design; not subject to production test.
ADG333A
Rev. A | Page 4 of 12
SINGLE SUPPLY
VDD = +12 V, VSS = 0 V ± 10%, GND = 0 V, unless otherwise noted.1
Table 2.
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
RON 35 Ω typ VD = 1 V, 10 V, IS = –1 mA
75 Ω max
LEAKAGE CURRENTS VDD = 13.2 V
Source OFF Leakage IS (OFF) ±0.1 nA typ VD = 12.2 V/1 V, VS = 1 V/12.2 V
±0.25 ±3 nA max Figure 15
Channel ON Leakage ID, IS (ON) ±0.1 nA typ VS = VD = 12.2 V/1 V
±0.4 ±5 nA max Figure 16
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current
IINL or IINH ±0.005 µA typ VIN = 0 V or VDD
±0.5 µA max
DYNAMIC CHARACTERISTICS2
tON 110 ns typ RL = 300 Ω, CL = 35 pF;
200 ns max VS = 8 V; Figure 17
tOFF 100 ns typ RL = 300 Ω, CL = 35 pF;
180 ns max VS = 8 V; Figure 17
Break-Before-Make Delay, tOPEN 10 ns min RL = 300 Ω, CL = 35 pF;
ns min VS = 5 V; Figure 18
Charge Injection 5 pC typ VD = 6 V, RD = 0 W, CL = 10 nF;
V
DD = 12 V, VSS = 0 V; Figure 19
OFF Isolation 72 dB typ RL = 75 Ω, CL = 5 pF, f = 1 MHz;
V
S = 1.15 V rms; Figure 20
Channel-to-Channel Crosstalk 85 dB typ RL = 75 Ω, CL = 5 pF, f = 1 MHz;
V
S = 1.15 V rms; Figure 21
CS (OFF) 12 pF typ
CD, CS (ON) 25 pF typ
POWER REQUIREMENTS VDD = 13.5 V
IDD 0.05 mA typ Digital inputs = 0 V or 5 V
0.25 0.35 mA max
VDD ±3/±30 V min/V max
1 Temperature range is as follows: B Version: −40°C to +85°C.
2 Guaranteed by design; not subject to production test.
ADG333A
Rev. A | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 3.
Parameter Min
VDD to VSS +44 V
VDD to GND –0.3 V to +30 V
VSS to GND +0.3 V to –30 V
Analog, Digital Inputs1VSS – 2 V to VDD + 2 V or 20 mA,
whichever occurs first
Continuous Current, S or D 20 mA
Peak Current, S or D (Pulsed at
1 ms, 10% Duty Cycle Max)
40 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Junction Temperature 150°C
θJA, Thermal Impedance
PDIP Package 103°C/W
SOIC Package 74°C/W
SSOP Package 130°C/W
Lead Temperature, Soldering
(10 sec)
260°C
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 Overvoltage at IN, S, or D is clamped by internal diodes. Current should be
limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. Truth Table
Logic Switch A Switch B
0 Off On
1 On Off
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADG333A
Rev. A | Page 6 of 12
TERMINOLOGY
RON
Ohmic resistance between D and S.
∆RON
RON variation due to a change in the analog input voltage with a
constant load current.
RON Match
Difference between the RON of any two channels.
IS (OFF)
Source leakage current with the switch off.
ID (OFF)
Drain leakage current with the switch off.
ID, IS (ON)
Channel leakage current with the switch on.
VD (VS)
Analog voltage on Terminals D, S.
CS (OFF)
OFF switch source capacitance.
CD (OFF)
OFF switch drain capacitance.
CD, CS (ON)
ON switch capacitance.
tON
Delay between applying the digital control input and the output
switching on.
tOFF
Delay between applying the digital control input and the output
switching off.
tOPEN
Break-before-make delay when switches are configured as a
multiplexer.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
Crosstalk
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling through an OFF switch.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ADG333A
Rev. A | Page 7 of 12
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
1
S1A
2
D1
3
S1B
4
IN4
20
S4A
19
D4
18
S4B
17
V
SS 5
GND
6
S2B
7
V
DD
16
NC
15
S3B
14
D2
8
D3
13
S2A
9
S3A
12
IN2
10
IN3
11
NC = NO CONNECT
ADG333A
TOP VIEW
(Not to Scale)
01212-002
IN1
1
S1A
2
D1
3
S1B
4
IN4
20
S4A
19
D4
18
S4B
17
V
SS 5
V
DD
16
GND
6
NC
15
S2B
7
S3B
14
D2
8
D3
13
S2A
9
S3A
12
IN2
10
IN3
11
NC = NO CONNECT
ADG333A
TOP VIEW
(Not to Scale)
01212-003
IN1
1
S1A
2
D1
3
S1B
4
IN4
20
S4A
19
D4
18
S4B
17
V
SS 5
GND
6
S2B
7
V
DD
16
NC
15
S3B
14
D2
8
D3
13
S2A
9
S3A
12
IN2
10
IN3
11
NC = NO CONNECT
ADG333A
TOP VIEW
(Not to Scale)
01212-004
Figure 2. PDIP Pin Configuration Figure 3. SOIC Pin Configuration Figure 4. SSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1, 10, 11, 20 IN1, IN2, IN3, IN4 Logic Control Input.
2, 4, 7, 9, 12, 14,
17, 19
S1A, S1B, S2B, S2A,
S3A, S3B, S4B, S4A
Source Terminal. Can be an input or output.
3, 8, 13, 18 D1, D2, D3, D4 Drain Terminal. Can be an input or output.
5 VSS Most Negative Power Supply Potential in Dual Supplies. In single-supply applications, it can be
connected to ground.
6 GND Ground (0 V) Reference.
15 NC No Connect.
16 VDD Most Positive Power Supply Potential.
ADG333A
Rev. A | Page 8 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C
V
DD
= +5V
V
SS
= –5V
V
DD
= +10V
V
SS
= –10V
V
DD
= +15V
V
SS
= –15V
V
DD
, V
S
(V)
R
ON
(Ω)
60
50
40
30
10
20
–15 –10 0–5 5 10 15
01212-005
Figure 5. RON as a Function of VD (VS):
Dual Supply
T
A
= 25°C
V
DD
= +5V
V
SS
= –5V
V
DD
= +10V
V
SS
= –10V V
DD
= +15V
V
SS
= –15V
V
DD
, V
S
(V)
R
ON
(Ω)
100
90
80
70
60
50
40
30
20 03 9612
01212-006
15
Figure 6. RON as a Function of VD (VS):
Single Supply
+125°C
+85°C
+25°C–40°C
V
DD
= +15V
V
SS
= –15V
V
DD
, V
S
(V)
R
ON
(Ω)
45
40
30
35
25
20
10
15
–15 –10 0–5 5 10 15
01212-007
Figure 7. RON as a Function of VD (VS) for Different Temperatures:
Dual Supply
V
DD
, V
S
(V)
R
ON
(Ω)
60
50
40
30
10
20
0 3 6 9 12 15
01212-008
+125°C+85°C
+25°C
–40°C
V
DD
= 15V
V
SS
= 0V
Figure 8. RON as a Function of VD (VS) for Different Temperatures:
Single Supply
I
S
(OFF)
I
D
(ON)
V
DD
= +16.5V
V
SS
= –16.5V
T
A
= 25°C
V
D
, V
S
(V)
LEAKAGE CURRENT (nA)
0.004
0.002
–0.002
0
–0.004
–0.006
–0.010
–0.008
–15 –10 0–5 5 10 15
01212-009
I
S
(ON)
Figure 9. Leakage Currents as a Function of VD (VS):
Dual Supply
I
S
(OFF)
I
S
(ON)
V
DD
= +16.5V
V
SS
= –16.5V
T
A
= 25°C
V
D
, V
S
(V)
LEAKAGE CURRENT (nA)
0.001
–0.001
0
–0.002
–0.004
–0.003
03 69
01212-010
12
I
D
(ON)
Figure 10. Leakage Currents as a Function of VD (VS):
Single Supply
ADG333A
Rev. A | Page 9 of 12
C
L
= 10nF
V
DD
= +12V
V
SS
= 0V
V
DD
= +16.5V
V
SS
= –16.5V
V
S
(V)
Q (pC)
20
15
10
5
–20
–15
–10
–5
0
–15 –10 0–5 5 10 15
01212-011
Figure 11. Charge Injection as a Function of VS
V
D
= +2V
V
S
= –2V
V
DD
(V)
SWITCHING TIME (ns)
160
140
120
100
80
60 0 5 10 2015
01212-012
Figure 12. Switching Time as a Function of VD
V
DD
= +16.5V
V
SS
= –16.5V
T
A
= 25°C
SWITCHING FREQUENCY (kHz)
I
DD
(mA)
1
0.8
0.6
0.4
0.2
00 200 400 1000600 800
01212-013
Figure 13. IDD as a Function of Switching Frequency
ADG333A
Rev. A | Page 10 of 12
TEST CIRCUITS
V
D
I
DS
SD
R
ON
= V
1
/I
DS
V
1
01212-014
Figure 14. On Resistance
V
D
SD
I
S
(OFF)
V
S
01212-015
A
Figure 15. Off Leakage
V
D
SD
NC
NC = NO CONNECT
01212-016
I
D
(ON)
A
Figure 16. On Leakage
D
GND
IN
SA
SB
–10V
+10V
V
DD
V
DD
V
SS
V
SS
V
S
V
OUT
R
L
300Ω
C
L
35pF
0.1µF
0.1µF
50% 50%
50% 50%
t
ON
t
OFF
V
IN
V
S
+3V
0V
+10V
0V
–10V
01212-017
Figure 17. Switching Times
D
GND
IN
SA
SB
V
DD
V
DD
V
SS
V
SS
V
S
V
OUT
R
L
300Ω
C
L
35pF
0.1µF
0.1µF
01212-018
3V
0V
V
IN
V
OUT
V
S
50% 50%
t
OPEN
Figure 18. Break-Before-Make Delay, tOPEN
V
DD
V
DD
V
SS
V
SS
V
OUT
IN C
L
10nF
GND
V
IN
V
OUT
Q
INJ
= C
L
×
∆V
OUT
∆V
OUT
3V
0V
0V
DSA
V
D
R
D
01212-019
Figure 19. Charge Injection
V
SS
V
OUT
GND
SD
V
IN
V
S
01212-020
V
DD
V
DD
V
SS
0.1µF
0.1µF
R
L
75Ω
VSS
GND
SD
VIN1
VS
01212-021
VDD
VDD
VSS
0.1µF
0.1µF
VOUT NC
CHANNEL-TO-CHANNEL
CROSSTALK
20
×
LOG |VS/VOUT|
VIN2
75Ω
RL
75Ω
SD
Figure 20. Off Isolation Figure 21. Channel-to-Channel Crosstalk
ADG333A
Rev. A | Page 11 of 12
APPLICATION INFORMATION
ADG333A SUPPLY VOLTAGES
The ADG333A can operate from a dual or signal supply. VSS
should be connected to GND when operating with a single
supply. When using a dual supply, the ADG333A can also
operate with unbalanced supplies; for example VDD = 20 V and
VSS = −5 V. The only restrictions are that VDD to GND must not
exceed 30 V, VSS to GND must not drop below −30 V, and VDD
to VSS must not exceed +44 V. It is important to remember that
the ADG333A supply voltage directly affects the input signal
range, the switch on resistance and the switching times of the
part. The effects of the power supplies on these characteristics
can be clearly seen from the Typical Performance Characteristics
curves.
POWER SUPPLY SEQUENCING
When using CMOS devices, care must be taken to ensure
correct power-supply sequencing. Incorrect power-supply
sequencing can result in the device being subjected to stresses
beyond those listed in the Absolute Maximum Ratings. This is
also true for the ADG333A. Always turn on VDD first, followed
by VSS and the logic signals. An external signal within the maxi-
mum specified ratings can then be safely presented to the source
or drain of the switch
ADG333A
Rev. A | Page 12 of 12
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AD
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
20
110
11
0.100 (2.54)
BSC
1.060 (26.92)
1.030 (26.16)
0.980 (24.89)
PIN 1
0.210
(5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 22. 20-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-20)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AC
0.75 (0.0295)
0.25 (0.0098)
20 11
10
1
8°
0°
× 45°
1.27 (0.0500)
0.40 (0.0157)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
0.33 (0.0130)
0.20 (0.0079)
1.27
(0.0500)
BSC
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
13.00 (0.5118)
12.60 (0.4961)
COPLANARITY
0.10
Figure 23. 20-Lead Standard Small Outline Package [SOIC]
Wide Body (R-20)
Dimensions shown in millimeters and (inches)
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
COPLANARITY
0.10
0.05 MIN
1.85
1.75
1.65
0.65
BSC
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
2.00 MAX
0.38
0.22 SEATING
PLANE
PIN 1
COMPLIANT TO JEDEC STANDARDS MO-150AE
Figure 24. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG333ABN −40°C to +85°C 20-Lead Plastic Dual In-Line Package (PDIP) N-20
ADG333ABR −40°C to +85°C 20-Lead Standard Small Outline Package (SOIC) R-20
ADG333ABR-REEL −40°C to +85°C 20-Lead Standard Small Outline Package (SOIC) R-20
ADG333ABRZ1−40°C to +85°C 20-Lead Standard Small Outline Package (SOIC) R-20
ADG333ABRZ-REEL1−40°C to +85°C 20-Lead Standard Small Outline Package (SOIC) R-20
ADG333ABRS −40°C to +85°C 20-Lead Shrink Small Outline Package (SSOP) RS-20
ADG333ABRS-REEL −40°C to +85°C 20-Lead Shrink Small Outline Package (SSOP) RS-20
ADG333ABRSZ1−40°C to +85°C 20-Lead Shrink Small Outline Package (SSOP) RS-20
ADG333ABRSZ-REEL1−40°C to +85°C 20-Lead Shrink Small Outline Package (SSOP) RS-20
1 Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01212–0–3/05(A)
