L6983 Datasheet 38 V, 3 A synchronous step-down converter with 17 A quiescent current Features QFN16 (3 x 3 mm) * * 3.5 V to 38 V operating input voltage Output voltage from 0.85 V to VIN * * * * * 3.3 V and 5 V fixed output voltage versions 3 A DC output current 17 A operating quiescent current Internal compensation network Two different versions: LCM for high efficiency at light loads and LNM for noise sensitive applications 2 A shutdown current Internal soft-start Enable Overvoltage protection Output voltage sequencing Thermal protection 200 kHz to 2.2 MHz programmable switching frequency. Stable with low ESR capacitor Optional spread spectrum for improved EMC Power Good Synchronization to external clock for LNM devices QFN16 package * * * * * * * * * * * Maturity status link L6983 Applications * * * * * Designed for 24 V buses industrial power systems 24 V battery powered equipment Decentralized intelligent nodes Sensors and always-on applications Low noise applications Description The L6983 is an easy to use synchronous monolithic step-down regulator capable of delivering up to 3 A DC to the load. The wide input voltage range makes the device suitable for a broad range of applications. The L6983 is based on a peak current mode architecture and is packaged in a QFN16 3x3 with internal compensation thus minimizing design complexity and size. The L6983 is available both in low consumption mode (LCM) and low noise mode (LNM) versions. LCM maximizes the efficiency at light-load with controlled output voltage ripple so the device is suitable for battery-powered applications. LNM makes the switching frequency constant and minimizes the output voltage ripple for light load operations, meeting the specification for low noise sensitive applications. The L6983 allows the switching frequency to be selected in the 200 Hz - 2.2 MHz range with optional spread spectrum for improved EMC. DS13116 - Rev 1 - October 2019 For further information contact your local STMicroelectronics sales office. www.st.com L6983 The EN pin provides enable/disable function. The typical shutdown current is 2 A when disabled. As soon as the EN pin is pulled up, the device is enabled and the internal 1.3 ms soft-start takes place. The L6983 features Power Good open collector that monitors the FB voltage. Pulse-by-pulse current sensing on both power elements implements an effective constant current protection and thermal shutdown prevents thermal run-away. DS13116 - Rev 1 page 2/63 L6983 Diagram 1 Diagram Figure 1. Block diagram DS13116 - Rev 1 page 3/63 L6983 Pin configuration 2 Pin configuration PGND SW SW PGND Figure 2. Pin connection (top through view) 16 15 14 13 VIN 1 12 VIN VINLDO 2 11 BOOT AGND 3 10 AGND EN/CLKIN 4 9 VCC 5 6 7 8 PGOOD VBIAS FB/VOUT FSW E.P. Table 1. Pin description Pin Symbol 1 VIN 2 VINLDO 3 AGND Function DC input voltage. DC input voltage connected to the supply rail with a simple RC filter. Analog ground. Enable pin with internal voltage divider. Pull-down/up to disable/ enable the device. 4 EN / CLKIN 5 PGOOD The PGOOD open collector output is driven to low impedance when the output voltage is out of regulation and released once the output voltage becomes valid. VBIAS Typically connected to the regulated output voltage, an external voltage source can be used to supply part of the analog circuitry to reduce current consumptions at light load. Connect it to AGND if not used. 6 7 FB/VOUT In LNM versions, this pin is also used to provide an external clock signal, which synchronizes the device. This pin operates as VOUT or FB according to the selected part number. In fixed output voltage versions, VOUT is the output voltage sensing with selected internal voltage divider. In adjustable versions, FB is output voltage sensing with eternal voltage divider. DS13116 - Rev 1 8 FSW Connect an external resistor to program the oscillator frequency and enable the optional dithering. 9 VCC This pin supplies the embedded analog circuitry. Connect a ceramic capacitor ( 1 F) to filter internal voltage reference. 10 AGND Analog ground. 11 BOOT Connect an external capacitor (100 nF typ.) between BOOT and SW pins. The gate charge required to drive the internal NMOS is refreshed during the low-side switch conduction time. page 4/63 L6983 Pin configuration DS13116 - Rev 1 Pin Symbol Function 12 VIN 13 PGND Power ground. 14 SW Switching node. 15 SW Switching node. 16 PGND Power ground. - Exposed PAD DC input voltage. Exposed pad must be connected to AGND and PGND. page 5/63 L6983 Typical application circuit 3 Typical application circuit Figure 3. Basic application (adjustable version) L6983 RPGOOD VIN RFILT R FSW CIN CFILT C VCC VIN PGOOD VIN BOOT VINLDO SW EN/CLKIN SW FSW VBIAS VCC VOUT/FB E.P. VOUT RFBH COUT PGND AGND AGND L CBOOT RFBL PGND GND GND Table 2. Typical application component DS13116 - Rev 1 Symbol Value Description CIN 10 F Input capacitor RFILT 0.1 k VINLDO filter resistor CFILT 1 F VINLDO filter capacitor CVCC 1 F VCC bypass capacitor CBOOT 100 nF Bootstrap capacitor COUT 40 F Output capacitor RFBH 400 k VOUT divider upper resistor RFBL 82 k VOUT divider lower resistor L 4.7 H (FSW = 1 MHz) Output inductor RPGOOD 1 M PGOOD resistor RFSW 10 k FSW setting resistor page 6/63 L6983 Absolute maximum ratings 4 Absolute maximum ratings Stressing the device above the rating listed in Section 4 Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 3. Absolute maximum ratings Symbol Parameter Min. Max. Unit VIN Maximum pin voltage - 0.3 42 V AGND Maximum pin voltage 0 0 V PGND Maximum pin voltage - 0.3 0.3 V BOOT Maximum pin voltage SW - 0.3 SW + 4 V VCC Maximum pin voltage - 0.3 Min. (VIN + 0.3 V; 4 V) V VOUT/FB Maximum pin voltage - 0.3 8 V FSW Maximum pin voltage - 0.3 VCC + 0.3 V VBIAS Maximum pin voltage - 0.3 VIN + 0.3 V EN Maximum pin voltage - 0.3 VIN + 0.3 V PGOOD Maximum pin voltage - 0.3 VIN + 0.3 V SW Maximum pin voltage VIN + 0.3 V IHS, ILS TJ - 0.85 - 3.8 for 0.5 ns (1) High-side / Low-side RMS switch current V 3 A Operating temperature range - 40 150 C TSTG Storage temperature range - 65 150 C TLEAD Lead temperature (soldering 10 sec.) 260 C 1. Negative peak voltage during switching activities caused by parasitic layout elements. 4.1 ESD protection Table 4. ESD performance 4.2 Symbol Parameter Test conditions ESD ESD protection voltage Value Unit HBM 2 kV CDM non-corner pins 500 V Thermal characteristics Table 5. Thermal data Symbol Rth_JA DS13116 - Rev 1 Parameter Thermal resistance junction ambient (device soldered on the STMicroelectronics demonstration board, please refer to Section 9 Application board) Package Value Unit QFN16 30 C/W page 7/63 L6983 Electrical characteristics 5 Electrical characteristics TJ = 25 C, VIN = 24 V unless otherwise specified. Table 6. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Operating input voltage range 3.5 38 V VIN_H VCC rising threshold 2.3 3.3 V VIN_L VCC UVLO falling threshold 2.15 3.15 V IPK (1) Peak current limit IVY Valley current limit VIN ISKIP (1) (2) No slope contribution 4.1 4.6 A Full slope contribution 3.1 3.6 A 3.3 3.9 Skip current limit 4.5 0.6 A A IVY_SINK (1) Reverse current limit RDSON_HS High-side RDSON 0.130 RDSON_LS Low-side RDSON 0.85 TOFF_MIN Minimum off-time 200 ns TON_MIN Minimum on-time 75 ns LNM or VOUT overvoltage 1.25 1.5 1.75 A Enable VWAKE_UP VEN Wake-up threshold Enable threshold Rising 0.7 Falling 0.2 Rising 1.08 Hysteresis V V 1.2 1.32 0.2 V V VCC regulator VCC LDO output voltage 3.0 3.3 3.6 V 2 3 A Power consumption ISHTDWN Shutdown current from VIN VEN = GND LCM device IQ_VIN Quiescent current from VIN IQ_VBIAS Quiescent current from VBIAS VBIAS = GND 20 35 60 A VBIAS = 5 V 1 3.5 6 A VBIAS = 5 V 20 35 60 A VBIAS = GND 1.6 2.3 3 mA VBIAS = 5 V 300 550 800 A VBIAS = 5 V 1.3 1.8 2.3 mA LNM device IQ_VIN Quiescent current from VIN IQ_VBIAS Quiescent current from VBIAS Soft-start DS13116 - Rev 1 page 8/63 L6983 Electrical characteristics Symbol TSS Parameter Test conditions Min. Typ. Max. Unit 1 1.3 1.6 ms 0.845 0.85 0.855 V 0.842 0.85 0.858 V 3.27 3.3 3.33 V 3.284 3.3 3.346 V 4.955 5.0 5.045 V 4.93 5 5.07 V Internal soft-start Error amplifier Adjustable version TJ = 25 C Adjustable version TJ = - 40 C TJ 125 (4) Fixed 3.3 V version VFB Voltage feedback TJ = 25 C Fixed 3.3 V version TJ = -40 C TJ 125 C (4) Fixed 5.0 V version TJ = 25 C Fixed 5.0 V version TJ = -40 C TJ 125 C (4) Overvoltage protection VOVP Overvoltage trip (VOVP/ VREF) 115 120 125 % VOVP_HYST Overvoltage hysteresis 1 2 6 % 2200 kHz Synchronization (LNM versions only) fCLKIN (3) Synchronization range 200 VCLKIN_TH (3) Amplitude of synchronization clock 2.3 V 60 ns 20 ns VCLKIN_T (3) Synchronization pulse ON and OFF time 2.3 V VCLKIN_TH 2.5 V VCLKIN_TH = 2.3 V Synchronization pulse ON and OFF time VCLKIN_TH > 2.5 V Power Good Adjustable output version TJ = -40 C TJ 125 C (4) VTHR PGOOD threshold Fixed 3.3 output version TJ = -40 C TJ 125 C (4) Fixed 5.0 output version TJ = -40 C TJ 125 C (4) VTHR_HYST (4) PGOOD hysteresis 87 90 93 % 87 90 93 % 87 90 93 % 0.4 V 0.8 V 3 VIN > VIN_H AND VFB < VTH VPGOOD PGOOD open collector output 4 mA sinking load 2 < VIN < VIN_H 4 mA sinking load DS13116 - Rev 1 page 9/63 L6983 Frequency selection table Symbol Parameter Test conditions Min. Typ. Max. Unit TSHDWN (5) Thermal shutdown temperature 165 C THYS (5) Thermal shutdown hysteresis 30 C 1. Parameter tested in the static condition during testing phase. The parameter value may change over a dynamic application condition. 2. LCM version. 3. LNM version. 4. Specifications in the - 40 to 125 C temperature range are assured by characterization and statistical correlation. 5. Not tested in production. 5.1 Frequency selection table Specification referred to - 40 TJ 125 C and VIN = 24 V, assured by testing at TJ = 25 C, design, characterization and statistical correlation. Table 7. FSW selection Symbol Option Dithering (5 % FSW typ.) FSW No dithering DS13116 - Rev 1 RVCC (k) RGND (k) Min. 1.8 N.C. 200 kHz 0 N.C. 400 kHz 3.3 N.C. 500 kHz 5.6 N.C. 700 kHz 10 N.C. 1000 kHz 18 N.C. 1500 kHz 33 N.C. 2000 kHz 56 N.C. 2300 kHz N.C. 1.8 200 kHz N.C. 0 N.C. 3.3 N.C. 5.6 630 700 770 kHz N.C. 10 900 1000 1100 kHz N.C. 18 1500 kHz N.C. 33 2000 kHz N.C. 56 360 Typ. 400 Max. 440 500 2000 2300 Unit kHz kHz 2600 kHz page 10/63 L6983 Functional description 6 Functional description The L6983 device is based on a "peak current mode" architecture with constant frequency control. Therefore, the intersection between the error amplifier output and the sensed inductor current generates the PWM control signal to drive the power switch. The device features LNM (low noise mode) that is forced PWM control, or LCM (low consumption mode) to increase the efficiency at light-load on the selected part number. The main internal blocks shown in the block diagram in Figure 1. Block diagram and Figure 2. Pin connection (top through view) are: * Embedded power elements * A fully integrated adjustable oscillator which is able to set eight different switching frequencies from 200 to 2200 kHz * The ramp for the slope compensation avoiding subharmonic instability * A transconductance error amplifier with integrated compensation network * The high-side current sense amplifier to sense the inductor current * A "Pulse Width Modulator" (PWM) comparator and the driving circuitry of the embedded power elements * The soft-start block ramps up the reference voltage on error amplifier thus decreasing the inrush current at power-up. The EN pin inhibits the device when driven low * The EN/CLK pin section, which, for LNM versions, allows synchronizing the device to an external clock generator * The pulse-by-pulse high-side / low-side switch current sensing to implement the constant current protection * A circuit to implement the thermal protection function * The OVP circuitry to discharge the output capacitor in case of overvoltage event * The switchover capability of the internal regulator to supply a portion of the quiescent current when the VBIAS pin is connected to an external output voltage * Enable/ disable dithering operation 6.1 Enable The EN pin is a digital input that turns the device on or off. In order to maximize both the EN threshold accuracy and the current consumption, the device implements two different thresholds: 1. The wake-up threshold, VWAKE_UP = 0.5 V (see Table 6. Electrical characteristics) 2. The start-up threshold, VEN = 1.2 V (see Table 6. Electrical characteristics) The following picture shows the device behavior. DS13116 - Rev 1 page 11/63 L6983 Soft-start Figure 4. Power-up/down behavior When the voltage applied on the EN pin rises over VWAKEUP, RISING, the device powers up the internal circuit thus increasing the current consumption. As soon as the voltage rises over the VEN, RISING, the device starts the switching activities as described on Section 6.2 Soft-start. Once the voltage becomes lower than VEN, FALLING, the device interrupts the switching activities. As soon as the voltage becomes lower than VWAKEUP.FALLING, the device powers down the internal circuit reducing the current consumption. The pin is VIN compatible. Please refer to Table 6. Electrical characteristics for the reported thresholds. 6.2 Soft-start The soft-start (SS) limits the inrush current surge and makes the output voltage increase monotonically. The device implements the soft-start phase ramping the internal reference with very small steps. Once the SS ends the error amplifier reference is switched to the internal value of 0.85 V coming directly from the band gap cell. DS13116 - Rev 1 page 12/63 L6983 Undervoltage lockout Figure 5. Soft-start procedure During the normal operation, a new soft-start cycle takes place in case of: 1. Thermal shutdown event 2. UVLO event 3. EN pin rising over VEN threshold. Please refer to Table 6. Electrical characteristics Figure 6. Soft-start phase with IOUT = 2.5 A 6.3 Undervoltage lockout The device implements the undervoltage lockout (UVLO) continuously sensing the voltage on the VCC pin, if the UVLO lasts more than 10 s, the internal logic resets the device by turning off both LS and HS. After the reset, if the EN pin is still high, the device repeats the soft-start procedure. DS13116 - Rev 1 page 13/63 L6983 Light-load operation 6.4 Light-load operation The L6983 implements two different light load strategies: 1. Low consumption mode (LCM) 2. Low noise mode (LNM) Please refer to Table 12. Order codes to select the part number with the preferred light load strategy. 6.4.1 Low consumption mode (LCM) The LCM maximizes the efficiency at light load. When the switch peak current request is lower than the ISKIP threshold (see Table 6. Electrical characteristics), the device regulates VOUT by the skip threshold. The minimum voltage is given by: VOUT, LCM = VFB, LCM Where VFB, LCM is 1.8% (typ.) higher than VFB. RPH + RPL RPL (1) The device interrupts the switching activities when two conditions happen together: 1. The peak inductor current required is lower than ISKIP 2. The voltage on the FB pin is higher than VFB, LCM Figure 7. Light load operation VCOMP VFB t VCOMP,MIN VFB, LCM VFB VSW t IL t ISKIP t A new switching cycle takes place once the voltage on the FB pin becomes lower than VFB,LCM. The HS switch is kept on until the inductor current reaches ISKIP. Once the current on the HS reaches the defined value, the device turns the HS off and turns the LS on. The LS is kept enabled until one of the following conditions occurs: 1) The inductor current sensed by the LS becomes equal to zero 2) The switching period ends up If, at the end of the switching cycle, the voltage on the FB pin rises over the VFB,LCM threshold, the LS is kept enabled until the inductor current becomes equal to zero. Otherwise, the device turns on again the HS and starts a new switching pulse. During the burst pulse, if the energy transferred to COUT increases the VFB level over the threshold defined on Eq. (1), the device interrupts the switching activities. The new cycle takes place only when VFB becomes lower than the defined threshold. Otherwise, as soon as the LS is turned off the HS is turned on. Given the energy stored in the inductor during a burst, the voltage ripple depends on the capacitor value: T 0 BURST IL t dt QIL VOUTRIPPLE = = COUT COUT DS13116 - Rev 1 (2) page 14/63 L6983 Light-load operation Figure 8. LCM operation with ISKIP = 600 mA typ. at zero load. L = 15 H; COUT = 40 F Figure 9. LCM operation over loading condition (part 1-pulse skipping) DS13116 - Rev 1 page 15/63 L6983 Light-load operation Figure 10. LCM operation over loading condition (part 2-pulse skipping) Figure 11. LCM operation over loading condition (part 3-pulse skipping) DS13116 - Rev 1 page 16/63 L6983 Light-load operation Figure 12. LCM operation over loading condition (part 4-CCM) DS13116 - Rev 1 page 17/63 L6983 Light-load operation 6.4.2 Low noise mode (LNM) The low noise mode implements a forced PWM operation over the different loading conditions. The LNM features a constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed VIN. The regulator in steady loading condition operates in continuous conduction mode (CCM) over the different loading conditions. The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output voltage ripple, that depends on the capacitor value and the equivalent resistive component (ESR). Consequently, the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. ILMAX VOUTRIPPLE = ESR ILMAX + 8 COUT fSW (3) Usually the resistive component of the ripple can be neglected if the selected output capacitor is a multi-layer ceramic capacitor (MLCC). Figure 13. Low noise mode operation at zero load DS13116 - Rev 1 page 18/63 L6983 Light-load operation 6.4.3 Efficiency for low consumption mode and low noise mode part number Figure 14. Light-load efficiency for low consumption mode and low noise mode - linear scale, and Figure 15. Light-load efficiency for low consumption mode and low noise mode - log scale report the efficiency measurements to highlight the gap at the light-load between LNM and LCM part numbers. The graph reports also exactly the same efficiency at the medium / high load. Figure 14. Light-load efficiency for low consumption mode and low noise mode - linear scale VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 LCM LNM 30 20 10 0 0 0.5 1 1.5 2 2.5 3 I OUT [A] Figure 15. Light-load efficiency for low consumption mode and low noise mode - log scale VIN = 24 V; V OUT = 5 V; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 LCM 30 LNM 20 10 0 0.001 0.01 0.1 1 I OUT [A] DS13116 - Rev 1 page 19/63 L6983 Light-load operation 6.4.4 Load regulation for low consumption mode and Low noise mode part number Figure 16. Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - linear scale and Figure 17. Load regulation for low noise mode. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - log scale report the load regulation to highlight the gap, given by the different regulation strategy, at the light-load between LNM and LCM part numbers. When the required IOUT is higher than the threshold defined on the Section 6.4.1 Low consumption mode (LCM) the behavior of the different part number is exactly the same. Figure 16. Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - linear scale VIN = 24 V ; V OUT = 5 V; FSW = 0.4 MHz Load regulation [%] 2 LCM 1.5 LNM 1 0.5 0 -0.5 0 0.5 1 1.5 2 2.5 3 IOUT [A] Figure 17. Load regulation for low noise mode. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - log scale VIN = 24 V; V OUT = 5 V; FSW = 0.4 MHz Load regulation [%] 2 1.5 1 LCM 0.5 LNM 0 -0.5 0.001 0.01 0.1 1 I OUT [A] DS13116 - Rev 1 page 20/63 L6983 Switch-over feature 6.5 Switch-over feature The switch-over maximizes the efficiency at light load that is crucial for low consumption application. Figure 18. Switch-over No Switch -Over Switch -Over L6983 L6983 RPGOOD RPGOOD PGOOD PGOOD BOOT SW CBOOT BOOT L VOUT SW SW SW RFBH VBIAS L VOUT RFBH VBIAS VOUT/FB VOUT/FB COUT PGND E.P. CBOOT PGND RFBL PGND E.P. COUT RFBL PGND GND GND In order to minimize the regulator quiescent current sink from the input voltage, the VBIAS pin can be connected to an external voltage source in the range of 3 V < VBIAS < VIN. In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current drawn from the input voltage is given by the following equation: 6.6 Spread spectrum VBIAS 1 IQVIN = IQOPVIN + IQOPVBIAS L6983 VIN (4) The spread spectrum is selectable by connecting the RFSW resistor to VCC (please refer to Table 7. FSW selection). The internal dithering circuit changes the switching frequency in a range of 5%. FSW = 5% Fsw (5) The device updates the frequency every clock period by fixed steps: * Ramps up in 63 steps from minimum to maximum FSW * Ramps down in 63 steps from maximum to minimum FSW The modulation shape is almost triangular with a frequency of: 6.7 Overvoltage protection Fsw FDitering = 126 (6) The overvoltage protection monitors the FB pin and enables the low-side MOSFET to discharge the output capacitor if the output voltage is 20% (typ.) over the nominal value. This is a second level protection and it should never be triggered in normal operating conditions if the system is properly dimensioned. In other words, the selection of the external power components and the dynamic performance determined by the compensation network should guarantee an output voltage regulation within the overvoltage threshold even during the worst-case scenario in term of load transitions. The protection is reliable and able to operate even during normal load transitions for a system whose dynamic performance is not in line with the load dynamic request. Consequently, the output voltage regulation would be affected. The L6983 device implements a 1.5 A (IVY_SINK refer to Table 6. Electrical characteristics) negative current limitation to limit the maximum reversed switch current during the overvoltage operation. DS13116 - Rev 1 page 21/63 L6983 Overcurrent protection 6.8 Overcurrent protection The current protection circuitry features a constant current protection, so the device limits the maximum peak current (please refer to Table 6. Electrical characteristics) in overcurrent condition. The L6983 device implements a pulse-by-pulse current sensing on both power elements (high-side and low-side switches) for effective current protection over the duty cycle range. The high-side current sensing is called "peak" the low-side sensing "valley". The internal noise generated during the switching activity makes the current sensing circuitry ineffective for a minimum conduction time of the power element. This time is called "masking time" because the information from the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. Therefore, the peak current protection is disabled for a masking time after the high-side switch is turned on. The masking time for the valley sensing is activated after the low-side switch is turned on. In other words, the peak current protection can be ineffective at extremely low duty cycles, the valley current protection at extremely high duty cycles. The L6983 device assures an effective overcurrent protection sensing the current flowing in both power elements. In case one of the two current sensing circuitry is ineffective because of the masking time, the device is protected sensing the current on the opposite switch. Thus, the combination of the "peak" and "valley" current limits assure the effectiveness of the overcurrent protection even in extreme duty cycle conditions. In case the current diverges because of the high-side masking time, the low-side power element is turned on until the switch current level drops below the valley current sense threshold. The low-side operation is able to prevent the high-side turn on, so the device can skip pulses decreasing the switching frequency. Figure 19. Over current protection behavior In worst case scenario, reported in Figure 19. Over current protection behavior of the overcurrent protection the switch current is limited to: IMAX = IVY + VIN - VOUT TMASKHS L (7) Where IVY is the current threshold of the valley sensing circuitry (please refer to Table 6. Electrical characteristics) and TMASKHS is the masking time of the high-side switch (75 ns typ.). DS13116 - Rev 1 page 22/63 L6983 Overcurrent protection In most of the overcurrent conditions, the conduction time of the high-side switch is higher than the masking time and so the peak current protection limits the switch current. IMAX = IPK (8) The DC current flowing in the load in overcurrent condition is: IDCOUT = IMAX - IRIPPLE VOUT VIN - VOUT = IMAX - TON 2 2L (9) The Figure 20. Soft-start procedure with VOUT shorted to GND shows the L6983 soft-start procedure with VOUT shorted to GND. Figure 20. Soft-start procedure with VOUT shorted to GND The Figure 21. Over current procedure with persistent short circuit between VOUT and GND shows the L6983 over current protection with a persistent short circuit between VOUT and GND. DS13116 - Rev 1 page 23/63 L6983 Thermal shutdown Figure 21. Over current procedure with persistent short circuit between VOUT and GND 6.9 Thermal shutdown The shutdown block disables the switching activity if the junction temperature is higher than a fixed internal threshold (TSHDWN refer to Table 6. Electrical characteristics). The thermal sensing element is close to the power elements, assuring fast and accurate temperature detection. A hysteresis of approximately 30 C prevents the device from turning ON and OFF too fast. After a thermal protection event is expired, the L6983 restarts with a new soft-start. 6.10 Power Good The PGOOD pin indicates whether the output voltage is within its regulation level. The pin output is an open drain MOSFET. The PG is pulled low when: 1. The FB pin voltage is lower than 90% (typ.) of the nominal internal reference for more than 10 s 2. The FB pin voltage is higher than 120% (typ.) of the nominal internal reference for more than 10 s (see Section 6.7 Overvoltage protection) 3. During the soft-start procedure also with pre-charged VOUT 4. If a thermal shutdown event occurs 5. If a UVLO event occurs The PG pin is VIN compatible. DS13116 - Rev 1 page 24/63 L6983 Power Good Figure 22. PGOOD thresholds V FB 118% 120% 90% 87% V PGOOD V HIGH t V LOW t DS13116 - Rev 1 page 25/63 L6983 Closing the loop 7 Closing the loop The following picture shows the typical compensation network required to stabilize the system. Figure 23. Block diagram of the loop PWM control VIN Current sense HS switch LC filter L LS switch IHS/gCS Resistor divider COUT R1 FB Compensation network RLOAD VREF PWM comparator CC 7.1 R2 RC Error amplifier GCO(s) control to output transfer function The accurate control to output transfer function for a buck peak current mode converter can be written as follows: s Z GCO s = RLOAD gCS FH s RLOAD TSW s 1+ mC 1 - D - 0.5 1+ L P 1 1+ (10) Where RLOAD represents the load resistance, the gCS equivalent sensing trans-conductance of the current sense circuitry, P the single pole introduced by the power stage and the Z zero given by the ESR of the output capacitor. FH(s) accounts the sampling effect performed by the PWM comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. 1 Z = ESR COUT where: (11) mC 1 - D - 0.5 1 P = + RLOAD COUT L COUT fSW (12) Se mC = 1 + Sn Se = ISLOPE fSW Where ISLOPE is equal to 1 A. (13) VIN - VOUT Sn = L Sn represents the on-time slope of the sensed inductor current, Se the on-time slope of the external ramp that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%. The sampling effect contribution FH (s) is: DS13116 - Rev 1 page 26/63 L6983 Error amplifier compensation network Se mC = 1 + Sn Se = ISLOPE fSW (14) VIN - VOUT Sn = L FH s = where: 7.2 1 s s2 1+ + n QP 2 n (15) 1 QP = mC 1 - D - 0.5 (16) Error amplifier compensation network The following figure shows the typical compensation network required to stabilize the system. Figure 24. Trans-conductance embedded error amplifier VREF E/A FB RC CC V REF RC dV RO Gm dV CO CC VFB RC and CC introduce a pole and a zero in the open loop gain. The transfer function of the error amplifier and its compensation network is: where: AVO 1 + s RC CC AO s = s2 RO CO RC CC + s RO CC + RO CO + RC CC + 1 AVO = Gm RO (17) (18) The poles of this transfer function are (if CC >> CO): DS13116 - Rev 1 page 27/63 L6983 Voltage divider 1 fPLF = 2 RO CC 1 fPHF = 2 RO CO Whereas the zero is defined as: 7.3 (19) (20) 1 fZ = 2 RC CC Voltage divider (21) The contribution of a simple voltage divider is: R2 GDIV s = R1 + R2 (22) A small signal capacitor in parallel to the upper resistor (only for the adjustable part number) of the voltage divider implements a leading network (fZERO < fPOLE), sometimes necessary to improve the system phase margin: Figure 25. Leading network example L6983 RPGOOD VIN RFILT RFSW CIN CFILT CVCC VIN PGOOD VIN BOOT VINLDO SW EN/CLKIN SW FSW VBIAS VCC VOUT/FB PGND A GND A GND CBOOT E.P. L VOUT R1 CR1 COUT R2 PGND GND GND Laplace transformer of the leading network: R2 GDIV s = R1 + R2 where: 1 + s R1 CR1 R1 R2 1+s C R1 + R2 R1 1 fZ = 2 R1 CR1 fP = So closing the loop, the loop gain is: DS13116 - Rev 1 1 R1 R2 2 C R1 + R2 R1 (23) (24) (25) fZ < fP (26) G s = GDIV s GCO s AO s (27) page 28/63 L6983 Application notes 8 Application notes 8.1 Programmable power up threshold The enable rising threshold is equal to 1.2 V typical (refer to Table 6. Electrical characteristics). The power-up threshold is adjusted according to the following equation: RENH VPowerUp = 1.2V 1 + RENL (28) Figure 26. Leading network example VIN VIN VIN REN H RFILT VINLDO EN/CLKIN RFSW FSW CIN REN L CFILT VCC CVCC AGND AGND GND The enable falling threshold is equal to 1.0 V typical (refer to Table 6. Electrical characteristics). The turn threshold is obtained according to the following equation: 8.2 RENH VPowerUp = 1.0V 1 + RENL (29) External synchronization (available for low noise mode only) The device allows a direct connection between a clock source and the EN/CLKIN pin. Figure 27. External synchronization. Direct connection. VIN VIN EXT. Clock(t) RFILT VIN VPP VINLDO RFSW EN/CLKIN FSW CIN CFILT VCC Clock Source CVCC AGND AGND GND The device internally implements a low-pass filter connected to EN/CLKIN pin that is able to acquire the average value of the applied signal. DS13116 - Rev 1 page 29/63 L6983 Output voltage adjustment The device turns on when the average of the signal applied is higher than VEN rising (refer to Table 6. Electrical characteristics). The device turns off when the average of the signal should be lower than VEN falling (refer to Table 6. Electrical characteristics). Considering, for example, a clock source with VPP = 5.0 V, the minimum duty cycle to guarantee the power-up is given by: Dutymin = VEN, Rising = 0.24 VPP (30) The maximum duty cycle to guarantee the turn-off is given by: DutyMAX, = The device allows also the AC coupling. VEN, Falling = 0.2 VPP (31) Figure 28. External synchronization. AC coupling VIN VIN VIN REN H RFILT VINLDO CEN RFSW EN/CLKIN(*) FSW CIN CFILT EXT. Clock(t) Clock Source VPP VCC REN L CVCC AGND AGND GND The AC-coupling allows the device to keep the power-up and down thresholds defined by the partition connected to EN/CLKIN pin and described on Section 8.1 Programmable power up threshold. The following table resumes the minimum pulse duration for the external signal and maximum duty cycle that allows the synchronization by keeping the selected power-up and down thresholds. Table 8. External synchronization AC coupling suggested operation range VPP [V] TON, MIN, EXTClock [ns] DMAX, EXTClock [%] 2.3 70 45 3.3 20 30 5 20 20 The minimum amplitude for the external clock signal is, for both the configurations, equal to 2.3 V. The network given by CEN and RENL sets a high-pass filter. Considering a resistor in the order of 220 k, a capacitor equal to 1 nF is a correct choice. 8.3 Output voltage adjustment The error amplifier reference voltage is 0.85 V typical (refer to Table 6. Electrical characteristics). The output voltage is adjustable as per the following equation: R1 VOUT = 0.85V 1 + R2 DS13116 - Rev 1 (32) page 30/63 L6983 Switching frequency CR1 capacitor is sometimes useful to increase the small signal phase margin (please refer to the Section 7 Closing the loop). Figure 29. Application circuit L6983 RPGOOD VIN RFILT R FSW CIN CFILT C VCC VIN PGOOD VIN BOOT VINLDO SW EN/CLKIN SW FSW VBIAS VCC VOUT/FB PGND AGND AGND CBOOT E.P. VOUT R1 CR1 COUT R2 PGND GND 8.4 L GND Switching frequency A resistor connected to the FSW pin features the selection of the switching frequency (refer to the Table 7. FSW selection). Connecting the resistor between the pins RFSW and VCC, the internal dithering circuit is turned on. (refer to the Section 6.6 Spread spectrum). 8.5 8.5.1 Design of the power components Input capacitor selection The input capacitor voltage rating must be higher than the maximum input operating voltage of the application. During the switching activity a pulsed current flows into the input capacitor and so, its RMS current capability must be selected according to the application conditions. Internal losses of the input filter depends on the ESR value so usually low ESR capacitors (such as multilayer ceramic capacitors) have higher RMS current capability. On the other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher conversion efficiency. The maximum RMS input current, flowing through the capacitor, can be calculated as follows: IRMS = IOUT 1- D D (33) Where IOUT is the maximum DC output current, D is the duty cycles, is the efficiency. This function has a maximum at D = 0.5 and, considering = 1, it is equal to IOUT/2. In a specific application, the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: VOUT + VLOWSIDE DMAX = VINmin + VLOWSIDE - VHIGHSIDE VOUT + VLOWSIDE Dmin = VINMAX + VLOWSIDE - VHIGHSIDE (34) (35) Where VHIGHSIDE and VLOWSIDE are the voltage drops across the embedded switches. The peak-to-peak voltage across the input filter can be calculated as the equation below: IOUT D D VPP = + ESR IOUT + IL 1- CIN FSW DS13116 - Rev 1 (36) page 31/63 L6983 Design of the power components In case of negligible ESR (MLCC capacitor), the equation of CIN as a function of the target VPP can be written as follows: IOUT D D CIN = 1- VPP FSW (37) Considering = 1 this function has its maximum in D = 0.5: IOUT CINmin = 4 VPPMAX FSW (38) Typically, CIN is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 5% VINMAX. In the following table, some suitable capacitor part numbers are listed. Table 9. Capacitor part numbers Manufacturer Series Size Cap value (F) Rated voltage (V) TDK CGA5L3X5R1H106K160AB 1206 10 50 C3216X5R1H106K160AB 1206 10 50 GRT31CR61H106KE01 1206 10 50 Murata 8.5.2 Inductor selection The inductor current ripple flowing into the output capacitor determines the output voltage ripple. Usually the inductor value is selected in order to keep the current ripple lower than 20% - 40% of the output current over the input voltage range. The inductance value can be calculated by the following equation: IL = VIN - VOUT VOUT TON = TOFF L L (39) Where TON and TOFF are the on and off time of the internal power switch. The maximum current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle. So fixing IL = 20% to 40% of the maximum output current, the minimum inductance value can be calculated: VOUT 1 - Dmin Lmin = ILMAX FSW (40) In order to prevent the sub-harmonic instability in the peak current control loop, a slope compensation mechanism is internally implemented. This implies two limits on the inductor selection. In order to avoid poor slope compensation or over slopping with a pole coming back into the BW degrading phase margin, the inductor should be designed so that: 0.4 QP 1.33 (41) Where QP has been defined in Section 7.1 GCO(s) control to output transfer function. Given the QP defined range the inductor should be selected with a value between and: 1 1 + VIN, MAX - VOUT QP, MAX 2 LSLOPE, min = -1 Se VOUT 1- VIN, MAX 1 1 + VIN, min - VOUT QP, min 2 LSLOPE, MAX = -1 Se VOUT 1- VIN, min (42) (43) In order to have the correct ripple, avoid sub-harmonic instability or over slopping, the selected inductor should satisfy every reported conditions. The peak current through the inductor is given by: DS13116 - Rev 1 page 32/63 L6983 Design of the power components IL IL, PK = IOUT + 2 (44) So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. The higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit. 8.5.3 Output capacitor selection The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output voltage ripple, that depends on the capacitor value and the equivalent resistive component (ESR). Therefore, the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. The voltage ripple equation can be calculated as: IL, MAX VOUT = ESR IL, MAX + 8 COUT FSW (45) For a ceramic (MLCC) capacitor, the capacitive component of the ripple dominates the resistive one. While for an electrolytic capacitor the opposite is true. Neglecting the ESR contribution the minimum value of the output capacitor is given by: IL, MAX COUT, min, RIPPLE = 8 VOUT FSW (46) As the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop. A good rule to obtain a proper dimensioning for the minimum amount of the output capacitor is set the target system bandwidth equal to FSW/8. The following equation keep into account the precedent consideration: 8.04 COUT, BW, min = Fsw VOUT 8 (47) The maximum amount of the output capacitor is given by: COUT, BW, MAX = DS13116 - Rev 1 0.960 10-3 VOUT (48) page 33/63 GND VIN PGOOD CLKIN TP7 TP6 TP5 TP2 TP1 VIN EN NM Type = 50V C14 C9 L3 MPZ2012S221A J2 Type = 50V C13 4.7H L2 Type = 50V C12 100F 50V C15 + VIN_FLT Type = 50V 10F R2 NM R1 10k GND C1 GND NM R6 Type = 50V 1F C2A EP1-SGND EN/CLKIN SGND1 VINLDO VIN1 0 R11 1Meg R7 17 4 3 2 1 16 LX 15 FB NM Type = 16V C11 VOUT R12 NM PGND2 PGOOD 5 13 4.7H C8 R3 R4 VCC SGND2 BOOT VIN2 U1 L6983 L1B NM PGND1 14 SW2 VBIAS 6 SW1 FB 7 FSW 8 NM 400k 82k R9 9 VCC 10 11 12 NM C7 10F C6 GND 0 100nF R8 10k 1FType = 16V R5 Type = 50V 1F C2B Type = 16V C3 Type = 16V C4 DS13116 - Rev 1 Type = 16V GND VOUT 22F TP4 TP3 GND VOUT 9 C5 L1A Application board L6983 Application board The figure below shows the reference evaluation board schematic: Figure 30. Evaluation board schematic The additional input filter (C14, L3, C13, L2, C12, and C15) limits the conducted emission on the power supply. page 34/63 10F 4.7F 4.7F 4.7F L6983 Application board Table 10. Bill of material Reference Part number Description Manufacturer C1 CGA5L3X5R1H106K160AB 10 F 50 V TDK C2A CGA4J3X7R1H105K125AB 1 F 50 V TDK C2B CGA4J3X7R1H105K125AB 1 F 50 V TDK C3-C4 GCM31CR71C106KA64L 10 F 16 V MURATA C5 CGA6P1X7R1C226M250AC 22 F 16 V TDK C6 CGA3E2X7R1H104K080AA 100 nF 50 V TDK C7 C2012X8R1C105K125AB 1 F 16V TDK C8 NOT MOUNTED C9 NOT MOUNTED C11 NOT MOUNTED C12-C13-C14 GRM31CR71H475KA12L 4.7 F 50 V Murata C15 EEHZA1H101P 100 F, 50 V Panasonic L1B NOT MOUNTED L1A XAL6060-472ME 4.7 H Coilcraft L2 XAL4030-472ME 4.7 H Coilcraft L3 MPZ2012S221A 220 100 MHz TDK R1 10 k 1% any R2 NOT MOUNTED R3 400 k 1% any R4 82 k 1% any R5 0 any R6 NOT MOUNTED R7 1 M 1% any R8 10 k 1% any R9 NOT MOUNTED R11 0 any R12 NOT MOUNTED any J2 U1 DS13116 - Rev 1 L6983CQTR ST Microelectronics page 35/63 L6983 Application board Figure 31. Top layer Figure 32. Bottom layer DS13116 - Rev 1 page 36/63 L6983 Efficiency curves 10 Efficiency curves The following three figures show the efficiency and power losses acquired on the standard evaluation board of the device, STEVAL-ISA208V1, selecting the following output filter: * COUT: * - 1 x CGA6P1X7R1C226M250AC 22 F 16 V (TDK); - 2 x CGA5L3X5R1H106K160AB 10 F 50 V (TDK). Inductor: - XAL6060-153ME (Coilcraft) Figure 33. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] Figure 34. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale) VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 20 LCM 10 LNM 0 0.001 0.01 0.1 1 I OUT [A] DS13116 - Rev 1 page 37/63 L6983 Efficiency curves Figure 35. Power losses VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ VIN = 24 V ; VOUT = 5 V ; FSW = 0.4 MHz 2.5 16 Output Power [W] Power losses [W] 14 2 12 10 1.5 8 1 6 0.5 0 0 0.5 1 1.5 2 LCM 4 LNM 2 2.5 3 0 IOUT [A] The following three figures show the efficiency and power losses acquired on the standard evaluation board of the device, STEVAL-ISA208V1, selecting the following output filter: * COUT: * - 1 x CGA6P1X7R1C226M250AC 22 F 16 V (TDK); - 2 x CGA5L3X5R1H106K160AB 10 F 50 V (TDK). Inductor: - XAL6060-153ME (Coilcraft). Figure 36. Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] DS13116 - Rev 1 page 38/63 L6983 Efficiency curves Figure 37. Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale) VIN = 12 V; VOUT = 5 V ; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0.001 0.01 0.1 1 IOUT [A] Figure 38. Power losses VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ 16 1.8 14 1.6 12 1.4 10 1.2 1 8 0.8 6 0.6 0.4 0.2 0 LCM 4 LNM 2 POUT 0 0.5 1 1.5 2 2.5 3 Output Power [W] Power losses [W] VIN = 12 V ; VOUT = 5 V ; FSW = 0.4 MHz 2 0 IOUT [A] The following three figures show the efficiency and power losses acquired on the standard evaluation board of the device, STEVAL-ISA208V1, selecting the following output filter: * COUT: * DS13116 - Rev 1 - 2 x CGA6P1X7R1C226M250AC 22 F 16 V (TDK); - 2 x CGA5L3X5R1H106K160AB 10 F 50 V (TDK). Inductor: - XAL6060-822ME (Coilcraft). page 39/63 L6983 Efficiency curves Figure 39. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ VIN = 24 V; V OUT = 3.3 V; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] Figure 40. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale) VIN = 24 V ; VOUT = 3.3 V ; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0.001 0.01 0.1 1 I OUT [A] DS13116 - Rev 1 page 40/63 L6983 Efficiency curves Figure 41. Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ Vin = 24 V ; Vout = 3.3 V ; Fsw = 0.4 MHz 12 Power losses [W] 1.6 10 1.4 1.2 8 1 6 0.8 0.6 0.4 0.2 LCM 4 LNM 2 Output Power [W] 1.8 POUT 0 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] The following three figures show the efficiency and power losses acquired on the standard evaluation board of the device, STEVAL-ISA208V1, selecting the following output filter: * COUT: * - 2 x CGA6P1X7R1C226M250AC 22 F 16 V (TDK); - 2 x CGA5L3X5R1H106K160AB 10 F 50 V (TDK). Inductor: - XAL6060-822ME (Coilcraft) DS13116 - Rev 1 page 41/63 L6983 Efficiency curves Figure 42. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ VIN = 12 V ; V OUT = 3.3 V ; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] Figure 43. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale) VIN = 12 V ; V OUT = 3.3 V ; FSW = 0.4 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 10 0 0.001 LNM 0.01 0.1 1 IOUT [A] DS13116 - Rev 1 page 42/63 L6983 Efficiency curves Figure 44. Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHz 12 Power losses [W] 1.6 10 1.4 1.2 8 1 6 0.8 0.6 0.4 0.2 0 LCM 4 LNM 2 Output Power [W] 1.8 POUT 0 0.5 1 1.5 2 2.5 3 0 IOUT [A] The following three figures show the efficiency and power losses acquired on the standard evaluation board of the device, STEVAL-ISA208V1, selecting the following output filter: * COUT: * DS13116 - Rev 1 - 1 x CGA6P1X7R1C226M250AC 22 F 16 V (TDK); - 1 x CGA5L3X5R1H106K160AB 10 F 50 V (TDK). Inductor: - XAL6060-472ME (Coilcraft). page 43/63 L6983 Efficiency curves Figure 45. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ VIN = 24 V ; V OUT = 3.3 V ; FSW = 1.0 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] Figure 46. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ (log scale) VIN = 24 V ; V OUT = 3.3 V ; FSW = 1.0 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 10 0 0.001 LNM 0.01 0.1 1 IOUT [A] DS13116 - Rev 1 page 44/63 L6983 Efficiency curves Figure 47. Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ VIN = 24 V ; VOUT = 3.3 V ; FSW = 1.0 MHz 12 10 2 8 1.5 6 1 LCM 4 LNM 0.5 2 Output Power [W] Power losses [W] 2.5 POUT 0 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] The following three figures show the efficiency and power losses acquired on the standard evaluation board of the device, STEVAL-ISA208V1, selecting the following output filter: * COUT: * DS13116 - Rev 1 - 1 x CGA6P1X7R1C226M250AC 22 F 16 V (TDK); - 1 x CGA5L3X5R1H106K160AB 10 F 50 V (TDK). Inductor: - XAL6060-472ME (Coilcraft). page 45/63 L6983 Efficiency curves Figure 48. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ VIN = 12 V ; VOUT = 3.3 V ; FSW = 1.0 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] Figure 49. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ (log scale) VIN = 12 V ; VOUT = 3.3 V ; FSW = 1.0 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 10 0 0.001 LNM 0.01 0.1 1 IOUT [A] DS13116 - Rev 1 page 46/63 L6983 Efficiency curves Figure 50. Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ Vin = 12 V ; Vout = 3.3 V ; Fsw = 1.0 MHz 2 12 10 1.6 1.4 8 1.2 1 6 0.8 LCM 0.6 0.4 LNM 0.2 POUT 4 2 0 Output Power [W] Power losses [W] 1.8 0 0 0.5 1 1.5 2 2.5 3 I OUT [A] The following three figures show the efficiency and power losses acquired on the standard evaluation board of the device, STEVAL-ISA208V1, selecting the following output filter: * COUT: * DS13116 - Rev 1 - 1 x CGA6P1X7R1C226M250AC 22 F 16V (TDK); - 2 x CGA5L3X5R1H106K160AB 10 F 50V (TDK). Inductor: - XAL6060-472ME (Coilcraft). page 47/63 L6983 Efficiency curves Figure 51. . Efficiency VIN = 24 V; VOUT = 5 V; FSW = 1.0 MHZ VIN = 24 V ; VOUT = 5.0 V ; FSW = 1.0 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] Figure 52. Efficiency VIN = 24 V; VOUT = 5.0 V; FSW = 1.0 MHZ (log scale) VIN = 24 V ; VOUT = 5.0 V ; FSW = 1.0 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 10 0 0.001 LNM 0.01 0.1 1 IOUT [A] Figure 53. Power losses VIN = 24 V; VOUT = 5.0 V; FSW = 1.0 MHZ DS13116 - Rev 1 page 48/63 L6983 Efficiency curves V IN = 24 V ; V OUT = 5.0 V ; FSW = 1.0 MHz 16 14 2.5 12 2 10 1.5 8 1 0.5 LCM 6 LNM 4 2 POUT 0 0 0.5 1 1.5 2 2.5 Output Power [W] Power losses [W] 3 3 0 IOUT [A] The following three figures show the efficiency and power losses acquired on the standard evaluation board of the device, STEVAL-ISA208V1, selecting the following output filter: * COUT: * - 1 x CGA6P1X7R1C226M250AC 22 F 16 V (TDK); - 1 x CGA5L3X5R1H106K160AB 10 F 50 V (TDK). Inductor: - XAL6060-472ME (Coilcraft). Figure 54. Efficiency VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ VIN = 12 V ; VOUT = 5.0 V ; FSW = 1.0 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0 0.5 1 1.5 2 2.5 3 IOUT [A] DS13116 - Rev 1 page 49/63 L6983 Efficiency curves Figure 55. Efficiency VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ (log scale) VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHz 100 90 Efficiency [%] 80 70 60 50 40 30 LCM 20 LNM 10 0 0.001 0.01 0.1 1 IOUT [A] Figure 56. Power losses VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ Vin = 12 V ; Vout = 5.0 V ; Fsw = 1.0 MHz 2.5 16 12 10 1.5 8 1 0.5 0 6 LCM 0 0.5 1 1.5 2 2.5 LNM 4 POUT 2 3 Output Power [W] Power losses [W] 14 2 0 I OUT [A] DS13116 - Rev 1 page 50/63 L6983 Thermal dissipation 11 Thermal dissipation The thermal design is important in order to prevents thermal shutdown of the device if junction temperature goes above 165 C. The three different sources of losses within the device are: 1. Conduction losses due to the on-resistance of high-side switch (RDSON_HS) and low-side switch (RDSON_LS); these are equal to: 2 2 PCOND = RDSON_HS IOUT D + RDSON_LS IOUT 1-D (49) where D is the duty cycle of the selected application and is given by the following formula: D= VOUT + RDSON_LS + DCRl IOUT (50) VIN - RDSON - RDSON_LS IOUT HS In order to obtain a more accurate extimation it is necessary to keep into account that the amount of resistance of the internal power MOSFET increases together with the temperature. For this reason, the value of RDSONHS and RDSONLS, should be increased from the typical of a factor equal to 15%. 1. Switching losses due to high-side power MOSFET turn-ON and OFF; these can be calculated as per below: PSW = VIN IOUT TRISE + TFALL FSW = VIN IOUT TSW FSW 2 (51) where TRISE and TFALL are the overlap times of the voltage across the high side power switch (VDS) and the current flowing into it during turn-ON and turn-OFF phases, as shown in Figure 57. Switching losses. TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 20 ns. 1. Quiescent current losses, calculated as the equation below: PQ = VIN IQ, MAX (52) where IQ is the quiescent current and depends on the VBIAS connections. If VBIAS is connected to GND, the maximum is equal to 3 mA. Otherwise if VBIAS is connected to VOUT the quiescent current is given by: The power losses are given by: VBIAS 1 IQ, MAX = 0.8 mA + 2.3 mA L6983 VIN (53) PLOSS = PCOND + PSW + PQ (54) T J = TA + RtJA PLOSS (55) The junction temperature TJ can be calculated as: where TA is the ambient temperature. RthJA is the equivalent thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junctions to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA measured on the demonstration board described in the following section is about 30 C/W. DS13116 - Rev 1 page 51/63 L6983 Thermal dissipation Figure 57. Switching losses V IN V SW (t) ISW,HS (t) V DS,HS (t) t PSW PCOND,LS PCOND,HS t TFALL TRISE It is also possible to estimate the junction temperature directly from the efficiency measures acquired on a stationary application condition. Considering that the power losses are given by: PLOSS = PIN - POUT (56) Neglecting the AC losses of the selected inductor, the power losses related to the L6983 are given by: 2 PLOSSL6983 = VIN IIN - VOUT IOUT - DCRl IOUT (57) Therefore, the junction temperature TJ can be calculated as: T J = TA + RtJA PLOSS, L6983 DS13116 - Rev 1 (58) page 52/63 L6983 Package information 12 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS13116 - Rev 1 page 53/63 L6983 QFN16 (3x3 mm) package information 12.1 QFN16 (3x3 mm) package information Figure 58. QFN16 (3x3 mm) package outline DS13116 - Rev 1 page 54/63 L6983 QFN16 (3x3 mm) package information Table 11. QFN16 (3x3 mm) mechanical data mm Dim. Min. Typ. Max. A 0.7 0.75 0.8 A1 0 0.02 0.05 A3 0.203 Ref. b 0.18 0.25 0.3 D 3.00 BSC E 3.00 BSC e 0.50 BSC D2 0.43 0.48 0.53 E2 0.81 0.86 0.91 L 0.35 0.4 0.45 K 0.84 K1 0.5 K2 0.86 N 16 ND 4 NE 4 aaa 0.05 bbb 0.1 ccc 0.05 ddd 0.05 eee 0.05 Figure 59. QFN16 (3x3 mm) recommended footprint 0.85 0.43 0.30 0.90 0.50 0.77 0.80 DS13116 - Rev 1 0.50 page 55/63 L6983 Ordering information 13 Ordering information Table 12. Order codes DS13116 - Rev 1 Part numbers Output voltage L6983CQTR Adj. L6983C50QTR 5V L6983C33QTR 3.3 V L6983NQTR Adj. L6983N50QTR 5V L6983N33QTR 3.3 V Light load behavior Package Packaging QFN16 Tape and reel LCM (Low Consumption Mode) LNM (Low Noise Mode) page 56/63 L6983 Revision history Table 13. Document revision history DS13116 - Rev 1 Date Revision 29-Oct-2019 1 Changes Initial release. page 57/63 L6983 Contents Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Typical application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 4.1 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 6 7 8 Frequency selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 6.1 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 Soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.3 Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4.1 Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4.2 Low noise mode (LNM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4.3 Efficiency for low consumption mode and low noise mode part number . . . . . . . . . . . . . . 19 6.4.4 Load regulation for low consumption mode and Low noise mode part number . . . . . . . . . 20 6.5 Switch-over feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 Spread spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.7 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.8 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.9 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.10 Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7.1 GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 8.1 DS13116 - Rev 1 Programmable power up threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 page 58/63 L6983 Contents 8.2 External synchronization (available for low noise mode only) . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.4 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.5 Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.5.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.5.3 Output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Application board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 10 Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 11 Thermal dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 12 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 12.1 13 DFN6 (3x3) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 DS13116 - Rev 1 page 59/63 L6983 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical application component . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSW selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External synchronization AC coupling suggested operation range Capacitor part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QFN16 (3x3 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS13116 - Rev 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 6 . 7 . 7 . 7 . 8 10 30 32 35 55 56 57 page 60/63 L6983 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. DS13116 - Rev 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin connection (top through view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic application (adjustable version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-up/down behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-start procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-start phase with IOUT = 2.5 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Light load operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCM operation with ISKIP = 600 mA typ. at zero load. L = 15 H; COUT = 40 F. . . . . . . . LCM operation over loading condition (part 1-pulse skipping) . . . . . . . . . . . . . . . . . . . . LCM operation over loading condition (part 2-pulse skipping) . . . . . . . . . . . . . . . . . . . . LCM operation over loading condition (part 3-pulse skipping) . . . . . . . . . . . . . . . . . . . . LCM operation over loading condition (part 4-CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . Low noise mode operation at zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Light-load efficiency for low consumption mode and low noise mode - linear scale. . . . . . Light-load efficiency for low consumption mode and low noise mode - log scale . . . . . . . Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - linear scale. Load regulation for low noise mode. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - log scale. . Switch-over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over current protection behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-start procedure with VOUT shorted to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over current procedure with persistent short circuit between VOUT and GND . . . . . . . . . PGOOD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of the loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trans-conductance embedded error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Leading network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Leading network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External synchronization. Direct connection.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External synchronization. AC coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale). . . . . . . . . . . . . . . . . . . . Power losses VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale). . . . . . . . . . . . . . . . . . . . Power losses VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale) . . . . . . . . . . . . . . . . . . Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale) . . . . . . . . . . . . . . . . . . Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ (log scale) . . . . . . . . . . . . . . . . . . Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 6 12 13 13 14 15 15 16 16 17 18 19 19 20 20 21 22 23 24 25 26 27 28 29 29 30 31 34 36 36 37 37 38 38 39 39 40 40 41 42 42 43 44 44 45 46 46 page 61/63 L6983 List of figures Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. DS13116 - Rev 1 Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ . . . . . . Efficiency VIN = 24 V; VOUT = 5 V; FSW = 1.0 MHZ. . . . . . . . . Efficiency VIN = 24 V; VOUT = 5.0 V; FSW = 1.0 MHZ (log scale) Power losses VIN = 24 V; VOUT = 5.0 V; FSW = 1.0 MHZ . . . . . Efficiency VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ . . . . . . . . Efficiency VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ (log scale) Power losses VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ . . . . . Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . QFN16 (3x3 mm) package outline . . . . . . . . . . . . . . . . . . . . . QFN16 (3x3 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 48 48 48 49 50 50 52 54 55 page 62/63 L6983 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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