Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Low Voltage Adjustable Precision Shunt Regulator
FeaturesGeneral Description
Applications
The APL431L is a 3-terminal low voltage adjustable
precision reference with specified thermal stability
over applicable commercial temperature ranges.
Output voltage may be set to any value between
VREF (1.24 V) and 20 V with two external resistors
(see Figure 2). When used with an photocoupler,
the APL431L is an ideal voltage reference in isolated
feedback circuits for 3V to 12V switching-mode
power supplies. This device has a typical output
impedance of 0.1W. Active output circuitry provides
a very sharp turn-on characteristic, making the
APL431L excellent replacements for zener diodes
in many applications, including on-board regulation
and adjustable power supplies.
•Precise Reference Voltage to 1.24V
•Guaranteed 0.5%, 1% or 1.5% Reference Voltage
Tolerance
•Sink Current Capability, 80uA to 100mA
•Quick Turn-on
•Adjustable Output Voltage, VO = VREF to 20V
•Low Operational Cathode Current, 80µA Typical
•0.1Ω Typical Output Impedance
•SOT-23-3, SOT-23-5, TO-92 and SOT-89
Packages
•Lead Free and Green Devices Available
(RoHS Compliant)
•Linear Regulators
•Adjustable Power Supply
•Switching Power Supply
Symbol
Functional Diagram
CathodeAnode
REF
Vref
+
_
Cathode
REF
Anode
Pin Configuration
REF
ANODE
CATHODE
1 2
3
REF
NC
CATHODE
NC
ANODE
1 2 3
45
REF
ANODE
CATHODE3
2
1
REF ANODE CATHODE
1 2 3
SOT-23-3 (Top View) SOT-23-5 (Top View)
TO-92 (Top View) SOT-89 (Top View)
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw2
Symbol Parameter Rating Unit
VKA Cathode Voltage 21 V
IK Continuous Cathode Current Range 120 mA
IREF Reference Current Range 3 mA
θJA
Thermal Resistance from Junction to Ambient in Free Air
SOT-23-3
SOT-23-5
SOT-89
TO-
92
416
357
250
250
°C/W
T J Operating Junction Temperature Range -40 to 150 °C
TSTG Storage Temperature Range -65 to 150 °C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C
Ordering and Marking Information
Absolute Maximum Ratings
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
APL431L
Elec. Grade
Handling Code
Temperature Range
Package Code
Elec. Grade
A : 0.5% Reference Voltage Tolerance
B : 1% Reference Voltage Tolerance
C : 1.5% Reference Voltage Tolerance
Package Code
A : SOT-23-3 B : SOT-23-5
D : SOT-89 E : TO-92
Y : Chip Form
Temperature Range
C : 0 to 70 C I : -40 to 85 C
Handling Code
TR : Tape & Reel TB : Tape & Box
Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
°°
APL
431L
XXXXX XXXXX - Date Code
APL431L E :
APL431L D : APL431L
XXXXX - Date Code
XXXXX
APL431L A/B : 431L
Assembly Material
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw3
Electrical Characteristics TA= 25°C ( unless otherwise noted)
APL431L
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
APL431LA
1.234
1.240
1.246
APL431LB
1.228
1.240
1.252
VKA=VREF, IK=10mA
TA =25°C, (Fig. 1)
APL431LC
1.223
1.240
1.258
APL431LA
1.222
1.240
1.258
APL431LB
1.215
1.240
1.265
VREF Reference Voltage
TA =full range
(see Note1), (Fig.1)
APL431LC
1.212
1.240
1.262
V
VDEF VDEF Temp Deviation TA =full range (see Note1)
VKA=VREF, IK=10mA (Fig. 1) 5 15 mV
∆VREF /
∆VKA Ratio of Change in VREF to
Change in Cathods Votage
IK=10mA, VKA=16V to VREF (Fig. 2)
-0.2
-1.0
mV/V
IREF Reference Input Current IK=10mA,R1 =10kΩ,R2 =∞ (Fig. 2) 0.15
0.5 µA
IREF(DEV)
IREF Temp Deviation TK=full range (Note 1),
R1=10kΩ, R 2=∞, IK=10mA, (Fig. 2)
0.05
0.3 µA
VKA=6V 0.01
0.1
IK(off) Off-State Cathode Current VREF=0V, (Fig. 3) VKA=16V 0.01
0.5 µA
ZKA Dynamic Output Impedance
VKA=VREF, IK=1mA to 100mA,
f ≤1kHz (Fig. 1) 0.1 0.4 Ω
IK(MIN) Minimum Operating Current
VKA=VREF (Fig. 1) 80 100 µA
Note 1 : Full temperature range is 0°C to 70°C for APL431LXXC,and -40°C to 85°C for APL431LXXl.
Test Figures
Figure 1. Test Circuit for VKA=VREF , VO=VKA=VREFFigure 2. Test Circuit for IK(off)
V
IN
V
o
I
K
V
REF
V
o
V
IN
I
K(off)
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw4
Test Figures (Cont.)
Figure 3. Test Circuit for VKA>VREF,
VO= VKA= VREF× (1+R1/R2) + IREF × R1
V
IN
I
K
I
REF
V
REF
R1
R2
V
o
Application Circuits
VoVIN
R2
R1
VREF
RB
Precision Voltage Reference
Vo
VIN
RB
VREF
R2
R1
C1
Precision High-Current Series Regulator
Notes for Application Circuits:
1) For the series regulator applications, add a compensation capacitor C1 between CATHODE and REF is
strongly recommended to improve the stability of output voltage .
2) Set VO according to the following equation: VO = VREF(1+R1/R2)+lREF xR1
3) Choose the value for RB as follows:
A) The maximum limit for RB should be such that the cathode current (lK) is greater than the minimum
operating current (80µA) at VIN(MIN).
B) The minimum limit for RB should be such that the cathode current (lK) does not exceed 100mA under all
load conditions, and the instantaneous turn-on value for lK does not exceed 150mA.
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw5
-100
-50
0
50
100
-1.5 -1 -0.5 00.5 11.5
0.08
0.10
0.12
0.14
0.16
0.18
-50 -25 025 50 75 100 125 150
1.22
1.23
1.24
1.25
1.26
-50 -25 0 25 50 75 100 125 150
-250
-200
-150
-100
-50
0
50
100
150
200
250
-1 -0.5 00.5 11.5
Typical Characteristics
VKA=VREF
IKA=10mA
Cathode Voltage (V)
Cathode Current (mA)
Cathode Voltage (V)
Cathode Current (µA)
Cathode Current vs. Cathode Voltage Cathode Current vs. Cathode Voltage
Junction Temperature (°C)
Reference Voltage (V)
Reference Input Current (µA)
Junction Temperature (°C)
Referemce Voltage vs.
Junction TemperatureReference Input Current vs.
Junction Temperature
TA=25°CVKA=VREF
TA=25°C
R1=10kΩ, R2=∞
IKA=10mA
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw6
0
0.1
0.2
0.3
0.4
0.5
-50 -25 025 50 75 100 125 150
0S
µ
0
1V
0
5S
µ
3V
0S
µ
5S
µ
0
1V
0
3V
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
-50 -25 025 50 75 100 125 150
Typical Characteristics
Input
Junction Temperature (°C)
Ratio of Delta Reference Voltage to
Delta Cathode Voltage (-mV/V)
Junction Temperature (°C)
Off State Cathode Current (µA)
Off State Cathode Current vs.
Junction Temperature
∆VREF/∆VKA vs. Junction Temperature
VREF =0VVKA =16V
VKA =6V
IKA =1mA
Output
Input
Output
TA =25°CIKA =0.1mA
TA =25°C
∆VKA=VREF to 20V
IKA=10mA
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw7
0
10
20
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
-10
0
10
20
30
40
50
60
10 100 1000 10000 100000 1000000
0
50
100
150
200
250
300
350
Typical Characteristics
Frequency (Hz)
Gain (dB)
Phase Shift (degree)
Gain vs. Phase Shift vs. Frequency
CL-Load Capacitance (µF)
Ik (mA)
Stability Boundary Conditions
VKA =VREF
VKA =2.5V
VKA =3.3V
Stable
Unstable
TA =25°C
IKA=10mA
TA =25°C
Stability Test Circuit for VKA=VREF
Stability Test Circuit for VKA>VREF,
VO= VKA= VREF× (1+R1/R2) + IREF × R1
VIN
6.8k
4.3k
Vo
10uF
180
5V
Ω
Ω
Ω
Gain & Phase Test Circuit
Use the MLCC for CL
VIN Vo
CL
IK
Ω
100
VIN
R1
R2
Vo
CL
IK
100Ω
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw8
0.01
0.1
1
10
100
10 100 1000 10000 100000 1000000
Frequency (Hz)
Zka (Ω)
Zka vs. Frequency
VKA=VREF
IKA=10mA
TA =25°C
Typical Characteristics
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw9
SOT-23-3
0
L
VIEW A
0.25
GAUGE PLANE
SEATING PLANE
A
A2A1
e
D
E
E1
SEE
VIEW A
bc
e1
MAX.
0.057
0.051
0.024
0.006
0.009
0.0200.012
L0.30
0
e
e1
E1
E
D
c
b
0.08
0.30
0.60 0.012
0.95 BSC
1.90 BSC
0.22
0.50
0.037 BSC
0.075 BSC
0.003
MIN.
MILLIMETERS
S
Y
M
B
O
L
A1
A2
A
0.00
0.90
SOT-23
MAX.
1.45
0.15
1.30
MIN.
0.000
0.035
INCHES
°
8
°
0
°
8
°
0
1.40
2.60
1.80
3.00
2.70 3.10 0.122
0.071
0.1180.102
0.055
0.106
Note : Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
Package Information
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw10
Package Information
SOT-23-5
MAX.
0.057
0.051
0.024
0.006
0.009
0.0200.012
L0.30
0
e
e1
E1
E
D
c
b
0.08
0.30
0.60 0.012
0.95 BSC
1.90 BSC
0.22
0.50
0.037 BSC
0.075 BSC
0.003
MIN.
MILLIMETERS
S
Y
M
B
O
L
A1
A2
A
0.00
0.90
SOT-23-5
MAX.
1.45
0.15
1.30
MIN.
0.000
0.035
INCHES
°
8
°
0
°
8
°
0
bc
e1
0
L
VIEW A
0.25
GAUGE PLANE
SEATING PLANE
A
A2A1
e
D
E
E1
SEE
VIEW A
1.40
2.60
1.80
3.00
2.70 3.10 0.122
0.071
0.1180.102
0.055
0.016
Note : 1. Follow JEDEC TO-178 AA.
2. Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw11
Package Information
TO-92
j
D
E
S
j
L
e
e1
A
b
S
Y
M
B
O
LMIN. MAX.
5.33
3.18 4.19
2.42 2.66
0.53
3.43
A
b
E
e
e1
j
L
S
MILLIMETERS
D4.45 5.20
TO-92
12.70
2.03 2.66
MIN. MAX.
INCHES
0.210
0.175 0.205
0.125 0.165
0.095 0.105
0.135
0.500
0.080 0.105
4.32 0.170
0.021
0.055
1.15 1.39 0.045
0.41 0.016
Note : FollowJEDEC TO-92.
4.00 0.157
0.591
15.00
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw12
Package Information
SOT-89
S
Y
M
B
OMIN. MAX.
MILLIMETERS
SOT-89
MIN. MAX.
INCHES
A
C
e1
e
B
B1
D
D1
H
EL
E1
1.60
0.44
0.35 0.44
4.40 4.60
1.62 1.83
0.56
2.13
A
B
C
D
D1
E
E1
e
e1
B1 0.36 0.48
3.00 BSC
3.94 4.25
2.29 2.60
2.29
0.118 BSC
0.063
0.017
0.014 0.019
0.014 0.017
0.173 0.181
0.064 0.072
0.084
0.155 0.167
0.090 0.102
0.090
0.022
L0.89 0.035
H
1.50 BSC 0.059 BSC
1.40
1.20 0.047
0.055
L
Note : Follow JEDEC TO-243 AA.
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw13
Carrier Tape & Reel Dimensions
H
T1
A
d
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
Application
A H T1 C d D W E1 F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOT-23-3
4.0±0.10
4.0±0.10
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
Application
A H T1 C d D W E1 F
178.0±
2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.50±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOT-89
4.0±
0.10
8.0±
0.10
2.0±
0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.80±
0.20
4.50±
0.20
1.80±
0.20
Application
A H T1 C d D W E1 F
178.0±
2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±
0.30
1.75±
0.10
3.5±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOT-23-5
4.0±0.10
4.0±0.10
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
(mm)
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw14
Reflow Condition (IR/Convection or VPR Reflow)
t 25 C to Peak
tp
Ramp-up
tL
Ramp-down
ts
Preheat
Tsmax
Tsmin
TL
TP
25
Temperature
Time
Critical Zone
TL to TP
°
Carrier Tape & Box Dimensions
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw15
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
(TL to TP) 3°C/second max. 3°C/second max.
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
Time maintained above:
- Temperature (TL)
- Time (tL) 183°C
60-150 seconds 217°C
60-150 seconds
Peak/Classification Temperature (Tp)
See table 1 See table 2
Time within 5°C of actual
Peak Temperature (tp) 10-30 seconds 20-40 seconds
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Classification Reflow Profiles
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA
Reliability Test Program
Devices Per Unit
Package Type Unit Quantity
SOT-23-3 Tape & Reel 3000
SOT-89 Tape & Reel 1000
SOT-23-5 Tape & Reel 3000
TO-92 Tape & Box 2000
Copyright ANPEC Electronics Corp.
Rev. B.10 - Mar., 2008
APL431L
www.anpec.com.tw16
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Package Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Classification Reflow Profiles (Cont.)
