DGN−8D−8 DGK−8
1
2
3
4
8
7
6
5
VIN−
VOCM
VCC+
VOUT+
VIN+
PD
VCC−
VOUT−
THS4130
D, DGN, OR DGK PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
VIN−
VOCM
VCC+
VOUT+
VIN+
NC
VCC−
VOUT−
THS4131
D, DGN, OR DGK PACKAGE
(TOP VIEW)
SHUTDOWN
NUMBER OF
CHANNELS
DEVICE
THS4130
THS4131 1
1X
−
HIGH-SPEED DIFFERENTIAL I/O FAMILY
VDD
DIGITAL
OUTPUT
VIN
−
+−
+
DVDD
VOCM
AVSS
AVDD
AIN
AIN
Vref
5V
−5V
Typical A/D ApplicationCircuit
−100
−90
−80
−70
−60
−50
−40
−30
−20
100k 1M 10M
f − Frequency − Hz
THD − TotalHarmonicDistortion − dB
TOTAL HARMONICDISTORTIONvsFREQUENCY
VOUT PP
=2V
VCC =5Vto 5V±
VCC = 15V±
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
HIGH-SPEED, LOW-NOISE, FULLY-DIFFERENTIAL I/O AMPLIFIERS
Check for Samples: THS4130,THS4131
1FEATURES DESCRIPTION
The THS413x is one in a family of fully-differential
23•High Performance input/differential output devices fabricated using
–150 MHz, –3 dB Bandwidth (VCC =±15 V) Texas Instruments' state-of-the-art BiComI
–51 V/µs Slew Rate complementary bipolar process.
– –100 dB Third Harmonic Distortion at The THS413x is made of a true fully-differential signal
250 kHz path from input to output. This design leads to an
•Low Noise excellent common-mode noise rejection and
–1.3 nV/√Hz Input-Referred Noise improved total harmonic distortion.
•Differential-Input/Differential-Output
–Balanced Outputs Reject Common-Mode
Noise
–Reduced Second-Harmonic Distortion Due
to Differential Output
•Wide Power-Supply Range
–VCC = 5 V Single Supply to ±15 V Dual
Supply
•ICC(SD) = 860 µA in Shutdown Mode (THS4130)
APPLICATIONS
•Single-Ended To Differential Conversion
•Differential ADC Driver
•Differential Antialiasing
•Differential Transmitter And Receiver
•Output Level Shifter
RELATED DEVICES
DEVICE DESCRIPTION
THS412x 100 MHz, 43 V/µs, 3.7 nV/√Hz
THS414x 160 MHz, 450 V/µs, 6.5 nV/√Hz
THS415x 180 MHz, 850 V/µs, 9 nV/√Hz
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2000–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
PACKAGED DEVICES
MSOP PowerPAD™MSOP
SMALL OUTLINE EVALUATION
TA(D) (DGN) SYMBOL (DGK) SYMBOL MODULES
THS4130CD THS4130CDGN AOB THS4130CDGK ATP THS4130EVM
0°C to +70°CTHS4131CD THS4131CDGN AOD THS4131CDGK ATQ THS4131EVM
THS4130ID THS4130IDGN AOC THS4130IDGK ASO —
–40°C to +85°CTHS4131ID THS4131IDGN AOE THS4131IDGK ASP —
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range,unless otherwise noted. UNIT
VCC–to VCC+ Supply voltage ±33 V
VIInput voltage ±VCC
IO(2) Output current 150 mA
VID Differential input voltage ±6 V
Continuous total power dissipation See Dissipation Rating table
TJ(3) Maximum junction temperature +150°C
TJ(4) Maximum junction temperature, continuous operation, long-term reliability +125°C
TAOperating free-air temperature C-suffix 0°C to +70°C
I-suffix –40°C to +85°C
TSTG Storage temperature –65°C to +150°C
ESD ratings: HBM 2500 V
CDM 1500 V
MM 200 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS413x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally
dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could
permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about using the PowerPAD
thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
DISSIPATION RATING TABLE POWER RATING(2)
PACKAGE θJA(1) (°C/W) θJC (°C/W) TA= +25°C TA= +85°C
D 97.5 38.3 1.02 W 410 mW
DGN 58.4 4.7 1.71 W 685 mW
DGK 134 72 750 mW 300 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and
long-term reliability.
2Copyright ©2000–2011, Texas Instruments Incorporated
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT
Dual supply ±2.5 ±15
Supply voltage, VCC+ to VCC–V
Single supply 5 30
C-suffix 0 +70
Operating free-air temperature, TA°C
I-suffix –40 +85
ELECTRICAL CHARACTERISTICS(1)
VCC=±5 V, RL= 800Ω, and TA= +25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE
VCC = 5 Gain = 1, Rf= 390 Ω125
Small-signal bandwidth (–3 dB), single-ended input, VCC =±5 Gain = 1, Rf= 390 Ω135
differential output, VI= 63 mVPP VCC =±15 Gain = 1, Rf= 390 Ω150
BW MHz
VCC = 5 Gain = 2, Rf= 750 Ω80
Small-signal bandwidth (–3 dB), single-ended input, VCC =±5 Gain = 2, Rf= 750 Ω85
differential output, VI= 63 mVPP VCC =±15 Gain = 2, Rf= 750 Ω90
SR Slew rate(2) Gain = 1 52 V/µs
Settling time to 0.1% 78 ns
tsStep voltage = 2 V, gain = 1
Settling time to 0.01% 213 ns
DISTORTION PERFORMANCE
f = 250 kHz –95
VCC = 5 f = 1 MHz –81
f = 250 kHz –96
Total harmonic distortion, differential input, differential VCC =±5
output, gain = 1, Rf= 390 Ω, RL= 800 Ω, VO= 2 VPP f = 1 MHz –80
f = 250 kHz –97
THD VCC =±15 dBc
f = 1 MHz –80
f = 250 kHz –91
VCC =±5f = 1 MHz –75
VO= 4 VPP f = 250 kHz –91
VCC =±15 f = 1 MHz –75
VCC =±2.5 97
VO= 2 VPP VCC =±5 98
Spurious-free dynamic range, differential input,
SFDR differential output, gain = 1, Rf= 390 Ω, VCC =±15 99 dB
RL= 800 Ω, f = 250 kHz VCC =±5 93
VO= 4 VPP VCC =±15 95
Third intermodulation distortion VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz –53 dBc
Third-order intercept VI(PP) = 4 V, G = 1, F1 = 3 MHz, F2 = 3.5 MHz 41.5 dB
NOISE PERFORMANCE
VnInput voltage noise f = 10 kHz 1.3 nV/√Hz
InInput current noise f = 10 kHz 1 pA/√Hz
DC PERFORMANCE
TA= +25°C 71 78
Open-loop gain dB
TA= full range 69
TA= +25°C 0.2 2
Input offset voltage TA= full range 3 mV
V(OS) Common-mode input offset voltage, referred to VOCM TA= +25°C 0.2 3.5
Input offset voltage drift TA= full range 4.5 µV/°C
IIB Input bias current TA= full range 2 6 µA
IOS Input offset current TA= full range 100 500 nA
Offset drift 2 nA/°C
(1) The full range temperature is 0°C to +70°C for the C-suffix, and –40°C to +85°C for the I-suffix.
(2) Slew rate is measured from an output level range of 25% to 75%.
Copyright ©2000–2011, Texas Instruments Incorporated 3
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS(1) (continued)
VCC=±5 V, RL= 800Ω, and TA= +25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
CMRR Common-mode rejection ratio TA= full range 80 95 dB
–3.77 to
VICR Common-mode input voltage range –4 to 4.5 V
4.3
RIInput resistance Measured into each input terminal 34 MΩ
CIInput capacitance, closed loop 4 pF
roOutput resistance Open loop 41 Ω
OUTPUT CHARACTERISTICS
1.2 to 0.9 to
TA= +25°C3.8 4.1
VCC = 5 V 1.3 to
TA= full range ±4
3.7
Output voltage swing V
TA= +25°C±3.7
VCC =±5 V TA= full range ±3.6
TA= +25°C±10.5 ±12.4
VCC =±15 V TA= full range ±10.2
TA= +25°C 25 45
VCC = 5 V, RL= 7 ΩTA= full range 20
TA= +25°C 30 55
IOOutput current VCC =±5 V, RL= 7 ΩmA
TA= full range 28
TA= +25°C 60 85
VCC =±15 V, RL= 7 ΩTA= full range 65
POWER SUPPLY
Single supply 4 33
VCC Supply voltage range V
Split supply ±2±16.5
TA= +25°C 12.3 15
VCC =±5 V
ICC Quiescent current TA= full range 16 mA
VCC =±15 V TA= +25°C 14
TA= +25°C 0.86 1.4
ICC(SD) Quiescent current (shutdown) (THS4130 only)(3) V = –5 V mA
TA= full range 1.5
TA= +25°C 73 98
PSRR Power-supply rejection ratio (dc) dB
TA= full range 70
(3) For detailed information on the behavior of the power-down circuit, see the Power-Down Mode section in the Principles of Operation.
4Copyright ©2000–2011, Texas Instruments Incorporated
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS FIGURE
Figure 1,
Small-signal frequency response Figure 2
Small-signal frequency response (various supplies) Figure 3
Small-signal frequency response (various CF)Figure 4
Small-signal frequency response (various CL)Figure 5
Large-signal transient response (differential in/single out) Figure 6
Large-signal frequency response Figure 7
CMMR Common-mode rejection ratio vs Frequency Figure 8
vs Free-air temperature Figure 9
ICC Supply current vs Free-air temperature (shutdown state) Figure 10
IIB Input bias current vs Free-air temperature Figure 11
Settling time Figure 12
PSRR Power-supply rejection ratio vs Frequency (differential out) Figure 13
Large-signal transient response Figure 14
THD Total harmonic distortion vs Frequency Figure 15
Figure 16,
vs Frequency Figure 17
Second-harmonic distortion Figure 18,
vs Output voltage Figure 19
Figure 20,
vs Frequency Figure 21
Third-harmonic distortion Figure 22,
vs Output voltage Figure 23
VnVoltage noise vs Frequency Figure 24
InCurrent noise vs Frequency Figure 25
V(OS) Input offset voltage vs Common-mode output voltage Figure 26
VOOutput voltage vs Differential load resistance Figure 27
zoOutput impedance vs Frequency Figure 28
Copyright ©2000–2011, Texas Instruments Incorporated 5
−8
−3
2Gain = 1,
RL = 800 Ω,
VCC = ±5 V,
VI = 63 mVPP
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Output − dB
3
1
0
−1
−2
−4
−5
−6
−7
Rf = 620 Ω
Rf = 390 Ω
−10
−5
0
5
10
15
20
25
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Gain = 5_Rf = 2 kΩ
Gain = 10_Rf = 4 kΩ
Gain = 1_Rf = 390 Ω
Gain = 2_Rf = 750 Ω
RL = 800 Ω,
VCC = ±5 V,
VI = 63 mVPP
Output −dB
−8
−3
2
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Output − dB
VCC= 5
VCC= ±15
Gain = 1,
RL = 800 Ω,
Rf = 390 Ω,
VI = 63 mVPP
−7
−6
−5
−4
−2
−1
0
1
Output − dB
−10
−5
0
CF = 0 pF
CF = 1 pF
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
−9
−8
−7
−6
−4
−3
−2
−1
1
2
3
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS
SMALL-SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL FREQUENCY RESPONSE
Figure 1. Figure 2.
SMALL-SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL FREQUENCY RESPONSE
(VARIOUS SUPPLIES) (VARIOUS CF)
Figure 3. Figure 4.
6Copyright ©2000–2011, Texas Instruments Incorporated
−8
−3
2
CL = 10 pF
100 k 1 M 10 M 100 M 1 G
f − Frequency − Hz
Output − dB
Gain = 1,
RL = 800 Ω,
VCC = ±5 V,
VI = 63 mVPP,
Rf = 390 Ω
CL = 0 pF
−7
−6
−5
−4
−2
−1
−0
1
3
4
5
−1
−0.5
0
0.5
−0.5
0
0.5
1
00.2 0.4 0.6
Large Signal Transient Response − V
t − Time − µs
VO+
VO−
VI (Diff)
0.1 0.3 0.5
−25
−20
−15
−10
−5
0
5
100 k 10 M 100 M 1 G1 M
VCC = ±5 V
VCC = ±15 V
VCC = 5 V
Gain = 1
Rf = 390 Ω,
RL = 800 Ω,
CF = 0 pF,
VI = 0.2 VRMS
Output − dB
f − Frequency − Hz
−100
−95
−90
−85
−80
−75
−70
−65
−60
−55
−50
CMRR − Common Mode Rejection Ratio − dB
100 k 1 M 10 M 100 M
f − Frequency − Hz
Rf = 1 kΩ,
VCC = ±5 V
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
TYPICAL CHARACTERISTICS (continued)
SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL TRANSIENT RESPONSE
(VARIOUS CL) (DIFFERENTIAL IN/SINGLE OUT)
Figure 5. Figure 6.
COMMON-MODE REJECTION RATIO
vs
LARGE-SIGNAL FREQUENCY RESPONSE FREQUENCY
Figure 7. Figure 8.
Copyright ©2000–2011, Texas Instruments Incorporated 7
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
−40 −20 0 20 40 60 80 100
VCC = ±15 V
VCC = ±5 V
− Supply Current − mA
ICC
TA − Free-Air T emperature − °C
800
820
840
860
880
900
920
940
−50 −25 0 25 50 75 100
− Supply Current −
TA − Free-Air T emperature (Shutdown State) − °C
ICC Aµ
1.98
1.96
1.94
1.9 0 25 50 75
2
2.02
2.04
100 125 150
1.92
RF = 510 Ω
CF = 1 pF,
VCC = 5 V
VO = 4 VPP
RL = 800 Ω
− Output Voltage − V
t − Time − ns
VO
2.05
2.1
2.15
2.2
2.25
2.3
2.35
2.4
−50 −25 0 25 50 75 100
IIB+
IIB−
− Input Bias Current −
IIB Aµ
TA − Free-Air T emperature − °C
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
SUPPLY CURRENT vs
vs FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE (SHUTDOWN STATE)
Figure 9. Figure 10.
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE SETTLING TIME
Figure 11. Figure 12.
8Copyright ©2000–2011, Texas Instruments Incorporated
−100
−90
−80
−70
−60
−50
−40
10 k 100 k 1 M 10 M 100 M
VCC = 5 V
VCC = −5 V
PSRR − Power Supply Rejection Ratio − dB
f − Frequency (Differential Out) − Hz
Gain = 1,
Rf = 330 Ω,
RL = 400 Ω
−2.5
−2
−1.5
−1
−5
0
5
1
1.5
2
2.5
0 40 80 120 160 200
VO+
VO−
t − Time − nS
G = 1,
Rf = 390 Ω,
RL = 800 Ω,
CF = 0 pF,
CL = 10 pF,
VI_Peak = 2 V,
VCC = ±15 V
TA = 25°C
− Output Voltage − V
VO
−110
−100
−90
−80
−70
−60
−50
−40
−30
100 k 1 M 10 M
VCC = 5 V
VCC = ±15V, ±5V
Second Harmonic Distortion − dBc
f − Frequency − Hz
VO = 2 VPP,
RL = 800 Ω,
Rf = 390 Ω,
G = 1
Single Ended Input
Differential Output
−100
−90
−80
−70
−60
−50
−40
−30
−20
100k 1M 10M
VOUT = 2 VPP
VCC = 5 V to ± 5 V
VCC = ± 15 V
THD − Total Harmonic Distortion − dB
f − Frequency − Hz
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
TYPICAL CHARACTERISTICS (continued)
POWER-SUPPLY REJECTION RATIO
vs
FREQUENCY (DIFFERENTIAL OUT) LARGE-SIGNAL TRANSIENT RESPONSE
Figure 13. Figure 14.
TOTAL HARMONIC DISTORTION SECOND-HARMONIC DISTORTION
vs vs
FREQUENCY FREQUENCY
Figure 15. Figure 16.
Copyright ©2000–2011, Texas Instruments Incorporated 9
Second Harmonic Distortion − dBc
−106
−104
−102
−100
−98
−96
−94
−92
0 1 2 3 4 5 6 7
VCC = ±5 V
VCC = ±15 V
f = 250 KHz
RL = 800 Ω,
Rf = 390 Ω,
G = 1
VO − Output Voltage − V
VCC = 5 V
Single Ended Input
Differential Output
−110
−100
−90
−80
−70
−60
−50
−40
−30
VCC = ±5 V
VCC = ±15 V
VO = 4 VPP,
RL = 800 Ω,
Rf = 390 Ω,
G = 1
100 k 1 M 10 M
f − Frequency − Hz
Second Harmonic Distortion − dBc
Single Ended Input
Differential Output
Second Harmonic Distortion − dBc
−106
−104
−102
−100
−98
−96
−94
−92
−90
−88
0 1 2 3 4 5 6 7
VCC = ±15 V
VCC = ±5 V
VCC = 5 V
f = 500 KHz
RL = 800 Ω,
Rf = 390 Ω,
G = 1
VO − Output Voltage − V
Single Ended Input
Differential Output
−110
−100
−90
−80
−70
−60
−50
−40
−30
100 k 1 M 10 M
VCC = ±5 V
VO = 4 VPP
RL = 800 Ω,
Rf = 390 Ω,
G = 1
f − Frequency − Hz
VCC = ±15 V
Third Harmonic Distortion − dBc
Single Ended Input
Differential Output
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SECOND-HARMONIC DISTORTION SECOND-HARMONIC DISTORTION
vs vs
FREQUENCY OUTPUT VOLTAGE
Figure 17. Figure 18.
SECOND-HARMONIC DISTORTION THIRD-HARMONIC DISTORTION
vs vs
OUTPUT VOLTAGE FREQUENCY
Figure 19. Figure 20.
10 Copyright ©2000–2011, Texas Instruments Incorporated
−110
−100
−90
−80
−70
−60
−50
−40
−30
100 k 1 M 10 M
VCC = ±5 V
VCC = ±15 V
VCC = 5 V
VO = 2 VPP,
RL = 800 Ω,
Rf = 390 Ω,
Gain = 1
Third Harmonic Distortion − dBc
f − Frequency − Hz
Single Ended Input
Differential Output
−106
−104
−102
−100
−98
−96
−94
−92
−90
−88
0 1 2 3 4 5 6 7
VCC = ±5 V
VCC = 5 V
f = 500 KHz
RL = 800 Ω,
Rf = 390 Ω,
G = 1
Third Harmonic Distortion − dBc
VO − Output Voltage − V
VCC = ±15 V
Single Ended Input
Differential Output
Third Harmonic Distortion − dBc
−106
−104
−102
−100
−98
−96
−94
−92
−90
−88
0 1 2 3 4 5 6 7
VCC = 5 V
VCC = ±5 V
f = 250 KHz
RL = 800 Ω,
Rf = 390 Ω,
G = 1
VO − Output Voltage − V
VCC = ±15 V
Single Ended Input
Differential Output
10 100 1 k 10 k 100 k
f − Frequency − Hz
10
nV/ Hz− Voltage Noise −Vn
1
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
TYPICAL CHARACTERISTICS (continued)
THIRD-HARMONIC DISTORTION THIRD-HARMONIC DISTORTION
vs vs
FREQUENCY OUTPUT VOLTAGE
Figure 21. Figure 22.
THIRD-HARMONIC DISTORTION VOLTAGE NOISE
vs vs
OUTPUT VOLTAGE FREQUENCY
Figure 23. Figure 24.
Copyright ©2000–2011, Texas Instruments Incorporated 11
0
1E−12
2E−12
3E−12
4E−12
5E−12
6E−12
7E−12
1 10 100 1 k 10 k 100 k
f − Frequency − Hz
In− Current Noise − pA/ Hz
−600
−400
−200
0
200
400
600
800
1000
−12 −9 −6 −3 0 3 6 9 12
− Input Offset Voltage −
VCC = ±2.5 V
VCC = ±5 V
VCC = ±15 V
V(OS) Vµ
VOCM − Common-Mode Output Voltage − V
Rf = 1 k,
RL = 800 Ω,
G = 1
−15
−10
−5
0
5
10
15
100 1000 10 k 100 k
− Output Voltage − V
VO
RL − Differential Load Resistance − Ω
Rf = 1 k
G = 2 VCC = ±15 V
VCC = ±5 V
VCC = ±5 V
VCC = ±15 V
VOUT+
VOUT+
VOUT−
VOUT−
0.1
1
10
100
100 k 1 M 10 M 100 M 1 G
− Output impedance −
f − Frequency − Hz
Ω
VCC = ±5 V
zo
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CURRENT NOISE INPUT OFFSET VOLTAGE
vs vs
FREQUENCY COMMON-MODE OUTPUT VOLTAGE
Figure 25. Figure 26.
OUTPUT VOLTAGE OUTPUT IMPEDANCE
vs vs
DIFFERENTIAL LOAD RESISTANCE FREQUENCY
Figure 27. Figure 28.
12 Copyright ©2000–2011, Texas Instruments Incorporated
ǒVCC)Ǔ)ǒVCC–Ǔ
2
_
+
x1
Output Buffer
Vcm Error
Amplifier
C R
CR
x1
Output Buffer
VOUT+
VOUT−
VCC+
VCC−
VIN−
VIN+
30 kΩ30 kΩVCC+
VCC− VOCM
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
APPLICATION INFORMATION
RESISTOR MATCHING
Resistor matching is important in fully-differential amplifiers. The balance of the output on the reference voltage
depends on matched ratios of the resistor. CMRR, PSRR, and cancellation of the second-harmonic distortion
diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to
keep the performance optimized.
VOCM sets the dc level of the output signals. If no voltage is applied to the VOCMpin, it is set to the midrail voltage
internally defined as:
(1)
In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential
mode is the same as the input in the gain of 1. VOCM has a high bandwidth capability up to the typical operation
range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the VOCM
pin as a bypass capacitor. Figure 29 shows the simplified diagram of the THS413x.
Figure 29. THS413x Simplified Diagram
Copyright ©2000–2011, Texas Instruments Incorporated 13
VIN
−
+−
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
VDD
Vref
5 V
VCC
0.1 µF
−5 V
VCC−
VIN
−
+−
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
VDD
Vref
5 V
VCC
0.1 µF
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
DATA CONVERTERS
Data converters are one of the most popular applications for the fully-differential amplifiers. Figure 30 shows a
typical configuration of a fully-differential amplifier attached to a differential analog-to-digital converter (ADC).
Figure 30. Fully-Differential Amplifier Attached to a Differential ADC
Fully-differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The
differential output may be fed into a data converter. This method eliminates the use of a transformer in the circuit.
If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM of the
amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to the input
terminal of the amplifier should not exceed the common-mode input voltage range.
Figure 31. Fully-Differential Amplifier Using a Single Supply
14 Copyright ©2000–2011, Texas Instruments Incorporated
VIN
−
+−
+
DVDD
VOCM
AVSS
AVDD
AIN2
AIN1
VDD
Vref
5 V
VCC
0.1 µF
RPU
RPU
THS1206
VCC Rf
Rg
VCC Rf
Rg
VP
VOUT
VOUT
RPU +VP– VCC
ǒVIN – VPǓ1
RG )ǒVOUT – VPǓ1
RF
THS413x
Output
Output
20 Ω
20 Ω
390 Ω
390 Ω
390 Ω
390 Ω
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
Some single-supply applications may require the input voltage to exceed the common-mode input voltage range.
In such cases, the circuit configuration of Figure 32 is suggested to bring the common-mode input voltage within
the specifications of the amplifier.
Figure 32. Circuit With Improved Common-Mode Input Voltage
Equation 2 is used to calculate RPU:
(2)
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS413x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output decreases the device phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 33. A minimum value of 20 Ωshould work well for most applications. For
example, in 50-Ωtransmission systems, setting the series resistor value to 50 Ωboth isolates any capacitance
loading and provides the proper line impedance matching at the source end.
Figure 33. Driving a Capacitive Load
Copyright ©2000–2011, Texas Instruments Incorporated 15
VIN−
VIN++
−+
−
VOCM
VOCM
VIN−
VIN+
VCC−
THS1050
THS413x
C3
C3
R4
R(t)
R2
R4
+
C1
+
VCC
C1
R2
R3
R3
C2
R1
R1
Vs
VIC
Hd(f) +ȧ
ȧ
ȡ
Ȣ
K
–ǒf
FSF x fcǓ2)1
Qjf
FSF x fc )1ȧ
ȧ
ȣ
Ȥ
xȧ
ȡ
Ȣ
Rt
2R4 )Rt
1)j2πfR4RtC3
2R4 )Rt ȧ
ȣ
ȤWhere K +R2
R1
FSF x fc +1
2π2 x R2R3C1C2
Ǹand Q +2 x R2R3C1C2
Ǹ
R3C1 )R2C1 )KR3C1
FSF +Re2)|Im|2
Ǹand Q +Re2)|Im|2
Ǹ2Re
FSF x fc +1
2πRC 2 x mn
Ǹand Q +2 x mn
Ǹ
1)m(1)K)
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
ACTIVE ANTIALIAS FILTERING
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high-frequency noise with the frequency of operation. Figure 34 presents a
method by which the noise may be filtered in the THS413x.
Figure 34. Antialias Filtering
The transfer function for this filter circuit is:
(3)
(4)
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency scaling factor, and Q is the
quality factor.
(5)
where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR, C1 =
C, and C2 = nC results in:
(6)
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
16 Copyright ©2000–2011, Texas Instruments Incorporated
Rf
R(g)
R(g) Rf
_
+
Differential Amplifier
VOCM
_
+_
+
VCC+
VIN−
VIN+
VO+
VO−
THS413x
Fully differential Amplifier
VCC−
Input voltage definition VID +ǒVI)Ǔ–ǒVI–ǓVIC +ǒVI)Ǔ)ǒVI–Ǔ
2
Output voltage definition VOD +ǒVO)Ǔ–ǒVO–ǓVOC +ǒVO)Ǔ)ǒVO–Ǔ
2
Transfer function VOD +VID x AǒfǓ
Output common mode voltage VOC +VOCM
VOCM
_
+_
+
VCC+
VIN−
VIN+
VO+
VO−
Differential Structure Rejects
Coupled Noise at The Output
Differential Structure Rejects
Coupled Noise at The Input
Differential Structure Rejects
Coupled Noise at The Power Supply VCC−
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
PRINCIPLES OF OPERATION
THEORY OF OPERATION
The THS413x is a fully-differential amplifier. Differential amplifiers are typically differential in/single out, whereas
fully-differential amplifiers are differential in/differential out.
Figure 35. Differential Amplifier Versus a Fully-Differential Amplifier
To understand the THS413x fully-differential amplifiers, the definition for the pin outs of the amplifier are
provided.
(7)
(8)
(9)
(10)
Figure 36. Definition of the Fully-Differential Amplifier
Copyright ©2000–2011, Texas Instruments Incorporated 17
−
Rf
R(g)
+
+
−
VCC−
VCC+
R(g)
Rf
Vs
VIN−
VIN+
VO+
VO−
VOCM
Note: For proper operation, maintain symmetry by setting
Rf1 = Rf2 = Rf and R(g)1 = R(g)2 = R(g) ⇒ A = Rf/R(g)
−
Rf
R(g)
+
+
−
VCC−
VCC+
R(g)
Rf
Vs
VIN−
VIN+
VO+
VO−
VOCM
GAIN R(g) ΩRf Ω
1
2
5
10
390
374
402
402
390
750
2010
4020
RECOMMENDED RESISTOR VALUES
VO+1
2VI
VO+–1
2VI
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
Figure 37 and Figure 38 depict the differences between the operation of the THS413x fully-differential amplifier in
two different modes. Fully-differential amplifiers can work with differential input or can be implemented as single
in/differential out.
Figure 37. Amplifying Differential Signals
Figure 38. Single In With Differential Out
If each output is measured independently, each output is one-half of the input signal when gain is 1. The
following equations express the transfer function for each output:
(11)
The second output is equal and opposite in sign:
(12)
18 Copyright ©2000–2011, Texas Instruments Incorporated
VOCM
_
+_
+
VCC+
VIN−
VIN+
VO+
VO−
VOD= 1−0 = 1
VOD = 0−1 = −1
a
b
+1
0
+1
0
VCC−
VOD
VIN1 – VIN2 +Rf
R(g) ǒ1)2R2
R1 Ǔ
_
+
_
+
_
+
THS4012
THS4012
VIN1
VIN2
R2
R1
R2
R(g)
R(g)
Rf
Rf
THS413x
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
Fully-differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting
amplifier holds true for gain calculations. One advantage of fully-differential amplifiers is that they offer twice as
much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input
signal of 1 VPP. If the output of the amplifier is 2 VPP, then it is not as practical to feed a 2-VPP signal into the
targeted ADC. Using a fully-differential amplifier enables the user to break down the output into two 1-VPP signals
with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer has been
able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully-differential amplifier. The
final result indicates twice as much dynamic range. Figure 39 illustrates the increase in dynamic range. The gain
factor should be considered in this scenario. The THS413x fully-differential amplifier offers an improved CMRR
and PSRR due to its symmetrical input and output. Furthermore, second-harmonic distortion is improved. Second
harmonics tend to cancel because of the symmetrical output.
Figure 39. Fully-Differential Amplifier With Two 1-VPP Signals
Similar to the standard inverting amplifier configuration, input impedance of a fully-differential amplifier is selected
by the input resistor, R(g). If input impedance is a constraint in design, the designer may choose to implement the
differential amplifier as an instrumentation amplifier. This configuration improves the input impedance of the
fully-differential amplifier. Figure 40 depicts the general format of instrumentation amplifiers.
The general transfer function for this circuit is:
(13)
Figure 40. Instrumentation Amplifier
Copyright ©2000–2011, Texas Instruments Incorporated 19
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the levels of high-frequency performance of the THS413x, follow proper printed-circuit board (PCB)
high-frequency design techniques. A general set of guidelines is given below. In addition, a THS413x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
•Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
•Proper power-supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
•Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins often lead to stability problems. Surface-mount packages soldered directly to
the printed-circuit board are the best implementation.
•Short trace runs/compact part placements—Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance
at the input of the amplifier.
•Surface-mount passive components—Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
20 Copyright ©2000–2011, Texas Instruments Incorporated
VCC
PD
VCC−
To Internal Bias
Circuitry Control
50 kΩ
200
1200
2200
100 k 1 M 10 M 100 M 1 G
Output Impedance −
f − Frequency − Hz
Ω
VCC = ±5 V
G = 1
Rf = 1 kΩ
PD = VCC−
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
POWER-DOWN MODE
The power-down mode is used when power saving is required. The power-down terminal (PD) found on the
THS413x is an active low terminal. If it is left as a no-connect terminal, the device always stays on due to an
internal 50 kΩresistor to VCC. The threshold voltage for this terminal is approximately 1.4 V above VCC–. This
means that if the PD terminal is 1.4 V above VCC–, the device is active. If the PD terminal is less than 1.4 V
above VCC–, the device is off. For example, if VCC–=–5 V, then the device is on when PD reaches –3.6 V, (–5 V
+ 1.4 V = –3.6 V). By the same calculation, the device is off below –3.6 V. It is recommended to pull the terminal
to VCC–in order to turn the device off. Figure 41 shows the simplified version of the power-down circuit. While in
the power-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is typically
greater than 1 MΩin the power-down state.
Figure 41. Simplified Power-Down Circuit
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very
low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still
connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of
the amplifier. An example of the closed loop output impedance is shown in Figure 42.
Figure 42. Output Impedance (In Power-Down) vs Frequency
Copyright ©2000–2011, Texas Instruments Incorporated 21
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
THS4130
THS4131
SLOS318H –MAY 2000–REVISED MAY 2011
www.ti.com
GENERAL PowerPAD DESIGN CONSIDERATIONS
The THS413x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted (see Figure 43a and Figure 43b). This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package (see Figure 43c). Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the previously awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, (PowerPAD Thermally-Enhanced Package SLMA002). This document
can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also
be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
A. The thermal pad (PowerPAD) is electrically isolated from all other pins and can be connected to any potential from
VCC–to VCC+. Typically, the thermal pad is connected to the ground plane becase this plane tends to physically be the
largest and is able to dissipate the most amount of heat.
Figure 43. Views of Thermally-Enhanced DGN Package
22 Copyright ©2000–2011, Texas Instruments Incorporated
THS4130
THS4131
www.ti.com
SLOS318H –MAY 2000–REVISED MAY 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (January 2010) to Revision H Page
•Changed footnote A in Figure 43 ........................................................................................................................................ 22
Changes from Revision F (January 2006) to Revision G Page
•Changed DGK package specifications in the Dissipation Rating table ................................................................................ 2
Copyright ©2000–2011, Texas Instruments Incorporated 23
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4130CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130CDGKR ACTIVE VSSOP DGK 8 TBD Call TI Call TI
THS4130CDGKRG4 ACTIVE VSSOP DGK 8 TBD Call TI Call TI
THS4130CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4130IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4130IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
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Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
THS4131IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
THS4131IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
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Addendum-Page 4
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
THS4130CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4130IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4130IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4130IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4131CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4131CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4131CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
THS4131IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4131IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
THS4131IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THS4130CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4130IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
THS4130IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4130IDR SOIC D 8 2500 367.0 367.0 35.0
THS4131CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
THS4131CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4131CDR SOIC D 8 2500 367.0 367.0 35.0
THS4131IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
THS4131IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
THS4131IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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