DMOS
100mA Low-Dropout Regulator
FEATURES
NEW DMOS TOPOLOGY:
Ultra Low Dropout Voltage:
60mV typ at 100mA
Output capacitor NOT required for stability
FAST TRANSIENT RESPONSE
VERY LOW NOISE:
23
µ
Vrms
HIGH ACCURACY: ±1.5% max
HIGH EFFICIENCY:
I
GND
= 500
µ
A at I
OUT
= 100mA
Not Enabled: IGND = 10nA
2.5V, 2.8V, 2.85V, 3.0V, 3.3V, 5.0V, AND
ADJUSTABLE OUTPUT VERSIONS
OTHER OUTPUT VOLTAGES AVAILABLE
UPON REQUEST
FOLDBACK CURRENT LIMIT
THERMAL PROTECTION
SMALL SURFACE-MOUNT PACKAGES:
SOT23-5 and SO-8
APPLICATIONS
PORTABLE COMMUNICATION DEVICES
BATTERY-POWERED EQUIPMENT
PERSONAL DIGITAL ASSISTANTS
MODEMS
BAR-CODE SCANNERS
BACKUP POWER SUPPLIES
DESCRIPTION
The REG101 is a family of low-noise, low-dropout linear
regulators with low ground pin current. Its new DMOS
topology provides significant improvement over previous
designs, including low dropout voltage (only 60mV typ at
full load), and better transient performance. In addition, no
output capacitor is required for stability, unlike conventional
low-dropout regulators that are difficult to compensate and
require expensive low ESR capacitors greater than 1µF.
Typical ground pin current is only 500µA (at IOUT = 100mA)
and drops to 10nA when not in enabled mode. Unlike regula-
tors with PNP pass devices, quiescent current remains rela-
tively constant over load variation and under dropout condi-
tions.
The REG101 has very low output noise (typically 23µVrms
for VOUT = 3.3V with CNR = 0.01µF), making it ideal for use
in portable communications equipment. Accuracy is main-
tained over temperature, line, and load variations. Key
parameters are tested over the specified temperature range
(–40°C to +85°C).
The REG101 is well protected—internal circuitry provides a
current limit that protects the load from damage. Thermal
protection circuitry keeps the chip from being damaged by
excessive temperature. The REG101 is available in the
SOT23-5 and the SO-8 packages.
REG101
(Fixed Voltage
Versions)
Enable
Gnd
0.1µFC
OUT(1)
+
+V
OUT
V
IN
NR
NR = Noise Reduction NOTE: (1) Optional.
REG101-A
Gnd
Enable
0.1µF
+C
OUT(1)
+
V
OUT
V
IN
R
2
R
1
Adj
REG101
REG101
SBVS026D – JULY 2001 – REVISED SEPTEMBER 2005
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000-2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
REG101
2SBVS026D
ABSOLUTE MAXIMUM RATINGS(1)
Supply Input Voltage, VIN .......................................................–0.3V to 12V
Enable Input Voltage, VEN....................................................... –0.3V to VIN
Feedback Voltage, VFB ........................................................ –0.3V to 6.0V
NR Pin Voltage, VNR .............................................................–0.3V to 6.0V
Output Short-Circuit Duration ......................................................Indefinite
Operating Temperature Range (TJ) ................................ –55°C to +125°C
Storage Temperature Range (TA) ................................... –65°C to +150°C
Lead Temperature
(soldering, 3s, SOT23-5, and SO-8)
..................... +240°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PIN CONFIGURATIONS
Top View
V
OUT(2)
V
OUT(2)
NR/Adjust
(1)
GND
V
IN(3)
V
IN(3)
NC
Enable
SO-8
1
2
3
4
8
7
6
5
(U Package)
V
IN
GND
Enable
V
OUT
NR/Adjust
(1)
SOT23-5
1
2
3
5
4
(N Package)
NOTE: (1) For REG101A-A: voltage setting resistor pin. All other models: noise reduction capacitor pin.
(2) Both pin 1 and pin 2 must be connected.
(3) Both pin 7 and pin 8 must be connected.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT VOUT(2)
REG101xx-
yyyy/zzz
XX is package designator.
YYYY is typical output voltage (5 = 5.0V, 2.85 = 2.85V, A = Adjustable).
ZZZ is package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
(2) Output voltages from 2.5V to 5.1V in 50mV increments are available; minimum order quantities apply. Contact factory for details and availability.
REG101 3
SBVS026D
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TJ = 40°C to +85°C.
At TJ = +25°C, VIN = VOUT + 1V (VOUT = 2.5V for REG101-A), VENABLE = 1.8V, IOUT = 2mA, CNR = 0.01µF, and COUT = 0.1µF(1), unless otherwise noted.
REG101NA
REG101UA
PARAMETER CONDITION MIN TYP MAX UNITS
OUTPUT VOLTAGE
Output Voltage VOUT
REG101-2.5 2.5 V
REG101-2.8 2.8 V
REG101-2.85 2.85 V
REG101-3.0 3.0 V
REG101-3.3 3.3 V
REG101-5 5V
REG101-A 2.5 5.5 V
Reference Voltage VREF 1.267 V
Adjust Pin Current IADJ 0.2 1 µA
Accuracy ±0.5 ±1.5 %
Over Temperature ±2.2 %
vs Temperature dVOUT/dT 50 ppm/°C
Includes Line and Load
IOUT = 2mA to 100mA, VIN = (VOUT + 0.4V) to 10V
±0.8 ±2.0 %
Over Temperature VIN = (VOUT + 0.6V) to 10V ±2.7 %
DC DROPOUT VOLTAGE(2) VDROP IOUT = 2mA 4 10 mV
For all models IOUT = 100mA 60 100 mV
Over Temperature IOUT = 100mA 130 mV
VOLTAGE NOISE Vnf = 10Hz to 100kHz
Without CNR CNR = 0, COUT = 0 23µVrms/V VOUT µVrms
With CNR (all fixed voltage models) CNR = 0.01µF, COUT = 10µF7µVrms/V VOUT µVrms
OUTPUT CURRENT
Current Limit(3) ICL 130 170 220 mA
Over Temperature 110 240 mA
Short-Circuit Current ISC 60 mA
RIPPLE REJECTION
f = 120Hz IOUT = 100mA 65 dB
ENABLE CONTROL
VENABLE High (output enabled) VENABLE 1.8 VIN V
VENABLE Low (output disabled) 0.2 0.5 V
IENABLE High (output enabled) IENABLE VENABLE = 1.8V to VIN, VIN = 1.8V to 6.5(4) 1 100 nA
IENABLE Low (output disabled) VENABLE = 0V to 0.5V 2 100 nA
Output Disable Time COUT = 1.0µF, RLOAD = 33200 µs
Output Enable Time COUT = 1.0µF, RLOAD = 331.5 ms
THERMAL SHUTDOWN
Junction Temperature
Shutdown 160 °C
Reset from Shutdown 140 °C
GROUND PIN CURRENT
Ground Pin Current IGND IOUT = 2mA 400 500 µA
IOUT = 100mA 500 650 µA
Enable Pin Low VENABLE 0.5V 0.01 0.2 µA
INPUT VOLTAGE VIN
Operating Input Voltage Range(5) 1.8 10 V
Specified Input Voltage Range VIN > 1.8V VOUT + 0.4 10 V
Over Temperature VIN > 1.8V VOUT + 0.6 10 V
TEMPERATURE RANGE
Specified Range TJ40 +85 °C
Operating Range TJ55 +125 °C
Storage Range TA65 +150 °C
Thermal Resistance
SOT23-5 Surface Mount
θ
JA Junction-to-Ambient 200 °C/W
SO-8 Surface Mount
θ
JA Junction-to-Ambient 150 °C/W
NOTES: (1) The REG101 does not require a minimum output capacitor for stability. However, transient response can be improved with proper capacitor selection.
(2) Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at VIN = VOUT + 1V at fixed
load.
(3) Current limit is the output current that produces a 10% change in output voltage from VIN = VOUT + 1V and IOUT = 2mA.
(4) For VENABLE > 6.5V, see typical characteristic IENABLE vs VENABLE.
(5) The REG101 no longer regulates when VIN < VOUT + VDROP (MAX). In drop-out, the impedance from VIN to VOUT is typically less than 1 at TJ = +25°C.
REG101
4SBVS026D
TYPICAL CHARACTERISTICS
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
2004010 30 6050 70 80 90 100
0.80
0.60
0.40
0.20
0.00
0.20
0.40
0.60
0.80
Output Voltage Change (%)
I
OUT
(mA)
OUTPUT VOLTAGE CHANGE vs I
OUT
(V
IN
= V
OUT
+ 1V, Output Voltage % Change
Referred to I
OUT
= 50mA at +25°C)
55°C
+125°C
+25°C
2550 0 7525 50 100 125
0.0%
0.1%
0.2%
0.3%
0.4%
Output Voltage Change (%)
Temperature (°C)
LOAD REGULATION vs TEMPERATURE
(V
IN
= V
OUT
+ 1V)
10mA < I
OUT
< 100mA
2mA < I
OUT
< 1000mA
50 25 0 25 50 75 100 125
0.10
0.08
0.06
0.04
0.02
0.00
0.02
0.04
0.06
0.08
0.10
Output Voltage Change (%)
Temperature (°C)
LINE REGULATION vs TEMPERATURE
I
OUT
= 100mA
(V
OUT
+ 1V) < V
IN
< 10V
(V
OUT
+ 0.4V) < V
IN
< 10V
0 10 100
100
80
60
40
20
0
DC Dropout Voltage (mV)
I
OUT
(mA)
DC DROPOUT VOLTAGE vs I
OUT
20 30 40 50 60 70 80 90
55°C
+125°C
+25°C
012345 867
20
15
10
5
0
5
10
15
20
Output Voltage Change (mV)
V
IN
V
OUT
(V)
LINE REGULATION
(Referred to V
IN
= V
OUT
+ 1V at I
OUT
= 50mA)
I
OUT
= 2mA
I
OUT
= 50mA
I
OUT
= 100mA
50 125100755025025
100
80
60
40
20
0
DC Dropout Voltage (mV)
Temperature (°C)
DC DROPOUT VOLTAGE vs TEMPERATURE
IOUT = 100mA
REG101 5
SBVS026D
TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
50 2525 0 50 75 100 125
0.50
0.40
0.30
0.20
0.10
0.00
0.10
0.20
0.30
0.40
0.50
Output Voltage Change (%)
Temperature (°C)
OUTPUT VOLTAGE vs TEMPERATURE
(Output Voltage % Change Referred
to IOUT = 50mA at +25°C)
IOUT = 2mA
IOUT = 100mA
IOUT = 50mA
50 2525 0 50 75 100 125
1µ
100n
10n
1n
100p
I
GND
(A)
Temperature (°C)
GROUND PIN CURRENT, NOT ENABLED
vs TEMPERATURE
V
ENABLE
= 0.5V
V
IN
= V
OUT
+ 1V
1.0
0.8
0.6
0.4
0.2
0.0
0.2
0.4
0.6
0.8
1.0
18
16
14
12
10
8
6
4
2
0
Percentage of Units (%)
Error (%)
OUTPUT VOLTAGE ACCURACY HISTOGRAM
0
10
20
30
40
50
60
70
80
90
100
5
15
25
35
45
55
65
75
85
95
30
25
20
15
10
5
0
Percentage of Units (%)
VOUT Drift (ppm/°C)
OUTPUT VOLTAGE DRIFT HISTOGRAM
0203010 5040 7060 9080 100
600
500
400
300
200
100
0
I
GND
(µA)
I
OUT
(mA)
GROUND PIN CURRENT vs I
OUT
V
OUT
= 2.5V
V
IN
= V
OUT
+ 1V
V
OUT
= 3.3V
V
OUT
= 5.0V
50 25 0 25 50 75 125100
600
575
550
525
500
475
450
425
400
IGND (µA)
Temperature (°C)
GROUND PIN CURRENT vs TEMPERATURE
IOUT = 100mA
VOUT = 5V
VOUT = 3.3V
VOUT = 2.5V
VIN = VOUT + 1V
REG101
6SBVS026D
TTYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
10 100 1k 10k 100k
10
1
0.1
0.01
eN (µV/Hz)
Frequency (Hz)
NOISE SPECTRAL DENSITY
IOUT = 100mA
CNR = 0µF
COUT = 1µF
COUT = 0µF
COUT = 10µF
10 100 1k 10k 100k
10
1
0.1
0.01
eN (µV/Hz)
Frequency (Hz)
NOISE SPECTRAL DENSITY
IOUT = 100mA
CNR = 0.01µF
COUT = 1µF
COUT = 0µF
COUT = 10µF
0 0.1 0.40.2 0.3 0.5 0.6 0.7 10.8 0.9
30
25
20
15
10
5
0
Ripple Rejection (dB)
VIN - VOUT (V)
RIPPLE REJECTION vs (VIN VOUT)
REG101-3.3
Frequency = 100kHz
COUT = 10µF
IOUT = 100mA
0.1 110
60
50
40
30
20
10
0
Noise Voltage (µVrms)
C
OUT
(µF)
RMS NOISE VOLTAGE vs C
OUT
REG101-5.0
REG101-3.3
REG101-2.5
C
NR
= 0.01µF
10Hz < BW < 100kHz
110 1k
100 10k
110
100
90
80
70
60
50
40
30
20
Noise Voltage (µVrms)
C
NR
(pF)
RMS NOISE VOLTAGE vs C
NR
C
NR
= 0µF
10Hz < BW < 100kHz
REG101-5.0
REG101-2.5
REG101-3.3
10 100 1k 10k 100k 10M1M
80
70
60
50
40
30
20
10
0
Ripple Rejection (dB)
Frequency (Hz)
RIPPLE REJECTION vs FREQUENCY
I
OUT
= 2mA
I
OUT
= 100mA
I
OUT
= 2mA
C
OUT
= 10µFI
OUT
= 100mA
C
OUT
= 10µF
C
OUT
= 0µF
REG101 7
SBVS026D
TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
50 25
ISC
125
180
160
140
120
100
80
60
40
IOUT (mA)
Temperature (°C)
CURRENT LIMIT vs TEMPERATURE
ICL
0 25 50 75 100
VIN = VOUT + 1V
LINE TRANSIENT RESPONSE
50µs/div
5.3V
50mV/div50mV/div
V
IN
V
OUT
V
OUT
4.3V
REG101-3.3
I
OUT
= 100mA
C
OUT
= 0
C
OUT
= 10µF
LOAD TRANSIENT RESPONSE
10µs/div
REG101-3.3
V
IN
= 4.3V
100mA
200mV/div200mV/div
I
OUT
V
OUT
V
OUT
10mA
C
OUT
= 0µF
C
OUT
= 10µF
TURN-OFF
200µs/div
1V/div1V/div
V
ENABLE
V
OUT
REG101-3.3
CNR = 0.01µF
COUT = 0µF
RLOAD = 1600
COUT = 10µF
RLOAD = 33
COUT = 1.0µF
RLOAD = 33
TURN-ON
250µs/div
1V/div1V/div
V
ENABLE
V
OUT
REG101-3.3
VIN = VOUT + 1V
CNR = 0.01µF
COUT = 0µF
RLOAD = 33
COUT = 10µF
RLOAD = 33
COUT = 0µF
RLOAD = 1600
04020 140 160
80 100 12060 180
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Output Voltage (V)
Output Current (mA)
FOLDBACK CURRENT LIMIT
ICL
ISC
REG101-3.3
REG101
8SBVS026D
TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
678910
10µ
1µ
100n
10n
1n
IENABLE (A)
VENABLE (V)
IENABLE vs VENABLE
T = +25°C
T = 55°C
T = +125°C
POWER UP/POWER DOWN
1s/div
500mV/div
VOUT = 3.0V
RLOAD = 30
VOUT
VIN
10 100 1k 10k 100k
80
70
60
50
40
30
20
Vn (µVrms)
CADJ (pF)
RMS NOISE VOLTAGE vs CADJ
REG101A
VOUT = 3.3V
COUT = 0.1µF
10Hz < frequency < 100kHz
50 25 0 25 50 75 100 125
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
IADJ (µA)
Temperature (°C)
ADJUST PIN CURRENT vs TEMPERATURE
200mV/div
200mV/div
10mA
V
OUT
C
OUT
= 0
REG101A
V
IN
= 4.3V
V
OUT
= 3.3V
C
OUT
= 10µFV
OUT
I
OUT
100mA
LOAD TRANSIENT-ADJUSTABLE VERSION
50mV/div
50mV/div
4.3V
V
OUT
C
OUT
= 0
REG101A
I
OUT
= 100mA
C
FB
= 0.01µF
V
OUT
= 3.3V
C
OUT
= 10µFV
OUT
V
IN
5.3V
LINE TRANSIENT-ADJUSTABLE VERSION
REG101 9
SBVS026D
BASIC OPERATION
The REG101 series of LDO (Low Drop-Out) linear regula-
tors offers a wide selection of fixed output voltage versions
and an adjustable output version. The REG101 belongs to a
family of new generation LDO regulators that utilize a
DMOS pass transistor to achieve ultra-low dropout perfor-
mance and freedom from output capacitor constraints. Ground
pin current remains under 650µA over all line, load, and
temperature conditions. All versions have thermal and over-
current protection, including foldback current limit.
The REG101 does not require an output capacitor for regu-
lator stability and is stable over most output currents and
with almost any value and type of output capacitor up to
10µF or more. For applications where the regulator output
current drops below several milliamps, stability can be
enhanced by: adding a 1k to 2k load resistor; using
capacitance values less than 10µF; or keeping the effective
series resistance greater than 0.05 including the capacitor’s
ESR and parasitic resistance in printed circuit board traces,
solder joints, and sockets.
Although an input capacitor is not required, it is good analog
design practice to connect a 0.1µF low ESR capacitor across
FIGURE 1. Fixed Voltage Nominal Circuit for REG101.
REG101
Enable
V
OUT
C
OUT
V
IN
0.1µF
C
NR
0.01µF
Gnd NR
In Out
Optional
the input supply voltage. This is recommended to improve
ripple rejection by reducing input voltage ripple.
Figure 1 shows the basic circuit connections for the fixed
voltage models. Figure 2 gives the connections for the
adjustable output version (REG101A) and example resistor
values for some commonly used output voltages. Values for
other voltages can be calculated from the equation shown in
Figure 2.
INTERNAL CURRENT LIMIT
The REG101 internal current limit has a typical value of
170mA. A foldback feature limits the short-circuit current to
a typical short-circuit value of 60mA. This helps to protect
the regulator from damage under all load conditions. A
characteristic of VOUT versus IOUT is given in Figure 3 and
in the Typical Characteristics section.
FIGURE 2. Adjustable Voltage Circuit for REG101A.
FIGURE 3. Foldback Current Limit of the REG101-3.3 at
25°C.
04020 140 160
80 100 12060 180
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Output Voltage (V)
Output Current (mA)
FOLDBACK CURRENT LIMIT
ICL
ICL
REG101-3.3
V
OUT
= (1 + R
1
/R
2
) 1.267V
Pin numbers for SOT23 package.
REG101
V
IN
0.1µF
2
1
Gnd
V
OUT
R
1
C
FB
0.01µFC
OUT
Adj
R
2
I
ADJ
Load
5
4
3
Enable
To reduce current through divider, increase resistor
values (see table at right).
As the impedance of the resistor divider increases,
I
ADJ
(~200nA) may introduce an error.
C
FB
improves noise and transient response.
Optional
V
OUT
(V) R
1
(W)
(1)
R
2
()
(1)
2.5 11.3k 11.5k
1.13k 1.15k
3.0 15.8k 11.5k
1.58k 1.15k
3.3 18.7k 11.5k
1.87k 1.15k
5.0 34.0k 11.5k
3.40k 1.15k
NOTE: (1) Resistors are standard 1% values.
EXAMPLE RESISTOR VALUES
REG101
10 SBVS026D
FIGURE 4. Block Diagram.
FIGURE 5. Output Noise versus Noise Reduction Capacitor.
ENABLE
The Enable pin is active HIGH and compatible with stan-
dard TTL-CMOS levels. Inputs below 0.5V (max) turn the
regulator off and all circuitry is disabled. Under this condi-
tion, ground pin current drops to approximately 10nA. When
a pull-up resistor is used, and operation down to VIN = 1.8V
is required, use values < 50k.
OUTPUT NOISE
A precision band-gap reference is used for the internal
reference voltage, VREF. This reference is the dominant
noise source within the REG101 and it generates approxi-
mately 29µVrms in the 10Hz to 100kHz bandwidth at the
reference output. The regulator control loop gains up the
reference noise, so that the noise voltage of the regulator is
approximately given by:
V = 29 Vrms R+R
R2 Vrms V
V
N1 2 OUT
REF
µµ
=29
Since the value of V
REF
is 1.267V, this relationship reduces to:
V=23Vrms
VV
N OUT
µ
Connecting a capacitor, CNR, from the Noise Reduction (NR)
pin to ground, as shown in Figure 4, forms a low-pass filter for
the voltage reference. For CNR = 10nF, the total noise in the
10Hz to 100kHz bandwidth is reduced by approximately a
factor of 2.8 for VO = 3.3V. This noise reduction effect is
shown in Figure 5 and as “RMS Noise Voltage vs CNR” in the
Typical Characteristics section.
Noise can be further reduced by carefully choosing an
output capacitor, COUT. Best overall noise performance is
achieved with very low (< 0.22µF) or very high (> 2.2µF)
values of COUT. See “RMS Noise Voltage vs COUT” in the
Typical Characteristics section.
The REG101 utilizes an internal charge pump to develop an
internal supply voltage sufficient to drive the gate of the
DMOS pass element above VIN. The charge-pump switch-
ing noise (nominal switching frequency = 2MHz) is not
measurable at the output of the regulator over most values of
COUT and IOUT.
The REG101 adjustable version does not have the noise-
reduction pin available, however, the adjust pin is the sum-
ming junction of the error amplifier. A capacitor, CFB,
connected from the output to the adjust pin will reduce both
the output noise and the peak error from a load transient. See
the typical characteristics for output noise performance.
Over Current
Over Temp
Protection
VREF
(1.26V)
Low Noise
Charge Pump
DMOS
Pass
Transistor
R1
NOTE: R1 and R2 are internal
on fixed output versions.
VOUT
Adj
(Adjustable
Versions)
R2
NR
(fixed output
versions only)
Enable
REG101
VIN
CNR
(optional)
110 1k
100 10k
110
100
90
80
70
60
50
40
30
20
Noise Voltage (µVrms)
CNR (pF)
RMS NOISE VOLTAGE vs CNR
CNR = 0µF
10Hz < BW < 100kHz
REG101-5.0
REG101-2.5
REG101-3.3
REG101 11
SBVS026D
FIGURE 6. Transient and DC Dropout.
DROP-OUT VOLTAGE
The REG101 uses an N-channel DMOS as the “pass”
element. When the input voltage is within a few tens of
millivolts of the output voltage, the DMOS device behaves
like a resistor. Therefore, for low values of VIN to VOUT, the
regulator’s input-to-output resistance is the RdsON of the
DMOS pass element (typically 600mΩ). For static (DC)
loads, the REG101 will typically maintain regulation down
to VIN to VOUT voltage drop of 60mV at full rated output
current. In Figure 6, the bottom line (DC dropout) shows the
minimum VIN to VOUT voltage drop required to prevent
drop-out under DC load conditions.
For large step changes in load current, the REG101 requires
a larger voltage drop across it to avoid degraded transient
response. The boundary of this “transient drop-out” region is
shown as the top line in Figure 6. Values of VIN to VOUT
voltage drop above this line insure normal transient re-
sponse.
In the transient dropout region between “DC” and “Tran-
sient”, transient response recovery time increases. The time
required to recover from a load transient is a function of both
the magnitude and rate of the step change in load current and
the available “headroom” VIN to VOUT voltage drop. Under
worst-case conditions (full-scale load change with VIN to
VOUT voltage drop close to DC dropout levels), the REG101
can take several hundred microseconds to re-enter the speci-
fied window of regulation.
TRANSIENT RESPONSE
The REG101 response to transient line and load conditions
improves at lower output voltages. The addition of a capaci-
tor (nominal value 0.47µF) from the output pin to ground
may improve the transient response. In the adjustable ver-
sion, the addition of a capacitor, CFB (nominal value 10nF),
from the output to the adjust pin will also improve the
transient response.
THERMAL PROTECTION
The REG101 has thermal shutdown circuitry that protects
the regulator from damage. The thermal protection circuitry
disables the output when the junction temperature reaches
approximately 160°C, allowing the device to cool. When the
junction temperature cools to approximately 140°C, the
output circuitry is again enabled. Depending on various
conditions, the thermal protection circuit may cycle on and
off. This limits the dissipation of the regulator, but may have
an undesirable effect on the load.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inadequate heat
sink. For reliable operation, junction temperature should be
limited to 125°C, maximum. To estimate the margin of
safety in a complete design (including heat sink), increase
the ambient temperature until the thermal protection is
triggered. Use worst-case loads and signal conditions. For
good reliability, thermal protection should trigger more than
35°C above the maximum expected ambient condition of
your application. This produces a worst-case junction tem-
perature of 125°C at the highest expected ambient tempera-
ture and worst-case load.
The internal protection circuitry of the REG101 has been
designed to protect against overload conditions. It was not
intended to replace proper heat sinking. Continuously run-
ning the REG101 into thermal shutdown will degrade reli-
ability.
140
120
100
80
60
40
20
0
Dropout Voltage (mV)
0 25 50 75 100 150125
IOUT (mA)
DC
Full Scale IOUT
Transient
REG101
12 SBVS026D
FIGURE 7. Maximum Power Dissipation versus Ambient Temperature for the Various Packages.
POWER DISSIPATION
The REG101 is available in two different package configu-
rations. The ability to remove heat from the die is different
for each package type and, therefore, presents different
considerations in the printed circuit board (PCB) layout. The
PCB area around the device that is free of other components
moves the heat from the device to the ambient air. While it
is difficult to impossible to quantify all of the variables in a
thermal design of this type, performance data for several
configurations are shown in Figure 7.
Power dissipation depends on input voltage, load condition,
and duty cycle. Power dissipation is equal to the product of
the average output current times the voltage across the
output element, VIN to VOUT voltage drop.
Power dissipation can be minimized by using the lowest
possible input voltage necessary to assure the required
output voltage.
REGULATOR MOUNTING
Solder pad footprint recommendations for the various
REG101 devices are presented in the Application Bulletin
AB-132, “Solder Pad Recommendations for Surface-Mount
Devices” (SBFA015), available from the Texas Instruments
web site (www.ti.com).
1.2
1.0
0.8
0.6
0.4
0.3
0
Power Dissipation (W)
0 25 50 75 100 125
Ambient Temperature (°C)
CONDITIONS
SOT23-5
SO-8
PACKAGE JA
SOT23-5 200°C/W
SO-8 150°C/W
θ
P=V V I
D IN OUT OUT(AVG)
()
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
REG101NA-2.5/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-2.5/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-2.5/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-2.5/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-2.8/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-2.8/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-2.85/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-2.85/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-2.85/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-3.3/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-3.3/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-3.3/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-3.3/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-3/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-3/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-3/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-3/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
REG101NA-5/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-5/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-5/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-5/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-A/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-A/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-A/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA-A/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101NA2.85/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
REG101UA-2.5 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-2.5G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-2.8 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-2.8/2K5 ACTIVE SOIC D 8 TBD Call TI Call TI
REG101UA-2.8/2K5G4 ACTIVE SOIC D 8 TBD Call TI Call TI
REG101UA-2.85 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-2.85G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-2.8G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-3 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-3.3 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
REG101UA-3.3/2K5 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-3.3/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-3.3G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-3G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-5 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-5/2K5 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-5/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-5G4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-A ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
REG101UA-AG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 4
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
REG101NA-2.5/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-2.5/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-2.8/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-2.85/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-2.85/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-3.3/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-3.3/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-3/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-3/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-5/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-5/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-A/250 SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101NA-A/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
REG101UA-3.3/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
REG101UA-5/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
REG101NA-2.5/250 SOT-23 DBV 5 250 203.0 203.0 35.0
REG101NA-2.5/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
REG101NA-2.8/250 SOT-23 DBV 5 250 203.0 203.0 35.0
REG101NA-2.85/250 SOT-23 DBV 5 250 203.0 203.0 35.0
REG101NA-2.85/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
REG101NA-3.3/250 SOT-23 DBV 5 250 203.0 203.0 35.0
REG101NA-3.3/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
REG101NA-3/250 SOT-23 DBV 5 250 203.0 203.0 35.0
REG101NA-3/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
REG101NA-5/250 SOT-23 DBV 5 250 203.0 203.0 35.0
REG101NA-5/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
REG101NA-A/250 SOT-23 DBV 5 250 203.0 203.0 35.0
REG101NA-A/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
REG101UA-3.3/2K5 SOIC D 8 2500 367.0 367.0 35.0
REG101UA-5/2K5 SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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