DATA SH EET
Product specification
Supersedes data of 2002 Mar 8 2003 Feb 28
INTEGRATED CIRCUITS
74LVC126A
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state
2003 Feb 28 2
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
FEATURES
•5 V tolerant inputs/outputs for interfacing with 5 V logic
•Wide supply voltage range from 1.2 to 3.6 V
•CMOS low power consumption
•Direct interface with TTL levels
•Inputs accept voltages up to 5.5 V
•Complies with JEDEC standard no. 8-1A
•ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74LVC126A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V.
The 74LVC126A consists of four non-inverting buffers/line
drivers with 3-state outputs (nY) which are controlled by
the output enable input (nOE). A LOW at nOE causes the
outputs to assume a high-impedance OFF-state.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The condition is VI= GND to VCC.
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay nA to nY CL= 50 pF; VCC = 3.3 V 2.4 ns
CIinput capacitance 4.0 pF
CPD power dissipation capacitance per gate VCC = 3.3 V;
notes 1 and 2 12 pF
TYPE NUMBER TEMPERATURE RANGE PACKAGE
PINS PACKAGE MATERIAL CODE
74LVC126AD −40 to +125 °C 14 SO14 plastic SOT108-1
74LVC126ADB −40 to +125 °C 14 SSOP14 plastic SOT337-1
74LVC126APW −40 to +125 °C 14 TSSOP14 plastic SOT402-1
74LVC126ABQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1
2003 Feb 28 3
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
PINNING
INPUT OUTPUT
nOE nA nY
HLL
HHH
LXZ
PIN SYMBOL DESCRIPTION
1 1OE data enable input (active HIGH)
2 1A data input
3 1Y data output
4 2OE data enable input (active HIGH)
5 2A data input
6 2Y data output
7 GND ground (0 V)
8 3Y data output
9 3A data input
10 3OE data enable input (active HIGH)
11 4Y data output
12 4A data input
13 4OE data enable input (active HIGH)
14 VCC supply voltage
2003 Feb 28 4
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
MNA233
126
1
2
3
4
5
6
78
14
13
12
11
10
9
1OE
1A
1Y
2OE
2A
2Y
GND 3Y
3A
3OE
4Y
4A
4OE
VCC
Fig.1 Pin configuration SO14 and (T)SSOP14.
handbook, halfpage
114
1OE VCC
7
2
3
4
5
6
1A
1Y
2OE
2A
2Y
13
12
11
10
9
4OE
4A
4Y
3OE
3A
8
GND 3Y
GND
(1)
Top view
MCE197
Fig.2 Pin configuration DHVQFN14.
*Thediesubstrateisattachedtothispadusingconductivedieattach
material. It can not be used as a supply pin or input.
handbook, halfpage
MNA235
1A 1Y
2
1
3
1OE
2A 2Y
5
4
6
2OE
3A 3Y
9
10
8
3OE
4A 4Y
12
13
11
4OE
Fig.3 Logic symbol.
handbook, halfpage
MNA236
1EN1
13
2
46
5
10 8
9
13 11
12
Fig.4 Logic symbol (IEEE/IEC).
2003 Feb 28 5
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
handbook, halfpage
MNA234
nOE
nA nY
Fig.5 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage for maximum speed performance 2.7 3.6 V
for low voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage output HIGH or LOW state 0 VCC V
output 3-state 0 5.5 V
Tamb operating ambient temperature −40 +125 °C
tr,t
finput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI<0 −−50 mA
VIinput voltage note 1 −0.5 +6.5 V
IOK output diode current VO>V
CC or VO<0 −±50 mA
VOoutput voltage output HIGH or LOW state; note 1 −0.5 VCC + 0.5 V
output 3-state; note 1 −0.5 +6.5 V
IOoutput source or sink current VO= 0 to VCC −±50 mA
IGND, ICC VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation per package Tamb =−40 to +125 °C; note 2 −500 mW
2003 Feb 28 6
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground=0V).
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
Tamb =−40 to +85 °C
VIH HIGH-level input
voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input
voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.2 VCC −V
IO=−12 mA 2.7 VCC −0.5 −−V
I
O
=−18 mA 3.0 VCC −0.6 −−V
I
O
=−24 mA 3.0 VCC −0.8 −−V
V
OL LOW-level output
voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −GND 0.2 V
IO= 12 mA 2.7 −−0.4 V
IO= 24 mA 3.0 −−0.55 V
ILI input leakage
current VI= 5.5 Vor GND 3.6 −±0.1 ±5µA
IOZ 3-state output
OFF-state current VI=V
IH or VIL;
VO= 5.5 Vor GND;
note 2
3.6 −±0.1 ±5µA
Ioff power off leakage
supply VIor VO= 5.5 V 0 −±0.1 ±10 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 3.6 −0.1 10 µA
∆ICC additional quiescent
supply current per
input pin
VI=VCC −0.6 V;
IO=0 2.7 to 3.6 −5 500 µA
2003 Feb 28 7
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
Notes
1. All typical values are measured at Tamb =25°C.
2. For I/O ports the parameter IOZ includes the input leakage current.
Tamb =−40 to +125 °C
VIH HIGH-level input
voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input
voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.3 −−V
I
O
=−12 mA 2.7 VCC −0.65 −−V
I
O
=−18 mA 3.0 VCC −0.75 −−V
I
O
=−24 mA 3.0 VCC −1−−V
V
OL LOW-level output
voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.3 V
IO= 12 mA 2.7 −−0.6 V
IO= 24 mA 3.0 −−0.8 V
ILI input leakage
current VI= 5.5 Vor GND 3.6 −−±20 µA
IOZ 3-state output
OFF-state current VI=V
IH or VIL;
VO= 5.5 Vor GND;
note 2
3.6 −−±20 µA
Ioff power off leakage
supply VIor VO= 5.5 V 0.0 −−±20 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 3.6 −−40 µA
∆ICC additional quiescent
supply current per
input pin
VI=VCC −0.6 V;
IO=0 2.7 to 3.6 −−5000 µA
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
OTHER VCC (V)
2003 Feb 28 8
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
AC CHARACTERISTICS
GND = 0 V; tr=t
f≤2.5 ns.
Notes
1. Typical values are measured at Tamb =25°C.
2. Typical values are measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNIT
WAVEFORMS VCC (V)
Tamb =−40 to +85 °C
tPHL/tPLH propagation delay nA to nY see Figs 6 and 8 1.2 −11 −ns
2.7 1.5 2.7 5.2 ns
3.0 to 3.6 1.0 2.4(2) 4.7 ns
tPZH/tPZL 3-state output enable time
nOE to nY see Figs 7 and 8 1.2 −15 −ns
2.7 1.5 3.1 6.3 ns
3.0 to 3.6 1.0 2.9(2) 5.7 ns
tPHZ/tPLZ 3-state output disable time
nOE to nY see Figs 7 and 8 1.2 −8.0 −ns
2.7 1.5 3.8 6.7 ns
3.0 to 3.6 1.3 2.8(2) 6.0 ns
tsk(0) skew note 3 3.0 to 3.6 −−1.0 ns
Tamb =−40 to +125 °C
tPHL/tPLH propagation delay nA to nY see Figs 6 and 8 1.2 −−−ns
2.7 1.5 −6.5 ns
3.0 to 3.6 1.0 −6.0 ns
tPZH/tPZL 3-state output enable time
nOE to nY see Figs 7 and 8 1.2 −−−ns
2.7 1.5 −8.0 ns
3.0 to 3.6 1.0 −7.5 ns
tPHZ/tPLZ 3-state output disable time
nOE to nY see Figs 7 and 8 1.2 −−−ns
2.7 1.5 −8.5 ns
3.0 to 3.6 1.3 −7.5 ns
tsk(0) skew note 3 3.0 to 3.6 −−1.5 ns
2003 Feb 28 9
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
AC WAVEFORMS
handbook, halfpage
MNA237
tPHL tPLH
VM
VM
nA input
nY output
GND
VI
VOH
VOL
Fig.6 The input nA to output nY propagation delays.
VM= 1.5 V at VCC ≥2.7 V;
VM= 0.5VCC at VCC < 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.
handbook, full pagewidth
MNA684
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VCC
VM
VOL
VOH
GND
GND
tPZL
tPZH
VM
VM
Fig.7 3-state enable and disable times.
VM= 1.5 V at VCC ≥2.7 V;
VM= 0.5VCC at VCC < 2.7 V;
VX=V
OL + 0.3 V at VCC ≥2.7 V;
VX=V
OL + 0.1 V at VCC < 2.7 V;
VY=V
OH +0.3VatV
CC ≥2.7 V;
VY=V
OH +0.1VatV
CC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load.
2003 Feb 28 10
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
handbook, full pagewidth
open
GND
50 pF
2 × VCC
VCC
VIVO
MNA368
D.U.T.
CL
RT
RL
500 Ω
RL
500 Ω
PULSE
GENERATOR
S1
Fig.8 Load circuitry for switching times.
Definitions for test circuits:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
SWITCH POSITION
TEST S1
tPLH/tPHL open
tPLZ/tPZL 2×VCC
tPHZ/tPZH GND
VCC VI
<2.7 V VCC
2.7 to 3.6 V 2.7 V
2003 Feb 28 11
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
PACKAGE OUTLINES
UNIT A
max. A
1
A
2
A
3
b
p
cD
(1)
E
(1) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w
M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
2003 Feb 28 12
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
2003 Feb 28 13
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
w
M
b
p
D
Z
e
0.25
17
14 8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
2003 Feb 28 14
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
2003 Feb 28 15
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesaverybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,butitisnotsuitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuit board byscreenprinting, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferably be kept:
•below 220 °C for all the BGA packages and packages
with a thickness 2.5mm and packages with a thickness
<2.5 mm and a volume ≥350 mm3 so called thick/large
packages
•below 235 °C for packages with a thickness <2.5 mm
and a volume <350 mm3 so called small/thin packages.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2003 Feb 28 16
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formoredetailed information on theBGApackages refer to the
“(LF)BGAApplication Note
”(AN01026);order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO, VSSOP not recommended(6) suitable
2003 Feb 28 17
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratanyotherconditions above those given inthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythat such applicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorselling theseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2003 Feb 28 18
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
NOTES
2003 Feb 28 19
Philips Semiconductors Product specification
Quad buffer/line driver with 5 Volt
tolerant input/outputs; 3-state 74LVC126A
NOTES
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands 613508/05/pp20 Date of release: 2003 Feb 28 Document order number: 9397 750 10533
