CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
16 K/8 K/4 K × 16 MoBL® ADM
Asynchronous Dual-Port Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-08090 Rev. *G Revised May 2, 2011
16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM
Features
■True dual-ported memory block that allow simultaneous
independent access
❐One port with dedicated time multiplexed address and data
(ADM) interface
❐One port configurable to standard SRAM or time multiplexed
address and data interface
■16 K/8 K/4 K × 16 memory configuration
■High speed access
❐65 ns or 90 ns ADM interface
❐40 ns or 60 ns standard SRAM interface
■Fully asynchronous operation
■Port independent 1.8 V, 2.5 V, and 3.0 V IOs
■Ultra low operating power
❐Active: ICC = 15 mA (typical) at 90 ns
❐Active: ICC = 25 mA (typical) at 65 ns
❐Standby: ISB3 = 2 A (typical)
■Port independent power down
■On-chip arbitration logic
■Mailbox interrupt for port to port communication
■Input Read and Output Drive registers
■Upper byte and lower byte control
■Small package: 6 × 6 mm, 100-ball Pb-free BGA
■Industrial temperature range
Notes
1. A13-A0 for CYDMX256A16 and CYDMX256B16; A12-A0 for CYDMX128A16 and CYDMX128B16; and A11-A0 for CYDMX064A16 and CYDMX064B16.
2. IRR1 and IRR2 not available for CYDMX256A16 and CYDMX256B16.
Block Diagram
Mux'ed
Address /
Data
I/O Control
Address
Decode
Mux'ed
Address/
Data
I/O Control
I/OL15-I/OL8
I/OL7-I/OL0
Address
Decode
I/OR15-I/OR8
A13-A0 [note 1]
Control Logic
CS#L
OE#L
WE#L
BUSY#L
INT#L
BUSY#R
INT#R
CS#R
OE#R
WE#R
Dual Ported
Memory Array
16k/8k/4k x 16
ADV#L
UB#L
LB#L
DataL<15..0> DataR<15..0>
AddrL<13..0> AddrR<13..0> ADV#R
UB#R
LB#R
MSEL
I/OR7-I/OR0
IRR/ODR
SFEN# IRR1-IRR0 [note 2]
ODR4-ODR0
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 2 of 25
Contents
Pin Configurations ...........................................................3
Pin Definitions ..................................................................4
Functional Description .....................................................4
Power Supply ..............................................................4
ADM Interface Read or Write Operation ..................... 4
Standard SRAM Interface Read or Write Operation ... 5
Byte Select Operation .................................................5
Chip Select Operation .................................................5
Output Enable Operation ............................................. 5
Mailbox Interrupts ........................................................ 5
Arbitration Logic .......................................................... 5
Input Read Register ....................................................5
Output Drive Register ..................................................5
Architecture ...................................................................... 6
Maximum Ratings .............................................................8
Operating Range ............................................................... 8
Electrical Characteristics for VCC = 1.8 V ......................8
Electrical Characteristics for VCC = 2.5 V .................... 10
Electrical Characteristics for 3.0 V ............................... 11
Capacitance .................................................................... 11
Switching Characteristics for VCC = 1.8 V ................... 12
Switching Waveforms .................................................... 15
Ordering Information ...................................................... 21
Ordering Code Definitions ......................................... 21
Package Diagram ............................................................ 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC Solutions ......................................................... 25
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 3 of 25
Notes
3. This pin is A13 for CYDMX256A16 and CYDMX256B16.
4. This pin is DNU for CYDMX064A16 and CYDMX064B16.
5. This pin is DNU for CYDMX256A16 and CYDMX256B16.
6. DNU pins are “do not use” pins. No trace or power component can be connected to these pins.
Pin Configurations
Figure 1. 100-ball 0.5 mm pitch BGA (Top View)
.
12345678910
AA5 A8 A11 UB#R VSS ADV#R I/OR15 I/OR12 I/OR10 VSS A
BA3 A4 A7 A9 CE#R WE#R OE#R VDDIOR I/OR9 I/OR6 B
CA0 A1 A2 A6 LB#R IRR1[3] I/OR14 I/OR11 I/OR7 VSS C
DODR4 ODR2 BUSY#R INT#R A10 A12[4] I/OR13 I/OR8 I/OR5 I/O2R D
EVSS DNU ODR3 INT#L VSS VSS I/OR4 VDDIOR I/OR1 VSS E
FSFEN# ODR1 BUSY#L DNU VCC VSS I/OR3 I/OR0 I/OL15 VDDIOL F
GODR0 DNU DNU DNU OE#L I/OL3 I/OL11 I/OL12 I/OL14 I/OL13 G
HDNU DNU DNU LB#L CE#L I/OL1 VDDIOL MSEL DNU I/OL10 H
JDNU DNU DNU IRR0[5] VCC VSS I/OL4 I/OL6 I/OL8 I/OL9 J
KDNU DNU DNU UB#L ADV#L WE#L I/OL0 I/OL2 I/OL5 I/OL7 K
12345678910
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 4 of 25
Functional Description
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 are low
power CMOS 16K/8K/4K × 16 dual-port static RAMs. The two
ports are: one dedicated time multiplexed address and data
(ADM) interface and one configurable standard SRAM or ADM
interface. The two ports permit independent, asynchronous read
and write access to any memory locations. Each port has
independent control pins: Chip Select (CS#), Write Enable
(WE#), and Output Enable (OE#). Two output flags are provided
on each port (BUSY# and INT#). BUSY# flag is triggered when
the port is trying to access the same memory location currently
being accessed by the other port. The Interrupt flag (INT#)
permits communication between ports or systems by means of
a mailbox. Power down feature is controlled independently on
each port by a Chip Select (CS#) pin.
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 are
available in 100-ball 0.5-mm pitch Ball Grid Array (BGA)
packages. Application areas include interprocessor and
multiprocessor designs, communications status buffering, and
dual-port video and graphics memory.
Power Supply
The core voltage (VCC) can be 1.8 V, 2.5 V, or 3.0 V, as long as
it is lower than or equal to the IO voltage. Each port operates on
independent IO voltages. This is determined by what is
connected to the VDDIOL and VDDIOR pins. The supported IO
standards are 1.8 V and 2.5 V LVCMOS and 3.0 V LVTTL.
ADM Interface Read or Write Operation
This description is applicable to both the left ADM port and right
port configured as an ADM port.
Three control signals, ADV#, WE#, and CS# are used to perform
the read and write operations. Address signals are first applied
to the IO bus along with CS# LOW. The addresses are loaded
from the IO bus in response to the rising edge of the Address
Latch Enable (ADV#) signal. It is necessary to meet the setup
(tAVDS) and hold (tAVDH) times given in the AC specifications with
valid address information to properly latch the addresses.
After the address signals are latched in, a read operation is
issued when WE# stays HIGH. The IO bus becomes High Z
when the address signals meet tAVDH. The read data is driven on
the IO bus tOE after the OE# is asserted LOW, and held until
tHZOE or tHZCS after the rising edge of OE# or CS#, whichever
comes first.
A write operation is issued when WE# is asserted LOW. The
write data is applied to the IO bus right after address meets the
hold time (tAVDH). And write data is written with the rising edge
of either WE# or CS#, whichever comes first, and meets data
setup (tSD) and hold (tHD) times.
Pin Definitions
Left Port Right Port Description
CS#L CS#R Chip Select
WE#L WE#R Read/Write Enable
OE#L OE#R Output Enable
A0–A13 Address (A0–A11 for 4K device; A0–A12 for 8K device; A0–A13 for 16K device)
MSEL Right Port Interface Mode Select (0: Standard SRAM; 1: Address/Data Mux)
IOL0–IOL15 IOR0–IOR15 Address/Data Bus Input/Output
ADV#L ADV#R Address Latch Enable; ADV#R only use when R-port is in ADM mode
UB#L UB#R Upper Byte Select (IO8–IO15)
LB#L LB#R Lower Byte Select (IO0–IO7)
INT#L INT#R Interrupt Flag
BUSY#L BUSY#R Busy Flag
SFEN# Special Function Enable Signal
IRR0-IRR1 Input Signals for Input Read Registers for CYDMX128A16, CYDMX128B16,
CYDMX064A16 and CYDMX064B16;
IRR0 is DNU and IRR1 is A13 for CYDMX256A16 and CYDMX256B16.
ODR0-ODR4 Output Signals for Output Drive Registers; These are open drained outputs.
VCC Core Power Supply
GND Ground
VDDIOL Left Port IO Power Supply
VDDIOR Right Port IO Power Supply
DNU No Connect; Do not connect trace or power component to these pins.
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 5 of 25
Standard SRAM Interface Read or Write Operation
This description is applicable to the right access port configured
as standard SRAM port. Read and write operations with
standard SRAM interface configuration is the same as the ADM
port except addresses are presented on the A bus. Operation is
controlled by CS#, OE#, and WE#. A read operation is issued
when WE# is asserted HIGH. A write operation is issued when
WE# is asserted LOW. The IO bus is the destination for read data
and the source for write data when the read operation is issued.
However, write data must be driven to IO when the write
operation is issued.
Byte Select Operation
The fundamental word size is 16 bits. Each word is broken up
into two 8-bit bytes. Each port has two active LOW byte enables:
UB# and LB#. Activating or deactivating the byte enables alters
the result of read and write operations to the port. During a write,
byte enable asserted HIGH inhibits the corresponding byte to be
updated in the addressed memory location. During a read, both
byte enables are inputs to the asynchronous output enable
control logic. When a byte enable is asserted HIGH, the
corresponding data byte is tri-stated. Subsequently, when the
byte enable is asserted LOW, the corresponding data byte is
driven with the read data.
Chip Select Operation
Each port has one active LOW chip select signal, CS#. CS# must
be asserted LOW for the port to be considered active. To issue
a valid read or write operation, the chip select input must be
asserted LOW throughout the read or write cycle. When CS# is
deasserted HIGH during a write, if tWRL, tSD, and tHD are not met,
the contents of the addressed location is not altered.
An automatic power down feature controlled by deactivating the
chip select (CS# HIGH) permits the on-chip circuitry of each port
to enter a very low standby power mode.
Output Enable Operation
Each port has one output enable signal, OE#. When OE# is
asserted HIGH, IO bus is tri-stated after tHZOE. When OE# is
asserted LOW, control of the IO bus is assumed by the
asynchronous output enable logic (the logic is controlled by
inputs WE#, CS#, UB#, and LB#).
Mailbox Interrupts
The upper two memory locations are used for message passing.
The highest memory location (0xFFF for CYDMX064A16 and
CYDMX064B16, 0x1FFF for CYDMX128A16 and CYDMX128B16,
and 0x3FFF for CYDMX256A16 and CYDMX256B16) is the
mailbox for the right port. The second highest memory location
(0xFFE for CYDMX064A16 and CYDMX064B16, 0x1FFE for
CYDMX128A16 and CYDMX128B16, and 0x3FFE for
CYDMX256A16 and CYDMX256B16) is the mailbox for the left
port. When one port writes to the opposite port’s mailbox, an
interrupt signal is generated to the opposite port. The interrupt
resets when the owner reads the contents of its own mailbox.
The message written to the mailbox is user defined.
Each port reads the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and resetting the interrupt to it.
On power up, both interrupts are set by default. An initialization
program must be run to reset the interrupts.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
Arbitration Logic
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 provide
on-chip arbitration to resolve simultaneous memory location
access (collision). If both ports’ CS# signals are asserted and an
address match occurs within each other, the busy logic deter-
mines which port has access. If tPS is violated, one of the two
ports gains permission to the location, but it is not predictable
which port gets the permission. BUSY# is asserted tBLA after an
address match or tBLC after CS# is taken LOW.
Input Read Register
The Input Read Register (IRR) feature is available only for
CYDMX128A16, CYDMX128B16, CYDMX064A16, and
CYDMX064B16 devices. When SFEN# = VIL, the IRR captures
the status of two external devices connected to the Input Read
pins (IRR0 and IRR1) to address location 0x0000. Address
0x0000 is not available for standard memory accesses when
SFEN# = VIL. When SFEN# = VIH, address 0x0000 is available
for normal memory accesses. Either port accesses the contents
of IRR with normal read operation from address 0x0000. During
reads from the IRR, IO<1:0> are valid bits and IO<15:2> are
don’t care. The IRR inputs are 1.8 V and 2.5 V LVCMOS or 3.0 V
LVTTL, depending on the core voltage supply (VCC).
Output Drive Register
The Output Drive Register (ODR) determines the state of up to
five external binary state devices by providing a path to VSS for
the external circuit. These outputs are open drain. The five
external devices operates at different voltages
(1.5 V VDDIO 3.5 V) but the combined current cannot exceed
40 mA (8 mA maximum for each external device). The status of
the ODR bits are set using standard write accesses from either
port to address 0x0001 with a ‘1’ corresponding to on and ‘0’
corresponding to off. The status of the ODR bits are read with a
normal read access to address 0x0001. When SFEN# = VIL, the
ODR is active and address 0x0001 is not available for memory
accesses. When SFEN# = VIH, the ODR is inactive and address
0x0001 is used for standard accesses. During reads and writes
to ODR, IO<4:0> are valid and IO<15:5> are don’t care.
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 6 of 25
Architecture
The CYDMX256A16, CYDMX128A16, CYDMX064A16,
CYDMX256B16, CYDMX128B16, and CYDMX064B16 consist
of an array of 16K, 8K, and 4K words of 16 dual-ported SRAM
cells, IO, address lines, and control signals (CS#, ADV#, OE#,
and WE#). Between the two access ports, one is a dedicated
time multiplexed address and data interface; the other is a pin
selectable port to either standard SRAM or time multiplexed
address and data interface. Independent control signals for each
port permit simultaneous access to any location in memory. To
handle the situation of writing and reading to the same location,
a BUSY# pin is provided on each port. For port to port
communication, an Interrupt (INT#) pin is also available on each
port.
Table 1. ADM Interface Read/Write with Byte Select Operations
ADV# CS# WE# OE# UB# LB# IO0 - IO15 Mode
X H X X X X High Z Deselected or power down
X X X H X X High Z Output disable
XXXXHHHigh Z Upper and lower byte
deselected
Pulse L H L L L Data Out (IO0-IO15) Read upper and lower bytes
Pulse L H L H L Data Out (IO0-IO7)
High Z (IO8-IO15)
Read lower byte only
Pulse L H L L H High Z (IO0-IO7)
Data Out (IO8-IO15)
Read upper byte only
Pulse L L X L L Data In (IO0-IO15) Write upper and lower bytes
Pulse L L X H L Data In (IO0-IO7)
High Z (IO8-IO15)
Write lower byte only
Pulse L L X L H High Z (IO0-IO7)
Data In (IO8-IO15)
Write upper byte only
Table 2. Standard SRAM Interface Read/Write with Byte Select Operations
CS# WE# OE# UB# LB# IO0-IO15 Mode
H X X X X High Z Deselected or power down
X X H X X High Z Output disable
X X X H H High Z Upper and lower byte deselected
L H L L L Data Out (IO0-IO15) Read upper and lower bytes
L H L H L Data Out (IO0-IO7)
High Z (IO8-IO15)
Read lower byte only
L H L L H High Z (IO0-IO7)
Data Out (IO8-IO15)
Read upper byte only
L L X L L Data In (IO0-IO15) Write upper and lower bytes
L L X H L Data In (IO0-IO7)
High Z (IO8-IO15)
Write lower byte only
L L X L H High Z (IO0-IO7)
Data In (IO8-IO15)
Write upper byte only
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 7 of 25
Table 3. Interrupt Operation Example (Assumes BUSY#L = BUSY#R = HIGH)
Function Left Port Right Port
WE#L CS#L OE#L AddressL INT#L WE#R CS#R OE#R AddressR INT#R
Set Right INT#R Flag L L X 0x3FFF[7] XXXX X L
Reset Right INT#R Flag X X X X X X L L 0x3FFF[7] H
Set Left INT#L Flag X X X X L L L X 0x3FFE[8] X
Reset Left INT#L Flag X L L 0x3FFE[8] HXXX X X
Table 4. Arbitration Winning Port
CS#L CS#R Address Match
Left/Right Port BUSY#L BUSY#R Function
X X No Match H H Normal
HX Match HH Normal
XH Match HH Normal
L L Match See Note[9] See Note[9] Write Inhibit[10]
Table 5. Input Read Register Operation[11]
SFEN# CS# WE# OE# UB# LB# ADDR IO0–IO1IO2–IO15 Mode
HLHLLLx0000-MaxVALID
[12] VALID[12] Standard Memory Access
L L H L X L x0000 VALID[13] X IRR Read
Table 6. Output Drive Register[15]
SFEN# CS# WE# OE# UB# LB# ADDR IO0–IO4IO5–IO15 Mode
HLHX
[16] L[12] L[12] x0000-Max VALID[12] VALID[12] Standard Memory Access
LLLXXLx0001VALID
[13] X ODR Write[17]
LLHLXLx0001VALID
[13] X ODR Read
Notes
7. 0x3FFF for CYDMX256A16 and CYDMX256B16, 0x1FFF for CYDMX128A16 and CYDMX128B16, 0xFFF for CYDMX064A16 and CYDMX064B16.
8. 0x3FFE for CYDMX256A16 and CYDMX256B16, 0x1FFE for CYDMX128A16 and CYDMX128B16, 0xFFE for CYDMX064A16 and CYDMX064B16.
9. If it meets tPS, "L" if the CS# and address of the opposite port become stable BEFORE the current port; "H" if the CS# and address of the opposite port become
stable AFTER the current port. If tPS is not met, either BUSY#L or BUSY#R results “L”. BUSY#L and BUSY#R cannot be “L” simultaneously.
10. Write operations to the left port are internally ignored when BUSY#L is driving LOW regardless of actual logic level on the pin; Write operations to the right port are
internally ignored when BUSY#R is driving LOW regardless of actual logic level on the pin.
11. SFEN# = VIL for IRR reads.
12. UB# or LB# = VIL. If LB# = VIL, then IO<7:0> are valid. If UB# = VIL then IO<15:8> are valid.
13. LB# must be active (LB# = VIL) for these bits to be valid.
14. SFEN# active when either CS#L = VIL or CS#R = VIL. It is inactive when CS#L = CS#R = VIH.
15. SFEN# = VIL for ODR reads and writes.
16. Output enable must be low (OE# = VIL) during reads for valid data to be output.
17. During ODR writes data is also written to the memory.
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 8 of 25
Maximum Ratings
Exceeding maximum ratings[18] may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................ –65 °C to +150 °C
Ambient Temperature with
Power Applied .......................................... –55 °C to +125 °C
Supply Voltage to Ground Potential..............–0.5 V to +3.3 V
DC Voltage Applied to
Outputs in High Z State ....................... –0.5 V to VCC + 0.5 V
DC Input Voltage[19]............................. –0.5 V to VCC + 0.5 V
Output Current into Outputs (LOW)............................. 90 mA
Static Discharge Voltage......................................... > 2000 V
Latch up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40 °C to +85 °C 1.8 V ± 100 mV
2.5 V ± 100 mV
3.0 V ± 300 mV
Electrical Characteristics for VCC = 1.8 V
Over the Operating Range
Parameter
Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
Unit
–65 –65 –90
P1 IO
Voltage
P2 IO
Voltage Min Typ Max Min Typ Max Min Typ Max
VOH Output HIGH Voltage
(IOH = –100 A)
1.8 V (any port) VDDIO
– 0.2
––V
DDIO
– 0.2
––V
DDIO
– 0.2
––V
Output HIGH Voltage (IOH = –2 mA) 2.5 V (any port) 2.0 – – 2.0 – – 2.0 – – V
Output HIGH Voltage (IOH = –2 mA) 3.0 V (any port) 2.1 – – 2.1 – – 2.1 – – V
VOL Output LOW Voltage (IOL = 100 A1.8 V (any port) – – 0.2 – – 0.2 – – 0.2 V
Output HIGH Voltage (IOH = 2 mA) 2.5 V (any port) – – 0.4 – – 0.4 – – 0.4 V
Output HIGH Voltage (IOH = 2 mA) 3.0 V (any port) – – 0.4 – – 0.4 – – 0.4 V
VOL
ODR
ODR Output LOW Voltage
(IOL = 8 mA
1.8 V (any port) – – 0.2 – – 0.2 – – 0.2 V
2.5 V (any port) – – 0.2 – – 0.2 – – 0.2 V
3.0 V (any port) – – 0.2 – – 0.2 – – 0.2 V
VIH Input HIGH Voltage 1.8 V (any port) 1.2 – VDDIO
+ 0.2
1.2 – VDDIO
+ 0.2
1.2 – VDDIO
+ 0.2
V
2.5 V (any port) 1.7 – VDDIO
+ 0.3
1.7 – VDDIO
+ 0.3
1.7 – VDDIO
+ 0.3
V
3.0 V (any port) 2.0 – VDDIO
+ 0.2
2.0 – VDDIO
+ 0.2
2.0 – VDDIO
+ 0.2
V
VIL Input LOW Voltage 1.8 V (any port) –0.2 – 0.4 –0.2 – 0.4 –0.2 – 0.4 V
2.5 V (any port) –0.3 – 0.6 –0.3 – 0.6 –0.3 – 0.6 V
3.0 V (any port) –0.2 – 0.7 –0.2 – 0.7 –0.2 – 0.7 V
IOZ Output Leakage Current 1.8 V 1.8 V –1 – 1 –1 – 1 –1 – 1 A
2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
ICEX
ODR
ODR Output Leakage Current.
VOUT = VDDIO
1.8 V 1.8 V –1 – 1 –1 – 1 –1 – 1 A
2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 9 of 25
IIX Input Leakage Current 1.8 V 1.8 V –1 – 1 –1 – 1 –1 – 1 A
2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
ICC Operating Current
(VCC = Max, IOUT = 0 mA)
Outputs Disabled
Ind. 1.8 V 1.8 V – 25 40 – 25 40 – 15 25 mA
ISB1 Standby Current
(Both Ports TTL Level)
CE#L and CE#R VCC – 0.2,
f = fMAX
Ind. 1.8 V 1.8 V – 2 6 – 2 6 – 2 6 A
ISB2 Standby Current
(One Port TTL Level)
CE#L or CE#R VIH, f = fMAX
Ind. 1.8 V 1.8 V – 8.5 18 – 8.5 18 – 8.5 14 mA
ISB3 Standby Current
(Both Ports CMOS Level)
CE#L and CE#R VCC 0.2 V,
f = 0
Ind. 1.8 V 1.8 V – 2 6 – 2 6 – 2 6 A
ISB4 Standby Current
(One Port CMOS Level)
CE#L or CE#R VIH,
f = fMAX[20]
Ind. 1.8 V 1.8 V – 8.5 18 – 8.5 18 – 8.5 14 mA
Electrical Characteristics for VCC = 1.8 V (continued)
Over the Operating Range (continued)
Parameter
Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
Unit
–65 –65 –90
P1 IO
Voltage
P2 IO
Voltage Min Typ Max Min Typ Max Min Typ Max
[+] Feedback
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 10 of 25
Electrical Characteristics for VCC = 2.5 V
Over the Operating Range
Parameter
Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
Unit
–65 –65 –90
P1 IO
Voltage
P2 IO
Voltage Min Typ Max Min Typ Max Min Typ Max
VOH Output HIGH Voltage
(IOH = –2 mA)
2.5 V (any port) 2.0 – – 2.0 – – 2.0 – – V
3.0 V (any port) 2.1 – – 2.1 – – 2.1 – – V
VOL Output LOW Voltage
(IOL = 2 mA
2.5 V (any port) – – 0.4 – – 0.4 – – 0.4 V
3.0 V (any port) – – 0.4 – – 0.4 – – 0.4 V
VOL
ODR
ODR Output LOW Voltage
(IOL = 8 mA
2.5 V (any port) – – 0.2 – – 0.2 – – 0.2 V
3.0 V (any port) – – 0.2 – – 0.2 – – 0.2 V
VIH Input HIGH Voltage 2.5 V (any port) 1.7 – VDDIO
+ 0.3
1.7 – VDDIO
+ 0.3
1.7 – VDDIO
+ 0.3
V
3.0 V (any port) 2.0 – VDDIO
+ 0.2
2.0 – VDDIO
+ 0.2
2.0 – VDDIO
+ 0.2
V
VIL Input LOW Voltage 2.5 V (any port) –0.3 – 0.6 –0.3 – 0.6 –0.3 – 0.6 V
3.0 V (any port) –0.2 – 0.7 –0.2 – 0.7 –0.2 – 0.7 V
IOZ Output Leakage Current 2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
ICEX
ODR
ODR Output Leakage Current.
VOUT = VCC
2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
IIX Input Leakage Current 2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
ICC Operating Current
(VCC = Max, IOUT = 0 mA)
Outputs Disabled
Ind. 2.5 V 2.5 V – 39 55 – 39 55 – 28 40 mA
ISB1 Standby Current
(Both Ports TTL Level)
CE#L and
CE#R VCC – 0.2,
f = fMAX
Ind.2.5 V2.5 V–68–68–68A
ISB2 Standby Current
(One Port TTL Level)
CE#L or CE#R VIH,
f = fMAX
Ind. 2.5 V 2.5 V – 21 30 – 21 30 – 18 25 mA
ISB3 Standby Current
(Both Ports CMOS Level)
CE#L and
CE#R VCC 0.2 V, f = 0
Ind.2.5 V2.5 V–46–46–46A
ISB4 Standby Current
(One Port CMOS Level)
CE#L or CE#R VIH,
f = fMAX[21]
Ind. 2.5 V 2.5 V – 21 30 – 21 30 – 18 25 mA
Note
21. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
[+] Feedback
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CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 11 of 25
Electrical Characteristics for 3.0 V
Over the Operating Range
Parameter
Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
Unit
–65 –65 –90
P1 IO
Voltage
P2 IO
Voltage Min Typ Max Min Typ Max Min Typ Max
VOH Output HIGH Voltage (IOH = –2 mA) 3.0 V (any port) 2.1 – – 2.1 – – 2.1 – – V
VOL Output LOW Voltage (IOL = 2 mA3.0 V (any port) – – 0.4 – – 0.4 – – 0.4 V
VOL
ODR
ODR Output LOW Voltage (IOL = 8 mA3.0 V (any port) – – 0.2 – – 0.2 – – 0.2 V
VIH Input HIGH Voltage 3.0 V (any port) 2.0 – VDDIO
+ 0.2
2.0 – VDDIO
+ 0.2
2.0 – VDDIO
+ 0.2
V
VIL Input LOW Voltage 3.0 V (any port) –0.2 – 0.7 –0.2 – 0.7 –0.2 – 0.7 V
IOZ Output Leakage Current 3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
ICEX
ODR
ODR Output Leakage Current.
VOUT = VCC
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
IIX Input Leakage Current 3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
ICC Operating Current
(VCC = Max, IOUT = 0 mA)
Outputs Disabled
Ind. 3.0 V 3.0 V – 49 70 – 49 70 – 42 60 mA
ISB1 Standby Current
(Both Ports TTL Level)
CE#L and CE#R VCC – 0.2,
f = fMAX
Ind. 3.0 V 3.0 V 7 10 7 10 7 10 A
ISB2 Ind. 3.0 V 3.0 V 28 40 28 40 25 35 mA
ISB3 Standby Current
(One Port TTL Level)
CE#L or CE#R VIH, f = fMAX
Ind. 3.0 V 3.0 V 6 8 6 8 6 8 A
ISB4 Ind. 3.0 V 3.0 V 28 40 28 40 25 35 mA
Capacitance[22]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25 °C, f = 1 MHz, VCC = 3.0 V 9 pF
COUT Output Capacitance 10 pF
Note
22. Tested initially and after any design or process changes that may affect these parameters.
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Document #: 001-08090 Rev. *G Page 12 of 25
Figure 2. AC Test Loads and Waveforms
1.8 V
GND 90% 90%
10%
10%
ALL INPUT PULSES
(a) Normal Load
R1
3.0 V/2.5 V/1.8 V
OUTPUT
R2
C = 30 pF
VTH = 0.8 V
OUTPUT
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay (Load 2)
R1
R2
3.0 V/2.5 V/1.8 V
OUTPUT
RTH = 6 k
3 ns 3 ns
including scope and jig)
(Used for tLZ, tHZ, tHZWE, and tLZWE
3.0 V/2.5 V 1.8 V
R1 1022 13500
R2 792 10800
C = 30 pF
C = 5 pF
Switching Characteristics for VCC = 1.8 V
Over the Operating Range [23]
Parameter Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16 Unit
–65 –65 –90
Min Max Min Max Min Max
AD Mux Port Read Cycle [24]
tRC Read Cycle Time 65 – 65 – 90 – ns
tACC1 Random access ADV# Low to Data Valid – 65 – 65 – 90 ns
tACC2 Random access Address to Data Valid – 65 – 65 – 90 ns
tACC3 Random access CS# to Data Valid – 65 – 65 – 90 ns
tAVDA Random access ADV# High to Data Valid – 35 – 35 – 50 ns
tAVD ADV# Low Pulse 15 – 15 – 20 – ns
tAVDS Address Setup-up to ADV# rising edge 15 – 15 – 20 – ns
tAVDH Address Hold from ADV# rising edge 3 – 3 – 5 – ns
tCSS CS# Set-up to ADV# rising edge 7 – 7 – 10 – ns
tOE OE# Low to Data Valid – 35 – 35 – 50 ns
tLZOE[25] OE# Low to IO Low Z 3 – 3 – 5 – ns
tHZOE OE# High to IO High Z – 15 – 15 – 25 ns
tHZCS CS# High to IO High Z – 15 – 15 – 25 ns
tDBE UB#/LB# Low to IO Valid – 35 – 35 – 50 ns
tLZBE UB#/LB# Low to IO Low Z 3 – 3 – 5 – ns
tHZBE UB#/LB# High to IO High Z – 15 – 15 – 25 ns
tAVOE ADV# High to OE# Low 0 – 0 – 0 – ns
Notes
23. All timing parameters are measured with Load 2 specified in Figure 2.
24. AD Mux port timing applies to left AD Mux port and right port configured to AD Mux port.
25. This parameter is guaranteed by not tested.
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CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 13 of 25
AD Mux Port Write Cycle[26]
tWC Write Cycle Time 65 – 65 – 90 – ns
tSCS CS# Low to Write End 65 – 65 – 90 – ns
tAVD ADV# Low Pulse 15 – 15 – 20 – ns
tAVDS Address Set-up to ADV# rising edge 15 – 15 – 20 – ns
tAVDH Address Hold from ADV# rising edge 3 – 3 – 5 – ns
tCSS CS# Set-up to ADV# rising edge 7 – 7 – 10 – ns
tWRL WE# Pulse Width 28 – 28 – 45 – ns
tBW UB#/LB# Low to Write End 28 – 28 – 45 – ns
tSD Data Set-up to Write End 20 – 20 – 30 – ns
tHD Data Hold from Write End 0 – 0 – 0 – ns
tLZWE WE# High to IO Low Z 0 – 0 – 0 – ns
tAVWE ADV# High to WE# Low 0 – 0 – 0 – ns
Standard Port Read Cycle[27]
tRC Read Cycle Time 40 – 60 – 60 – ns
tAA Address to Data Valid – 40 – 60 – 60 ns
tOHA Output Hold From Address Change 5 – 5 – 5 – ns
tACS CS# to Data Valid – 40 – 60 – 60 ns
tDOE OE# Low to Data Valid – 25 – 35 – 35 ns
tLZOE[28] OE# Low to Data Low Z 5 – 5 – 5 – ns
tHZOE OE# High to Data High Z – 10 – 30 – 30 ns
tLZCS CS# Low to Data Low Z 5 – 5 – 5 – ns
tHZCS CS# High to Data High Z – 10 – 30 – 30 ns
tLZBE UB#/LB# Low to Data Low Z 5 – 5 – 5 – ns
tHZBE UB#/LB# High to Data High Z – 10 – 30 – 30 ns
tABE UB#/LB# Access Time – 40 – 60 – 60 ns
Standard SRAM Port Write Cycle
tWC Write Cycle Time 40 – 60 – 60 – ns
tSCS CS# Low to Write End 30 – 50 – 50 – ns
tAW Address Valid to Write End 30 – 50 – 50 – ns
tHA Address Hold from Write End 0 – 0 – 0 – ns
tSA Address Set-up to Write Start 0 – 0 – 0 – ns
Switching Characteristics for VCC = 1.8 V (continued)
Over the Operating Range [23] (continued)
Parameter Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16 Unit
–65 –65 –90
Min Max Min Max Min Max
Notes
26. AD Mux port timing applies to left AD Mux port and right port configured to AD Mux port.
27. Standard SRAM port timing applies to right port configured to standard SRAM port.
28. This parameter is guaranteed by not tested.
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CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 14 of 25
tWRL Write Pulse Width 25 – 45 – 45 – ns
tSD Data Set-up to Write End 20 – 30 – 30 – ns
tHD Data Hold from Write End 0 – 0 – 0 – ns
tHZWE WE# Low to Data High Z – 15 – 25 – 25 ns
tLZWE WE# High to Data Low Z 0 – 0 – 0 – ns
Arbitration Timing
tBLA BUSY# Low from Address Match – 30 – 50 – 50 ns
tBHA BUSY# High from Address Mismatch – 30 – 50 – 50 ns
tBLC BUSY# Low from CS# Low – 30 – 50 – 50 ns
tBHC BUSY# High from CS# High – 30 – 50 – 50 ns
tPS[29] Port Set-Up fro Priority 5 – 5 – 5 – ns
tBDD BUSY# High to Data Valid – 30 – 50 – 50 ns
tWDD Write Pulse to Data Delay – 55 – 85 – 85 ns
tDDD Write Data Valid to Read Data Valid – 45 – 70 – 70 ns
Interrupt Timing
tINS INT# Set Time – 35 – 55 – 55 ns
tINR INT# Reset Time – 35 – 55 – 55 ns
Switching Characteristics for VCC = 1.8 V (continued)
Over the Operating Range [23] (continued)
Parameter Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16 Unit
–65 –65 –90
Min Max Min Max Min Max
Note
29. Add 2 ns to this parameter if VCC and VDDIOR are < 1.8 V, and VDDIOL is > 2.5 V at temperature < 0 °C.
[+] Feedback
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CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 15 of 25
Switching Waveforms
Figure 3. ADM Port Read Cycle (Either Port Access, WE# High)
Figure 4. ADM Port Write Cycle (Either Port Access, WE# Controlled, OE# High)
Valid Address
I/O[15:0]
ADV#
OE#
WE#
CS#
Valid Data
tAVD
tAVDS tAVDH
tCSS
tAVOE
tACC3
tACC1
tACC2
tHZCS
tHZOE
tAVDA
tOE
UB#, LB#
tLZBE
tDBE
tHZBE
Addr1<15..0>
I/O[15:0]
ADV#
OE#
WE#
CS#
WData1<15..0>
tAVWE
tWRL
tSD tHD
tAVD
tAVDS tAVDH
tCSS
tSCS
UB#, LB# tBW
[+] Feedback
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CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 16 of 25
Figure 5. ADM Port Write Cycle (Either Port Access, CS# Controlled, OE# High)
Figure 6. Standard Port Read Cycle (Right Port Access, WE# High)
Addr1<15..0>
I/O[15:0]
ADV#
OE#
WE#
CS#
WData1<15..0>
tAVWE
tWRL
tSD
tHD
tAVD
tAVDS tAVDH
tCSS
tSCS
UB#, LB#
tBW
Valid Address
Address
OE#
WE#
CS#
tRC
tHZCS
tHZOE
UB#, LB# tHZBE
Data Out Valid Data
tOHAtAA
tACS
tDOE
tLZOE
tLZCS
tABE
tLZBE
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Document #: 001-08090 Rev. *G Page 17 of 25
Figure 7. Standard Port Write Cycle (Right Port Access, WE# Controlled)
Figure 8. Standard Port Write Cycle (Right Port Access, CS# Controlled)
Valid Address
Address
OE#
WE#
CS#
tWC
tLZWE
UB#, LB#
tBW
Data Valid Data
tAW
tSA
tWRL
tSD tHD
tHZWE
tHA
Valid Address
Address
OE#
WE#
CS#
tWC
tLZCS
UB#, LB#
tBW
Data Valid Data
tAW
tSA
tWRL
tSD tHD
tHZWE
tHA
tSCS
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CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 18 of 25
Figure 9. Arbitration Timing
Figure 10. Arbitration Timing (Address Controlled with Left ADM and Right Standard Configuration
Address Match
Address L & R
CS#L
BUSY#L
CS#R
tBLC
tPS
tBHC
Address Match
Address R
BUSY#R
tBLA
Left Address Valid First
tPS
tBHA
I/OL[15:0]
Mismatch
ADV#L
Address L
(Internal)
tAVDH
Valid Left Address
Address R
BUSY#L
tBLA
tPS
tBHA
I/OL[15:0]
ADV#L
Address L
(Internal)
tAVDH
Data
Address Match
tAVDH
Valid Address Valid Address
Mismatch
Valid Address
Right Address Valid First
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CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 19 of 25
Figure 11. Arbitration Timing (Address Controlled with Left ADM and Right ADM Configuration)
Figure 12. Read with BUSY# Timing
Address R
(internal)
BUSY#R
tBLA
tPS
tBHA
ADV#L
Address L
(Internal)
tAVDH tAVDH
Mismatch
ADV#R
tAVDH
Address Match
Address R
BUSY#R
I/OL[15:0]
AVD#L
WE#L
Data
Valid Address Valid Address
Address Match
tWDD
tDDD
Data Out R Valid Data
tBDD
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Document #: 001-08090 Rev. *G Page 20 of 25
Figure 13. Interrupt Timing
CS#L
INT#R
tINS
tHD
Right Mailbox Addr
I/OL[15:0]
OE#L
Write Data
WE#L
CS# or WE#, whichever
assert LOW later
CS# or WE#, whichever
assert HIGH first
Left Port Writes Right Mailbox to set INT#R
Right Port Reads Right Mailbox to Clear INT#R
Right Mailbox Addr
Address R
OE#R
WE#R
CS#R
INT#R
tINR
CS#, OE# or WE#,
whichever assert latest
[+] Feedback
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CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
Document #: 001-08090 Rev. *G Page 21 of 25
Ordering Information
Ordering Code Definitions
Table 7. 16 K × 16 MoBL ADM Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
65 CYDMX256A16-65BVXI BZ100 100-ball Pb-free 0.5 mm pitch BGA Industrial
65 CYDMX256B16-65BVXI BZ100 100-ball Pb-free 0.5 mm pitch BGA Industrial
90 CYDMX256A16-90BVXI BZ100 100-ball Pb-free 0.5 mm pitch BGA Industrial
Table 8. 8 K × 16 MoBL ADM Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
65 CYDMX128A16-65BVXI BZ100 100-ball Pb-free 0.5 mm pitch BGA Industrial
65 CYDMX128B16-65BVXI BZ100 100-ball Pb-free 0.5 mm pitch BGA Industrial
Table 9. 4 K × 16 MoBL ADM Asynchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
65 CYDMX064B16-65BVXI BZ100 100-ball Pb-free 0.5 mm pitch BGA Industrial
90 CYDMX064A16-90BVXI BZ100 100-ball Pb-free 0.5 mm pitch BGA Industrial
Temperature Range: I = Industrial
X = Pb-free
Package Type:
BV = 100-ball BGA
Latency in ns: 65 / 90
Bus Width
Version
Dual-Port density in Kb: 064 / 128 / 256
X = AD Mux interface
No X = standard SRAM interface
CYDM = Cypress MoBL Dual-Port
CYDM XXX XX - IBVXXX XX
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Document #: 001-08090 Rev. *G Page 22 of 25
Package Diagram
Figure 14. 100-ball VFBGA (6 × 6 × 1.0 mm) BZ100A
51-85209 *D
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Document #: 001-08090 Rev. *G Page 23 of 25
Acronyms Document Conventions
Units of Measure
Acronym Description
CS# Chip Select
BGA ball grid array
CMOS complementary metal oxide semiconductor
I/O input/output
LVCMOS low voltage complementary metal oxide
semiconductor
LVTTL low voltage transistor-transistor logic
ODR output drive register
OE# Output Enable
SRAM static random access memory
TTL transistor-transistor logic
VFBGA Very fine-pitch ball grid array
WE# Write Enable
Symbol Unit of Measure
°C degree Celsius
µA micro Amperes
MHz Mega Hertz
mA milli Amperes
ms milli seconds
mm milli meter
ns nano seconds
ohms
pF pico Farad
mV milli Volts
VVolts
WWatts
% percent
[+] Feedback
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Document #: 001-08090 Rev. *G Page 24 of 25
Document History Page
Document Title: CYDMX256A16, CYDMX128A16, CYDMX064A16, CYDMX256B16, CYDMX128B16, CYDMX064B16,
16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM
Document Number: 001-08090
REV. ECN NO. Orig. of
Change
Submission
Date Description of Change
** 462234 HKH New data sheet
*A 491702 HKH Removed none applicable timing tBW
Revised standard port timing numbers
Corrected typo
*B 500425 HKH Updated tWC, tSCS to reflect bin spec
Added note for special condition of tPS
Updated DC data that are previously TBD
Added note for tLZOE that is guaranteed by design by not tested
*C 2147866 YDT/HKH
/AESA
See ECN Relaxed -65 Standard port timing to match the standard port timing of -90.
Added new devices CYDMX256B16, CYDMX128B16 and CYDMX064B16.
*D 3031102 VED 09/15/2010 Changed to post on the external web. No other change.
*E 3053582 HKH 10/08/2010 Removed pruned device CYDMX064A16-65BVXI from Ordering Information.
Updated sales links. Added Ordering Code Definition and Table of Contents.
*F 3209987 HKH 03/30/2011 Updated Ordering Information.
Updated Package Diagram.
Updated in new template.
*G 3246085 HKH 05/02/2011 Added Acronyms and Units of Measure.
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Document #: 001-08090 Rev. *G Revised May 2, 2011 Page 25 of 25
MoBL is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
CYDMX256A16, CYDMX256B16
CYDMX128A16, CYDMX128B16
CYDMX064A16, CYDMX064B16
© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
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