PCA9543AD - NXP - Datasheet.Directory

1. General description

The PCA9543A/43B/43C is a bidirectional translating switch, controlled by the I2C-bus.

The SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any

individual SCx/SDx channels or combination of channels can be selected, determined by

the contents of the programmable control register. Two interrupt inputs, INT0 and INT1,

one for each of the downstream pairs, are provided. One interrupt output, INT, which acts

as an AND of the two interrupt inputs, is provided.

An active LOW reset input allows the PCA9543X to recover from a situation where one of

the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the

I2C-bus state machine and causes all the channels to be deselected, as does the internal

power-on reset function.

The pass gates of the switches are constructed such that the VDD pin can be used to limit

the maximum high voltage which will be passed by the PCA9543X. This allows the use of

different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts can

communicate with 5 V parts without any additional protection. External pull-up resistors

pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.

The PCA9543A, PCA9543B and PCA9543C are identical except for the ﬁxed portion of

the slave address.

2. Features

n1-of-2 bidirectional translating switches

nI2C-bus interface logic; compatible with SMBus standards

n2 active LOW interrupt inputs

nActive LOW interrupt output

nActive LOW reset input

n2 address pins allowing up to 4 devices on the I2C-bus

nAlternate address versions A, B and C allow up to a total of 12 devices on the bus for

larger systems or to resolve address conﬂicts

nChannel selection via I2C-bus, in any combination

nPower-up with all switch channels deselected

nLow Ron switches

nAllows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses

nNo glitch on power-up

nSupports hot insertion

nLow standby current

nOperating power supply voltage range of 2.3 V to 5.5 V

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

Rev. 06 — 15 June 2009 Product data sheet

Product data sheet Rev. 06 — 15 June 2009 2 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

n5 V tolerant inputs

n0 Hz to 400 kHz clock frequency

nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

nPackages offered: SO14, TSSOP14

3. Ordering information

3.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

PCA9543AD SO14 plastic small outline package; 14 leads;

body width 3.9 mm SOT108-1

PCA9543APW TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

PCA9543BPW

PCA9543CPW

Table 2. Ordering options

Type number Topside mark Temperature range (Tamb)

PCA9543AD PCA9543AD Tamb =−40 °C to +85 °C

PCA9543APW PA9543A Tamb =−40 °C to +85 °C

PCA9543BPW PA9543B Tamb =−40 °C to +85 °C

PCA9543CPW PA9543C Tamb =−40 °C to +85 °C

Product data sheet Rev. 06 — 15 June 2009 3 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

4. Block diagram

Fig 1. Block diagram of PCA9543A/43B/43C

SWITCH CONTROL LOGIC

PCA9543A/43B/43C

POWER-ON

RESET

002aab180

SC0

SC1

SD0

SD1

VSS

VDD

RESET

I2C-BUS

CONTROL

INPUT

FILTER

SCL

SDA

INTERRUPT LOGIC

INT0

INT1

INT

Product data sheet Rev. 06 — 15 June 2009 4 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 2. Pin conﬁguration for SO14 Fig 3. Pin conﬁguration for TSSOP14

PCA9543AD

A0 VDD

A1 SDA

RESET SCL

INT0 INT

SD0 SC1

SC0 SD1

VSS INT1

002aab178

7 8

VDD

SDA

SCL

INT

SC1

SD1

INT1

RESET

INT0

SD0

SC0

VSS

PCA9543APW

PCA9543BPW

PCA9543CPW

002aab179

Table 3. Pin description

Symbol Pin Description

A0 1 address input 0

A1 2 address input 1

RESET 3 active LOW reset input

INT0 4 active LOW interrupt input 0

SD0 5 serial data 0

SC0 6 serial clock 0

VSS 7 supply ground

INT1 8 active LOW interrupt input 1

SD1 9 serial data 1

SC1 10 serial clock 1

INT 11 active LOW interrupt output

SCL 12 serial clock line

SDA 13 serial data line

VDD 14 supply voltage

Product data sheet Rev. 06 — 15 June 2009 5 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

6. Functional description

Refer to Figure 1 “Block diagram of PCA9543A/43B/43C”.

6.1 Device address

Following a START condition, the bus master must output the address of the slave it is

accessing. The address of the PCA9543A is shown in Figure 4. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

The last bit of the slave address deﬁnes the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

The PCA9543B and PCA9543C are alternate address versions if needed for larger

systems or to resolve address conﬂicts. The data sheet will reference the PCA9543A, but

the PCA9543B and PCA9543C function identically except for the slave address.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9543A, which will be stored in the control register. If multiple bytes are

received by the PCA9543A, it will save the last byte received. This register can be written

and read via the I2C-bus.

Fig 4. Slave address PCA9543A

Fig 5. Slave address PCA9543B Fig 6. Slave address PCA9543C

002aab169

1 1 1 0 0 A1 A0 R/W

fixed hardware

selectable

002aab799

1 1 1 1 0 A1 A0 R/W

fixed hardware

selectable

002aab800

0 1 1 0 0 A1 A0 R/W

fixed hardware

selectable

Fig 7. Control register

002aab181

X X INT

1INT

0X X B1 B0

channel selection bits

(read/write)

76543210

interrupt bits

(read only)

channel 0

channel 1

INT0

INT1

Product data sheet Rev. 06 — 15 June 2009 6 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

6.2.1 Control register deﬁnition

One or several SCx/SDx downstream pair, or channel, is selected by the contents of the

control register. This register is written after the PCA9543A has been addressed. The

2 LSBs of the control byte are used to determine which channel is to be selected. When a

channel is selected, the channel will become active after a STOP condition has been

placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when

the channel is made active, so that no false conditions are generated at the time of

connection.

Remark: Channel 0 and channel 1 can be enabled at the same time. Care should be

taken not to exceed the maximum bus capacitance.

6.2.2 Interrupt handling

The PCA9543A provides 2 interrupt inputs, one for each channel, and one open-drain

interrupt output. When an interrupt is generated by any device, it will be detected by the

PCA9543A and the interrupt output will be driven LOW. The channel need not be active

for detection of the interrupt. A bit is also set in the control register.

Bit 4 and bit 5 of the control register corresponds to the INT0 and INT1 inputs of the

PCA9543A, respectively. Therefore, if an interrupt is generated by any device connected

to channel 1, the state of the interrupt inputs is loaded into the control register when a

read is accomplished. Likewise, an interrupt on any device connected to channel 0 would

cause bit 4 of the control register to be set on the read. The master can then address the

PCA9543A and read the contents of the control register to determine which channel

contains the device generating the interrupt. The master can then reconﬁgure the

PCA9543A to select this channel, and locate the device generating the interrupt and

clear it.

It should be noted that more than one device can provide an interrupt on a channel, so it is

up to the master to ensure that all devices on a channel are interrogated for an interrupt.

The interrupt inputs may be used as general purpose inputs if the interrupt function is not

required.

If unused, interrupt input(s) must be connected to VDD through a pull-up resistor.

Table 4. Control register: Write—channel selection; Read—channel status

D7 D6 INT1 INT0 D3 D2 B1 B0 Command

XXXXXXX0 channel 0 disabled

1 channel 0 enabled

XXXXXX0Xchannel 1 disabled

1 channel 1 enabled

00000000no channel selected;

power-up/reset default state

Table 5. Control register: Read—interrupt

7 6 INT1 INT0 3 2 B1 B0 Command

XXX0XXXXno interrupt on channel 0

1 interrupt on channel 0

XX0XXXXXno interrupt on channel 1

1 interrupt on channel 1

Product data sheet Rev. 06 — 15 June 2009 7 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

Remark: Two interrupts can be active at the same time.

6.3 RESET input

The RESET input is an active LOW signal which may be used to recover from a bus fault

condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9543A will reset

its registers and I2C-bus state machine and will deselect all channels. The RESET input

must be connected to VDD through a pull-up resistor.

6.4 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9543A in

a reset condition until VDD has reached VPOR. At this point, the reset condition is released

and the PCA9543A registers and I2C-bus state machine are initialized to their default

states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be

lowered below 0.2 V to reset the device.

6.5 Voltage translation

The pass gate transistors of the PCA9543A are constructed such that the VDD voltage can

be used to limit the maximum voltage that will be passed from one I2C-bus to another.

Figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph

was generated using the data speciﬁed in Section 10 “Static characteristics” of this data

sheet). In order for the PCA9543A to act as a voltage translator, the Vo(sw) voltage should

be equal to, or lower than the lowest bus voltage. For example, if the main bus was

running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be

equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at

(1) maximum

(2) typical

(3) minimum

Fig 8. Pass gate voltage versus supply voltage

VDD (V)

2.0 5.54.53.0 4.0

002aaa964

3.0

2.0

4.0

5.0

Vo(sw)

(V)

1.0 3.5 5.02.5

(1)

(2)

(3)

Product data sheet Rev. 06 — 15 June 2009 8 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

Figure 8, we see that Vo(sw)(max) will be at 2.7 V when the PCA9543A supply voltage is

3.5 V or lower, so the PCA9543A supply voltage could be set to 3.3 V. Pull-up resistors

can then be used to bring the bus voltages to their appropriate levels (see Figure 15).

More Information can be found in Application Note

AN262: PCA954X family of I

C/SMBus

multiplexers and switches

7. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 9).

7.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 10).

Fig 9. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 10. Deﬁnition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

START condition

Product data sheet Rev. 06 — 15 June 2009 9 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

7.3 System conﬁguration

A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 11).

7.4 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also, a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 11. System conﬁguration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 12. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 06 — 15 June 2009 10 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

7.5 Bus transactions

Data is transmitted to the PCA9543A control register using the Write mode as shown in

Figure 13.

Data is read from PCA9543A using the Read mode as shown in Figure 14.

Fig 13. Write control register

Fig 14. Read control register

002aab182

XXXXXXB1B01 1 0 0 A1 A0 0 AS 1 A P

slave address

START condition R/W acknowledge

from slave acknowledge

from slave

control register

SDA

STOP condition

002aab183

X X INT1 INT0 X X B1 B01 1 0 0 A1 A0 1 AS 1 NA P

slave address

START condition R/W acknowledge

from slave no acknowledge

from master

control register

SDA

STOP condition

last byte

Product data sheet Rev. 06 — 15 June 2009 11 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

8. Application design-in information

9. Limiting values

[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal

environment can create junction temperatures which are detrimental to reliability. The maximum junction

temperature of this integrated circuit should not exceed 125 °C.

(1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a

pull-up resistor is required.

If the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a

pull-up resistor is not required.

The interrupt inputs should not be left ﬂoating.

Fig 15. Typical application

PCA9543A

SD0

SC0

VSS

SDA

SCL

RESET

VDD = 3.3 V

VDD = 2.7 V to 5.5 V

I2C/SMBus master

002aab184

SDA

SCL channel 0

V = 2.7 V to 5.5 V

INT INT0

see note (1)

SD1

SC1 channel 1

V = 2.7 V to 5.5 V

INT1

see note (1)

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

(ground=0V).

[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +7.0 V

VIinput voltage −0.5 +7.0 V

IIinput current - ±20 mA

IOoutput current - ±25 mA

IDD supply current - ±100 mA

ISS ground supply current - ±100 mA

Ptot total power dissipation - 400 mW

Tstg storage temperature −60 +150 °C

Tamb ambient temperature operating −40 +85 °C

Product data sheet Rev. 06 — 15 June 2009 12 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

10. Static characteristics

[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.

[2] VDD must be lowered to 0.2 V in order to reset part.

Table 7. Static characteristics at VDD = 2.3 V to 3.6 V

=0V; T

amb

−

C to +85

C; unless otherwise speciﬁed. See Table 8 on page 13 for V

= 4.5 V to 5.5 V.

[1]

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 2.3 - 3.6 V

IDD supply current operating mode; VDD = 3.6 V; no load;

VI=V

DD or VSS; fSCL = 100 kHz - 40 100 µA

Istb standby current Standby mode; VDD = 3.6 V; no load;

VI=V

DD or VSS; fSCL = 0 kHz - 0.2 1 µA

VPOR power-on reset voltage no load; VI=V

DD or VSS [2] - 1.6 2.1 V

Input SCL; input/output SDA

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -6 V

IOL LOW-level output current VOL = 0.4 V 3 - - mA

VOL = 0.6 V 6 - - mA

ILleakage current VI=V

DD or VSS −1-+1 µA

Ciinput capacitance VI=V

SS - 9 10 pF

Select inputs A0, A1, INT0, INT1, RESET

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -V

DD + 0.5 V

ILI input leakage current VI=V

DD or VSS −1-+1 µA

Ciinput capacitance VI=V

SS - 1.6 3 pF

Pass gate

Ron ON-state resistance VDD = 3.0 to 3.6 V; VO= 0.4 V;

IO=15mA 51130Ω

VDD = 2.3 V to 2.7 V; VO= 0.4 V;

IO=10mA 71655Ω

Vo(sw) switch output voltage Vi(sw) =V

DD = 3.3 V; Io(sw) =−100 µA - 1.9 - V

Vi(sw) =V

DD = 3.0 V to 3.6 V;

Io(sw) =−100 µA1.6 - 2.8 V

Vi(sw) =V

DD = 2.5 V; Io(sw) =−100 µA - 1.5 - V

Vi(sw) =V

DD = 2.5 V to 2.7 V;

Io(sw) =−100 µA1.1 - 2.0 V

ILleakage current VI=V

DD or VSS −1-+1 µA

Cio input/output capacitance VI=V

SS -35 pF

INT output

IOL LOW-level output current VOL = 0.4 V 3 - - mA

IOH HIGH-level output current - - +100 µA

Product data sheet Rev. 06 — 15 June 2009 13 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.

[2] VDD must be lowered to 0.2 V in order to reset part.

Table 8. Static characteristics at VDD = 4.5 V to 5.5 V

= 0 V; T

amb

−

C to +85

C; unless otherwise speciﬁed. See Table 7 on page 12 for V

= 2.3 V to 3.6 V.

[1]

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 4.5 - 5.5 V

IDD supply current Operating mode; VDD = 5.5 V;

no load; VI=V

DD or VSS;

fSCL = 100 kHz

- 25 100 µA

Istb standby current Standby mode; VDD = 5.5 V;

no load; VI=V

DD or VSS;

fSCL = 0 kHz

- 0.2 1 µA

VPOR power-on reset voltage no load; VI=V

DD or VSS [2] - 1.7 2.1 V

Input SCL; input/output SDA

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -6 V

IOL LOW-level output current VOL = 0.4 V 3 - - mA

VOL = 0.6 V 6 - - mA

ILleakage current VI=V

DD or VSS −1- +1 µA

Ciinput capacitance VI=V

SS - 9 10 pF

Select inputs A0, A1, INT0 to INT3, RESET

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -V

DD + 0.5 V

ILI input leakage current VI=V

DD or VSS −1 - +50 µA

Ciinput capacitance VI=V

SS -25 pF

Pass gate

Ron on-state resistance VDD = 4.5 V to 5.5 V; VO= 0.4 V;

IO=15mA 4924Ω

Vo(sw) switch output voltage Vi(sw) =V

DD = 5.0 V;

Io(sw) =−100 µA- 3.6 - V

Vi(sw) =V

DD = 4.5 V to 5.5 V;

Io(sw) =−100 µA2.6 - 4.5 V

ILleakage current VI=V

DD or VSS −1 - +100 µA

Cio input/output capacitance VI=V

SS -35 pF

INT output

IOL LOW-level output current VOL = 0.4 V 3 - - mA

IOH HIGH-level output current - - +100 µA

Product data sheet Rev. 06 — 15 June 2009 14 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

11. Dynamic characteristics

[1] Pass gate propagation delay is calculated from the 20 Ω typical Ron and the 15 pF load capacitance.

[2] Hold time (repeated) START condition. After this period, the ﬁrst clock pulse is generated.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to

bridge the undeﬁned region of the falling edge of SCL.

[4] Cb= total capacitance of one bus line in pF.

[5] Measurements taken with 1 kΩ pull-up resistor and 50 pF load.

Table 9. Dynamic characteristics

Symbol Parameter Conditions Standard-mode

I2C-bus Fast-mode I2C-bus Unit

Min Max Min Max

tPD propagation delay from SDA to SDx,

or SCL to SCx - 0.3[1] - 0.3[1] ns

fSCL SCL clock frequency 0 100 0 400 kHz

tBUF bus free time between a STOP and

START condition 4.7 - 1.3 - µs

tHD;STA hold time (repeated) START condition [2] 4.0 - 0.6 - µs

tLOW LOW period of the SCL clock 4.7 - 1.3 - µs

tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs

tSU;STA set-up time for a repeated START

condition 4.7 - 0.6 - µs

tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs

tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 µs

tSU;DAT data set-up time 250 - 100 - ns

trrise time of both SDA and SCL

signals - 1000 20 + 0.1Cb[4] 300 ns

tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 ns

Cbcapacitive load for each bus line - 400 - 400 pF

tSP pulse width of spikes that must be

suppressed by the input ﬁlter - 50 - 50 ns

tVD;DAT data valid time HIGH-to-LOW [5] -1 - 1µs

LOW-to-HIGH [5] - 0.6 - 0.6 µs

tVD;ACK data valid acknowledge time - 1 - 1 µs

INT

tv(INTnN-INTN) valid time from INTn to INT signal - 4 - 4 µs

td(INTnN-INTN) delay time from INTn to INT inactive - 2 - 2 µs

tw(rej)L LOW-level rejection time INTn inputs 1 - 1 - µs

tw(rej)H HIGH-level rejection time INTn inputs 0.5 - 0.5 - µs

RESET

tw(rst)L LOW-level reset time 4 - 4 - ns

trst reset time SDA clear 500 - 500 - ns

tREC;STA recovery time to START condition 0 - 0 - ns

Product data sheet Rev. 06 — 15 June 2009 15 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

Fig 16. Deﬁnition of timing on the I2C-bus

tSP

tBUF

tHD;STA PP S

tLOW

tHD;DAT

tHIGH tSU;DAT tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

Fig 17. Deﬁnition of RESET timing

SDA

SCL

002aac549

50 %

30 %

50 % 50 %

tREC;STA tw(rst)L

RESET

START

trst

ACK or read cycle

Rise and fall times refer to VIL and VIH.

Fig 18. I2C-bus timing diagram

SCL

SDA

tHD;STA tSU;DAT tHD;DAT

tBUF

tSU;STA tLOW tHIGH

tVD;ACK

002aab175

tSU;STO

protocol START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6) bit 0

(R/W) acknowledge

(A)

STOP

condition

(P)

1/fSCL

tVD;DAT

Product data sheet Rev. 06 — 15 June 2009 16 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

12. Package outline

Fig 19. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 06 — 15 June 2009 17 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

Fig 20. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 06 — 15 June 2009 18 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 06 — 15 June 2009 19 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 21) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 10 and 11

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 21.

Table 10. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 11. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 06 — 15 June 2009 20 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

14. Abbreviations

MSL: Moisture Sensitivity Level

Fig 21. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 12. Abbreviations

Acronym Description

CDM Charged-Device Model

ESD ElectroStatic Discharge

HBM Human Body Model

IC Integrated Circuit

I2C-bus Inter-Integrated Circuit bus

LSB Least Signiﬁcant Bit

MM Machine Model

MSB Most Signiﬁcant Bit

PCB Printed-Circuit Board

SMBus System Management Bus

Product data sheet Rev. 06 — 15 June 2009 21 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

15. Revision history

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9543A_43B_43C_6 20090615 Product data sheet - PCA9543A_43B_43C_5

Modiﬁcations: •Table 9 “Dynamic characteristics”:

–Symbol tf: changed Unit from “µs” to “ns”

–Symbol Cb: changed Unit from “µs” to “pF”

PCA9543A_43B_43C_5 20081117 Product data sheet - PCA9543A_43B_43C_4

PCA9543A_43B_43C_4 20061020 Product data sheet - PCA9543A_3

PCA9543A_3

(9397 750 14316) 20050321 Product data sheet - PCA9543A_2

PCA9543A_2

(9397 750 13988) 20040929 Objective data sheet - PCA9543A_1

PCA9543A_1

(9397 750 13299) 20040728 Objective data sheet - -

Product data sheet Rev. 06 — 15 June 2009 22 of 23

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 June 2009

Document identifier: PCA9543A_43B_43C_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 5

6.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2.1 Control register deﬁnition . . . . . . . . . . . . . . . . . 6

6.2.2 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 6

6.3 RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.5 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 7

7 Characteristics of the I2C-bus. . . . . . . . . . . . . . 8

7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2 START and STOP conditions . . . . . . . . . . . . . . 8

7.3 System conﬁguration . . . . . . . . . . . . . . . . . . . . 9

7.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.5 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 10

8 Application design-in information . . . . . . . . . 11

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 12

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 14

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

13 Soldering of SMD packages . . . . . . . . . . . . . . 18

13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 18

13.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 18

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 18

13.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 19

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

17 Contact information. . . . . . . . . . . . . . . . . . . . . 22

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23