TECHNICAL DATA
321
Quad 2-Input Data Selector /M ultiple xe r
wi th 3-State Outputs
High-Perform ance Silicon-Gate C MOS
The IN74HC257 is identical in pinout to the LS/ALS257. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device selects a (4-bit) nibble from either the A or B inputs as
determined by the Select input. The nibble is presented at the outputs
in noninverted from when the Output Enable pin is at a low level. A
high level on the Output Enable pin switches the outputs into the high-
impedance state.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
IN74HC257
ORDERING INFORMATION
IN74HC257N Plastic
IN74HC257D SOIC
TA = -55° to 125° C for all packages
FUNCTION TABLE
Inputs Outputs
Output
Enable Select Y0-Y3
HXZ
LLA0-A3
LHB0-B3
X=don’t care
Z = high-impe dance state
A0-A3,B0 -B3=the levels of the respective
Nibble Inputs
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
PIN ASSIGNMENT
IN74HC257
322
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±35 mA
ICC DC Supply Current, VCC and GND Pins ±75 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types -55 +125 °C
tr, tfInput Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
Thi s device contains p rote ction c ircuitr y to guard a gainst damage due to hi gh static voltage s or electr ic
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
IN74HC257
323
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C≤125
°CUnit
VIH Minimum High-Level
Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT≤ 20 µA2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Maximum Low -
Level Input Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH Minimum High-Level
Output Voltage VIN=VIH or VIL
IOUT ≤ 20 µA2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
IOUT ≤ 6.0 mA
IOUT ≤ 7.8 mA 4.5
6.0 3.98
5.48 3.84
5.34 3.7
5.2
VOL Maximum Low-Level
Output Voltage VIN=VIH or VIL
IOUT ≤ 20 µA2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or VIL
IOUT ≤ 6.0 mA
IOUT ≤.7.8 mA 4.5
6.0 0.26
0.26 0.33
0.33 0.4
0.4
IIN Maximum Input
Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
IOZ Maximum Three-
State Leakage
Current
Output in High-Impedance
State
VIN= VIL or VIH
VOUT= VCC or GND
6.0 ±0.5 ±5.0 ±10 µA
ICC Maximum Qui escent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA6.0 8.0 80 160 µA
IN74HC257
324
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V 25 °C
to
-55°C
≤85°C≤125°CUnit
tPLH, tPHL Maximum Propagation Delay, Nibble A or B to
Output Y (Figures 1and 4) 2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tPLH, tPHL Maximum Propagation Delay , Select to
Output Y (Figures 2 and 4) 2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tPLZ, tPHZ Maximum Propagation Delay , Output Enable to
Output Y (Figures 3 and 5) 2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZL, tPZH Maximum Propagation Delay , Output Enable to
Output Y (Figures 3 and 5) 2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4) 2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
CIN Maximum Input Capacitance - 10 10 10 pF
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State) -151515pF
Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
39 pF
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
IN74HC257
325
Figure 3. Switching Waveforms
Figure 4. Test Circuit Figure 5. Test Circuit
EXPANDED LOGIC DIAGRAM
