Micropower
Quad-Channel Digital Isolators
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Rev. D Document Feedback
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FEATURES
Ultralow power operation
3.3 V operation (typical)
5.6 μA per channel quiescent current, refresh enabled
0.3 μA per channel quiescent current, refresh disabled
148 μA/Mbps per channel typical dynamic current
2.5 V operation (typical)
3.1 μA per channel quiescent current, refresh enabled
0.1 μA per channel quiescent current, refresh disabled
117 μA/Mbps per channel typical dynamic current
Small, 16-lead QSOP and 20-Lead SSOP
Bidirectional communication
Up to 2 Mbps data rate (NRZ)
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL 1577 component recognition program
2500 V rms for 1 minute per UL 1577 QSOP package
3750V rms for 1 minute per UL 1577 SSOP package
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 VPEAK QSOP package
VIORM = 849 VPEAK SSOP package
APPLICATIONS
General-purpose, low power multichannel isolation
1 MHz, low power peripheral interface (SPI)
4 mA to 20 mA loop process controls
GENERAL DESCRIPTION
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM14471 are micropower, 4-channel digital
isolators based on the Analog Devices, Inc., iCoupler® technology.
Combining high speed, complementary metal oxide semiconductor
(CMOS) and monolithic air core transformer technologies,
these isolation components provide outstanding performance
characteristics superior to the alternatives, such as optocoupler
devices. As shown in Figure 3, in standard operating mode,
when ENx = 0 (internal refresh enabled), the current per channel is
less than 10 μA. When ENx = 1 (internal refresh disabled), the
current per channel drops to less than 1 μA.
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 family of quad 2.5 kV digital isolation
devices are packaged in a small 16-lead QSOP and 20-lead SSOP,
freeing almost 70% of board space compared to isolators packages
in wide body SOIC packages.
FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
IC
/V
OC
V
ID
/V
OD
EN
1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC
/V
IC
V
OD
/V
ID
EN
2
GND
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADuM144x QSOP
11845-002
Figure 1.
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
V
IA
V
IB
V
IC
/V
OC
V
ID
/V
OD
EN
1
NIC
V
DD2
GND
2
V
OA
V
OB
V
OC
/V
IC
V
OD
/V
ID
EN
2
NIC
1
2
3
4
5
7
8
20
19
18
17
16
14
13
NIC
GND
1
NIC
GND
2
9
10
12
11
ADuM144x
ENCODE DECODE
615
11845-102
Figure 2.
The devices withstand high isolation voltages and meet regulatory
requirements, such as UL and CSA standards. In addition to the
space savings, the ADuM1440/ADuM1441/ADuM1442/
ADuM1445/ADuM1446/ADuM1447 operate with supplies as
low as 2.25 V.
Despite the low power consumption, all models of the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
provide low, pulse width distortion at <8 ns. In addition, every
model has an input glitch filter to protect against extraneous
noise disturbances.
0.1
1
10
100
1000
0.1 1 10 100 1000 10000
CURRENT PE R CH ANNEL
(
µA)
DATA RATE (kbps)
EN
x
= 1
EN
x
= 0
11845-001
Figure 3. Typical Total Supply Current per Channel (VDDx = 3.3 V)
1 Protected by U.S. Patents 5,952,849, 6,873,065, 7,075,329, 6,262,600. Other patents pending.
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—3.3 V Operation ............................ 3
Electrical Characteristics—2.5 V Operation ............................ 5
Electrical Characteristics—VDD1 = 3.3 V, VDD2 = 2.5 V
Operation ....................................................................................... 7
Electrical Characteristics—VDD1 = 2.5 V, VDD2 = 3.3 V
Operation ....................................................................................... 8
Package Characteristics ............................................................... 9
Regulatory Information ............................................................... 9
Insulation and Safety Related Specifications .......................... 10
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation
Characteristics ............................................................................ 10
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings ......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 16
Applications Information .............................................................. 19
Printed Circuit Board (PCB) Layout ....................................... 19
Propagation Delay-Related Parameters ................................... 19
DC Correctness ............................................................................ 19
Magnetic Field Immunity ............................................................. 20
Power Consumption .................................................................. 21
Insulation Lifetime ..................................................................... 21
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 24
REVISION HISTORY
4/15—Rev. C to Rev. D
Change to General Description Section ........................................ 1
4/15—Rev. B to Rev. C
Changes to Regulatory Information Section ................................ 9
3/15—Rev. A to Rev. B
Changes to Features Section and Figure 3 ..................................... 1
Changes to Table 12 .......................................................................... 9
Changes to Table 13 and Table 14 ................................................ 10
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 24
3/14—Rev. 0 to Rev. A
Added SSOP Package ......................................................... Universal
Changes to Features Section, Added Figure 2,
Renumbered Sequentially ................................................................ 1
Changes to Output Voltage Logic High Parameter, Table 3 ........ 4
Added Table 15, Renumbered Sequentially; Changes to
Figure 4 ............................................................................................ 11
Change to Supply Voltages (VDD1, VDD2) Parameter, Table 17 ........ 12
Added Figure 6; Changes to Table 20 .......................................... 13
Added Figure 8; Changes to Table 21 .......................................... 14
Added Figure 10, Changes to Table 22 ........................................ 15
Added Figure 30 ............................................................................. 19
Changes to Power Consumption Section; Added Table 23 ...... 21
Added Figure 27 ............................................................................. 23
Changes to Ordering Guide .......................................................... 24
10/13—Revision 0: Initial Version
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operating range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate
2
Mbps
Within pulse-width distortion (PWD) limit
Propagation Delay tPHL, tPLH 80 180 ns 50% input to 50% output
Change vs. Temperature 200 ps/°C
Minimum Pulse Width PW 500 ns Within PWD limit
Pulse-Width Distortion PWD 8 ns |tPLH − tPHL|
Propagation Delay Skew1 tPSK 10 ns
Channel Matching
Codirectional tPSKCD 10 ns
Opposing Direction tPSKOD 15 ns
1 tPSK is the magnitude of the worst-case difference in tPHL and tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT 2 Mbps, no load
ADuM1440/ADuM1445 IDD1 732 1000 µA ENX = 0 V, VIH = VDD, VIL = 0 V
I
DD2
492
750
µA
EN
X
= 0 V, V
IH
= V
DD
, V
IL
= 0 V
ADuM1441/ADuM1446 IDD1 672 900 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 552 900 µA ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1442/ADuM1447 IDD1 612 900 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 612 900 µA ENX = 0 V, VIH = VDD, VIL = 0 V
Rev. D | Page 3 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
Table 3. For All Models
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Threshold
Logic High VIH 0.7 VDDx1 V
Logic Low VIL 0.3 VDDx1 V
Output Voltages
Logic High VOH VDDx1 − 0.1 3.3 V IOUTx = −20 µA, VIx = VIxH
VDDx1 − 0.4 3.1 V IOUTx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOUTx = 20 µA, VIx = VIxL
0.2 0.4 V IOUTx = 4 mA, VIx = VIxL
Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VIx ≤ VDDx1
Input Switching Thresholds
Positive Threshold Voltage VT+ 1.8 V
Negative Going Threshold VT− 1.2 V
Input Hysteresis ΔVT 0.6 V
Undervoltage Lockout, VDD1 or VDD2 UVLO 1.5 V
Supply Current per Channel
Quiescent Current
Input Supply IDDI (Q) 4.8 10 µA ENX low
Output Supply IDDO (Q) 0.8 3.3 µA ENX low
Input (Refresh Off ) IDDI (Q) 0.12 µA ENX high
Output (Refresh Off)
I
DDO (Q)
0.13
µA
EN
X
high
Dynamic Supply Current
Input IDDI (D) 88 µA/Mbps
Output IDDO (D) 60 µA/Mbps
AC SPECIFICATIONS
Output Rise Time/Fall Time tR/tF 2 ns 10% to 90%
Common-Mode Transient Immunity2 |CM| 25 40 kV/µs VIx = VDDx1, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 14 kbps
1 VDDx = VDD1 or VDD2.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and
falling common-mode voltage edges.
Rev. D | Page 4 of 24
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
ELECTRICAL CHARACTERISTICS—2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire recommended
operating range of 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate 2 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 112 180 ns 50% input to 50% output
Change vs. Temperature 280 ps/°C
Pulse-Width Distortion PWD 12 ns |tPLH − tPHL|
Minimum Pulse Width PW 500 ns Within PWD limit
Propagation Delay Skew1 tPSK 10 ns
Channel Matching
Codirectional tPSKCD 10 ns
Opposing Direction
t
PSKOD
30
ns
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT 2 Mbps, no load
ADuM1440/ADuM1445 IDD1 623 800 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 337 500 µA ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1441/ADuM1446 IDD1 552 750 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 409 750 µA ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1442/ADuM1447
I
DD1
480
750
µA
EN
X
= 0 V, V
IH
= V
DD
, V
IL
= 0 V
IDD2 480 750 µA ENX = 0 V, VIH = VDD, VIL = 0 V
Rev. D | Page 5 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
Table 6. For All Models
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC SPECIFICATIONS
Input Threshold
Logic High VIH 0.7 VDDx1 V
Logic Low VIL 0.3 VDDx1 V
Output Voltages
Logic High VOH VDDx1 − 0.1 2.5 V IOx = −20 µA, VIx = VIxH
VDDx1 − 0.4 2.35 V IOx = −4 mA, VIx = VIxH
Logic Low VOL 0.0 0.1 V IOx = 20 µA, VIx = VIxL
0.1 0.4 V IOx = 4 mA, VIx = VIxL
Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VIx ≤ VDDx1
Input Switching Thresholds
Positive Threshold Voltage VT+ 1.5 V
Negative Going Threshold VT− 1.0 V
Input Hysteresis ΔVT 0.5 V
Undervoltage Lockout, VDD1 or VDD2 UVLO 1.5 V
Supply Current per Channel
Quiescent Current
Input Supply IDDI (Q) 2.6 3.3 µA ENX low
Output Supply IDDO (Q) 0.5 1.8 µA ENX low
Input (Refresh Off ) IDDI (Q) 0.05 µA ENX high
Output (Refresh Off)
I
DDO (Q)
0.05
µA
EN
X
high
Dynamic Supply Current
Input IDDI (D) 76 µA/Mbps
Output IDDO (D) 41 µA/Mbps
AC SPECIFICATIONS
Output Rise Time/Fall Time tR/tF 2 ns 10% to 90%
Common-Mode Transient Immunity2 |CM| 25 40 kV/µs VIx = VDDx1, VCM = 1000 V,
transient magnitude = 800 V
Refresh Rate fr 14 kbps
1 VDDx = VDD1 or VDD2.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and
falling common-mode voltage edges.
Rev. D | Page 6 of 24
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
ELECTRICAL CHARACTERISTICS—VDD1 = 3.3 V, VDD2 = 2.5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V, and.VDD2 = 2.5 V. Minimum/maximum specifications apply over the entire
recommended operating range of 3.0 V ≤ VDD1 ≤ 3.6 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
For dc specifications and ac specifications, see Table 3 for Side 1 and see Table 6 for Side 2.
Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate 2 Mbps Within PWD limit
Propagation Delay
Side 1 to Side 2
t
PHL
, t
PLH
84
180
ns
50% input to 50% output
Side 2 to Side 1 tPHL, tPLH 120 180 ns 50% input to 50% output
Change vs. Temperature 280 ps/°C
Pulse-Width Distortion PWD 12 ns |tPLH − tPHL|
Pulse Width PW 500 ns Within PWD limit
Propagation Delay Skew
1
t
PSK
10
ns
Channel Matching
Codirectional tPSKCD 10 ns
Opposing Direction tPSKOD 60 ns
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT 2 Mbps, no load
ADuM1440/ADuM1445 IDD1 732 1000 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 337 750 µA ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1441/ADuM1446 IDD1 672 900 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 409 750 µA ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1442/ADuM1447 IDD1 612 900 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 480 750 µA ENX = 0 V, VIH = VDD, VIL = 0 V
Rev. D | Page 7 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
ELECTRICAL CHARACTERISTICS—VDD1 = 2.5 V, VDD2 = 3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 2.5, and VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire
recommended operating range of 2.25 V ≤ VDD1 ≤ 2.75 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted.
For dc specifications and ac specifications, see Table 6 for Side 1 and see Table 3 for Side 2.
Table 9.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS
Data Rate 2 Mbps Within PWD limit
Propagation Delay
Side 1 to Side 2
t
PHL,
t
PLH
120
180
ns
50% input to 50% output
Side 2 to Side 1 tPHL, tPLH 84 180 ns 50% input to 50% output
Change vs. Temperature 200 ps/°C
Pulse-Width Distortion PWD 12 ns |tPLH − tPHL|
Pulse Width PW 500 ns Within PWD limit
Propagation Delay Skew
1
t
PSK
10
ns
Channel Matching
Codirectional tPSKCD 10 ns
Opposing Direction tPSKOD 60 ns
1 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
Table 10.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT 2 Mbps, no load
ADuM1440/ADuM1445 IDD1 623 1000 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 492 750 µA ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1441/ADuM1446 IDD1 552 750 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 552 900 µA ENX = 0 V, VIH = VDD, VIL = 0 V
ADuM1442/ADuM1447 IDD1 480 750 µA ENX = 0 V, VIH = VDD, VIL = 0 V
IDD2 612 900 µA ENX = 0 V, VIH = VDD, VIL = 0 V
Rev. D | Page 8 of 24
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
PACKAGE CHARACTERISTICS
Table 11.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input-to-Output)
1
R
I-O
10
13
Ω
Capacitance (Input-to-Output)1 CI-O 2 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction-to-Ambient Thermal
Resistance (QSOP)
θJA 76 °C/W Thermocouple located at center of package underside
IC Junction-to-Ambient Thermal
Resistance (SSOP)
θJA 50.5 °C/W Thermocouple located at center of package underside
1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
See Table 18 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross-isolation waveforms
and insulation levels.
Table 12.
UL CSA VDE
Recognized Under UL 1577 Component
Recognition Program
1
Approved under CSA Component
Acceptance Notice 5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
2
CSA 60950-1-07+A1+A2 and IEC 60950-1
second edition +A1+A2
Single Protection QSOP package QSOP package
2500 V RMS Isolation Voltage (RQ-16 Only) Basic insulation, 310 V rms maximum
working voltage
Reinforced insulation, 565 VPEAK QSOP package
3750 V RMS Isolation Voltage (RS-20 Only) SSOP package SSOP package
Basic insulation at 510 V rms (721 VPEAK)
maximum working voltage
Reinforced insulation, 849 VPEAK SSOP package
IEC60601-1 Edition 3.1 250 V (1 means of
patient protection (MOPP))
Reinforced insulation at 255 V rms
(360 VPEAK) maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 is proof tested by applying an insulation test voltage and
measuring leakage during final production testing. QSOP package devices are tested at ≥3000 V rms for 1 sec with a current leakage detection limit = 5 μA. SSOP
package devices are tested at ≥4500 V rms for 1 sec with a current leakage detection limit = 10 μA.
2 In accordance with DIN V VDE V 0884-10, each ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 is proof tested by applying an insulation test
voltage ≥1059 VPEAK for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
Rev. D | Page 9 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 13.
Parameter Symbol Value Unit Test Conditions/Comments
Rated Dielectric Insulation Voltage (RQ-16)
2500
V rms
1-minute duration
Rated Dielectric Insulation Voltage (RS-20) 3750 V rms 1-minute duration
Minimum External Tracking and Air Gap, RQ-16 (Creepage
and Clearance)
L(I02) 3.1 mm min Measured from input terminals to output
terminals, shortest distance path along
package body
Minimum Clearance in the Plane of the Printed Circuit
Board, RQ-16 (PCB Clearance)
L(I01) 3.8 mm min Measured from input terminals to output
terminals, shortest distance through air, line
of sight, in the PCB mounting plane
Minimum External Tracking and Air Gap, RS-20 (Creepage
and Clearance)
L(I01) 5.1 mm min Measured from input terminals to output
terminals, shortest distance path along
package body
Minimum Clearance in the Plane of the Printed Circuit
Board, RS-20 (PCB Clearance)
L(I02) 5.1 mm min Measured from input terminals to output
terminals, shortest distance through air, line
of sight, in the PCB mounting plane
Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table 1)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.
Table 14. 16-Lead QSOP (RQ-16)
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 565 VPEAK
Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd(m) 1059 VPEAK
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Vpd(m) 847 VPEAK
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Vpd(m) 678 VPEAK
Highest Allowable Overvoltage VIOTM 4000 VPEAK
Surge Isolation Voltage VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time VIOSM 6250 VPEAK
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 4)
Case Temperature TS 150 °C
Total Power Dissipation at 25°C IS1 1.64 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
Rev. D | Page 10 of 24
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
Table 15. 20-Lead SSOP (RS-20)
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to IV
For Rated Mains Voltage ≤ 400 V rms I to III
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 849 VPEAK
Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = Vpd(m), 100% production test, tini = tm =
1 sec, partial discharge < 5 pC
Vpd(m) 1592 VPEAK
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
Vpd(m) 1273 VPEAK
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd(m),tini = 60 sec, tm = 10 sec, partial
discharge < 5 pC
Vpd(m) 1018 VPEAK
Highest Allowable Overvoltage VIOTM 6000 VPEAK
Surge Isolation Voltage
V
PEAK
= 10 kV, 1.2 µs rise time, 50µs, 50% fall time
V
IOSM
6000
V
PEAK
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 4)
Case Temperature TS 150 °C
Total Power Dissipation at 25°C IS1 2.5 W
Insulation Resistance at TS VIO = 500 V RS >109 Ω
0
0.5
1.0
1.5
2.0
2.5
3.0
050 100 150 200
SAFE LIMITING POWER (W)
AMBIENT TEMPERATURE (°C)
11845-003
SSOP20
QSOP16
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 16.
Parameter Symbol Value
Operating Temperature TA −40°C to +125°C
Supply Voltages
1
V
DD1
, V
DD2
2.25 V to 3.6 V
Input Signal Rise and Fall Times 1.0 ms
1 All voltages are relative to their respective grounds. See the DC Correctness
section for information on immunity to external magnetic fields.
Rev. D | Page 11 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 17.
Parameter Rating
Supply Voltages (VDD1, VDD2) −0.5 V to +5 V
Input Voltages (VIA, VIB ) −0.5 V to VDDI + 0.5 V
Output Voltages (VOA, VOB) −0.5 V to VDD2 + 0.5 V
Average Output Current per Pin1
Side 1 (IO1) −10 mA to +10 mA
Side 2 (IO2) −10 mA to +10 mA
Common-Mode Transients
2
−100 kV/µs to +100 kV/µs
Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature
(TA) Range
−40°C to +125°C
1 See Figure 4 for maximum safety power values for various temperatures.
2 Refers to common-mode transients across the insulation barrier. Common-mode
transients exceeding the absolute maximum ratings can cause latch-up or
permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 18. Maximum Continuous Working Voltage1
Parameter Value Constraint
AC Voltage
60 Hz Bipolar Waveform 565 VPEAK 50-year minimum lifetime
60 Hz Unipolar Waveform
Basic Insulation
975 V
PEAK
50-year minimum lifetime
DC Voltage
Basic Insulation 975 VPEAK 50-year minimum lifetime
1 Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
ESD CAUTION
Table 19. Truth Table (Positive Logic) for all Models
VIx Input1, 2 VDDI State3 VDDO State4 ENx Input1 VOx Output1 Description
H Powered Powered L H Normal operation; data is high and refresh is enabled.
L Powered Powered L L Normal operation; data is low and refresh is enabled.
H
Powered
Powered
H
H
Output is high, and refresh is disabled.
L Powered Powered H L5 Output is low, and refresh is disabled.
L Unpowered Powered L Default Input unpowered. Outputs are in the default state, high for
ADuM1440, ADuM1441, and ADuM1442, and low ADuM1445,
ADuM1446, and ADuM1447. Outputs return to input state
within 150 µs of VDDI power restoration. See the pin function
descriptions (Table 20 through Table 22) for more details.
L Unpowered Powered H Hold Input unpowered. Outputs are the last state before input
power is shut down.
X Powered Unpowered X Z Output unpowered. Output pins are in high impedance state.
Outputs return to input state within 34 µs of VDDO power
restoration. See the pin function descriptions (Table 20 through
Table 22) for more details.
1 H = high, L = low, X = don’t care, and Z = high impedance.
2 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
3 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D).
4 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).
5 Low input must follow a falling edge; otherwise, it can be in the default low state.
Rev. D | Page 12 of 24
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD1 1
GND
112
V
IA 3
V
IB 4
V
DD2
16
GND
22
15
V
OA
14
V
OB
13
V
IC 5
V
OC
12
V
ID 6
V
OD
11
EN
17
EN
2
10
GND
118
GND
22
9
ADuM1440/
ADuM1445
TOP VIEW
(No t t o Scal e)
1
PIN 2 AND P IN 8 ARE INTE RNALL Y CONNECTED. CONNECTING BO TH
TO GND
1
IS RECOMMENDED.
2
PIN 9 AND P IN 15 ARE INT ERNALL Y CONNECTED. CONNECTING
BOTH TO GND
2
IS RECOMMENDED.
11845-004
Figure 5. ADuM1440/ADuM1445 QSOP Pin Configuration
VDD1 1
GND112
VIA 3
VIB 4
VDD2
NIC = NOT INT E RNALLY CONNECTED.
20
GND22
19
VOA
18
VOB
17
VIC 5VOC
16
VID 6VOD
15
EN17EN2
14
NIC 8NIC
13
NIC 9NIC
12
GND1110 GND22
11
ADuM1440/
ADuM1445
TOP VIEW
(No t t o Scal e)
11845-104
1PIN 2 AND P IN 10 ARE INT E RNALLY CONNECTED.
CONNECTING BOTH TO GND1 IS RECOMMENDED.
2PIN 11 AND P IN 19 ARE INT ERNALL Y CONNECTED.
CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 6. ADuM1440/ADuM1445 SSOP Pin Configuration
Table 20. ADuM1440/ADuM1445 Pin Function Descriptions1
QSOP
Pin No.2
SSOP
Pin No. Mnemonic Description
1 1 VDD1 Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between VDD1 (Pin 1) and GND1 (Pin 2).
2, 8 2, 10 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting
both to GND1 is recommended.
3 3 VIA Logic Input A.
4 4 VIB Logic Input B.
5 5 VIC Logic Input C.
6 3 VID Logic Input D.
7 7 EN1 Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables input/output refresh and
watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for a detailed description of this mode. EN1 and EN2 must be set to the same
logic state.
9, 15 11, 19 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and
connecting both to GND2 is recommended.
10 14 EN2 Refresh/Watchdog Enable 2. Connecting Pin 10 to GND2 enables input/output refresh and
watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 10 to VDD2
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for a detailed description of this mode. EN1 and EN2 must be set to the same
logic state.
11 15 VOD Logic Output D.
12 16 VOC Logic Output C.
13 17 VOB Logic Output B.
14 18 VOA Logic Output A.
16 20 VDD2 Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between VDD2 (Pin 16) and GND2 (Pin 15).
N/A 8, 9, 12, 13 NC No Connect. Do not connect to this pin.
1 Reference the AN-1109 Application Note for specific layout guidelines.
2 N/A = not applicable.
Rev. D | Page 13 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
VDD1 1
GND112
VIA 3
VIB 4
VDD2
16
GND22
15
VOA
14
VOB
13
VIC 5VOC
12
VOD 6VID
11
EN17EN2
10
GND118GND22
9
ADuM1441/
ADuM1446
TOP VIEW
(No t t o Scal e)
1PIN 2 AND P IN 8 ARE INTE RNALL Y CONNECTED. CONNECTING BO TH
TO GND1 IS RECOMMENDED.
2PIN 9 AND P IN 15 ARE INT ERNALL Y CONNECTED. CONNECTING
BOTH TO GND2 IS RECOMMENDED.
11845-005
Figure 7. ADuM1441/ADuM1446 QSOP Pin Configuration
VDD1 1
GND112
VIA 3
VIB 4
VDD2
NIC = NOT INT E RNALLY CONNECTED.
20
GND22
19
VOA
18
VOB
17
VIC 5VOC
16
VOD 6VID
15
EN17EN2
14
NIC 8NIC
13
NIC 9NIC
12
GND1110 GND22
11
ADuM1441/
ADuM1446
TOP VIEW
(No t t o Scal e)
1PIN 2 AND P IN 10 ARE INT E RNALLY CONNECTED.
CONNECTING BOTH TO GND1 IS RECOMMENDED.
2PIN 11 AND P IN 19 ARE INT ERNALL Y CONNECTED.
CONNECTING BOTH TO GND2 IS RECOMMENDED.
11845-108
Figure 8. ADuM1441/ADuM1446 SSOP Pin Configuration
Table 21. ADuM1441/ADuM1446 Pin Function Descriptions1
QSOP
Pin No. 2
SSOP
Pin No. Mnemonic Description
1 1 VDD1 Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between VDD1 (Pin 1) and GND1 (Pin 2).
2, 8 2, 10 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting
both to GND1 is recommended.
3 3 VIA Logic Input A.
4 4 VIB Logic Input B.
5 5 VIC Logic Input C.
6 3 VOD Logic Output D.
7 7 EN1 Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables input/output refresh and
watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for a detailed description of this mode. EN1 and EN2 must be set to the same
logic state.
9, 15 11, 19 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and
connecting both to GND2 is recommended.
10 14 EN2 Refresh/Watchdog Enable 2. Connecting Pin 10 to GND2 enables input/output refresh and
watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 10 to VDD2
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for a detailed description of this mode. EN1 and EN2 must be set to the same
logic state.
11 15 VID Logic Input D.
12 16 VOC Logic Output C.
13 17 VOB Logic Output B.
14 18 VOA Logic Output A.
16 20 VDD2 Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between VDD2 (Pin 16) and GND2 (Pin 15).
N/A 8, 9, 12, 13 NC No Connect. Do not connect to this pin.
1 Reference the AN-1109 Application Note for specific layout guidelines.
2 N/A = not applicable.
Rev. D | Page 14 of 24
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
V
DD1 1
GND
112
V
IA 3
V
IB 4
V
DD2
16
GND
22
15
V
OA
14
V
OB
13
V
OC 5
V
IC
12
V
OD 6
V
ID
11
EN
17
EN
2
10
GND
118
GND
22
9
ADuM1442/
ADuM1447
TOP VIEW
(No t t o Scal e)
1
PIN 2 AND P IN 8 ARE INT E RNALLY CONNECTED. CONNECTING BO TH
TO GND
1
IS RECOMMENDED.
2
PIN 9 AND P IN 15 ARE INT E RNALLY CONNECTED. CONNECTING
BOTH TO GND
2
IS RECOMMENDED.
11845-006
Figure 9. ADuM1442/ADuM1447 QSOP Pin Configuration
V
DD1 1
GND
112
V
IA 3
V
IB 4
V
DD2
NIC = NOT INT ERNALL Y CONNECTED.
20
GND
22
19
V
OA
18
V
OB
17
V
OC 5
V
IC
16
V
OD 6
V
ID
15
EN
17
EN
2
14
NIC
8
NIC
13
NIC
9
NIC
12
GND
1110
GND
22
11
ADuM1442/
ADuM1447
TOP VIEW
(No t t o Scal e)
11845-110
1
PIN 2 AND P IN 10 ARE INT ERNALL Y CONNECTED.
CONNECTING BOTH TO GND
1
IS RECOMMENDED.
2
PIN 11 AND P IN 19 ARE INTE RNALL Y CONNECTED.
CONNECTING BOTH TO GND
2
IS RECOMMENDED.
Figure 10. ADuM1442/ADuM1447 SSOP Pin Configuration
Table 22. ADuM1442/ADuM1447 Pin Function Descriptions1
QSOP
Pin No. 2
SSOP
Pin No. Mnemonic Description
1 1 VDD1 Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between VDD1 (Pin 1) and GND1 (Pin 2).
2, 8 2, 10 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting
both to GND1 is recommended.
3
3
V
IA
Logic Input A.
4 4 VIB Logic Input B.
5 5 VOC Logic Output C.
6 3 VOD Logic Output D.
7 7 EN1 Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables input/output refresh and
watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for detailed description of this mode. EN1 and EN2 must be set to the same
logic state.
9, 15 11, 19 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and
connecting both to GND2 is recommended.
10
14
EN
2
Refresh/Watchdog Enable 2. Connecting Pin 10 to GND
2
enables input/output refresh and
watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 10 to VDD2
disables refresh and watchdog functionality for lowest power operation, see the Applications
Information section for a detailed description of this mode. EN1 and EN2 must be set to the same
logic state.
11 15 VID Logic Input D.
12
16
V
IC
Logic Input C.
13 17 VOB Logic Output B.
14 18 VOA Logic Output A.
16 20 VDD2 Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the 0.01
µF to 0.1 µF range between VDD2 (Pin 16) and GND2 (Pin 15).
N/A 8, 9, 12, 13 NC No Connect. Do not connect to this pin.
1 Reference the AN-1109 Application Note for specific layout guidelines.
2 N/A = not applicable.
Rev. D | Page 15 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
50
100
150
200
250
300
350
0500 1000 1500 2000
CURRENT CONSUM P TI ON PER INPUT (µ A)
DATA RATE (kbps)
V
DDx
INPUT CURRENT
11845-007
0
5
10
15
020 40
Figure 11. Current Consumption per Input vs. Data Rate for 2.5 V,
ENx = Low Operation
0
10
20
30
40
50
60
70
80
90
0500 1000 1500 2000
CURRENT CONSUM P TI ON PER OUT P UT (µ A)
DATA RATE (kbps)
V
DDx
OUT P UT CURRENT
11845-008
0
2
4
020 40
Figure 12. Current Consumption per Output vs. Data Rate for 2.5 V,
ENx = Low Operation
0
50
100
150
200
250
300
350
400
0500 1000 1500 2000
CURRENT CONSUM P TI ON PER INPUT (µA)
DATA RATE (kbps)
VDDx INP UT CURRENT
11845-009
0
5
10
15
020 40
Figure 13. Current Consumption per Input vs. Data Rate for 3.3 V,
ENx = Low Operation
0
20
40
60
80
100
120
140
0500 1000 1500 2000
CURRENT CONSUM P TI ON PER OUT P UT (µ A)
DATA RATE (kbps)
V
DDx
OUT P UT CURRENT
11845-010
0
2
4
020 40
Figure 14. Current Consumption per Output vs. Data Rate for 3.3 V,
ENx = Low Operation
0
20
40
60
80
100
120
140
160
0500 1000 1500 2000
CURRENT CONSUM P TI ON PER INPUT (µ A)
DATA RATE (kbps)
VDDx INP UT CURRENT
11845-011
0
0.5
1.0
0 5 10
Figure 15. Current Consumption per Input vs. Data Rate for 2.5 V,
ENx = High Operation
0
10
20
30
40
50
60
70
80
90
0500 1000 1500 2000
CURRENT CONSUM P TI ON PER OUT P UT (µ A)
DATA RATE (kbps)
V
DDx
OUT P UT CURRENT
11845-012
0
0.5
1.0
0 5 10
Figure 16. Current Consumption per Output vs. Data Rate for 2.5 V,
ENx = High Operation
Rev. D | Page 16 of 24
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
0
20
60
40
100
80
120
140
160
180
200
0500 1000 1500 2000
CURRENT CONSUM P TI ON PER INPUT (µ A)
DATA RATE (kbps)
VDDx INP UT CURRENT
11845-013
0
0.5
1.0
0 5 10
Figure 17. Current Consumption per Input vs. Data Rate for VDDX = 3.3 V,
ENx = High Operation
0
20
40
60
80
100
120
140
0500 1000 1500 2000
CURRENT CONSUM P TI ON PER OUT P UT (µ A)
DATA RATE (kbps)
V
DDx
OUT P UT CURRENT
11845-014
0
0.5
1.0
0 5 10
Figure 18. Current Consumption per Output vs. Data Rate for VDDx = 3.3 V,
ENx = High Operation
0
100
200
300
400
500
600
0 1 2 3 4
I
DDx
CURRENT ( µ A)
DATA INPUT VOLTAGE (V)
FALLING
RISING
11845-015
Figure 19. Typical IDDx Current per Input vs.
Data Input Voltage for VDDx = 3.3 V
0
50
100
150
200
250
300
00.5 1.0 1.5 2.0 2.5 3.0
I
DDx
CURRENT ( µ A)
DATA INPUT VOLTAGE (V)
FALLING
RISING
11845-016
Figure 20. IDDx Current per Input vs. Data Input Voltage for VDDx = 2.5 V
0
1
2
3
4
5
6
7
8
9
10
–40 –20 020 40 60 80 100 120 140
SUPPLY CURRENT / CHANNEL (µA)
TEMPERATURE ( °C)
OUTPUT
INPUT
11845-117
Figure 21. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 2.5 V, Data Rate = 100 kbps
0
1
2
3
4
5
6
7
8
9
10
–40 –20 020 40 60 80 100 120 140
SUPPLY CURRENT / CHANNEL (µA)
TEMPERATURE ( °C)
OUTPUT
INPUT
11845-118
Figure 22. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 3.3 V, Data Rate = 100 kbps
Rev. D | Page 17 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
Rev. D | Page 18 of 24
0
10
20
30
40
50
60
70
80
90
100
–40 –20 0 20 40 60 80 100 120 140
SUPPLY CURRENT/CHANN EL
(
µA)
TEMPERATURE (°C)
OUTPUT
INPUT
11845-119
Figure 23. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 2.5 V, Data Rate = 1000 kbps
0
10
20
30
40
50
60
70
80
90
100
–40 –20 0 20 40 60 80 100 120 140
SUPPLY CURRE N T/ CHANNEL (µA)
TEMPERAT URE (°C)
OUTPUT
INPUT
11845-120
Figure 24. Typical Input and Output Supply Current per Channel vs.
Temperature for VDDx = 3.3 V, Data Rate = 1000 kbps
0
20
40
60
80
100
120
140
–40 –20 0 20 40 60 80 100 120 140
PROPA
G
A
TION DEL
A
Y (n s)
TE M P ERAT URE (°C)
VDDx = 2.5V
VDDx = 3.3V
11845-121
Figure 25. Typical Propagation Delay vs. Temperature for
VDDx = 3.3 V or VDDx = 2.5 V
0
20
40
60
80
100
120
2.0 2.5 3.0 3.5 4.0
GLITCH F ILTE R WIDTH (ns)
TRANSM I TT ER V
DDx
(V)
11845-017
Figure 26. Typical Glitch Filter Operation Threshold
0
20
40
60
80
100
120
140
–40 –20 0 20 40 60 80 100 120 140
REFRESH PERI OD (µs)
TEMPERATURE (°C)
V
DDx
= 2.5V
V
DDx
= 3.3V
11845-122
Figure 27. Typical Refresh Period vs. Temperature for
3.3 V and 2.5 V Operation
0
20
40
60
80
100
120
2.0 2.5 3.0 3.5 4.0
REFRESH PERIOD (µs)
V
DDx
VOLTAGE (V)
11845-123
Figure 28. Typical Refresh Period vs. VDDX Voltage
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at both input and output supply pins:
VDD1 and VDD2 (see Figure 29). Choose a capacitor value between
0.01 µF and 0.1 µF. The total lead length between both ends of the
capacitor and the input power supply pin must not exceed 20 mm.
Using proper PCB design choices, the ADuM1440/ADuM1441/
ADuM1442/ADuM1445/ADuM1446/ADuM1447 readily meets
CISPR 22 Class A (and FCC Class A) emissions standards, as
well as the more stringent CISPR 22 Class B (and FCC Class B)
standards in an unshielded environment. Refer to the AN-1109
Application Note, Recommendations for Control of Radiated
Emissions with iCoupler Devices, for PCB-related EMI mitigation
techniques, including board layout and stack-up issues.
VDD1
GND1
VIA
VIB
VIC/VOC
VID/VOD
EN1
GND1
VDD2
GND2
VOA
VOB
VOC/VIC
VOD/VID
EN2
GND2
11845-018
Figure 29. Recommended Printed Circuit Board Layout, QSOP
V
DD1
GND
1
V
IA
V
IB
V
IC/
V
OC
V
ID/
V
OD
NC/CTRL
1
EN
1
NC
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC/
V
IC
V
OD/
V
ID
CTRL
2
NC/EN
2
NC
GND
2
11845-126
Figure 30. Recommended Printed Circuit Board Layout, SSOP
For applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, design the board layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage.
PROPAGATION DELAY-RELATED PARAMETERS
These products are optimized for minimum power consumption
by eliminating as many internal bias currents as possible. As a
result, the timing characteristics are more sensitive to operating
voltage and temperature than in standard iCoupler products.
Refer to Figure 21 through Figure 28 for the expected variation
of these parameters.
Propagation delay is a parameter defined as the time it takes a
logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition can
differ from the propagation delay time of a low-to-high transition.
INPUT(V
Ix
)
OUTPUT(V
Ox
)
t
PLH
t
PHL
50%
50%
11845-019
Figure 31. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching is the maximum amount of time
the propagation delay differs between channels within a single
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 component.
Propagation delay skew is the maximum amount of time the
propagation delay differs between multiple ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
components operating under the same conditions.
In edge-based systems, it is critical to reject pulses that are too
short to be handled by the encode and decode circuits. The
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 implement a glitch filter to reject pulses less than
the glitch filter operating threshold. This threshold depends on
the operating voltage, as shown in Figure 26. Any pulse shorter
than the glitch filter does not pass to the output. When the refresh
circuit is enabled, pulses that match the glitch filter width have a
small probability of being stretched until corrected by the next
refresh cycle, or by the next valid data through that channel. To
avoid issues with pulse stretching, observe the minimum pulse
width requirements listed in the switching specifications.
DC CORRECTNESS
Standard Operating Mode
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. When
refresh and watchdog functions are enabled by pulling EN1 and
EN2 low, in the absence of logic transitions at the input for more
than ~140 µs, a periodic set of refresh pulses indicative of the
correct input state is sent to ensure dc correctness at the output. If
the decoder receives no internal pulses of more than approximately
200 µs, the input side is assumed unpowered or nonfunctional,
in which case, the isolator watchdog circuit forces the output to
a default state. The default state is either high as in the ADuM1440,
ADuM1441, and ADuM1442 versions, or low as in the ADuM1445,
ADuM1446, and ADuM1447 versions.
Low Power Operating Mode
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 allow the refresh and watchdog
functions to be disabled by pulling EN1 and EN2 to logic high for
the lowest power consumption. These control pins must be set to
the same value on each side of the component for proper operation.
Rev. D | Page 19 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
In this mode, the current consumption of the chip drops to the
microamp range. However, be careful when using this mode
because dc correctness is no longer guaranteed at startup. For
example, if the following sequence of events occurs:
1. Power is applied to Side 1
2. A high level is asserted on the VIA input
3. Power is applied to Side 2
The high on VIA is not automatically transferred to the Side 2
VOA, and there can be a level mismatch that is not corrected until a
transition occurs at VIA. After power is stable on each side and a
transition occurs on the input of the channel, that channel’s input
and output state is correctly matched. This contingency can be
addressed in several ways, such as sending dummy data, or toggling
refresh on for a short period to force synchronization after turn on.
Recommended Input Voltage for Low Power Operation
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 implement Schmitt trigger input buffers
so that the devices operate cleanly in low data rate or noisy
environments. Schmitt triggers allow a small amount of shoot
through current when their input voltage is not approximate to
either VDDx or GNDx levels. This is because the two transistors are
both slightly on when input voltages are in the middle of the supply
range. For many digital devices, this leakage is not a large portion
of the total supply current and may not be noticed; however, in
the ultralow power ADuM1440/ADuM1441/ADuM1442/
ADuM1445/ADuM1446/ADuM1447, this leakage can be larger
than the total operating current of the device and cannot be
ignored.
To achieve optimum power consumption with the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ ADuM1447,
always drive the inputs as near to VDDx or GNDx levels as possible.
Figure 19 and Figure 20 illustrate the shoot through leakage of
an input; therefore, whereas the logic thresholds of the input are
standard CMOS levels, optimum power performance is achieved
when the input logic levels are driven within 0.5 V of either
VDDx or GNDx levels.
MAGNETIC FIELD IMMUNITY
The magnetic field immunity of the ADuM1440/ADuM1441/
ADuM1442/ADuM1445/ADuM1446/ADuM1447 is determined
by the changing magnetic field, which induces a voltage in the
receiving coil of the transformer large enough to either falsely
set or reset the decoder. The following analysis defines the
conditions under which this can occur. The 3.3 V operating
condition of the ADuM1440/ADuM1441/ADuM1442/
ADuM1445/ADuM1446/ADuM1447 is examined because it
represents the most typical mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑ π rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
and an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field at a given frequency can be calculated. The result
is shown in Figure 32.
1000
1k 100M10k
MAXIMUM ALLOWABLE MAGNETIC FLUX (kgauss)
100k 1M 10M
MAG NE TIC FI E LD FRE QUENCY ( Hz )
100
10
1
0.1
0.01
0.001
11845-020
Figure 32. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.5 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurred during a transmitted pulse
(and was of the worst-case polarity), it would reduce the received
pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
transformers. Figure 33 shows these allowable current magnitudes
as a function of frequency for selected distances. As shown, the
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 are extremely immune and can be affected only by
extremely large currents operating at a high frequency very near
to the component. For the 1 MHz example noted previously, a
1.2 kA current would have to be placed 5 mm away from the
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/
ADuM1447 to affect the operation of the component.
Rev. D | Page 20 of 24
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
1k 100M10k
MAXIMUM ALLOWABLE CURRENT (kA)
100k 1M 10M
MAGNETIC FIELD FREQUENCY (Hz)
DISTANCE = 5mm
DISTANCE = 100mm
DISTANCE = 1m
1000
100
10
1
0.1
0.01
11845-021
Figure 33. Maximum Allowable Current for Various Current-to-ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large enough to trigger the thresholds of
succeeding circuitry. Take care in the layout of such traces to
avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
isolator is a function of the supply voltage, the data rate of the
channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
f is the input logic signal frequency (MHz); it is half the input
data rate, expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 11 through
Figure 18 show per channel supply currents as a function of
data rate for an unloaded output condition.
The ADuM1440/ADuM1441/ADuM1442/ADuM1445/
ADuM1446/ADuM1447 devices are intended to operate at an
ultralow current. This is achieved by operating the part at a low
average data rate, either by bursting data at high speed at a low
duty factor or by running low bit rates. If data is burst at high
data rates, the part sits quiescent for the majority of the time, at
low data rates, the power consumption approaches the
quiescent power consumption. Table 23 shows the typical
current for an input and output channel pair as well as the total
power dissipated for that channel. The total power is summed
across both sides of the device, so the power is being drawn
from two different supplies. However, it shows how the power
depends on the VDD values and the state of the refresh.
Table 23. Typical Total Power Dissipation Per Channel
State of
Refresh
Typical Input
Channel
Typical Output
Channel
Power/Ch
VDDI IDDI(Q) VDDO IDDO(Q)
Enabled 2.5 V 2.6 µA 2.5 V 0.5 µA 7.8 µW
3.3 V 4.8 µA 3.3 V 0.8 µA 18.5 µW
Disabled 2.5 V 0.05 µA 2.5 V 0.05 µA 0.3 µW
3.3 V 0.12 µA 3.3 V 0.13 µA 0.8 µW
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the
lifetime of the insulation structure within the ADuM1440/
ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447.
Analog Devices performs accelerated life testing using voltage levels
higher than the rated continuous working voltage. Acceleration
factors for several operating conditions are determined. These
factors allow calculation of the time to failure at the actual
working voltage. The values shown in Table 18 summarize the
peak voltage for 50 years of service life for a bipolar ac operating
condition and the maximum CSA approved working voltages.
In many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life, in some cases.
The insulation lifetime of the ADuM1440/ADuM1441/
ADuM1442/ADuM1445/ADuM1446/ADuM1447 depends on
the voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 34, Figure 35, and Figure 36 illustrate these
different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
Rev. D | Page 21 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
voltages while still achieving a 50-year service life. The working
voltages listed in Table 18 can be applied while maintaining the
50-year minimum lifetime provided the voltage conforms to
either the unipolar ac or dc voltage case. Treat any cross-insulation
voltage waveform that does not conform to Figure 35 or Figure 36
as a bipolar ac waveform, and limit its peak voltage to the 50-year
lifetime voltage value listed in Table 18.
Note that the voltage presented in Figure 35 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
0V
RATED P E AK V OL TAGE
11845-022
Figure 34. Bipolar AC Waveform
0V
RATED P E AK V OL TAGE
11845-023
Figure 35. Unipolar AC Waveform
0V
RATED P E AK V OL TAGE
11845-024
Figure 36. DC Waveform
Rev. D | Page 22 of 24
Data Sheet ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447
OUTLINE DIMENSIONS
COMPLIANT TO JEDE C S TANDARDS MO-137- AB
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED- OF F INCH E QUIVALENTS FOR
REF ERE NCE ON LY AND ARE NO T APPROPRIATE FOR USE IN DESIGN.
16 9
8
1
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025 (0. 64)
BSC
0.041 (1. 04)
REF
0.010 ( 0.25)
0.006 ( 0.15)
0.050 (1.27)
0.016 (0.41)
0.020 (0.51)
0.010 (0.25)
8°
0°
COPLANARITY
0.004 ( 0.10)
0.065 (1.65)
0.049 (1.25) 0.069 (1. 75)
0.053 (1. 35)
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
0.158 (4.01)
0.154 (3.91)
0.150 (3.81) 0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
09-12-2014-A
Figure 37. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
(Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDE C S TANDARDS MO-150- AE
060106-A
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 M IN
0.65 BSC
2.00 M AX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 38. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
Rev. D | Page 23 of 24
ADuM1440/ADuM1441/ADuM1442/ADuM1445/ADuM1446/ADuM1447 Data Sheet
ORDERING GUIDE
Model1, 2
Number
of Inputs,
VDD1 Side
Number
of Inputs,
VDD2 Side
Maximum
Data Rate
(Mbps)
Default
Output
State
Maximum
Propagation
Delay, 3.3 V (ns)
Temperature
Range
Package
Description
Package
Option
ADuM1440ARQZ 4 0 2 High 180 −40°C to +125°C 16-Lead QSOP RQ-16
ADuM1441ARQZ 3 1 2 High 180 −40°C to +125°C 16-Lead QSOP RQ-16
ADuM1442ARQZ 2 2 2 High 180 −40°C to +125°C 16-Lead QSOP RQ-16
ADuM1445ARQZ 4 0 2 Low 180 −40°C to +125°C 16-Lead QSOP RQ-16
ADuM1446ARQZ 3 1 2 Low 180 −40°C to +125°C 16-Lead QSOP RQ-16
ADuM1447ARQZ 2 2 2 Low 180 −40°C to +125°C 16-Lead QSOP RQ-16
ADuM1440ARSZ 4 0 2 High 180 −40°C to +125°C 20-Lead SSOP RS-20
ADuM1441ARSZ 3 1 2 High 180 −40°C to +125°C 20-Lead SSOP RS-20
ADuM1442ARSZ 2 2 2 High 180 −40°C to +125°C 20-Lead SSOP RS-20
ADuM1445ARSZ 4 0 2 Low 180 −40°C to +125°C 20-Lead SSOP RS-20
ADuM1446ARSZ 3 1 2 Low 180 −40°C to +125°C 20-Lead SSOP RS-20
ADuM1447ARSZ
2
2
2
Low
180
−40°C to +125°C
20-Lead SSOP
RS-20
EVAL-ADUM1441EBZ Evaluation
Board
1 Z = RoHS Compliant Part.
2 Tape and reel is available. The addition of the –RL7 suffix indicates that the product is shipped on 7” tape and reel.
©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11845-0-4/15(D)
Rev. D | Page 24 of 24
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