DSP56309UMAD - Freescale Semiconductor / Motorola

1 Introduction

This document provides updated information for revision 0 of the DSP56309 User’s Manual

(DSP56309UM/D). The updates include the following:

• Modified signal definitions

• New Operating Mode Register (OMR) layout and bit definitions

• Updated SCI Receive Register (SRX) description

• Updated OMR and Timer Registers (TLR, TCPR, TCR) programming sheets

2 Modif ied Signal Definition s

Area to Change Change Description

Table 2-1, p. 2-3 • Change Ground (GND) to Ground (GND)5.

• Add Note 5 as follows:

5. The number of Ground signals listed are for the 144-pin TQFP package.

For the 196-ball MAP-BGA package, there are 66 GND connections.

Figure 2-1, p. 2-4 • Change HA10 to HA10

• Change HRW to HRW

• Change AA0–AA3 to AA0–AA3

• Change TMS to TMS

• Change Grounds: to Grounds4:

• At the bottom of the figure, add the following note:

4. The GND signals are listed for the 144-pin TQFP package. For the 196-ball

MAP-BGA pack age, all grounds except GNDP and GNDP1 are connected together

and referenced as GND. There are 64 GND connections.

Table 2-3, p. 2-7 • Change the note at the end of the table to the following:

Note: The subsystem GND signals (GNDQ, GND A, GNDD, GNDC, G N D H, and

GNDS) are listed for the 144-pin TQFP package. For the 196-ball MAP-BGA

package, all grounds except GNDP and GNDP1 are connected together inside

the package and referenced as GND.

Ta ble 2-8, pp. 2-11 to

2-12 • Change BR signal State During Reset, Stop, or Wait to:

Reset: Output (deasserted)

State during Stop/Wait depends on BRH bit setting:

• BRH = 0: Output, deasserted

• BRH = 1: Maintains last state (that is, if asserted, remains asserted)

• Change BB signal State During Reset, Stop, or Wait to Ignored input

Addendum

DSP56309UMAD/D

Rev. 1, 11/2002

DSP56309 User’s

Manual Addendum

CONTENTS

1 Introduction...............1

2 Modified Signal

Definitions.................1

3 Operating Mode

and Definition............3

4 SCI Receive Re gister

(SRX) Description .....3

5 Updated Programming

Sheets.........................3

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Modified Signal Definitions

Table 2-11, pp. 2-17

to 2-21 • Change the title of the third column to State During Reset1,2.

• Add the following notes to the end of the table:

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines are tri-stated.

2. The Wait processing state does not affect the signal state.

• Change State During Reset or Stop for all signals to Ignored input.

• Change the signal description for PB14 to:

Port B14—When the HI08 is configured as GPIO through the HPCR, this signal is

individually programmed through the HDDR.

Table 2-12, pp. 2-22

to 2-25 • Change the title for the third column to State During Reset1,2.

• Change State During Reset for all signals to Ignored input.

• Add notes that state:

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines are tri-stated.

2. The Wait processing state does not affect the signal state.

• For all signals, delete the middle paragraph in the signal description. ESSI0 does not

support keeper circuits.

• For all signals, change PCR0 to PCRC and PRR0 to PRRC.

Table 2-13, pp. 2-26

to 2-28 • Change the title for the third column to State During Reset1,2.

• Change State During Reset for all signals to Ignored input.

• Add notes that state:

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines are tri-stated.

2. The Wait processing state does not affect the signal state.

• For all signals, delete the middle paragraph in the signal description. ESSI1 does not

support keeper circuits.

• For all signals, change PCR1 to PCRD and PRR1 to PRRD.

Table 2-14, pp. 2-29

to 2-30 • Change the title for the third column to State During Reset1,2.

• Change State During Reset for all signals to Ignored input.

• Add notes that state:

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines are tri-stated.

2. The Wait processing state does not affect the signal state.

• For all signals, delete the middle paragraph in the signal description. The SCI does not

support keeper circuits.

• For all signals, change PCR to PCRE and PRR to PRRE.

Table 2-15, p. 2-31 • Change the title for the third column to State During Reset1,2.

• Change State During Reset for all signals to Ignored input.

• Add notes that state:

Notes: 1. In the Stop state, the signal maintains the last state as follows:

• If the last state is input, the signal is an ignored input.

• If the last state is output, these lines are tri-stated.

2. The Wait processing state does not affect the signal state.

• For all signals, delete the middle paragraph in the signal description. The triple timer

module does not support keeper circuits.

Area to Change Change Description

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Operating Mode Register (OMR) Layout and Definition

3 Operating Mode Register (OMR) Layout and Definition

4 SCI Receive Register (SRX) Description

5 Updated Programming Sheets

Use the following examples to replace Figure D-2 and Figure D-21 in the DSP56309 User’s Manual.

Area to Change Change Description

Figure 4-3, p. 4-17 Replace with the following:

Stack Control/Status (SCS) Extended Operating Mode (EOM) Chip Operating Mode (COM)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP[1–0] MS SD EBD MD MC MB MA

Reset:

0000000000000011 0 000****

* After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA, respectively).

SEN—Stack Ex tension Enab le ATE—Address Tracing Enable MS—Mem ory Switc h Mode

WRP—Extended Stack Wrap Flag APD—Address Priority Disable SD—Stop Delay

EOV—Extended Stack Overflow Flag ABE—Asynch. Bus Arbitration Enable EBD—External Bus Disable

EUN—Extended Stack Underflow Flag BRT—Bus Release Timing MD—Operating Mode D

XYS—Stack Extension Space Select TAS—TA Synchronize Select MC—Operating Mode C

BE—Burst Mode Enable MB—Operating Mode B

CDP1—Core-DMA Priority 1 MA—Operating Mode A

CDP0—Core-DMA Priority 0

Reserved bit. Read as zero; write to zero for future compatibility

Figure 4-3. Operating Mode Register (OMR)

Area to Change Change Description

Section 8.6.4.1, p.

8-20 Change the beginning of the fourth paragraph from “In Synchronous mode” to “In

Asynchronous mode”.

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Updated Programming Sheets

Figure D-2. Operating Mode Register (OMR)

Central Processor

Operating Mode Register

Reset = $00030X; X = latched from levels on Mode pins

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MS EBD MC MB MA

19 18 17 1623 22 21 20 SDBRT TAS CPD0

* = Reserved, Program as 0

BEEUN APD ABE MD

Stack Extension Enable, Bit 20

0 = Stack extension disabled

1 = Stack extension enabled

Stack Extension Wrap Flag, Bit 19

0 = No stack extension wrap

1 = Stack extension wrap (sticky bit)

Stack Extension Overflow Flag, Bit 18

0 = No stack overflow

1 = Stack overflow

Stack Extension X Y Select, Bit 16

0 = Mapped to X memory

1 = Mapped to Y memory

Stack Extension Underflow Flag, Bit 17

0 = No stack underflow

1 = Stack underflow

0 = Enables external bus

1 = Disables external bus

External Bus Disable, Bit 4

0 = Delay is 128K clock cycles

1 = Delay is 16 clock cycles

Memory Switch Mode, Bit 7

0 = Memory switching disabled

CPD1XYSWRP EOVSEN

Chip Operating Mode, Bits 3–0

Refer to the operating modes

Stop Delay Mode, Bit 6

1 = Memory switching enabled

Core-DMA Priority, Bits 9–8

TA Sy nchronize Selec t, Bit 11

0 = Not synchronized

1 = Synchronized

CPD[1:0] Description

00 Compare SR[CP] to

active DMA channel

priority

01 DMA has higher

priority than core

10 DMA has same

priority as core

11 DMA has lower

priority than core

Cache Burst Mode Enable, Bit 10

0 = Burst Mode disabled

1 = Burst Mode enabled

Address Attribute Priority Disable, Bit 14

0 = Priority mechanism enabled

1 = Priority mechanism disabled

Bus Release Timing, Bit 12

0 = Fast Bus Release mode

1 = Slow Bus Release mode

Asynchronous Bus Ar bitration Enable, Bit 13

0 = Synchronization disabled

1 = Synchronization enabled

table in Chapter 4.

0ATE

Address Trace Enable, Bit 15

0 = Address Trace mode disabled

1 = Address Trace mode enabled

Application: Date:

Programmer: Sheet 2 of 5

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Updated Programming Sheets

Figure D-21. Timer Load, Compare, Count Registers (TLR, TCPR, TCR)

Application: Date:

Programmer: Sheet 3 of 3

Timers

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20

Timer Reload Value

Timer Load Register TLR0—X:$FFFF8E Write Only

Reset = $xxxxxx, value indeterminate after reset TLR1—X:$FFFF8A Write Only

TLR2—X:$FFFF86 Write Only

Timer Compare Register TCPR0—X:$FFFF8D Read/Write

Reset = $xxxxxx, value indeterminate after reset TCPR1—X:$FFFF89 Read/Write

TCPR2—X:$FFFF85 Read/Write

Timer Count Register TCR0—X:$FFFF8C Read Only

TCR1—X:$FFFF88 Read Only

TCR2—X:$FFFF84 Read Only

Reset = $000000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20

Value Compared to Counter Value

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 019 18 17 1623 22 21 20

Timer Count Value

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Updated Programming Sheets

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Updated Programming Sheets

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DSP56309UMAD/D

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81-3-3440-3569

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