Dual, Current-Output,
Serial-Input, 16-/14-Bit DACs
Data Sheet
AD5545/AD5555
Rev. E
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FEATURES
16-bit resolution AD5545
14-bit resolution AD5555
±1 LSB DNL monotonic
±1 LSB INL
2 mA full-scale current ±20%, with VREF = 10 V
0.5 µs settling time
2Q multiplying reference-input 6.9 MHz BW
Zero or midscale power-up preset
Zero or midscale dynamic reset
3-wire interface
Compact TSSOP-16 package
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Industrial control PLCs
Programmable attenuator
PRODUCT OVERVIEW
The AD5545/AD5555 are 16-bit/14-bit, current-output, digital-
to-analog converters designed to operate from a single 5 V
supply with bipolar output up to ±15 V capability.
An external reference is needed to establish the full-scale
output-current. An internal feedback resistor (RFB) enhances
the resistance and temperature tracking when combined
with an external op amp to complete the I-to-V conversion.
A serial data interface offers high speed, 3-wire microcontroller
compatible inputs using serial data in (SDI), clock (CLK), and
chip select (CS). Additional LDAC function allows
simultaneous update operation. The internal reset logic allows
power-on preset and dynamic reset at either zero or midscale,
depending on the state of the MSB pin.
The AD5545/AD5555 are packaged in the compact TSSOP-16
package and can be operated from –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD5545/
AD5555
V
DD
R
FB
A
V
REF
BV
REF
A
I
OUT
A
A
GND
A
SDI
CS
CLK
DGND MSB
RS LDAC
DAC A
DAC A
B
D0..DX
EN
R
R
R
R
16 OR 14
ADDR
DECODE
INPUT
REGISTER
POWER-
ON
RESET
INPUT
REGISTER
DAC A
REGISTER
DAC B
REGISTER
R
FB
B
I
OUT
B
A
GND
B
DAC B
02918-0-001
Figure 1.
AD5545/AD5555 Data Sheet
Rev. E | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Product Overview ............................................................................. 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Timing Diagrams .......................................................................... 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Functional Descriptions .......................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Digital-to-Analog Converter ...................................................... 9
Serial Data Interface ................................................................... 10
Power-Up Sequence ................................................................... 11
Layout and Power Supply Bypassing ....................................... 11
Grounding ................................................................................... 11
Applications Information .............................................................. 12
Stability ........................................................................................ 12
Positive Voltage Output ............................................................. 12
Bipolar Output ............................................................................ 12
Programmable Current Source ................................................ 13
DAC with Programmable Input Reference Range ................ 14
Reference Selection .................................................................... 15
Amplifier Selection .................................................................... 15
Evaluation Board for the AD5545 ................................................ 17
System Demonstration Platform .............................................. 17
Operating the Evaluation Board .............................................. 17
Evaluation Board Schematics ................................................... 18
Evaluation Board Layout ........................................................... 21
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
12/11—Rev. D to Rev. E
Added Figure 13; Renumbered Sequentially ................................ 8
5/11—Rev. C to Rev. D
Added Evaluation Board for the AD5545 Section, System
Demonstration Platform Section, and Operating the Evaluation
Board Section .................................................................................. 17
Added Figure 25 and Figure 26; Renumbered Sequentially ..... 17
Added Evaluation Board Schematics Section, Figure 27 .......... 18
Added Figure 28 .............................................................................. 19
Added Figure 29 .............................................................................. 20
Added Evaluation Board Layout Section, Figure 30, and
Figure 31, ......................................................................................... 21
Added Figure 32 .............................................................................. 22
Changes to Ordering Guide .......................................................... 23
3/11—Rev. B to Rev. C
Change to Equation 4, Bipolar Output Section .......................... 12
4/10—Rev. A to Rev. B
Changes to 2Q Multiplying Reference Input ................................. 1
Changes to AC Characteristics and Endnote 3 in Table 1 ........... 4
Changes to Figure 13 and Figure 15 ............................................... 8
Added Reference Selection Section, Amplifier Selection Section,
and Table 10 .................................................................................... 15
Added Table 11 and Table 12 ........................................................ 16
Changes to Ordering Guide .......................................................... 17
9/09—Rev. 0 to Rev. A
Changes to Features Section ............................................................ 1
Changes to Static Performance, Relative Accuracy, AD5545C
Parameter, Table 1 ............................................................................. 3
Moved ESD Caution.......................................................................... 5
Changes to Ordering Guide .......................................................... 16
7/03—Revision 0: Initial Version
Data Sheet AD5545/AD5555
Rev. E | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 5 V ± 10%, IOUT = virtual GND, GND = 0 V, VREF = 10 V, TA = full operating temperature range, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
STATIC PERFORMANCE1
Resolution N AD5545, 1 LSB = VREF/216 = 153 µV when VREF = 10 V 16 Bits
AD5555, 1 LSB = VREF/214 = 610 µV when VREF = 10 V 14 Bits
Relative Accuracy INL AD5545B ±2 LSB
AD5555C ±1 LSB
AD5545C
±1
LSB
Differential Nonlinearity DNL Monotonic ±1 LSB
Output Leakage Current IOUT Data = 0x0000, TA = 25°C 10 nA
Data = 0x0000, TA = TA Max 20 nA
Full-Scale Gain Error GFSE Data = full scale ±1 ±4 mV
Full-Scale Temperature Coefficient
2
TCV
FS
1
ppm/°C
REFERENCE INPUT
VREF Range VREF –12 +12 V
Input Resistance RREF 5 kΩ3
Input Capacitance2 CREF 5 pF
ANALOG OUTPUT
Output Current IOUT Data = full scale 2 mA
Output Capacitance2 COUT Code dependent 200 pF
LOGIC INPUTS AND OUTPUT
Logic Input Low Voltage VIL 0.8 V
Logic Input High Voltage VIH 2.4 V
Input Leakage Current IIL 10 µA
Input Capacitance2 CIL 10 pF
INTERFACE TIMING2, 4
50
MHz
Clock Input Frequency fCLK 10 ns
Clock Width High tCH 10 ns
Clock Width Low tCL 0 ns
CS to Clock Setup tCSS 10 ns
Clock to
CS
Hold
tCSH 5
ns
Data Setup tDS 10 ns
Data Hold tDH 5 ns
LDAC Setup tLDS 10 ns
Hold tLDH 10 ns
LDAC Width tLDAC 50 MHz
SUPPLY CHARACTERISTICS
Power Supply Range VDD range 4.5 5.5 V
Positive Supply Current IDD Logic inputs = 0 V 10 µA
Power Dissipation PDISS Logic inputs = 0 V 0.055 mW
Power Supply Sensitivity
PSS
∆V
DD
= ±5%
0.006
%/%
AD5545/AD5555 Data Sheet
Rev. E | Page 4 of 24
Parameter Symbol Conditions Min Typ Max Unit
AC CHARACTERISTICS
Output Voltage Setting Time tS To ±0.1% full scale, data = zero scale to
full scale to zero scale
0.5 µs
Reference Multiplying BW BW VREF = 100 mV rms, data = full scale, C1 = 5.6 pF 6.9 MHz
DAC Glitch Impulse Q VREF = 0 V, data = midscale minus 1 to midscale –2 nV-s
Feedthrough Error VOUT/VREF Data = zero scale, VREF = 100 mV rms,
f = 1 kHz, same channel
–81 dB
Digital Feedthrough Q CS = logic high and fCLK = 1 MHz 7 nV-s
Total Harmonic Distortion THD VREF = 5 V p-p, data = full scale, f = 1 kHz to 10 kHz –104 dB
Analog Crosstalk CTA VREFB = 0 V, measure VOUTB with VREFA = 5 V p-p
sine wave, data = full scale, f = 1 kHz to 10 kHz
–95 dB
Output Spot Noise Voltage eN f = 1 kHz, BW = 1 Hz 12 nV/√Hz
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal
is tied to the amplifier output. Typical values represent average readings measured at 25°C.
2 These parameters are guaranteed by design and not subject to production testing.
3 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier and the AD8065 for the THD specification.
4 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
TIMING DIAGRAMS
02918-0-003
A1SDI
CLK
CS t
CSS
t
DS
t
DH
t
CH
t
CL
t
LDAC
t
CSH
t
LDS
t
LDH
LDAC
A0
INPUT REG LD
D1 D0D15 D14 D13 D12 D11 D10
Figure 2. AD5545 18-Bit Data Word Timing Diagram
02918-0-004
A1SDI
CLK
CS
t
CSS
t
DS
t
DH
t
CH
t
CL
t
LDAC
t
CSH
t
LDS
t
LDH
LDAC
A0
INPUT REG LD
D1 D0D13 D12 D11 D10 D09 D08
Figure 3. AD5555 16-Bit Data Word Timing Diagram
Data Sheet AD5545/AD5555
Rev. E | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VDD to GND –0.3 V to +8 V
VREF to GND –18 V to +18 V
Logic Inputs to GND –0.3 V to +8 V
V(IOUT) to GND –0.3 V to VDD + 0.3 V
Input Current to Any Pin except
Supplies
±50 mA
Package Power Dissipation
(T
J
max – T
A
)/θ
JA
Thermal Resistance θ
JA
16-Lead TSSOP 150°C/W
Maximum Junction Temperature
(TJ max)
150°C
Operating Temperature Range –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Lead Temperature
RU-16 (Vapor Phase, 60 sec) 215°C
RU-16 (Infrared, 15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5545/AD5555 Data Sheet
Rev. E | Page 6 of 24
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
AD5545/
AD5555
TOP VIEW
(Not to Scale)
8
7
6
5
1
4
3
2
9
10
11
12
16
13
14
15
CS
DGND
CLK
V
DD
MSB
LDAC
RS
SDI
V
REF
B
R
FB
B
A
GND
B
I
OUT
B
R
FB
A
A
GND
A
I
OUT
A
V
REF
A
02918-0-002
Figure 4. 16-Lead TSSOP
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 RFBA Establish voltage output for DAC A by connecting this pin to an external amplifier output.
2 VREFA DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can
be tied to the VDD pin.
3 IOUTA DAC A Current Output.
4 AGNDA DAC A Analog Ground.
5 AGNDB DAC B Analog Ground.
6 IOUTB DAC B Current Output.
7 VREFB DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.
This pin can be tied to the VDD pin.
8 RFBB Establish voltage output for DAC B by the RFBB pin connecting to an external amplifier output.
9 SDI Serial Data Input. Input data loads directly into the shift register.
10 RS Reset
Pin, Active Low Input. Input registers and DAC registers are set to all 0s or midscale. Register
Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and 0x2000 for AD5555 when
MSB = 1.
11 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register
data to the input register when CS/LDAC returns high. This does not affect LDAC operation.
12 DGND Digital Ground Pin.
13 VDD Positive Power Supply Input. Specified range of operation 5 V ± 10% or 3 V ± 10%.
14 MSB MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system power-on.
Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can also be tied
permanently to ground or VDD.
15 LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC
registers. Asynchronous active low input. See Table 7 and Table 8 for operation.
16 CLK Clock Input. Positive edge clocks data into shift register.
Data Sheet AD5545/AD5555
Rev. E | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0 8192 16384 24576 32768 40960 49152 57344 65536
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
INL (LSB)
CODE (Decimal) 02918-0-009
Figure 5. AD5545 Integral Nonlinearity Error
1.0
0.8
0.6
0 8192 16384 24576 32768 40960 49152 57344 65536
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
DNL (LSB)
CODE (Decimal)
02918-0-010
Figure 6. AD5545 Differential Nonlinearity Error
1.0
0.8
0.6
0 2048 4096 6144 8192 10240 12288 14336 16384
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
INL (LSB)
CODE (Decimal)
02918-0-011
Figure 7. AD5555 Integral Nonlinearity Error
1.0
0.8
0.6
0 0248 4096 6144 8192 10240 12288 14336 16384
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
DNL (LSB)
CODE (Decimal)
02918-0-012
Figure 8. AD5555 Differential Nonlinearity Error
1.5
1.0
2 4
GE
DNL
INL
6 8 10
0.5
0
–0.5
–1.0
–1.5
LINEARITY ERROR (LSB)
SUPPLY VOLTAGE VDD (V)
VREF = 2.5V
TA= 25°C
02918-0-013
Figure 9. Linearity Errors vs. VDD
5
4
0 0.5 1.0 1.5 2.0 3.0 3.52.5 4.0 4.5 5.0
3
2
1
0
SUPPLY CURRENT IDD (LSB)
LOGIC INPUT VOLTAGE VIH (V)
VDD = 5V
TA= 25°C
02918-0-014
Figure 10. Supply Current vs. Logic Input Voltage
AD5545/AD5555 Data Sheet
Rev. E | Page 8 of 24
3.0
2.5
10k 100k 1M 10M 100M
2.0
1.5
1.0
0.5
0
SUPPLY CURRENT (mA)
CLOCK FREQUENCY (Hz)
0x5555
0x8000
0xFFFF
0x0000
02918-0-015
Figure 11. Supply Current vs. Clock Frequency
90
70
10 100 1k 10k 100k 1M
50
40
60
80
30
10
20
0
PSSR (-dB)
FREQUENCY (Hz)
V
DD
= 5V ± 10%
V
REF
= 10V
02918-0-016
Figure 12. Power Supply Rejection Ration vs. Frequency
02918-0-113
20
0
–20
–40
–60
–80
–100
–120
–140
–160
POWER SPECTRUM (dB)
FREQUENCY (Hz)
0 5 10 15 20 25
Figure 13. AD5545/AD5555 Analog THD
02918-0-117
2
–14
–12
–10
–8
–6
–4
–2
0
10k 100k 1M 10M 100M
GAIN (d B)
FRE QUENCY ( Hz )
Figure 14. Reference Multiplying Bandwidth
02918-0-018
VOUT
CS
Figure 15. Settling Time
02918-0-119
–3.70
–4.05
–4.00
–3.95
–3.90
–3.85
–3.80
–3.75
–200 4003002001000–100
V
OUT
(V)
TIME (n s)
Figure 16. Midscale Transition and Digital Feedthrough
Data Sheet AD5545/AD5555
Rev. E | Page 9 of 24
THEORY OF OPERATION
The AD5545/AD5555 contain a 16-/14-bit, current-output,
digital-to-analog converter, a serial-input register, and a DAC
register. Both parts require a minimum of a 3-wire serial data
interface with an additional LDAC for dual channel simultaneous
update.
DIGITAL-TO-ANALOG CONVERTER
The DAC architecture uses a current-steering R-2R ladder
design. Figure 17 shows the typical equivalent DAC. The DAC
contains a matching feedback resistor for use with an external
I-to-V converter amplifier. The RFB pin is connected to the
output of the external amplifier. The IOUT terminal is connected
to the inverting input of the external amplifier. These DACs are
designed to operate with both negative or positive reference
voltages. The VDD power pin is used only by the logic to drive
the DAC switches on and off. Note that a matching switch is
used in series with the internal 5 kΩ feedback resistor. If users
attempt to measure the RFB value, power must be applied to VDD
to achieve continuity. The VREF input voltage and the digital data
(D) loaded into the corresponding DAC register, according to
Equation 1 and Equation 2, determine the DAC output voltage.
536,65/– DVV REF
OUT ×=
(1)
384,16/– DVV REF
OUT ×=
(2)
Note that the output full-scale polarity is the opposite of the
VREF polarity for dc reference voltages.
VREF
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:
SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED
R
2R 2R 2R R 5kΩ
S2 S1
R R
VDD
RFB
IOUT
GND
02918-0-005
Figure 17. Equivalent R-2R DAC Circuit
These DACs are also designed to accommodate ac reference input
signals. The AD5545/AD5555 accommodate input reference
voltages in the range of –12 V to +12 V. The reference voltage
inputs exhibit a constant nominal input-resistance value of
5 kΩ, ±30%. The DAC output (IOUT) is code dependent, pro-
ducing various output resistances and capacitances. When
choosing an external amplifier, the user should take into
account the variation in impedance generated by the AD5545/
AD5555 on the amplifiers inverting input node. The feedback
resistance in parallel with the DAC ladder resistance dominates
output voltage noise.
V
REF
A
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY:
SWITCHES S1 AND S2 ARE CLOSED, V
DD
MUST BE POWERED
R
2R 2R 2R R 5kΩ
S2 S1
+3V
–3V
R R
V
OUT
V
IN
V
DD
5V
2.500V
R
FB
A
I
OUT
A
A
GND
A
GND
02918-0-006
AD5545/AD5555
ADR03
AD8628
LOAD
V
OUT
V
EE
V
CC
Figure 18. Recommended System Connections
AD5545/AD5555 Data Sheet
Rev. E | Page 10 of 24
SERIAL DATA INTERFACE
The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK)
serial data interface for single channel update operation. With
Table 7 as an example (AD5545), users can tie LDAC low and
RS high, then pull CS low for an 18-bit duration. New serial
data is then clocked into the serial-input register in an 18-bit
data-word format with the MSB bit loaded first. Table 8 defines
the truth table for the AD5555. Data is placed on the SDI pin
and clocked into the register on the positive clock edge of CLK.
For the AD5545, only the last 18-bits clocked into the serial
register are interrogated when the CS pin is strobed high,
transferring the serial register data to the DAC register and
updating the output. If the applied microcontroller outputs
serial data in different lengths than the AD5545, such as 8-bit
bytes, three right justified data bytes can be written to the
AD5545. The AD5545 ignores the six MSB and recognizes the
18 LSB as valid data. After loading the serial register, the rising
edge of CS transfers the serial register data to the DAC register
and updates the output; during the CS strobe, the CLK should
not be toggled.
If users want to program each channel separately but update them
simultaneously, program LDAC and RS high initially, then pull
CS low for an 18-bit duration and program DAC A with the
proper address and data bits. CS is then pulled high to latch data
to the DAC A register. At this time, the output is not updated. To
load DAC B data, pull CS low for an 18-bit duration and program
DAC B with the proper address and data, then pull CS high to
latch data to the DAC B register. Finally, pull LDAC low and then
high to update both the DAC A and DAC B outputs
simultaneously.
Table 6 shows that each DAC A and DAC B can be individually
loaded with a new data value. In addition, a common new data
value can be loaded into both DACs simultaneously by setting Bit
A1 = A0 = high. This command enables the parallel combination
of both DACs, with IOUTA and IOUTB tied together, to act as one
DAC with significant improved noise performance.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to digital ground (DGND) and VDD as shown in
Figure 19.
V
DD
02918-0-007
5k
DGND
DIGITAL
INPUTS
Figure 19. Equivalent ESD Protection Circuits
Table 4. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB LSB
Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 Note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 5. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB LSB
Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 Note that only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 6. Address Decode
A1 A0 DAC Decoded
0 0 None
0 1 DAC A
1 0 DAC B
1 1 DAC A and DAC B
Data Sheet AD5545/AD5555
Rev. E | Page 11 of 24
Table 7. AD5545 Control Logic Truth Table1, 2
CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register
H X H H X No effect Latched Latched
L L H H X No effect Latched Latched
L + H H X Shift register data advanced one bit Latched Latched
L H H H X No effect Latched Latched
+ L H H X No effect Selected DAC updated
with current SR current
Latched
H X L H X No effect Latched Transparent
H X H H X No effect Latched Latched
H X + H X No effect Latched Latched
H X H L 0 No effect Latched data = 0x0000 Latched data = 0x0000
H X H L H No effect Latched data = 0x8000 Latched data = 0x8000
1 SR = shift register, + = positive logic transition, and X = don’t care.
2 At power-on, both the input register and the DAC register are loaded with all 0s.
Table 8. AD5555 Control Logic Truth Table1, 2
CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register
H X H H X No effect Latched Latched
L L H H X No effect Latched Latched
L + H H X Shift register data advanced one bit Latched Latched
L H H H X No effect Latched Latched
+ L H H X No effect Selected DAC updated
with current SR current
Latched
H X L H X No effect Latched Transparent
H X H H X No effect Latched Latched
H X + H X No effect Latched Latched
H X H L 0 No effect Latched data = 0x0000 Latched data = 0x0000
H X H L H No effect Latched data = 0x2000 Latched data = 0x2000
1 SR = shift register, + = positive logic transition, and X = don’t care.
2 At power-on, both the input register and the DAC register are loaded with all 0s.
POWER-UP SEQUENCE
It is recommended to power-up VDD and ground prior to any
reference voltages. The ideal power-up sequence is AGNDx,
DGND, VDD, VREFx, and digital inputs. A noncompliance
power-up sequence can elevate reference current, but the device
will resume normal operation once VDD is powered.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at VDD to minimize
any transient disturbance and to filter any low frequency ripple
(see Figure 20). Users should not apply switching regulators for
VDD due to the power supply rejection ratio degradation over
frequency.
AD5545/
AD5555
V
DD
V
DD
A
GND
X
DGND
02918-0-008
C1
+
C2 10F 0.1F
Figure 20. Power Supply Bypassing and Grounding Connection
GROUNDING
The DGND and AGNDx pins of the AD5545/AD5555 refer to the
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 20).
AD5545/AD5555 Data Sheet
Rev. E | Page 12 of 24
APPLICATIONS INFORMATION
STABILITY
AD5545/AD5555
AD8628
VREF VREF IOUT VO
VDD
VDD RFB
U1
U2
C1
GND
02918-0-020
Figure 21. Operational Compensation Capacitor for Gain Peaking
Prevention
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP, and if there
is excessive parasitic capacitance at the inverting node.
An optional compensation capacitor, C1, can be added for
stability as shown in Figure 21. C1 should be found empirically,
but 6 pF is generally more than adequate for the compensation.
POSITIVE VOLTAGE OUTPUT
To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the
resistors’ tolerance errors. To generate a negative reference, the
reference can be level shifted by an op amp such that the VOUT
and GND pins of the reference become the virtual ground and
−2.5 V, respectively (see Figure 22).
AD5545/AD5555
1/2
AD8628
1/2
AD8620
ADR03
V
REF
I
OUT
V
OUT
V
IN
V
DD
GND
GND
02918-0-021
V
O
0 < V
O
< +2.5
R
FB
U2
U1
+5V
V+
–5V
V–
+5V
–2.5V
U3
C1
U4
Figure 22. Positive Voltage Output Configuration
BIPOLAR OUTPUT
The AD5545/AD5555 is inherently a 2-quadrant multiplying
DAC. It can easily be set up for unipolar output operation. The
full-scale output polarity is the inverse of the reference input
voltage.
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier,
U4, configured as a summing amplifier (see Figure 23). In this
circuit, the second amplifier, U4, provides a gain of 2, which
increases the output span magnitude to 5 V. Biasing the external
amplifier with a 2.5 V offset from the reference voltage results in a
full 4-quadrant multiplying circuit. The transfer equation of this
circuit shows that both negative and positive output voltages are
created because the input data (D) is incremented from code zero
(VOUT = −2.5 V) to midscale (VOUT = 0 V) to full scale (VOUT =
+2.5 V).
VOUT = (D/32,768 − 1) × VREF (AD5545) (3)
VOUT = (D/8192 − 1) × VREF (AD5555) (4)
For the AD5545, the external resistance tolerance becomes the
dominant error that users should be aware of.
AD5545/AD5555
1/2
AD8620
1/2
AD8620
ADR03
V
REF
I
OUT
V
OUT
V
IN
V
DD
GND GND
02918-0-022
V
O
–2.5 < V
O
< +2.5
R
FB
U2
U3
U1
+5V +5V
V+
–5V
5V V–
U4
C1
C2
R1
10kΩ±0.01% 10kΩ±0.01%
5kΩ±0.01%
R2
R3
Figure 23. Four-Quadrant Multiplying Application Circuit
Data Sheet AD5545/AD5555
Rev. E | Page 13 of 24
PROGRAMMABLE CURRENT SOURCE
Figure 24 shows a versatile V-to-I conversion circuit using
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirec-
tional current flow and high voltage compliance. This circuit
can be used in a 4 mA to 20 mA current transmitter with up to
a 500 Ω of load. In Figure 24, it shows that if the resistor
network is matched, the load current is
( )
DV
R3
R1
R3R2
I
REFL
××
+
=
(5)
R3, in theory, can be made small to achieve the current needed
within the U3 output current driving capability. This circuit is
versatile such that the AD8510 can deliver ±20 mA in both
directions, and the voltage compliance approaches 15 V, which
is mainly limited by the supply voltages of U3. However, users
must pay attention to the compensation. Without C1, it can be
shown that the output impedance becomes
( )
( )
( )
R3R21R3R2RR1
R2R1R31R
Z
O
+
′′
+
′
+
′
=–
(6)
If the resistors are perfectly matched, ZO is infinite, which is
desirable, and the resistors behave as an ideal current source.
On the other hand, if they are not matched, ZO can be either
positive or negative. The latter can cause oscillation. As a result,
C1 is needed to prevent the oscillation. For critical applications,
C1 could be found empirically but typically falls in the range of
a few picofarads.
AD5545/AD5555
AD8628
AD8510
VREF
VREF IOUT
V
DD
V
DD
V
DD
C1
10pF
V
SS
LOAD
GND
02918-0-023
V
L
I
L
R
FB
U2
U3
U1
V+
V–
R3'
50Ω
R1'
150kΩR2'
15kΩ
R1
150kΩR2
15kΩ
R3
50Ω
Figure 24. Programmable Current Source with Bidirectional
Current Control and High Voltage Compliance Capabilities
AD5545/AD5555 Data Sheet
Rev. E | Page 14 of 24
DAC WITH PROGRAMMABLE INPUT
REFERENCE RANGE
Because high voltage references can be costly, users may
consider using one of the DACs, a digital potentiometer, and a
low voltage reference to form a single-channel DAC with a
programmable input reference range. This approach optimizes
the programmable range as well as facilitates future system
upgrades with just software changes. Figure 25 shows this
implementation. VREFAB is in the feedback network, therefore,
WA
WB
N
A
REF_AB
WA
WB
REFREF R
R
2
D
V
R
R
VABV ––1 (7)
where:
VREFAB = reference voltage of VREFA and VREFB
VREF = external reference voltage
DA = DAC A digital code in decimal
N = number of bits of DAC
RWB and RWA are digital potentiometer 128-step programmable
resistances and are given by
AB
C
WB R
D
R128
(8)
AB
C
WA R
D
R128
128
(9)
C
C
WA
WB
D
D
R
R
128 (10)
where DC = digital potentiometer digital code in decimal
(0 ≤ DC ≤ 127).
By putting Equations 7 through 10 together, the following
results:
C
C
N
A
C
C
REFREF
D
D
D
D
D
VABV
128
2
1
128
1
(11)
Table 9 shows a few examples of VREFAB of the 14-bit AD5555.
Table 9. VREFAB vs. DB and DC of the AD5555
DC D
A V
REFAB
0 X VREF
32 0 1.33 VREF
32 8192 1.6 VREF
64 0 2 VREF
64 8192 4 VREF
96 0 4 VREF
96 8192 –8 VREF
The output of DAC B is, therefore,
N
B
REF
OB
D
ABVV 2
(12)
where DB is the DAC B digital code in decimal.
The accuracy of VREFAB is affected by the matching of the input
and feedback resistors and, therefore, a digital potentiometer is
used for U4 because of its inherent resistance
matching. The AD7376 is a 30 V or ±15 V, 128-step digital
potentiometer. If 15 V or ±7.5 V is adequate for the application,
a 256-step AD5260 digital potentiometer can be used instead.
AD5555
V
OUT
V
IN
GND
02918-0-024
V
O
B
TRIMTEMP
POT
U2A
U4
W
AB
U3
53
2
4
6
+5V
+15V
+15V
V+
–15V
V–
C1
C3
V
REF
A
V
REF
V
REF_AB
I
OUT
A
A
GND
A
V
DD
R
FB
A
C2 2.2p
OP4177
U2B
V
REF
BI
OUT
B
A
GND
B
R
FB
B
OP4177
U2C
OP4177
ADR03
AD7376
U1A
U1B
Figure 25. DAC with Programmable Input Reference Range
Data Sheet AD5545/AD5555
Rev. E | Page 15 of 24
REFERENCE SELECTION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage,
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 10 lists some of the references
available from Analog Devices, Inc., that are suitable for use
with this range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed upon the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, can cause the DAC to be
nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-switching
DAC circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, minimize capacitance
at the VREF node (the voltage output node in this application) of
the DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 11 and Table 12.
Table 10. Suitable Analog Devices Precision References
Part No. Output Voltage (V) Initial Tolerance (%)
Maximum Temperature
Drift (ppm/°C) ISS (mA) Output Noise (µV p-p) Package(s)
ADR01 10 0.05 3 1 20 SOIC-8
ADR01 10 0.05 9 1 20 TSOT-5, SC70-5
ADR02 5.0 0.06 3 1 10 SOIC-8
ADR02 5.0 0.06 9 1 10 TSOT-5, SC70-5
ADR03 2.5 0.1 3 1 6 SOIC-8
ADR03 2.5 0.1 9 1 6 TSOT-5, SC70-5
ADR06 3.0 0.1 3 1 10 SOIC-8
ADR06 3.0 0.1 9 1 10 TSOT-5, SC70-5
ADR420 2.048 0.05 3 0.5 1.75 SOIC-8, MSOP-8
ADR421 2.50 0.04 3 0.5 1.75 SOIC-8, MSOP-8
ADR423 3.00 0.04 3 0.5 2 SOIC-8, MSOP-8
ADR425 5.00 0.04 3 0.5 3.4 SOIC-8, MSOP-8
ADR431 2.500 0.04 3 0.8 3.5 SOIC-8, MSOP-8
ADR435
5.000
0.04
3
0.8
8
SOIC-8, MSOP-8
ADR391 2.5 0.16 9 0.12 5 TSOT-5
ADR395 5.0 0.10 9 0.12 8 TSOT-5
AD5545/AD5555 Data Sheet
Rev. E | Page 16 of 24
Table 11. Suitable Analog Devices Precision Op Amps
Part No. Supply Voltage (V)
VOS Maximum
(µV)
IB Maximum
(nA)
0.1 Hz to 10 Hz
Noise (µV p-p) Supply Current (µA) Package(s)
OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 , PDIP-8
OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP-8, SOIC-8
AD8675 ±5 to ±18 75 2 0.1 2300 MSOP-8, SOIC-8
AD8671 ±5 to ±15 75 12 0.077 3000 MSOP-8, SOIC-8
ADA4004-1 ±5 to ±15 125 90 0.1 2000 SOIC-8, SOT-23-5
AD8603 1.8 to 5 50 0.001 2.3 40 TSOT-5
AD8607 1.8 to 5 50 0.001 2.3 40 MSOP-8, SOIC-8
AD8605 2.7 to 5 65 0.001 2.3 1000 WLCSP-5, SOT-23-5
AD8615 2.7 to 5 65 0.001 2.4 2000 TSOT-5
AD8616 2.7 to 5 65 0.001 2.4 2000 MSOP-8, SOIC-8
Table 12. Suitable Analog Devices High Speed Op Amps
Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) VOS (Max) (µV) IB (Max) (nA) Package(s)
AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23-5
AD8066 5 to 24 145 180 1500 0.006 SOIC-8, MSOP-8
AD8021
5 to 24
490
120
1000
10,500
SOIC-8, MSOP-8
AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5
ADA4899 5 to 12 600 310 35 100 LFCSP-8, SOIC-8
AD8057 3 to 12 325 1000 5000 500 SOT-23-5, SOIC-8
AD8058 3 to 12 325 850 5000 500 SOIC-8, MSOP-8
AD8061 2.7 to 8 320 650 6000 350 SOT-23-5, SOIC-8
AD8062 2.7 to 8 320 650 6000 350 SOIC-8, MSOP-8
AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8, PDIP-8
Data Sheet AD5545/AD5555
Rev. E | Page 17 of 24
EVALUATION BOARD FOR THE AD5545
The EVAL-AD5545SDZ is used in conjunction with an SDP1Z
system demonstration platform board available from Analog
Devices, which is purchased separately from the evaluation
board. The USB-to-SPI communication to the AD5545 is
completed using this Blackfin®-based demonstration board.
SYSTEM DEMONSTRATION PLATFORM
The system demonstration platform (SDP) is a hardware and
software evaluation tool for use in conjunction with product
evaluation boards. The SDP board is based on the Blackfin
ADSP-BF527 processor with USB connectivity to the PC
through a USB 2.0 high speed port. For more information about
this device, see the system demonstration platform web page.
OPERATING THE EVALUATION BOARD
The evaluation board requires ±12 V and +5 V supplies.
The +12 V VDD and −12 V VSS are used to power the output
amplifier, and the +5 V is used to power the DAC (DVDD).
02918-0-025
Figure 26. Evaluation Board Software – Device Selection Window
02918-0-027
Figure 27. Evaluation Board Software—AD5545 Dual DAC
AD5545/AD5555 Data Sheet
Rev. E | Page 18 of 24
EVALUATION BOARD SCHEMATICS
02918-0-028
Figure 28. EVAL-AD5545SDZ Schematic Part A
Data Sheet AD5545/AD5555
Rev. E | Page 19 of 24
02918-0-029
Figure 29. EVAL-AD5545SDZ Schematic Part B
AD5545/AD5555 Data Sheet
Rev. E | Page 20 of 24
02918-0-030
Figure 30. EVAL-AD5545SDZ Schematic Part B
Data Sheet AD5545/AD5555
Rev. E | Page 21 of 24
EVALUATION BOARD LAYOUT
02918-0-031
Figure 31. Silkscreen
02918-0-032
Figure 32. Component Side
AD5545/AD5555 Data Sheet
Rev. E | Page 22 of 24
02918-0-033
Figure 33. Solder Side
Data Sheet AD5545/AD5555
Rev. E | Page 23 of 24
OUTLINE DIMENSIONS
16 9
81
PI N 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM P LIANT T O JEDE C S TANDARDS M O-153-AB
Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
INL
LSB
DNL
LSB
Resolution
(Bits)
Temperature
Range
Package
Description
Package
Option
Ordering
Qty
AD5545BRU ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5545BRU-REEL7 ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 1000
AD5545BRUZ ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5545BRUZ-REEL7 ±2 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 1000
AD5545CRUZ ±1 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5545CRUZ-REEL7 ±1 ±1 16 −40°C to +85°C 16-Lead TSSOP RU-16 1000
AD5555CRU ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5555CRU-REEL7 ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 1000
AD5555CRUZ ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 96
AD5555CRUZ-REEL7 ±1 ±1 14 −40°C to +85°C 16-Lead TSSOP RU-16 1000
EVAL-AD5545SDZ Evaluation Board
1 The AD5545/AD5555 contain 3131 transistors. The die size measures 71 mil. × 96 mil., 6816 sq. mil.
2 Z = RoHS Compliant Part.
AD5545/AD5555 Data Sheet
Rev. E | Page 24 of 24
NOTES
©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02918-0-12/11(E)
