1999 Microchip Technology Inc. Advance Information DS30275A-page 1
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which a re two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 4K x 14 words of Program Memory,
256 x 8 bytes of Data Memory (RAM )
• Interrupt capability (up to 14 internal/external
inter rupt sour ce s)
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Pr ogrammable code-pr otect ion
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• In-Circuit Serial Programming (ISCP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 µA typical @ 3V, 32 kHz
-< 1 µA typical standby current
Pin Di agram
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM max. resolution is 10-bit
• 12-bit multi-channel Analog-to-Digital converter
• On-chip absolute bandgap voltage reference
generator
• Synchronous Serial Port (SSP) with SPI (Mast er
Mode) and I2C
• Universal Synchronous Asynchronous Receiver
Transmitter, supports high/low speeds and 9-bit
address mode (USART/SCI)
• Para lle l Slave Port (PSP) 8-bits wide, with
external RD, WR and CS control s
• Programmable Brown-out detection circuitry for
Brown-out Reset (BOR)
• Programmable Low-voltage detection circuitry
600 mil. PDIP, Windowed CERDIP
RB7
RB6
RB5
RB4
RB3/AN9/LVDIN
RB2/AN8
RB1/SS
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
AVDD
AVSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16C774
*
*
*
*
*
*
PIC16C77X
28/40-Pin, 8-Bit CMOS Micr ocontrollers w/ 12-Bit A/D
* Enhanced feat ures
This is an advanced copy of the data sheet and therefore the contents and
specifications are subject to change based on device characterization.
PIC16C77X
DS30275A-page 2 Advance Information 1999 Microchip Technology Inc.
Pin Diagra ms
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RA4/T0CKI
AVDD
AVSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3/AN9/LVDIN
RB2/AN8
RB1/SS
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
300 mil. SDIP, SOIC, Windowed CERDIP, SSOP
PIC16C773
RB3/AN9/LVDIN
RB2/AN8
RB1/SS
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
AVDD
AVSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1 6
5
4
3
2
1
44
43
42
41
40
28
27
26
25
24
23
22
21
20
19
18
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
AVSS
AVDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1/SS
RB2/AN8
RB3/AN9/LVDIN
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
RA0/AN0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC 44
43
42
41
40
39
38
37
36
35
34
22
21
20
19
18
17
16
15
14
13
12
MQFP
PLCC
TQFP
PIC16C774
PIC16C774
RC1/T1OSI/CCP2
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 3
Key Features
PICmicro™ Mid-Range Reference Manual
(DS33023) PIC16C773 PIC16C774
Operating Frequency DC - 20 MHz DC - 20 MHz
Resets (and Delays) POR, BOR, MCLR, WDT
(PWRT, OST) POR, BOR, MCLR, WDT
(PWRT, OST)
Program Memory (14-bit words) 4K 4K
Data Memo ry (bytes) 256 256
Interrupts 13 14
I/O Ports Ports A,B,C Ports A,B,C,D,E
Timers 3 3
Capture/Compare/PWM modules 2 2
Serial Communications MSSP, USART MSSP, USART
Parallel Communications — PSP
12-bit Analog-to-Digital Module 6 input channels 10 input channels
Instruction Set 35 Instructions 35 Instructions
PIC16C77X
DS30275A-page 4 Advance Information 1999 Microchip Technology Inc.
Table of Contents
1.0 Device Overview............................................................................................................................................................................ 5
2.0 Memory O rganization................................................................................................................................................................... 11
3.0 I/O Ports............... ............... .......... ............... ........... .......... ............... .......... ........... ................ ......... .......... ............... ........... .......... 27
4.0 Timer0 Module............................................................................................................................................................................. 39
5.0 Timer1 Module............................................................................................................................................................................. 41
6.0 Timer2 Module............................................................................................................................................................................. 45
7.0 Capture/Compare/PWM (CCP) Module(s).......................................................................... ......................................................... 47
8.0 Master Sy nchronous Serial Port (M SSP ) Module....................... ................................................................................................. 53
9.0 Addressable Universal Synchronous Asynchronous Receiv er Transmitter (USA RT ) . ................................................................ 97
10.0 Voltage Reference Module and Low-voltage Detect............. .. .. ....... .. .. .... .. .. .. ....... .. .... .. .. .. ....... .. .. .... .. ........................................ 113
11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117
12.0 Special Features of the CPU ..................................................................................................................................................... 127
13.0 Instruction Set Summ ary............................................................................................................................................................ 143
14.0 Development Support ................................................................................................................................................................ 145
15.0 Electrical Characteristics............................................................................................................................................................ 151
16.0 DC and AC Characteristics Graphs and Tables ....................... ....... .... .... .... .. ......... .... .... .. ......... .... ............................................ 173
17.0 P a cka g i n g In fo rmation .................. ............... ........... .......... ........... .......... ........... .............. ............... .......... ........... .......... ........... ..175
Appendix A: Revision History......................... .... ...... ......... ...... .... ........... .... .... .... ........... .... ...... ....................................................... 187
Appendix B: Device Differences................. .... .... .. .... ....... .... .. .... .. ......... .. .... .. .... .. ......... .. .... .. .... ....................................................... 187
Appendix C: Conversion Considerations.............. .. ....... .... .. .... .. .. ....... .... .. .. .... .. ....... .. .... .. .... .. .. ....... ................................................ 187
Index .................................................................................................................................................................................................. 189
Bit/Register Cross-Reference List...................................................................................................................................................... 196
On-Line Support.................................... .. ......... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. ................................................................... 197
Reader Response.............................................................................................................................................................................. 198
PIC16C77X Product Identification System........................................ ........... .... .... ........... .... ...... ......................................................... 199
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is vers ion A of document DS30000.
Errata
An errata sheet may exist for cu rrent devices, describing m inor operational differences (from the data sheet) and recomm ended
workarounds. As de vice/documentation issues become known to us, we will pub lish an errata sheet. The errata wil l specify the re vi-
sion of silicon and re vision of document to which it applies.
To deter mine if an errata sheet ex ists for a particular device, please check with one of the fo llowing:
• Microchip’s Worldwide W eb site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U . S. FAX: (602) 786-7277
When contacting a sales office or the literature center , please specify which device , re vision of silicon and data sheet (include liter-
ature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have s pent a great deal of time to ens ure
that this document is correct. Howe v er, we realize that w e ma y have missed a few things. If you fi nd an y information that is missing
or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet.
• E-mail us at webmaster@microchip.com.
We appreciate your assistance in making this a better document.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 5
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Addition al information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary docu ment to this dat a sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There a two devices (PIC16C773 and PIC16C774)
covered by this datasheet. The PIC16C773 devices
come in 28-pin packages and the PIC16C774 devices
come in 40-pin packages. The 28-pin devices do not
have a Parallel Slave Port implemented.
The following two figures are device block diagrams
sor ted by pin number; 28-pin for Figure 1-1 and 40-pi n
for Figure 1-2. The 28-pin and 40-p in pinouts are li sted
in Table 1-1 and Table 1-2, respectively.
FIGURE 1-1: PIC16C773 BLOCK DIAGRAM
EPROM
Program
Memory
4K x 14
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
256 x 8
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RB0/INT
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
USART
CCP1,2 Synchronous
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
RA0/AN0
8
3
Timing
Generation
12-bit
ADC
Precision
Reference
RB1/SS
RB2/AN8
RB3/AN9/LVDIN
Low-voltage
Detect
AVDD
AVSS
PIC16C77X
DS30275A-page 6 Advance Information 1999 Microchip Technology Inc.
FIGURE 1-2: PIC16C774 BLOCK DIAGRAM
EPROM
Program
Memory
4K x 14
13 Data Bus 8
14
Program
Bus
Instruction reg
Program Counter
8 Level S tack
(13-bit)
RAM
File
Registers
256 x 8
Direct Addr 7
RAM Addr (1) 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKI
RA5/AN4
RB0/INT
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD7/PSP7:RD0/PSP0
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
USART
CCP1,2 Synchronous
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
RA0/AN0
Parallel Slave Port
8
3
Timing
Generation
12-bit
ADC
Precision
Reference
RB1/SS
RB2/AN8
RB3/AN9/LVDIN
Low-voltage
Detect
AVDD
AVSS
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 7
TABLE 1-1 PIC16C773 PINOUT DESCRIPTION
Pin Name
DIP,
SSOP,
SOIC
Pin#
I/O/P
Type Buffer
Type Description
OSC1/CLKIN 9 I ST/CMOS(3) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 O — Oscillator cr ystal output. Connects to crysta l or resonator in crystal
oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR/VPP 1 I/P ST Master clear (reset) input or programming voltage input. This pin is an
active low reset to the device.
PORTA is a bi-directional I/O port .
RA0/AN0 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 I/O TTL RA1 can also be analog input1
RA2/AN2/VREF-/VRL 4 I/O TTL RA2 can also be analog input2 or negativ e analog reference voltage
input or internal voltage reference low
RA3/AN3/VREF+/VRH 5 I/O TTL RA3 can also be analog input3 or positiv e analog reference volt age
input or internal voltage reference high
RA4/T0CKI 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is
open drain type.
PORTB is a bi-directional I/O por t . PORTB can be software pro-
grammed for internal weak pull-up on all inputs.
RB0/INT 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1/SS 22 I/O TTL/ST(1) RB1 can also be the SSP slave select
RB2/AN8 23 I/O TTL RB2 can also be analog input8
RB3/AN9/LVDIN 24 I/O TTL RB3 can also be analog input9 or the low voltage detect input
reference
RB4 25 I/O TTL Interrupt on change pin.
RB5 26 I/O TTL Interrupt on change pin.
RB6 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T 1OSO/T1CK I 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input.
RC1/T1OSI/CCP2 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1
output.
RC3/SCK/SCL 14 I/O ST RC3 can also be the synchronous serial clock input/output for both
SPI and I2C modes.
RC4/SDI/SDA 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 18 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
AVSS 8 P Ground reference for A/D converter
AVDD 7 P Positive supply for A/D converter
VSS 19 P — Ground reference for logic and I/O pins.
VDD 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured for the multiplexed function.
2: This buffer is a Schmitt Trigger input when used in ser ial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
PIC16C77X
DS30275A-page 8 Advance Information 1999 Microchip Technology Inc.
TABLE 1-2 PIC16C774 PINOUT DESCRIPTION
Pin Name DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input.
OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator
in crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input.
This pin is an activ e low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 3 19 I/O TT L RA0 can also be analog input0
RA1/AN1 3 4 20 I/O TT L RA1 can also be analog input1
RA2/AN2/VREF-/VRL 4 5 21 I/O TTL RA2 can also be analog input2 or negative analog
reference voltage input or internal v oltage reference
low
RA3/AN3/VREF+/VRH 5 6 22 I/O TTL RA3 can also be analog input3 or positive analog
reference voltage input or internal v oltage reference
high
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input t o t he Timer0 timer/
counter. Output is open drain type.
RA5/AN4 7 8 24 I/O TT L RA5 can also be analog input4
PORTB is a bi-directional I/O port. PORTB can be soft-
ware progr ammed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin.
RB1/SS 34 37 9 I/O TTL/ST(1) RB1 can also be the SSP slave select
RB2/AN8 35 38 10 I/O TTL RB2 can also be analog input8
RB3/AN9/LVDIN 36 39 11 I/O TTL RB3 can also be analog input9 or input reference for
low v oltage detect
RB4 37 41 14 I/O TTL Interrupt on change pin.
RB5 38 42 15 I/O TTL Interrupt on change pin.
RB6 39 43 16 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock.
RB7 40 44 17 I/O TTL/ST(2) Interrupt on change pin. Serial programming data.
Legend: I = input O = output I/O = input/output P = pow er
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured for the multiplexed function.
2: This buffer is a Schmitt Trigger input when used in ser ial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 9
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or
Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1
output/PWM1 output.
RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/
output for both SPI and I2C modes.
RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART A synchronous
Transmit or Synchronous Clock.
RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive
or Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0 19 21 38 I/O ST/TTL(3)
RD1/PSP1 20 22 39 I/O ST/TTL(3)
RD2/PSP2 21 23 40 I/O ST/TTL(3)
RD3/PSP3 22 24 41 I/O ST/TTL(3)
RD4/PSP4 27 30 2 I/O ST/TTL(3)
RD5/PSP5 28 31 3 I/O ST/TTL(3)
RD6/PSP6 29 32 4 I/O ST/TTL(3)
RD7/PSP7 30 33 5 I/O ST/TTL(3)
PORTE is a bi-directional I/O port.
RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE0 can also be read control for the parallel slave
por t, or analog input5.
RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 can also be write control for the parallel slave
por t, or analog input6.
RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select cont rol f or the parallel slave
por t, or analog input7.
AVss 12 13 29 P Ground reference for A/D converter
AVDD 11 12 28 P Positive supply for A/D converter
VSS 31 34 6 P — Ground reference for logic and I/O pins.
VDD 32 35 7 P — Positive supply for logic and I/O pins.
NC — 1,17,28,
40 12,13,
33,34 — These pins are not internally connected. These pins
should be left unconnected.
TABLE 1-2 PIC16C774 PINOUT DESCRIPTION (Cont.’d)
Pin Name DIP
Pin# PLCC
Pin# QFP
Pin# I/O/P
Type Buffer
Type Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured for the multiplexed function.
2: This buffer is a Schmitt Trigger input when used in ser ial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
PIC16C77X
DS30275A-page 10 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 11
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro® microcontrollers. Each block (Pro-
gram Memory and Data Memory) has its own bus
so that concurrent access can occur.
Addit ional information on devi ce memory ma y be found
in the PICmicro Mid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
The PIC16C77X PICmicros have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space . Each device has 4K x 14 words of pro-
gram memory. Accessing a location above the physi-
cally implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Functio n Regist ers . Abo v e the Special Functi on Re gis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The regi ster fi le can be accessed either di rectly, or ind i-
rectly through the File Select Register FSR.
PC<12:0>
13
0000h
0004h
0005h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip
CALL , RETURN
RETFI E , RETLW
Stac k Level 2
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
3FFFh
RP1 RP0 (STATUS<6:5>)
PIC16C77X
DS30275A-page 12 Advance Information 1999 Microchip Technology Inc.
FIGURE 2-2: REGISTER FILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
7Fh FFh
Bank 0 Bank 1
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Indirect addr.(*)
PORTD
PORTE TRISD
ADRESL
TRISE
PIR2 PIE2
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
TXSTA
SPBRG
ADCON1
General
Purpose
Register
General
Purpose
Register
EFh
F0h
accesses
70h-7Fh
96 Bytes 80 Bytes
(1)
(1)
(1)
(1)
(1) Not implemented on PIC16C773.
LVDCON
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
17Fh
Bank 2
6Fh
70h
File
Address
PCL
STATUS
FSR
PCLATH
INTCON
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
1FFh
Bank 3
Indirect addr.(*)
OPTION_REG
1EFh
1F0h
accesses
70h - 7Fh
TRISB
PCL
STATUS
FSR
PCLATH
INTCON
Indirect addr.(*)
TMR0
General
Purpose
Register
accesses
70h - 7Fh
PORTB
80 Bytes
File
Address
File
Address
File
Address
REFCON
SSPCON2
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 13
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The sp ecial fu nction register s can b e class ified in to tw o
sets; core (CPU) a nd periphe ral. Those reg isters asso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(2)
Bank 0
00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
04h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA ——PORTA5
(5) PORTA Data Latch when written: PORTA<4:0> pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx 11xx uuuu 11uu
07h P ORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h(5) PORTD PORTD Data Latch when written: POR TD pins when read xxxx xxxx uuuu uuuu
09h(5) PORTE — — — — — RE2 RE1 RE0 ---- -000 ---- -000
0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 LVDIF — — –BCLIF—— CCP2IF 0--- 0--0 0--- 0--0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuu u uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuu u uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 000 0 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuu u uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 000 0 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuu u uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuu u uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h T XREG USART Transmit Data Register 0000 0000 000 0 0000
1Ah RCREG USART Receive Data Register 0000 0000 000 0 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuu u uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON —— CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuu u uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: These registers/bits are not implemented on the 28-pin devices read as '0'.
PIC16C77X
DS30275A-page 14 Advance Information 1999 Microchip Technology Inc.
Bank 1
80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(4) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000 q quuu
84h(4) FSR Indirect data memory address pointer xxxx xxxx uuu u uuuu
85h TRISA ——bit5
(5) PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h(5) TRISD POR TD Data Direction Register 1111 1111 1111 1111
89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 LVDIE — — —BCLIE—— CCP2IE 0--- 0--0 0--- 0--0
8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu
8Fh —Unimplemented — —
90h —Unimplemented — —
91h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPA DD Synchr on ous Ser i al Por t (I2C mode) Address Register 0000 0000 000 0 0000
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
95h —Unimplemented — —
96h —Unimplemented — —
97h —Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 000 0 0000
9Ah —Unimplemented — —
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 0000 ----
9Ch LVDCON —— BGST LVDEN LV3 LV2 LV1 LV0 --00 0101 --00 0101
9Ah —Unimplemented — —
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuu u uuuu
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: These registers/bits are not implemented on the 28-pin devices read as '0'.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 15
Bank 2
100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
101h TMR0 Timer0 module’s register xxxx xxxx uuu u uuuu
102h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
103h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
104h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
105h —Unimplemented — —
106h PORTB P ORTB Data Latch when written: PORTB pins when read xxxx 11xx uuuu 11uu
107h —Unimplemented — —
108h —Unimplemented — —
109h —Unimplemented — —
10Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 000 0 000u
10Ch-
10Fh —Unimplemented — —
Bank 3
180h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 000 0 0000
183h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
184h(4) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
185h —Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch-
18Fh —Unimplemented — —
TABLE 2-1 PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
4: These registers can be addressed from any bank.
5: These registers/bits are not implemented on the 28-pin devices read as '0'.
PIC16C77X
DS30275A-page 16 Advance Information 1999 Microchip Technology Inc.
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Figure 2-3, contains
the arithmeti c status of th e ALU , the RESET statu s and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disab led . The se bi ts ar e set o r clea red a ccordi ng to the
device logi c. Fur t her more, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will cl ear t he up p er -t h ree
bits an d set the Z bi t. T his l ea ve s the STATUS regist er
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect t he Z, C or DC b its from the STATUS register. F or
other i nst ruction s , not affec t in g an y sta tus bit s , s ee the
"Instruction Set Summary."
FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
Note 1: The C and DC bits operate a s a borrow and
digit bo rrow bit, respectively , in subtraction.
See the SUBLW and SUBWF instructions for
examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FF h)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4: TO: T ime-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borro w bi t ( ADDWF, ADDLW,SUBLW,SUBWF instructions) (f or bo rro w th e po larity i s rever sed )
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 17
2.2.2.2 OPTION_REG REGISTER
The OPTION_REG regi ster is a readable and writable
register which co ntains v arious co ntrol bits to c onfigur e
the TMR0 prescaler/WDT postscaler (single assign-
abl e regist er kno wn als o as th e prescale r), the External
INT Interrupt, TMR0, and the weak pull-ups on POR TB.
FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h, 181h)
Note: To achieve a 1:1 prescaler assi gnment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORT B pull-u ps are enabled by indiv idu al port latch va lue s
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescale r is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16C77X
DS30275A-page 18 Advance Information 1999 Microchip Technology Inc.
2.2.2.3 INTCON REGISTER
The I NTCON Regi ster i s a rea dab le a nd w ritabl e regi s-
ter which contains var ious enable and flag bits for the
TMR0 register overflow, RB Por t change and Exter nal
RB0/INT pin interrupts.
FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
Note: Interrupt fl ag b its get s et wh en a n in terrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral In terrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: IINTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (mu s t be cleared in software)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 19
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6: ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5: RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4: TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on the 28-pin devices, always maintain this bit clear.
PIC16C77X
DS30275A-page 20 Advance Information 1999 Microchip Technology Inc.
2.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch)
Note: Interrupt fl ag b its get s et wh en a n in terrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a wr ite operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6: ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5: RCIF: USART Rece ive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is empty
bit 4: TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1: TMR2IF: TMR2 to PR 2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PSPIF is reserved on the 28-pin devices, always maintain this bit clear.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 21
2.2.2.6 PIE2 REGISTER
This register contains the individual enable bits for the
CCP2, SSP bus collision, and low voltage detect inter-
rupts.
FIGURE 2-8: PIE2 REGISTER (ADDRESS 8Dh)
R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
LVDIE ———BCLIE —— CCP2IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7 LVDIE: Low-voltage Detect Interrupt Enable bit
1 = LVD Interrupt is enabled
0 = LVD Interrupt is disabled
bit 6-4: Unimplemented: Read as ’0 ’
bit 3: BCLIE: Bus Collision Interrupt Enable bit
1 = Bus Collision interrupt is enabled
0 = Bus Collision interrupt is disabled
bit 2-1: Unimplemented: Read as ’0 ’
bit 0: CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
PIC16C77X
DS30275A-page 22 Advance Information 1999 Microchip Technology Inc.
2.2.2.7 PIR2 REGISTER
This register contains the CCP2, SSP Bus Collision,
and Low-voltage detect interrupt flag bits.
.
FIGURE 2-9: PIR2 REGISTER (ADDRESS 0Dh)
Note: Interrupt fl ag b its get s et wh en a n in terrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
LVDIF ———BCLIF —— CCP2IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: LVDIF: Low-voltage Detect Interrupt Flag bit
1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software)
0 = The supply voltage is greater than the specified LVD voltage
bit 6-4: Unimplemented: Read as ’0 ’
bit 3: BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred while the SSP module configured in I2C Master was transmitting
(must be cleared in software)
0 = No bus collision occurred
bit 2-1: Unimplemented: Read as ’0 ’
bit 0: CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 23
2.2.2.8 PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry con-
tain an additional bit to differentiate a Brown-out Reset
condition from a Powe r-on Reset condition.
FIGURE 2-10: PCON REGISTER (ADDRESS 8Eh)
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR is
clear, indicating a brown-out has o cc urre d.
The BOR status bit is a don’t care and is
not necessarily predictab le if the brown-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
————— —PORBOR R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as ’0 ’
bit 1: POR: Powe r-on Reset Status bi t
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR: Brown-out Reset Status bit
1 = No Brow n-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
PIC16C77X
DS30275A-page 24 Advance Information 1999 Microchip Technology Inc.
2.3 PCL and PCLATH
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is no t directly readable or writab le. All updates
to the PCH register go through the PCLATH register.
2.3.1 STACK
The stac k allo ws a co mbination o f up to 8 pr ogram c alls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Midrange devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readab le or writab le . The PC is PUSHed on to the stac k
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After t he stac k has been PUSHe d eight t imes , the nin th
push overwrites th e value that was stored from the firs t
push. The tenth push o verwrites the second pus h (an d
so on).
2.4 Program Memory Paging
PIC16C77X devices are capable of addressing a con-
tinuou s 8K word block of pr ogram mem ory. T he CALL
and GOTO instr uctions provide only 11 bits of address
to allow branching within any 2K program memory
page. When doing a CALL or GOTO instruction the
upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the user must ensure that the page select bits are
programmed so that the desired program memory
page is addressed. If a retur n from a CALL instr uct ion
(or interrupt) i s ex ecuted, t he entire 13-b it PC is pushe d
onto the stack. Therefore, manipulation of the
PCLATH<4:3> bits are not required for the return
instructions (which POPs the address from the stack).
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 25
The IN DF r egist er is not a physical r e gis ter. A dd ress-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer
). This is in dir ec t ad dressi ng .
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.
EXAMPLE 2-1: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
An effec ti ve 9-bit a ddre ss is obta in ed by conca tena tin g
the 8-bit F SR regist er and the IRP b it (STATUS<7>), as
shown i n Figure 2-11.
FIGURE 2-11: DIRECT/INDIRECT ADDRESSING
Note 1: For register file map detail see Figure 2-2.
Data
Memory(1)
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6 0
from opcode IRP FSR register
70
bank select location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
PIC16C77X
DS30275A-page 26 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 27
3.0 I/O PORT S
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general pur pose I/O pin.
Addit ional in formation on I/O ports ma y b e found in the
PICmicro™ Mid-Range Reference Manual,
(DS33023).
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional por t for the 40/44
pin devices and is 5-bits wide for the 28-pin devices.
PORTA<5> is not on the 28-pin devices. The corre-
sponding data direction register is TRISA. Setting a
TRISA b it (=1 ) wi ll m ake the corres po ndi ng PO RTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
mak e th e c orre sp ond ing PORTA pin an o utpu t, i .e., put
the contents of the output latch on the selected pin.
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies th at the port pins are
read, thi s v al ue is m odifie d, and then written to th e port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and analog VREF inputs and precision on-board refer-
ences (VRL/VRH). The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
The TRISA register controls the direction of the RA
pins, even when they a re being used as analog inputs.
The user m ust ensure the bits in the T RISA registe r are
maintain ed set when using them as analog i nput s.
EXAMPLE 3- 1: INITIALIZI NG PORTA
BCF STATUS, RP0 ;
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA2 PINS
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
Data
bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and
VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter
VRH, VRL
VRHOEN, VRLOEN
Sense input for
VRO+, VRO- amplifier
PIC16C77X
DS30275A-page 28 Advance Information 1999 Microchip Technology Inc.
FIGURE 3-2: BLOCK DIAGRAM OF
RA1:RA0 AND RA5 PINS FIGURE 3-3: BLOCK DIAGRAM OF
RA4/T0CKI PIN
TABLE 3-1 PORTA FUNCTIONS
TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Data
bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and
VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
VSS
I/O pi n (1)
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
QD
Q
CK
QD
Q
CK
EN
QD
EN
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input0
RA1/AN1 bit1 TTL Input/output or analog input1
RA2/AN2/VREF-/VRL bit2 TTL Input/output or analog input2 or VREF- input or internal reference
voltage low
RA3/AN3/VREF+/VRH bit3 TTL Input/output or analog input or VREF+ input or output of internal
reference voltage high
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0
Output is open drain type
RA5/AN4(1) bit5 TTL Input/output or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: RA5 is reserved on the 28-pin devices, maintain this bit clear.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
05h PORTA(1) —— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA(1) —— PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unc hanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: PORTA<5>, TRISA<5> are reser ved on the 28-pin dev ices, maintain these bits clear.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 29
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional por t. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will mak e the corres ponding POR TB pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISB bit (=0) will
mak e th e corr espond ing PORTB pin an ou tput, i .e. , put
the contents of the output latch on the selected pin.
EXAMPLE 3- 1: INITIALIZI NG PORTB
BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each o f the POR TB pi ns h as a weak internal pull -up. A
single control bit can tu rn on all the pull-ups . This is per-
formed by cl earing bit RBPU (OPTION_REG<7>). The
weak pu ll-up i s automa tically t ur ned off wh en the po rt
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
The RB0 pin is multiplexed with the external interrupt
(RB0/INT).
FIGURE 3-4: BLOCK DIAGRAM OF RB0 PIN
The RB1 pin is multiplexed with the SSP module slave
select (RB1/SS).
FIGURE 3-5: BLOCK DIAGRAM OF RB1/SS
PIN
The RB2 pin is multiplexed with analog channel 8
(RB2/AN8).
FIGURE 3-6: BLOCK DIAGRAM OF
RB2/AN8 PIN
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
Schmitt Trigger
Buffer
TRIS Latch
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
SS input
I/O
pin(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
Schmitt Trigger
Buffer
TRIS Latch
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
To A/D converter
I/O
pin(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
TRIS Latch
Analog
input mode
PIC16C77X
DS30275A-page 30 Advance Information 1999 Microchip Technology Inc.
The RB3 pin is multiplexed with analog channel 9 and
the low voltage detect input (RB3/AN9/LVDIN)
FIGURE 3-7: BLOCK DIAGRAM OF
RB3/AN9/LVDIN PIN
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause t his interrupt to occur (i.e . an y RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compare d with the old v a lue latc hed on the la st read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to genera te the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user , in th e interrupt service routine , can clear the inter-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the inte rrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 3-8: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
To A/D converter and LVD reference input
I/O
pin(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
TRIS Latch
Analog
input mode
or LVD input
mode
Data Latch
From other
RBPU(2) P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pi ns
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
ST
Buffer
RB7:RB6 in serial programming mode Q3
Q1
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 31
TABLE 3-3 PORTB FUNCTIONS
TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software
programmab le weak pull-up.
RB1/SS bit1 TTL/ST(3) Input/output pin or SSP slave select. Internal software programmable
weak pull-up.
RB2/AN8 bit2 TTL Input/output pin or analog input8. Internal software programmable
weak pull-up.
RB3/AN9/LVDIN bit3 TTL Input/output pin or analog input9 or Low-voltage detect input. Internal
software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software
programmab le weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software
programmab le weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software
programmable weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software
programmable weak pull-up. Serial progra mming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when used as the SSP slave select.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
V alue on all
other re s ets
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx 11xx uuuu 11uu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16C77X
DS30275A-page 32 Advance Information 1999 Microchip Technology Inc.
3.3 PORTC and the TRISC Register
PORTC is an 8-bit wide bi-directional por t. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (=1) will make th e correspondin g PORTC pi n
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output, i.e., put
the contents of the output latch on the selected pin.
POR TC is m ultiple x ed with se ver al periphera l function s
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in de fining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-mod-
ify-wri te in stru cti ons (BSF, BCF, XOR WF) with TRISC
as destination should be avoided. The user should refer
to the corresponding peripheral section for the correct
TRIS bit settings.
EXAMPLE 3- 1: INITIALIZI NG PORTC
BCF STATUS, RP0 ; Select Bank 0
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
FIGURE 3-9: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORT/PERIPHERAL Select(2)
Data bu s
WR
PORT
WR
TRIS
RD
Data Latch
TRIS Latch
RD TRIS Schmitt
Trigger
QD
Q
CK
QD
EN
Peripheral Data Out 0
1
QD
Q
CK
P
N
VDD
VSS
PORT
Peripheral
OE(3)
Peripheral input
I/O
pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: P ort/P eripheral select signal selects between port
data and peripheral output.
3: Per ipheral OE (output enable) is only activat ed if
peripheral select is active.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 33
TABLE 3-5 PORTC FUNCTIONS
TABLE 3-6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2
input/Compare2 output/P WM2 outpu t
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C
modes.
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output
RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous transmit or
Synchronous clock
RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous receive or
Synchrono us data
Legend: ST = Schmitt Trigger input
Addr e s s Name B it 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unc hanged.
PIC16C77X
DS30275A-page 34 Advance Information 1999 Microchip Technology Inc.
3.4 PORTD and TRISD Registers
This s ection is ap plica b le to th e 40/4 4-pin d e vic es on ly.
PORTD is an 8-bit por t with Schmitt Tr igger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode , the in put buffe rs
are TTL.
FIGURE 3-10: PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
TABLE 3-7 PORTD FUNCTIONS
TABLE 3-8 SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
I/O pin (1)
Note 1: I/O pins have protection diodes to VDD and VSS.
QD
CK
QD
CK
EN
QD
EN
Name Bit# Buffer Type Function
RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave por t bit0
RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave por t bit1
RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave por t bit2
RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave por t bit3
RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave por t bit4
RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave por t bit5
RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave por t bit6
RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave por t bit7
Legend: ST = Schmitt Tr igger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on:
POR,
BOR
Value on all
other resets
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE IBF OBF IBOV PSPMODE —PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 35
3.5 PORTE and TRISE Register
This s ection is a pplicab le to the 40/44-pin de vice s only.
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADCON1 is conf igured for digital I/O . In
this mode the input buffers are TTL.
Figure 3-12 shows th e TR ISE re gi ster, w hic h a lso con-
trols the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
select ed as an analo g input, these pins will r ead as ’ 0’s .
TRISE control s the direction of th e RE pins, e v en when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
FIGURE 3-11: PORTE BLOCK DIAGRAM (IN
I/O PORT MODE)
FIGURE 3-12: TRISE REGISTER (ADDRESS 89h)
Note: On a Power-on Reset these pins are con-
figured as analog inputs.
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
QD
CK
QD
CK
EN
QD
EN
I/O pin (1)
Note 1: I/O pins have protection diodes to VDD and VSS.
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE — bit2 bit1 bit0 R = Readable bit
W = Writable bit
U = Unimplem ented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7 : IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6: OBF: Output Buffer Full Status bit
1 = The output buf fer still holds a previously written word
0 = The output buffer has been read
bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4: PSPMODE: Parallel Slave Port Mode Select bit
1 = Parall el slave port mode
0 = General purpose I/O mode
bit 3: Unimplemented: Rea d as '0'
PORTE Data Direction Bits
bit 2: Bit2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1: Bit1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0: Bit0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
PIC16C77X
DS30275A-page 36 Advance Information 1999 Microchip Technology Inc.
TABLE 3-9 PORTE FUNCTIONS
TABLE 3-10 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name Bit# Buffer Type Function
RE0/RD/AN5 bit0 ST/TTL(1) In put /out put port pin or read control in put in p arallel sla ve port mode or
analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR/AN6 bit1 ST/TTL(1) Input/out put port pi n or write control input in par a llel sla v e po rt mode or
analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Tr igger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other re sets
09h PORTE — — — — —RE2RE1RE0---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — P ORTE Data Direction Bits 0000 -111 0000 -111
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 37
3.6 Parallel Slave Port
The Parallel Slave Port is implemented on the
40/44-pin devices only.
PORTD operates as an 8-bit wide Parallel Slave Por t,
or microprocessor port when control bit PSPMODE
(TRISE <4>) i s set. I n slave mode it is as ynchron ously
readab le and writab le by the e xternal world thro ugh RD
control input pin RE0/RD and WR control input pin
RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus . Th e e xte rnal microproc esso r can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables por t pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The configuration
bits, PCFG3:PCFG0 (ADCON1<3:0>) must be config-
ured to make pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines a re first de tected lo w . A read fro m the PSP occu rs
when both the CS and RD lines are first detected low.
FIGURE 3-13: PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL SLAVE
PORT)
FIGURE 3-14: PARALLEL SLAVE PORT WRITE WAVEFORMS
Data bus
WR
PORT
RD
RDx
QD
CK
EN
QD
EN
PORT
pin
One bit of PORTD
Set interrupt flag
PSPI F (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
PIC16C77X
DS30275A-page 38 Advance Information 1999 Microchip Technology Inc.
FIGURE 3-15: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 3-11 REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
08h PORTD Port data latch when written: Port pins when read xxxx xxxx uuuu uuuu
09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
Legend: x = unknown, u = unc hanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 39
4.0 TIMER0 MODULE
The Timer0 module timer/counte r has the following fea-
tures:
• 8-bit time r/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
4.1 Timer0 Operation
Timer0 ca n operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule wi ll i nc rem ent every instruct ion cy cl e (without pres-
caler). If the TMR0 register is wr itten, the increment is
inhibited for the following two instruction cycles. The
use r can work around thi s by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG <4 >). Cl eari ng b it T0SE sel ec ts the ris-
ing edge. Restrictions on the external clock input are
discussed in below.
When an e xternal cloc k input i s used for T imer0, it m ust
meet certain requirements. The requirements ensure
the e xternal cloc k can b e synchron ized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is available in the PICmicro™ Mid-Range Reference
Manu al, (DS330 23).
4.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which i s m utually exclusiv el y shared betw een
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler a ssignment an d prescale ratio .
Clearing bit PSA wil l assign t he presc aler to the Ti mer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TM R0 register (e .g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
FIGURE 4-1: TIMER0 BLOCK DIAGRAM
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the presca ler
count, but will not change the prescaler
assignment.
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
RA4/T0CKI
T0SE
0
1
1
0
pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
clocks TMR0
PSout
(2 cycle delay)
PSout
Data bus
8
PSA
PS2, PS1, PS0 Se t interrupt
flag bit T0IF
on ov erfl ow
3
PIC16C77X
DS30275A-page 40 Advance Information 1999 Microchip Technology Inc.
4.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the fly” during program
executio n.
4.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister ove rflows from FFh to 00 h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in s oftwa re b y th e Tim er0 mo dule interrupt s er-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro™ Mid-Range Reference Man-
ual, DS33023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other resets
01h,101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unc hanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer 0.
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (=Fosc/4)
SYNC
2
Cycles TMR 0 r e g
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
01
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
10
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
T0CS
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 41
5.0 TIMER1 MODULE
The Timer1 module timer/counte r has the following fea-
tures:
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• Readable and writable (Both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• Reset from CCP mo dule trigger
Timer1 has a control register, shown in Figure 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1O N (T1CO N<0 >).
Figure 5-3 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
5.1 Timer1 Operation
Timer1 can operate in one of these modes:
•As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is deter mined by the clock select
bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction
cycle. In coun ter mo de, it in creme nts on every ri sing
edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 a lso has an in ternal “reset input ”. This reset can
be generated by the CCP module (Section 7.0).
FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as ’0 ’
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 P rescale value
10 = 1:4 P rescale value
01 = 1:2 P rescale value
00 = 1:1 P rescale value
bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drai n
bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 us es the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Tim er1
0 = Stops Timer1
PIC16C77X
DS30275A-page 42 Advance Information 1999 Microchip Technology Inc.
5.1.1 TIMER1 COUNTER OPERATION
In this m ode, Tim er1 is bein g incremented via an e xter-
nal source. Increments occur on a rising edge. After
Timer1 is enabled in counter mode, the module must
first have a falling edge before the counter begins to
increment.
FIGURE 5-2: TIMER1 INCREMENTING EDGE
FIGURE 5-3: TIMER1 BLOCK DIAGRAM
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
TMR1H TMR1L
T1OSC T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 SLEEP input
T1OSCEN
Enable
Oscillator(1) FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
clock input
2
RC0/T1OSO/T1CKI
RC1/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverte r and feedback resistor are turned off. This eliminates power drain.
Set flag bit
TMR1IF on
Overflow TMR1
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 43
5.2 Timer1 Oscillator
A crystal oscill ator circuit is b uilt in betw een pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The osc illa-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 5-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 5-1 CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
5.3 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PI R1<0>).
This inte rrupt can be enab led/d isab led by setting/c lear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4 Resetting T imer1 us ing a CCP Trigger
Output
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer 1 mus t be c on f i gur ed fo r ei th er ti me r or sy nc hr o-
niz ed counte r mode to ta ke ad va ntage of thi s feature . If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the e v ent that a write to Timer1 coi ncides with a spe-
cial event trigger from CCP1, the wr ite will take prece-
dence.
In this mode of oper ation, the CCPR1H:CC PR1L regis -
ters pair effectively becomes the period register for
Timer1.
TABLE 5-2 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Ep son C -001 R32.768K-A ± 20 PPM
100 kHz Epson C-2 100.00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator but als o increases the start-up
time.
2: Since each resonator/crystal ha s its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
Note: The special event tr iggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unk nown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.
PIC16C77X
DS30275A-page 44 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 45
6.0 TIMER2 MODULE
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (Both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to gen-
erate clock shift
Timer2 has a control register, shown in Figure 6-1.
Timer2 can be shut off by clearing control bit TMR2O N
(T2CON<2>) to minimize power consumption.
Figure 6-2 is a simplified block diagram of the Timer2
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
6.1 Timer2 Operation
Timer2 can be used as the PWM time-base for PWM
mode of the CCP module.
The TMR2 register is readable and writable, and is
cleared on any device reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
Watchdog Timer reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
FIGURE 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2: TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
PIC16C77X
DS30275A-page 46 Advance Information 1999 Microchip Technology Inc.
6.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readab le and writable register . The PR2 register is ini-
tialized to FFh upon reset.
6.3 Output of TMR2
The out put of T MR2 (before th e postscaler) is fed to the
Synchro nou s Serial Port module whi ch op tio nal ly use s
it to generate shift clock.
FIGURE 6-2: TIMER2 BLOCK DIAGRAM
TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Comparator
TMR2
Sets flag
TMR2 reg
output (1)
Reset
Postscaler
Prescaler
PR2 reg
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
to
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unk nown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: These bits are reserved on the 28-pin, always maintain these bits clear.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 47
7.0 CAPTURE/COMPARE/PWM
(CCP) MODULE(S)
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/s lave Duty Cycle register. Table 7-1 shows the
timer resources of the CCP module modes.
The oper ation of CCP1 is identical to that of CCP2, with
the exception of the special trigger. Therefore, opera-
tion of a CCP module in the following sections is
described with respect to CCP1.
Table 7-2 shows the interaction of the CCP modules.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
CCP2 Module
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
Additional infor mation on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
TABLE 7-1 CCP MODE - TIMER
RESOURCE
TABLE 7-2 INTERACTION OF TWO CCP MODULES
FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time-base.
Capture Compare The compare should be configured for the special event trigger, which clears TMR1.
Compare C ompare The compare(s) should be configured for the speci al event tri gger, which clears TM R1.
PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM Capture None
PWM Compare None
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit
W =Writable bit
U = Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7-6: Unimpl emente d: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits ar e th e tw o LSbs of the PWM duty cycle . Th e ei ght MSbs are foun d in C CPR xL .
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = C ompare mode , genera te softw are interrupt on match (C CPxIF bit is set, CCPx pin is unaffect ed)
1011 = Compare mode , trigger special e vent (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1
and starts an A/D conversion (if A/D module is enabled))
11xx = PWM mode
PIC16C77X
DS30275A-page 48 Advance Information 1999 Microchip Technology Inc.
7.1 Captu re Mod e
In Capture mode, CCPR1H:CCPR1L captures the
16-bit v alue of th e TMR1 register wh en an ev ent oc curs
on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cle ared in softw are. If another capt ure occurs b efore
the value in register CCPR1 is read, the old captured
value will be lost.
7.1.1 CCP PIN CONFIGURATION
In Captu re m ode, the RC2/CCP1 p in s hou ld be config-
ured as an input by setting the TRISC<2> bit.
FIGURE 7-2: CAPTURE MODE OPERATION
BLOCK DIAGRAM
7.1.2 TIMER1 MODE SELECTION
Timer1 m ust be runni ng in timer m ode or s ynchr oniz ed
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
7.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
7.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not b e cl ea re d, th er e for e th e f i rs t c ap t ure m ay be f ro m
a non-zero prescaler. Example 7-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 7-1: CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
Note: If the RC2/CCP1 is configured as an out-
put, a write to th e port can cause a ca pture
conditi on.
CCPR1H CCPR1L
TMR1H TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
Pin
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 49
7.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. Wh en a match occurs, th e RC2/CCP1 pin is:
•driven High
• driven Low
• remain s Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 7-3: COMPARE MODE
OPERATION BLOCK
DIAGRAM
7.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
7.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation ma y not work.
7.2.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not affect ed. Only a CCP inte rrupt is gene rated (if
enabled).
7.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bi t prog r ammab le period regis ter for
Timer1.
The special trigger output of CCP2 resets the TMR1
register pair, and starts an A/D conversion (if the A/D
module is enabled).
TABLE 7-3 REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND T IMER1
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Ev ent Trigger (CCP2 only)
Set flag bit CCP1IF
(PIR1<2>)
match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enable
Pin
Special event trigger will:
reset Time r1 , but no t se t inte rr u pt flag bit T M R1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>)
which starts an A/D conv ersion
Note: Clearing the CCP1CON register will force
the RC2/ CCP1 comp are output latc h to the
default low level. This is not the data latch.
Note: The special event trigger from the CCP2
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all othe r
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplement ed read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin, alway s mainta in these bits clear.
PIC16C77X
DS30275A-page 50 Advance Information 1999 Microchip Technology Inc.
7.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is m ultiplex ed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 7-4 shows a simplified block diagram of t he CCP
module in PWM mode.
F or a step by step pro cedure on h ow t o set up the CCP
module for PWM operation, see Section 7.3.3.
FIGURE 7-4: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 7-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period (1/
period).
FIGURE 7-5: PWM OUTPUT
7.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR 2 is equal t o PR2, the follo wing three ev ents
occur on the next incr ement cycle:
•TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from C CPR1L into
CCPR1H
7.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
To sc • (TMR2 prescale value)
CCPR1L and CC P1CON <5:4> c an be writ ten to at an y
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to dou ble buffer the PWM duty cy cl e . This doubl e
buffer ing is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolut ion (bits) for a gi ven PWM
frequency:
For an example PWM period and duty cycle calcu-
lation, see the PICmicro™ Mid-Range Reference
Manual, (DS33023).
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty cycle registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time -base.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Tim er2 p ostscaler (see Section 6.0) is
not us ed in t he det erm inati on of t he PWM
frequenc y. The pos tscaler cou ld be used to
have a servo update rate at a different fre-
quency than the PWM output.
Note: If the PWM duty cycle va lue is longer than
the PWM per iod the CCP1 pin will not be
cleared.
log( FPWM
log(2)
FOSC )bits
=
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 51
7.3.3 SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period b y writin g to the PR2 re gis-
ter.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC< 2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 7-4 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 7-5 REGISTERS ASSOCIATED WITH PWM AND TIMER2
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Presca ler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 5.5
Address Name Bit 7 Bit 6 B it 5 B it 4 B it 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h T RISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 mod ule’s register 0000 0000 0000 0000
92h PR2 Timer2 module’s period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/ PWM r egister1 ( MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin, alway s mainta in these bits clear.
PIC16C77X
DS30275A-page 52 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 53
8.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The Master Synchronous Serial P ort (MSSP) module is
a serial interface useful for communicating with other
peripher al or mi crocontro ller devices . These periphera l
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two mode s:
• Serial Peripheral Interface ( SPI)
• Inter-Integrated Circuit (I2C™)
PIC16C77X
DS30275A-page 54 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF R =Readable bit
W =Writable bit
U =Unimp lemented bit, read
as ‘0 ’
- n =Value at POR reset
bit7 bit0
bit 7: SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at mi ddle of data output time
SPI Slave Mode
SMP must be cleared when SPI is us ed in slave mode
In I2C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6: CKE: SPI Clock Edge Select (Figure 8-6, Figure 8-8, and Figure 8-9)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5: D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4: P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3: S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2: R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or not ACK bit.
In I2C slave mode:
1 = Read
0 = Write
In I2C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
Or’ing this bit with SEN, RSEN, PEN, RCEN, or AKEN will indicate if the MSSP is in IDLE mode
bit 1: UA: Update Addres s (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0: BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 55
FIGURE 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit
W = Writable b i t
- n =Value at POR reset
bit7 bit0
bit 7: WCOL: Write Collision Detect bit
Master Mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0 = No collision
Slave Mode:
1 = The SSPBU F register is written whil e it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6: SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPB UF register is still holding the previous data. In case of ov erflow ,
the data in SSPSR is lost. Ov erflo w can only occur in slav e mode . In sla v e mode , the us er must rea d the
SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode, the overflow bit is not
set since each new reception (and transmission) is initiated by writing to the SSPBUF register. (Must be
cleared in software).
0 = No overflow
In I2C mode
1 = A byte is receiv ed while the SSPBUF register is still ho lding the previous b yte. SSPO V is a "don’t care"
in transmit mode. (Must be cleared in software).
0 = No overflow
bit 5: SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output.
In SPI mode
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables seri al port and configures these pi ns as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables seri al port and configures these pi ns as I/O port pins
bit 4: CKP: Clock Po larity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C slave mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
In I2C master mode
Unused in this mode
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C sl ave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1000 = I2C master mode, clock = FOSC / (4 * (SSPADD+1) )
1xx1 = Reserved
1x1x = Reserved
PIC16C77X
DS30275A-page 56 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN R =Readable bit
W =Writable bit
U =Unimplem en t ed bit ,
Read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7: GCEN: General Call Enable bit (In I2C slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.
0 = General call address disabled.
bit 6: AKSTAT: Acknowledge Status bi t (In I2C mast er mode only)
In master transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5: AKDT: Acknowledge Data bit (In I2C master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4: AKEN: Acknowled ge Sequence Enable bit (In I2C master mode only).
In master receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence idle
bit 3: RCEN: Receive Enable bit (In I2C master mode only).
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2: PEN: Stop Condition Enable bit (In I2C master mode only).
SCK release control
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition idle
bit 1: RSEN: Repeated Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition idle.
bit 0: SEN: Start Condition Enabled bit (In I2C master mode only)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition idle.
Note: Fo r bits AKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the idle mode, this bit may not be
set (no spooling), and the SSPBUF m ay not be written (or writes to the SSPBUF are disabled).
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 57
8.1 SPI Mode
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. All
four modes of SPI are suppor ted. To accomplish com-
munication, typically three pins are used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally, a four th pin may be used when in a slave
mode of operation:
•Slave Select (SS
)
8.1.1 OPERATION
When initializing the SPI, several options need to be
specif ied. This is don e by prog ramming the ap propriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These co ntrol bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data input sample phase
(middle or end of data output time)
• Clock edge
(output data on rising/falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode on ly)
Figure 8-4 shows the b loc k d iagr am of the MSSP mod-
ule when in SPI mode .
FIGURE 8-4: MSSP BLOCK DIAGRAM
(SPI MODE)
The MSSP consis ts of a transmit/re ceive Shift Register
(SSPSR) and a buffer register (SSPB UF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF hold s the data that w as written to the SSPSR,
until the received data is ready. Once the 8-bits of data
hav e bee n receiv ed, that b yte is mov ed to the SSPB UF
register. Then the buffer full detect bit BF
(SSPSTAT<0>) and the interrupt flag bit SSPIF
(PIR1<3>) are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
trans miss io n/re cep tio n of dat a wil l be igno re d, an d the
write collision detect bit WCOL (SSPCON<7>) will be
set. User software must clear the WCOL bit so that it
can be determined if the following write(s) to the SSP-
BUF register completed successfully.
When the application software is expecting to receive
v alid d ata, the SSPBUF s hould be read b efore th e ne xt
by te of data to transfer is written to the SSPB UF. Buffer
full bit, BF (SSPSTAT<0>), indicates when the SSP-
BUF h as been l oaded with the receiv ed data (tr ansmis-
sion is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
Read Write
Internal
data bus
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0 shift
clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/R X in SS PS R
Data direction bit
2
SMP:CKE
SDI
SDO
SS
SCK
PIC16C77X
DS30275A-page 58 Advance Information 1999 Microchip Technology Inc.
determine when the transmission/reception has com-
pleted. The SSPBUF must b e read and/or written. If the
inter rupt me tho d i s not go ing to be used, then softwa re
polling can be done to ensure that a write collision does
not occur. Example 8-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
EXAMPLE 8-1: LOADING THE SSPBUF
(SSPSR) REGISTER
The SSPSR is not di rectly readable or writable, and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP status register (SSPSTAT) indi-
cates the various status conditions.
8.1.2 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) m ust be set. To reset or recon figure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
SDI, SDO, SCK, and SS pins as serial port pins. F or the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is au tom ati ca lly co ntrolled by th e SPI mo du le
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
•SS
must have TRISA<5> set
Any s erial port func tion that is n ot desired m ay be ov er-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
8.1.3 TYPICAL CONNECTION
Figure 8-5 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite edge
of the clock. Bo th processo rs should b e program med to
same Cloc k Polarity (CKP), then both control lers woul d
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data tr ans mi ss io n:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
FIGURE 8-5: SPI MASTER/SLAVE CONNECTION
BSF STATUS, RP0 ;Specify Bank 1
LOOP BTFSS SSPSTAT, BF ;Has data been
;received
;(transmit
;complete)?
GOTO LOOP ;No
BCF STATUS, RP0 ;Specify Bank 0
MOVF SSPBUF, W ;W reg = contents
;of SSPBUF
MOVWF RXDATA ;Save in user RAM
MOVF TXDATA, W ;W reg = contents
; of TXDATA
MOVWF SSPBUF ;New data to xmit
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PR OCESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROC ES S O R 2
SCK
SPI Slave SSPM3:SSPM0 = 010xb
Serial Clock
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 59
8.1.4 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 8-5) is to broad-
cast data by the software protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will conti nue to shif t in the signa l present o n the
SDI pin at the programmed clock rate. As each byte is
recei ved, it wi ll be lo ad e d i nt o t he S SPB UF r e gister as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
The cloc k polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 8-6, Figure 8-8, and Figure 8-9 where the MSb
is transmitted first. In master mode, the SPI clock rate
(bit rate) is user programmable to be one of the follow-
ing:
•F
OSC/4 (or TCY)
•F
OSC/16 (or 4 • TCY)
•FOSC/64 (or 16 • TCY)
• Timer2 ou tput/2
This al lows a maxi mum b it cloc k freq uency (at 20 MHz)
of 8.25 MHz.
Figure 8-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received da ta is
shown.
FIGURE 8-6: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 clock
modes
Input
Sample
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Wr it e to
SSPBUF
SSPSR to
SSPBUF
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(CKE = 0)
(CKE = 1)
Next Q4 cycle
after Q2↓
PIC16C77X
DS30275A-page 60 Advance Information 1999 Microchip Technology Inc.
8.1.5 SLAVE MODE
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latch ed the interrupt flag bit SSPIF (PIR1<3>)
is set.
While in slave mode the external clock is supplied by
the e x ternal cloc k sour ce o n the SCK pin. This e xt ernal
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in sleep mode, the slave can transmit/receive
data. When a byte is received the device will wake-up
from sleep.
8.1.6 SLAVE SELECT SYNCHRONIZATION
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode with SS pin control
enabled (SSPCON<3:0> = 0100). The pin must not
be driven low for the SS pin to function as an input.
TRISA<5> must be set. When the SS pin is low,
transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output.
External pull-up/ pull-down resistors may be desirable,
depending on the application.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a rece iver the SDO pi n can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 8-7: SLAVE SYNCHRONIZATION WAVEFORM
Note: When the SPI module is in Slave Mode
with SS pin control enabled, (SSP-
CON<3:0> = 0100) the SPI module will
reset if the SS pin is set to VDD.
Note: If the SPI is used in Slave Mode with
CKE = ’1’, then SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7
SDO bit7 bit6 bit7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPS R to
SSPBUF
SS
Flag
bit0
bit7 bit0
Next Q4 cycle
after Q2↓
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 61
FIGURE 8-8: SPI SLAVE MODE W AVEFORM (CKE = 0)
FIGURE 8-9: SPI SLAVE MODE WAVEFORM (CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPS R to
SSPBUF
SS
Flag
optional
Next Q4 cycle
after Q2↓
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
not optional
Next Q4 cycle
after Q2↓
PIC16C77X
DS30275A-page 62 Advance Information 1999 Microchip Technology Inc.
8.1.7 SLEEP OPERATION
In master mode all module clocks are halted, and the
tra nsmiss ion/rec eption will re main i n that sta te unti l the
device wakes from sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In slave mode, the SPI transmit/receive shift register
oper at es as y nch ron ous ly to the device. This allows th e
device to be placed in sleep mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits hav e been received , the MSSP interrupt
flag bit will be set and if enabled will wake the device
from sleep.
8.1.8 EFFECTS OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
TABLE 8-1 REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’ . Shaded cells are not used by the SSP in SPI mode.
Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 63
8.2 MSSP I2C Operation
The MSSP module in I2C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications a s well as 7-bit and 10-bit address-
ing.
Refer to Application Note AN578,
"Use of the SSP
Module in the I
2
C Multi-Ma ste r Enviro nm ent. "
A "glitch" filter is on the SCL and SD A pins when the pin
is an in pu t. Th is filter operat es in b oth the 100 kHz and
400 kHz modes . In the 100 kHz mode , when these pins
are an ou tput, there is a s lew ra te control of the pin that
is independant of device frequency.
FIGURE 8-10: I2C SLAVE MODE BLOCK
DIAGRAM
FIGURE 8-11: I2C MASTER MODE BLOCK
DIAGRAM
Two p ins are used for dat a tr ansfe r . These a re the SC L
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins that are automatically
configured when the I2C mode is enabled. The SSP
module functions are enabled by setting SSP Enable
bit SSPEN (SSPCON<5>).
The MSSP module has six registers for I2C operation.
They are the:
• SSP Control Regist er (SSPCON)
• SSP Control Regist er2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I2C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I2C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the cl ock and data lines in I2C mode.
Read Write
SSPSR reg
Match detect
SSPADD reg
Start and
Stop bit detect
SSPBU F reg
Internal
data bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
SCL
shift
clock
MSb LSb
SDA
Read Write
SSPSR reg
Match detect
SSPADD reg
Start and Stop bit
detect / generate
SSPBU F reg
Internal
data bus
Addr Match
Set/Clear S bit
Clear/Set P bit
(SSPSTAT reg)
SCL
shift
clock
MSb LSb
SDA
Baud Rate Generator
7
SSPADD<6:0>
and
and Set SSPIF
PIC16C77X
DS30275A-page 64 Advance Information 1999 Microchip Technology Inc.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
by te was data or add ress if the ne xt b yte is the comple-
tion of 10-bit address, and if this will be a read or wr ite
data trans fer.
SSPBUF is the register to which the transfer data is
written to or read from. The SSPSR register sh ifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiv e r. This allo ws rece ption o f the next byte to b egin
befor e readi ng the last byte of re ceived data. W hen th e
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF regi ster
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD regis ter holds the sla ve ad dress. In 1 0-bit
mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0 ).
8.2.1 S LAVE MODE
In slave mode, the SCL and SDA pins must be config-
ured as inputs. The MSSP module will override the
input state with the output data when required (slave-
transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF regi st er with the recei ved value
currently in the SSPSR regis ter.
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The ov erflo w bit SSPO V (SSPCON<6>) w as set
before the transfer was received.
If the BF bit is set, the SSPSR register value is not
loaded in to the SSPBUF, bu t bit SSPIF and SSPO V are
set. Table 8-2 shows what h appens when a data trans-
fer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user sof tw are did not pro perly clear the overflow condi-
tion. Fl ag bit B F is cleare d b y reading the SSPB UF reg-
ister while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I2C specification as well as t he requirement of the
MSSP module is shown in timing parameter #100 and
parameter #101 of the Electrical Specifications.
8.2.1.1 ADDRESSING
Once the MSSP module has been enabled, it waits for
a STAR T cond iti on to oc cur. Following the START con-
dition, th e 8-bits are shifted in to the SSPSR register . All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register on the falling edge of the 8th
SCL pulse.
b) The buffer ful l bit, BF is set o n the falli ng edge of
the 8th SCL pulse.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(inter rupt is g enera ted i f enab le d) - o n the fallin g
edge of the 9th SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte sp ecify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the tw o MSbs
of the address. The sequence of events for a 10-bit
address is as follows, with steps 7- 9 for slave-transmit-
ter:
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the fir st (high)
byte of Address. This will clear bit UA and
release the SC L line.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Note: Following the Repeated Start condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit a ddress . The
user does not update the SSPADD for the
second half of the addres s.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 65
8.2.1.2 S LAVE R ECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is clea red. The re ce ive d ad dress is lo aded in to
the SSPBUF register.
When the address byte overflow condition exists, then
no ac knowled ge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
by te. Fla g bit SSPIF (PI R1<3>) m ust be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
TABLE 8-2 DATA TRANSF ER RECEIVED BYTE ACTIONS
8.2.1.3 SLAVE TRANSMISSION
When the R/W bit of the i ncoming ad dress byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register , which also loads the SSPSR register. Then the
SCL pin should be enabled by setting bit CKP (SSP-
CON<4>). The master must monitor the SCL pin prior
to asserting another clock pulse. The slave devices
may be hold ing off th e master by s tretchi ng the clo ck.
The eight d ata bits are sh ifted out on the falling edg e of
the SCL input. Th is ensur es that th e SD A signal is v alid
during the SCL high time ( Figure 8-13).
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software,
and the SSPSTAT register is used to determine the sta-
tus of the byte tran fer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
As a slave-transmitte r, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SD A line was high (not ACK), then the
data tr ansf er is co mplete . Wh en the no t A CK is latche d
by the slave, the slave logic is reset and the slave then
monitors for a nother occurrence of the START bi t. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then the SCL pin s hould be enabled
by setting the CKP bit.
FIGURE 8-12: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Note: The SSPBU F will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occured. The ACK is not sent and the SSP-
BUF is updated.
Status Bits as Data
Transfer is Received
SSPSR → SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
00 Yes Yes Yes
1 0 No No Yes
1 1 No No Yes
0 1 Yes No Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
P
9
8
76
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 123456789123456789123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Ad dr ess
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.
Not
PIC16C77X
DS30275A-page 66 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-13: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 Not ACK
Tran smitting Data
R/W = 1
Receiving Address
123456789 123456789 P
cleared in software
SSPBUF is written in softw are From SSP interrupt
service routine
Set bit after writing to SSPBUF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written-to
before the CKP bit can be set)
R/W = 0
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 67
FIGURE 8-14: I2C SLAVE-TRANSMITTER (10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
11110A9A8 A7 A6A5A4A3A2A1A0 11110 A8
R/W=1
ACK
ACK
R/W = 0
ACK
Receive First Byte of A ddress
Clear ed in software
Master sends NACK
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Transmit is complete
CKP has to be set for clock to be released
Bus Master
terminates
transfer
PIC16C77X
DS30275A-page 68 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-15: I2C SLAVE-RECEIVER (10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456 789 1 2345 67 89 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of A ddress
Cleared in software
Bus Master
terminates
transfer
D2
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
R/W = 1
Cleared in software
Dummy read of SSPBUF
to clear BF flag Read of SSPBUF
clears BF flag
Cleared by hardware when
SSPADD is updated with high
byte of address.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 69
8.2.2 GENERAL CALL ADDRESS SUPPORT
The addres sing procedure for the I2C bus is such t hat
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master . The e xception is the gener al call address which
can addres s all dev ices. When thi s address is used, all
devices should, in theory, respond with an acknowl-
edge.
The general call address is one of eight addresses
reser ved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0
The general call address is recognized when the Gen-
eral Ca ll En able bit (GCEN) is enabled (SSPCON2<7>
is set). Following a start-bit detect, 8-bits are shifted
into SSPSR and the address is compared against
SSPADD, and is also compared to the general call
address, fixed in hardware.
If the general call address matches, the SSPSR is
transfered to the SSPBUF, the BF flag is set (eighth bit),
and on the falling edge of the ninth bit (ACK bit) the
SSPIF flag is set.
When the interrupt is serviced. The source for the
interrupt can b e chec ke d by readi ng the conte nts of the
SSPBUF to determine if the address was device spe-
cific or a gene ral call address.
In 10-bit mode, the SSPADD is required to be updated
for the s econd hal f of the ad dress to m atch, an d the U A
bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set while the slave is config-
ured in 10-bit address mode, then the second half of
the address is not nece ss ary, the UA bit will no t be set,
and the slave will begin receiving data after the
acknowledge (Figure 8-16).
FIGURE 8-16: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
SDA
SCL S
SSPIF
BF
SSPOV
Cleared in software
SSPBUF is read
R/W = 0ACK
General Cal l Address
Address is compared t o General Call Address
GCEN
Receiving data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt flag
’0’
’1’
(SSPSTAT<0>)
(SSPCON<6>)
(SSPCON2<7>)
PIC16C77X
DS30275A-page 70 Advance Information 1999 Microchip Technology Inc.
8.2.3 SLEEP OPERATION
While in sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete b yte tr ansfer occ urs wak e the proce ssor from
sleep (if the SSP interrupt is enabled).
8.2.4 EFFECTS OF A RESET
A reset diables the SSP module and terminates the
current transfer.
TABLE 8-3 REGISTERS ASSOCIATED WITH I2C OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Dh PIR2 LVDIF — — —BCLIF — — CCP2IF 0--- 0--0 0--- 0--0
8Dh PIE2 LVDIE — — —BCLIE — — CCP2IE 0--- 0--0 0--- 0--0
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
91h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A PS R/WUA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode.
Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.
2: These bits are reserved on these devices, always maintain these bits clear.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 71
8.2.5 MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abl ed . C ont rol of the I2C bus ma y be taken whe n th e P
bit is set, or the bus is idle with both the S and P bits
clear.
In master mode, the SCL and SDA lines are manipu-
lated b y the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Ack nowledge trans mit
• Repeat ed Start
FIGURE 8-17: SSP BLOCK DIAGRAM (I2C MASTER MODE)
Read Write
SSPSR
Start bit, Stop bit,
Start bit detect,
SSPBUF
Internal
data bus
Set/Reset, S, P, WCOL (SSPSTAT)
shift
clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
Receive Enable
clock cntl
clock arbitrate/WCOL detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset AKSTAT, PEN (SSPCON2)
rate
generator
SSPM3:SSPM0,
PIC16C77X
DS30275A-page 72 Advance Information 1999 Microchip Technology Inc.
8.2.6 MULTI-MASTER OPERATI ON
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the MSSP module is disabled. Control of the I2C
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored, for abitration, to see if the signal level is the
e xpec ted outp ut le v e l. This chec k is performed in ha rd-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Dat a Transfer
• A Start Condition
• A Repeated Start Condition
• An A cknowledge Condition
8.2.7 I2C MASTER OPERATION SUPPOR T
Master Mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCO N and by setting the
SSPEN bit. Once master mode is enabled, the user
has six options.
- Assert a start condition on SDA and SCL.
- Assert a Repeated Start condition on SD A and
SCL.
- Write to the SSPBUF register initiating trans-
mission of data/address.
- Generate a stop condition on SDA and SCL.
- Configure the I2C port to receive data.
- Gener ate an Ac kno wledg e con dition at the end
of a received byte of data.
8.2.7.4 I2C MASTER MODE OPERATION
The master device generates all of the serial clock
pulses an d t he STAR T and STOP con dit ion s . A trans-
fer is ended with a STOP condition or with a Repeated
Start condition. Since the Repeated Star t condition is
also the beginning of the next serial transfer, the I2C
bus will not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an acknowledg e bit is rec ei ved. START a nd STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master receive mode the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case the R/W bit will be
logic '1'. Thus the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Ser ial
data is received via SDA while SCL outputs the serial
cloc k. Serial data is receiv ed 8 bits at a time . After each
byte is received, an acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of tra ns miss ion .
The baud rate generator used for SPI mode operation
is now used to set the SC L clock frequency for either
100 kHz, 400 kHz, or 1 MHz I2C operation. The baud
rate generator reload value is contai ned in the lower 7
bits of the SSPADD register. The baud rate generator
will automa tically begin counting on a write to the SSP-
BUF. Once the given operation is complete (i.e. trans-
mission of the last data bit is followed by ACK), the
internal clock will automatically stop counting and the
SCL pin will remain in its last state
A typical transmit sequence would go as follows:
a) The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
b) SSPIF is set. The module will wait the required
start time before any other operation takes
place.
c) The user loads the SSPBUF with address to
transmit.
d) Address is s hif ted ou t th e SDA pin unti l a ll 8 bits
are transmitted.
e) The MSSP Module shifts in the ACK bit fr om the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
f) Th e mo dul e gen erates an i nte rrupt a t t he end of
the ninth clock cycle by setting SSPIF.
g) The user loads the SSPBUF with eight bits of
data.
h) DATA is shifted out the SDA pin until all 8 bits
are transmitted.
Note: The MSSP Module , when configured in I2C
Master Mode, does not allow queueing of
events. For instance: The user is not
allowed to initiate a start condition, and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case the
SSPBUF will not be written to, and the
WCOL bit will be s et, in dicat ing t hat a write
to the SSPBUF did not occur.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 73
i) The MSSP Modu le shifts in the A CK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
j) The MSSP modul e generate s an interrupt at the
end of the ninth cloc k cyc le by setting the SSPIF
bit.
k) The user genera tes a ST OP con dition b y settin g
the STOP enable bit PEN in SSPCON2.
l) Interrupt is generated once the STOP condition
is complete.
8.2.8 BAUD RATE GENERATOR
In I2C master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 8-18). When the BRG is loa ded with th is v alue ,
the BRG counts down to 0 and stops until another
reload h as taken place. The BRG count is decremented
twice per instruction cycle (TCY) on the Q2 and Q4
clock.
In I2C mas ter mode , the BRG is reloaded auto matically.
If Clock Arbitration is taking place for instance, the BRG
will be reloaded when the SCL pin is sampled high
(Figure 8-19).
FIGURE 8-18: BAUD RATE GENERATOR
BLOCK DIAGRAM
FIGURE 8-19: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SSPM3:SSPM0
BRG Down Counter
CLKOUT Fosc/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control Reload
SDA
SCL
SCL de-asserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place, and BRG starts its count.
03h 02h 01h 00h (hold off) 03h 02h
reload
BRG
value
SCL low (clock arbitration) SCL allowed to transition high
BRG decrements
(on Q2 and Q4 cycles)
PIC16C77X
DS30275A-page 74 Advance Information 1999 Microchip Technology Inc.
8.2.9 I2C MASTER MODE START CONDITION
TIMING
To initiate a START condition, the user sets the start
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL p ins are sam ple d hi gh, the baud rate gen er a-
tor is re-loaded with the contents of SSPADD<6:0>,
and starts its count. If SCL and SDA are both sampled
high when the baud rate generator times out (TBRG),
the SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended
lea ving the SD A line hel d low, and the START conditio n
is complete.
8.2.9.5 WCOL STATUS FLAG
If the user writes the SSPBUF when an START
sequence is in progress, then WCOL is set and the
contents of the bu ffer are unc hanged (the write doesn ’t
occur).
FIGURE 8-20: FIRST START BIT TIMING
Note: If at the beginning of START condition the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low , a b us collision occurs, the
Bus Collision Interrupt Flag (BCLIF) is set,
the START condition is aborted, and the
I2C module is reset into its IDLE state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
conditi on is complete.
SDA
SCL
S
TBRG
1st Bit 2nd Bit
TBRG
SDA = 1, A t com pletion of start bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
Hardware clears SEN bit
TBRG
Write to SEN bit occurs here. Set S bit (SSPSTAT<3>)
and sets SSPIF bit
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 75
FIGURE 8-21: START CONDITION FLOWCHART
Idle Mode
SEN (SSPCON2<0> = 1)
Bus collision detected,
Set BCLIF, SD A = 1?
Load BRG with
Yes
BRG
Rollover?
Force SDA = 0,
Load BRG with
SSPADD<6:0>,
No
Yes
Force SCL = 0,
Clear SEN
Set S bit.
SSPADD<6:0>
SCL = 1?
SDA = 0? No
Yes
BRG
rollover?
No
Clear SEN
Start Condition Done,
No
Yes
Reset BRG
SCL= 0?
No
Yes
SCL = 0?
No
Yes
Reset BRG
Release SC L,
SSPEN = 1,
SSPCON<3:0> = 1000
and set SSPIF
PIC16C77X
DS30275A-page 76 Advance Information 1999 Microchip Technology Inc.
8.2.10 I2C MASTER MODE REPEATED START
CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is prog ram med high and the I2C mod-
ule is in the idle state. When the RSEN bit is set, the
SCL pin is asserted low . When the SCL pin is sampled
low, the baud rate genera tor is loaded w ith the contents
of SSPADD<6:0>, and begins counting. The SDA pin
is released (brought high) for one baud rate generator
count (TBRG) . When th e baud r at e gener ator ti mes ou t,
if SD A i s samp led high, the SCL pi n will be de-asserted
(brought high). When SCL is sampled high the baud
rate generator is re-loaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one TBRG. This action is then
followe d by asser tio n of the SDA pin (SDA is low) f or
one TBRG whil e SCL is high. F ollo w ing this , th e RSEN
bit in the SSPCON2 register will be automatically
cleared, and the baud rate generator is not reloaded,
leaving the SDA pin held low. As soon as a star t con-
dition is detected on the SDA and SCL pins, the S bit
(SSPSTAT<3>) will b e set. The SSPIF bit will not be set
until the baud rate generator has timed-out.
Immediately following the SSPIF bit getting set, the
user may wr ite the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
8.2.10.6 WCOL STATUS FLAG
If the us er writes the SSPBUF when a Repeated Start
sequence is in progress, then WCOL is set and the
contents of the bu ffer are unc hanged (the write doesn ’t
occur).
FIGURE 8-22: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
Note 2: A bus collision during the Repeated Star t
condition occurs if:
• SD A is sam pled lo w w hen SCL go es from lo w to
high.
• SCL goes low before SDA is asserted low. This
may indicate that another master is attempting
to transmit a data "1".
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
Write to SSPBUF occurs here.
Falling edge of ninth clock
End of Xmit
At completion of start bit,
hardwar e cle ar RSEN bit
1st Bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SD A = 1,
SCL(no chan ge ) SCL = 1
occurs here.
TBRG TBRG TBRG
and set SSPIF
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 77
FIGURE 8-23: REPEATED START CONDITION FLOWCHART (PAGE 1)
Idle Mode,
SSPEN = 1,
Force SCL = 0
SCL = 0?
Release SDA,
Load BRG with
SCL = 1? No
Yes
No
Yes
BRG
No
Yes
Release SCL
SSPCON<3:0> = 1000
rollover?
SSPADD<6:0>
Load BRG with
SSPADD<6:0>
(Clock Arbitra tion)
A
B
C
SD A = 1?
No
Yes
Start
RSEN = 1
Bus Collision,
Set BCLIF,
Release SDA,
Clear RSEN
PIC16C77X
DS30275A-page 78 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-24: REPEATED START CONDITION FLOWCHART (PAGE 2)
Fo rce SDA = 0,
Load BRG with
SSPADD<6:0>
Yes
Repeated Start
Clear RSEN,
Yes
BRG
rollover?
BRG
rollover?
Yes
SD A = 0?
No SCL = 1? No
B
Set S
CA
No
No
Yes
Force SCL = 0,
Reset BRG
Set SSPIF.
SCL = ’0’?
Reset BRG
No
Yes
condi tion don e,
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 79
8.2.11 I2C MASTER MODE TRANSMISSION
Transmission of a data byte, a 7-bit address, or either
half of a 10-bit address is accomplished by simply writ-
ing a v alue to SSPBUF regi ster . This act ion will set the
buf fer full flag (BF) and al low the ba ud rate gener ator to
begin counting and star t the next transmission. Each
bit of address/data will be shifted out onto the SDA pin
after the falling edge of SCL is as se rted (see data hold
time spec). SCL is held low for one baud rate gener-
ator roll o ver co unt (TBRG). Data should be valid before
SCL is released high (see Data setup time spec).
When the SCL pin is released high, it is held that way
for TBRG, the data on the SDA pin must remain stable
for that duration and some hold time after the next fall-
ing edge of SCL. After the eighth bit is shifted ou t (the
falling edge of the eighth clock), the BF flag is cleared
and the mast er r elease s SDA allo wing the s la v e d e vice
being add ressed to respond w ith an ACK bit du ring the
ninth b it tim e, if an addre ss m atch oc curs or if d ata w a s
recei ved prop erl y. The stat us of ACK is read into the
AKDT on the fa lling edge of the ninth cloc k. If the ma s-
ter receives an acknowledge, the acknowledge status
bit (AKSTAT) is cleared. If not, the bit is set. After the
ninth clock the SSPIF is set, and the master clock
(baud rate generator) is suspended until the next data
byte is loaded into the SSPBUF leaving SCL low and
SDA unchanged (Figure 8-26).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock the master will de-asser t
the SDA pin allowing the slave to respond with an
ac kn owledge. O n the fal li ng edg e o f th e n inth c lock the
master will sample the SDA pin to see if the address
wa s recog niz ed b y a sl ave. The st atus of th e A CK bit is
loaded into the AKSTAT status bit (SSPCON2<6>). F ol-
lowing the falling edge of the ninth clock transmiss ion
of the addre ss , the SSPIF is se t, the BF fla g is cleare d,
and the baud rate generator is turned off until another
write to t he SSPB UF t akes place, ho ld ing SCL low and
allowing SDA to float.
8.2.11.7 BF STATUS FLAG
In tran smit mode, the BF bit (SSPSTAT<0>) is se t when
the CPU writes to SSPBUF and is cleared when all 8
bits are shifted out.
8.2.11.8 WCOL STATUS FLAG
If the user writes the SSPBUF when a transmit is
already in progress (i.e. SSPSR is still shifting out a
data byte), then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
8.2.11.9 AKSTAT STATUS FLAG
In transmit mode, the AKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge
(ACK = 0), an d is set when the sla ve does n ot acknowl-
edge (ACK = 1). A slave sends an acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
PIC16C77X
DS30275A-page 80 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-25: MASTER TRANSMIT FLOWCHART
Idle Mode
Num_Clocks = 0,
Release SDA so
slave can drive ACK,
Num_Clocks
Load BRG with
SDA = Current Data bit
Yes
BRG
rollover?
No
BRG
No
Yes
Force SCL = 0
= 8?
Yes
No
Yes
BRG
rollover? No
F orce SCL = 1,
Stop BRG
SCL = 1?
Load BRG with
count high time
Rollover? No
Read SDA and place into
AKSTAT bit (SSPCON2<6>)
Force SCL = 0,
SCL = 1?
SDA =
Data bit?
No
Yes
Yes
rollover?
No
Yes
Stop BRG,
Force SCL = 1
(Clock Arbitration)
(Clock Arbitration)
Num_Clocks
= Num_Clocks + 1
Bus collision detected
Set BCLIF, hold prescale off,
Yes
No
BF = 1
Force BF = 0
SSPADD<6:0>,
start BRG count,
Load BRG with
SSPA DD<6:0>,
start BRG count
SSPADD<6:0>,
Load BRG with
count SCL high time
SSPADD<6:0>,
SDA =
Data bit?
Yes
No
Clear XMIT enable
SCL = 0? No
Yes
Reset BRG
Write SSPBUF
Set SSPIF
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 81
FIGURE 8-26: I2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7D6D5D4D3D2D1D0
ACK
Transmitting Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
cleared in software service routine
SSPBUF is written in software
From SSP interrupt
After start condition SEN cleared by hardware.
S
SSPBUF written with 7 bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> SEN = 1
START condition begins From slav e clear AKSTAT bit SSPCON2<6>
AKSTAT in
SSPCON2 = 1
cleared in software
SSPBUF written
PEN
Cleared in software
R/W
PIC16C77X
DS30275A-page 82 Advance Information 1999 Microchip Technology Inc.
8.2.12 I2C MASTER MODE RECEPTION
Master m ode re ce ption is enabled b y p rog ramming the
receive enable bit, RCEN (SSPCON2<3>).
The baud rate generato r begins c ounting, a nd on eac h
rollover, the state of the SCL pin change s (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded in to the SSPBUF, the BF flag is set,
the SSPIF is set, and the baud rate generator is sus-
pended from counting, holding SCL low. The SSP is
now in IDLE state, awaiting the next command. When
the buffer is read by the CPU, the BF flag is automati-
cally c lea red . T he user c an then send an ac knowledge
bit at the end of reception, by setting the acknowledge
sequence enable bit, AKEN (SSPCON2<4>).
8.2.12.10 BF STATUS FLAG
In rece ive oper ation, BF is set when an address or da ta
byte is loaded into SSPBUF from SSPSR. It is cleared
when SSPBUF is read.
8.2.12.11 SSPOV STATUS FLAG
In receive operation, SSPOV is set when 8 bits are
receiv ed into the SSPSR, and the BF fla g is already set
from a previous reception.
8.2.12.12 WCOL STATUS FLAG
If the user writes the SSPBUF when a receive is
already in progress (i.e . SSPSR is still sh ifting in a da ta
byte), then WCOL is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note: The SSP Module must be in an IDLE
STATE before the RCEN bit is set, or the
RCEN bit will be disregarded.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 83
FIGURE 8-27: MASTER RECEIVER FLOWCHART
Idle mode
Num_Clocks = 0,
Release SDA
F orce SCL=0,
Yes
No
BRG
rollover?
Release SCL
Yes
No
SCL = 1?
Load BRG with
Yes
No
BRG
rollover?
(Clock Arbitration)
Load BRG w/
start count
SSPADD<6:0>,
start count.
Sample SDA,
Shift data into SSPSR
Num_Clocks
= Num_Clocks + 1
Yes
Num_Clocks
= 8?
No
Force SCL = 0,
Set SSPIF,
Set BF.
Move contents of SSPSR
into SSPBUF,
Clear RCEN.
RCEN = 1
SSPADD<6:0>,
SCL = 0?
Yes
No
PIC16C77X
DS30275A-page 84 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-28: I2C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus Master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1)
Write to SSPBUF occurs here ACK from Slave
Master configur ed as a receiver
by programming SSPCON2<3>, (RCEN = 1) PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
Start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Clear ed in software
Cleare d in software
Set SSPIF inter rupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SS PIF at end
Set SSPIF interrupt
at end of acknowledge
sequence
Set SSPIF inter rupt
at end of acknow-
ledge sequence
of receive
Set AKEN start acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = AKDT = 1
RCEN cleared
automatically
RCEN = 1 start
next receive
Write to SSPCON2<4>
to start acknowledge sequence
SDA = AKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
AKEN
Begin Start Condition
Cleared in software
SDA = AKDT = 0
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 85
8.2.13 ACKNOWLEDGE SEQUENCE TIMING
An acknowledge sequence is enabled by setting the
acknowledge sequence enable bit, AKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the acknowledge data
bit is presented on the SDA pin. If the user wishes to
genera te an ac knowledge , then the AKDT bit should b e
cleared . If not, the user sho uld set the AKDT bit befo re
starting an acknowledge sequence. The baud rate
generator then counts for one rollover period (TBRG),
and the SCL pin is de-asserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the baud
rate generator counts for TBRG . The SCL pi n is then
pulled low. Following this, the AKEN bit is automati-
cally cleared, the b aud ra te generator is turned off, and
the SSP module then goes into IDLE mode. (Figure 8-
29)
8.2.13.13 WCOL STATUS FLAG
If the user writes the SSPBUF when an acknowledege
sequence is in progress, then WCOL is set and the
contents of the bu ffer are unc hanged (the write doesn ’t
occur).
FIGURE 8-29: ACKNOWLEDGE SEQUENCE WAVEFORM
Note: TBRG= one baud rate generator period.
SDA
SCL
Set SSPIF at the end
Ackno wledge sequence starts here,
Write to SS PCO N 2 AKEN automatically cleared
Cleared in
TBRG TBRG
of receive
ACK
8
AKEN = 1, AKDT = 0
D0
9
SSPIF
software Set SSPIF at the end
of acknowledge sequenc e
Cleared in
software
PIC16C77X
DS30275A-page 86 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-30: ACKNOWLEDGE FLOWCHART
Idle mode
Force SCL = 0
Yes
No SCL = 0?
Drive AKDT bit
Yes
No BRG
rollover?
(SSPCON2<5>)
onto SDA pin,
Load BRG with
SSPADD<6:0>,
start count.
Force SCL = 1
Yes
No SCL = 1?
No AKDT = 1?
Load BRG with
No
BRG
rollover?
SSPADD <6:0>,
start count.
No
SDA = 1?
Bus collision detected,
Set BCLIF,
Yes
Force SCL = 0,
(Clock Arbitration)
Clear AKEN
No
SCL = 0? Reset BRG Clear AKEN,
Set AKEN
Release SCL,
Yes
Yes
Yes
Set SSPIF
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 87
8.2.14 STOP CONDITION TIMING
A stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit PEN (SSPCON2<2> ). At the end of a re ceiv e/tr ans-
mit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts do wn to 0. Wh en th e bau d r ate g enera tor ti mes
out, the SCL pin will be brought high, and one TBRG
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. Wh en the SD A pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
TBRG later the PEN bit is cleared and the SSPIF bit is
set (Figure 8-31).
Whenever the firmware decides to take control of the
bus, it will firs t det ermine if th e bus is bu sy by check in g
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a Stop bit is detected (i.e. bus is free).
8.2.14.14 WCOL STATUS FLAG
If the use r writes the SSPBUF when a ST OP sequenc e
is in pr ogress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 8-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL
SDA
SDA asserted low before rising edge of clock
Write to SS PCO N 2
Set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one baud rate generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set
TBRG
to setup stop condition.
ACK P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
PIC16C77X
DS30275A-page 88 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-32: STOP CONDITION FLOWCHART
Idle Mode,
SSPEN = 1,
Force SDA = 0
SCL doesn’t change
SD A = 0?
De-assert SCL,
SCL = 1
SCL = 1? No
Yes
Start BRG
No
Yes
BRG
SD A going from
0 to 1 while SCL = 1
No
Yes
Set SSPIF,
Release SDA,
Start BRG
Stop Condition done
SSPCON<3:0> = 1000
rollover?
No
BRG
rollover?
Yes
P bit Set? No
Yes
Bus Collision detected,
Set BCLIF,
Clear PEN
Start BRG
No
Yes
BRG
rollover?
(Clock Arbitrat ion)
PEN = 1
PEN cleared.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 89
8.2.15 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
recei ve, tran smit, or repea ted star t /stop co nditio n, de-
asserts the SCL pin (SCL allo wed to fl oat high). When
the SCL pin is allowed to float high, the baud rate gen-
era tor (BRG) is susp ended f rom cou nting u ntil th e SCL
pin is actually sampled h igh. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time w ill always be at least
one BRG rollover count in the event that the clock is
held low by an external device (Figure 8-33).
8.2.16 SLEEP OPERATION
While in sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete b yte tr ansfer occurs wak e the processor from
sleep ( if the SSP interrupt is enabled).
8.2.17 EFFECTS OF A RESET
A reset disables the SSP module and terminates the
current transfer.
FIGURE 8-33: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
SCL
SDA
BRG over f low,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count BRG ove rflow oc cu r s,
Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting
clock high interval.
SCL line sampled once ever y ma chine cycle (Tosc • 4).
Hold off BRG until SCL is sampled high.
TBRG TBRG TBRG
to measure high time interval
PIC16C77X
DS30275A-page 90 Advance Information 1999 Microchip Technology Inc.
8.2.18 MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ’1’ on SDA by letting SDA float high and
another master asserts a ’0’. Wh en the SC L pin fl oat s
high, data should be stable. If the expected data on
SD A is a ’ 1’ and the data sa mpled on the SD A pin = ’ 0’,
then a bus collision has taken place. The master will
set the Bus Collision Interrupt Flag, BCLIF and reset
the I2C port to i ts IDL E state. (Figure 8-34).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF c an be written to . When the user services
the b us co llisi on inte rrupt service routin e , and if the I2C
bus is free, the user can resume communication by
asserting a START cond iti on.
If a START, Repeated Start, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is abor ted, the SDA and SCL
lines a re d e-asserted, and t he res pectiv e c ontrol bits i n
the SSPCON2 register are cleared. When the user
services the bus collision interrupt service routine, and
if the I2C bus is free, the user can resume communica-
tion by asserting a START condition.
The Master will continue to monitor the SDA and SCL
pins , and if a STOP conditio n occu rs, th e SSPIF bit wil l
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In multi-master mode, the interrupt generation on the
detection of start and stop conditions allows the deter-
minatio n of when th e bus is free . Cont rol of the I2C b us
can be tak en whe n the P bit is set in the SSPSTAT reg-
ister , or the b us is idle a nd the S and P bits are cleared.
FIGURE 8-34: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source Sample SDA. While SCL is high
data doesn’t match what is driven
Bus collision has occurred.
Set bus collision
interrupt.
by the master.
by maste r
Data changes
while SCL = 0
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 91
8.2.18.15 BUS COLLISION DURING A START
CONDITION
During a START condition, a bus collision occurs if:
a) SDA or SCL ar e sampled lo w at the beginnin g of
the START condition (Figure 8-35).
b) SCL is sampled low before SDA is asserted low .
(Figure 8-36).
During a START condition both the SDA and the SCL
pins are monitored.
If: the SDA pin is already low
or the SCL pin is already low,
then:
the START condition is aborted,
and the BCLIF flag is set,
and the SSP module is reset to its IDLE state
(Figure 8-35).
The START condition begins with the SDA and SCL
pins de -asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ’1’ during the START condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 8-37). If however a ’1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pins
is sam pled as ’0’ , a b us collis ion do es no t occ ur. At the
end of the BRG count the SCL pin is asserted low.
FIGURE 8-35: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a fact or
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This cond ition does not caus e a bu s
collision because the two masters must be
allo wed to arbitr ate the f irst addre ss follo w-
ing the START condition, and if the
address is the same, arbitration must be
allowed to continue into the data portion,
REPEATED STAR T, or STOP condit ion s.
SDA
SCL
SEN
SD A sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable star t
condition if SDA = 1, SCL=1
SDA = 0, SCL = 1
BCLIF
S
SSPIF
SDA = 0, SCL = 1 SSPIF and BCLIF are
cleared in software.
SSPIF and BCLIF are
cleared in software.
Set BCLIF,
Set BCLIF.
START condition.
PIC16C77X
DS30275A-page 92 Advance Information 1999 Microchip Technology Inc.
FIGURE 8-36: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 8-37: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA
SCL
SEN Bus collision occurs, Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Inte rru p ts cl e a r e d
in software.
Bus collision occurs, Set BCLIF.
SCL = 0 before BRG time out,
’0’
’0’
’0’
’0’
SDA
SCL
SEN
Set S
Set SEN, enable start
sequence if SDA = 1, SCL = 1
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
in softw are.
Set SS PIF
SDA = 0, SCL = 1
SDA pulled low by other master.
Reset BRG and assert SDA
SCL pulled low after BRG
Timeout
Set SS PIF
’0’
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 93
8.2.18.16 BUS COLLISION DURING A REPEATED
START CONDITION
During a Repeated Start condition, a bus collision
occu rs if:
a) A low leve l is sampled on SDA when SCL goes
from low level to high level.
b) S CL go e s low b e fo re S DA is as se rted l ow, i n di-
cating that another master is atte mpting to tran s-
mit a data ’1’.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>,
and counts down to 0. The SCL pin is then de-
asserted, and when sam pled high , the SD A pin is sam -
pled. If SDA is low, a bus collision has occurred (i.e.
another master is attempting to transmit a data ’0’). If
however SDA is sampled high then the BRG is
reloaded and begins counting. If SDA goes from high
to low before the BRG times out, no bus collision
occurs, because no two masters can assert SDA at
exactly the same time.
If, how ever, SCL goes from hi gh to low before the BRG
times ou t and SD A has not already been asserted, then
a bus collision occurs. In this case, another master is
attempting to transmit a data ’1’ during the Repeated
Start condition.
If at the end of the BRG time out b oth SCL and SD A are
still high, the SDA pin is driven low, the BRG is
reloaded , and begins counting. At the end of th e count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is com-
plete (Figure 8-38).
FIGURE 8-38: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 8-39: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SD A = 0, set BCLIF and release SDA and SCL
Cleared in software
’0’
’0’
’0’
’0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL
TBRG TBRG
’0’
’0’
’0’
’0’
PIC16C77X
DS30275A-page 94 Advance Information 1999 Microchip Technology Inc.
8.2.18.17 BUS COLLISION DURING A STOP
CONDITION
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
The STOP condition begins with SDA asserted low.
When SDA is sampl ed lo w , the SCL pin is allo w to floa t.
When the pin is sampled high (clock arbitration), the
baud rate generator is loaded with SSPADD<6:0> and
counts do wn to 0. After the BRG times out SDA is sam-
pled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ’0’. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs.
This is another case of another master attempting to
drive a data ’0’ (Figure 8-40).
FIGURE 8-40: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 8-41: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
Set BCLIF
’0’
’0’
’0’
’0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SD A SCL goes low before SDA goes high
Set BCLIF
’0’
’0’
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 95
8.3 Connection Considerations for I2C
Bus
For standard-mode I2C bus devices, the values of
resistors
R
p
R
s
in Figure 8-42 d epends on the f ollowing
parameters
• Supply voltage
• Bus capacita nce
• Number of connected devices
(input current + leakage current).
The supp ly v ol tag e limi ts the m inim um value of res istor
R
p
due to the specified minimum sink current of 3 mA
at VOL max = 0.4V for the specified output stages. For
example, with a supply voltage of VDD = 5V+10% and
VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 =
1.7 kΩ. VDD as a function of
R
p
is shown in Figure 8-42.
The desired noise margin of 0.1VDD for the low level
limits the maximum value of
R
s
. Series resistors are
optional and used to improve ESD susceptibility.
The bus capacitance is the total capacitance of wire,
connec tions, an d pins. This capac itance limits the max-
imum value of
R
p
due to the specified rise time
(Figure 8-42).
The SMP b it is the sl ew rate c ontrol enab led bit. This bit
is in the SSPSTAT register, and controls the slew rate
of the I/O pins when in I2C mode (master or slave).
FIGURE 8-42: SAMPLE DEVICE CONFIGURATION FOR I2C BUS
Rp
Rp
VDD + 10%
SDA
SCL
NOTE: I2C devices with input levels related to VDD must have one common supply
line to which the pull up resistor is also connected.
DEVICE
Cb=10 - 400 pF
Rs
Rs
PIC16C77X
DS30275A-page 96 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 97
9.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
muni cations Interface o r SCI). The USART c an be co n-
figured as a full duplex asynchronous system that can
comm un ic a te with peripher al devices su ch as C RT ter-
minals and person al compu ters, or it can b e configure d
as a half dup lex synchronous sy s t em th at can commu-
nicate w it h periphe ral devi ce s s uch as A/D or D/A inte-
grat ed cir cui ts, Serial EEPROMs etc.
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to
be set in order to configure pins RC6/TX/CK and RC7/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.
The USART module also has a multi-processor com-
munication capability using 9-bit address detection.
FIGURE 9-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D R = Readable bit
W = Writable bit
U = Unimplem ented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7: CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6: TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5: TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overri des TXEN in SYNC mode.
bit 4: SYNC: USART Mode Select bit
1 = Synchronous mo de
0 = Asynchronous mode
bit 3: Unimplemented: Read as '0'
bit 2: BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1: TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0: TX9D: 9th bit of transmit data. Can be parity bi t.
PIC16C77X
DS30275A-page 98 Advance Information 1999 Microchip Technology Inc.
FIGURE 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D R = Readable bit
W = Writable bit
U = Unimplem ented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7: SPEN: Serial P o rt Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial por t pins)
0 = Serial port disabled
bit 6: RX9: 9-bit Rece ive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5: SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables si ngle receive
0 = Disables single receive
This bit is cleared afte r receptio n is comple te.
Synchronous mode - slave
Unused in this mode
bit 4: CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous rece ive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3: ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1)
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set
0 = Disables addres s detection, all bytes are received, and ninth bit can be used as parity bit
bit 2: FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1: OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0: RX9D: 9t h bit of received data (Can be parity bit)
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 99
9.1 USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register co ntrols the
period of a free running 8-bit timer. In asynchronous
mode bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode bit BRGH is ignored.
Table 9-1 shows the formula for computation of the
baud r at e for di ffere nt USART modes whic h on ly appl y
in master mode (internal clock).
Giv en the desired baud r ate and Fo sc, the neare st inte-
ger value for the SPBRG register can be calculated
using the formula in Table 9-1. From this, the error in
baud rate can be determined.
Example 9-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
EXAMPLE 9-1: CALCULATING BAUD RATE
ERROR
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
becaus e the FOSC/(16(X + 1)) eq uati on ca n red uce th e
baud rate err or in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
9.1.1 SAMPLING
The data on th e RC7/RX/DT pi n is sampled three ti mes
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 9-1 BAUD RATE FORMULA
TABLE 9-2 REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Desired Bau d rat e = Fosc / (64 (X + 1))
9600 = 16000000 /(64 (X + 1))
X=25.042 = 25
Calculat ed Baud Rate =16000000 / (64 (25 + 1))
=9615
Er ror = (Calculated Ba ud Rat e - Desired Baud Rate)
Desired Baud Rate
= (9615 - 9600) / 9600
=0.16%
SYNC BRGH = 0 (Low Speed) BRG H = 1 (High Speed)
0
1(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1)) Baud Rate= FOSC/(16(X+1))
NA
X = value in SPBRG (0 to 255)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Val ue on all
other resets
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
PIC16C77X
DS30275A-page 100 Advance Information 1999 Microchip Technology Inc.
TABLE 9-3 BAUD RATES FOR SYNCHRONOUS MODE
TABLE 9-4 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
7.15909 MHz SPBRG
value
(decimal)
KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
0.3NA- -NA- -NA- -NA- -
1.2NA- -NA- -NA- -NA- -
2.4NA- -NA- -NA- -NA- -
9.6 NA - - NA - - 9.766 +1.73 255 9.622 +0.23 185
19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92
76.8 76.92 +0.16 64 76.92 + 0 .16 5 1 75.76 -1.3 6 32 77.82 +1.32 22
96 96.15 + 0 .16 5 1 95.24 -0.7 9 41 96.15 +0.16 25 94.20 -1.88 18
300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5
500 500 0 9 500 0 7 500 0 4 NA - -
HIGH 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0
LOW 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255
BAUD
RATE
(K)
FOSC = 5.0688 MHz 4 MHz
SPBRG
value
(decimal)
3.579545 MHz
SPBRG
value
(decimal)
1 MHz
SPBRG
value
(decimal)
32.768 kHz
SPBRG
value
(decimal)
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
0.3NA- - NA- - NA- - NA- -0.303+1.1426
1.2 NA - - NA - - NA - - 1.202 +0.16 207 1.170 -2.48 6
2.4 NA - - NA - - NA - - 2.404 +0.16 103 NA - -
9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 NA - -
19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 NA - -
76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 NA - -
96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 NA - - NA - -
300 316.8 +5.60 3 NA - - 298.3 -0.57 2 NA - - NA - -
500NA- - NA- - NA- - NA- - NA- -
HIGH 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0
LOW 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255
BAUD
RATE
(K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
7.15909 MHz SPBRG
value
(decimal)KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
0.3NA--NA --NA --NA--
1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92
2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46
9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11
19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5
76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 NA - -
96 104.2 +8.51 2 NA - - NA - - NA - -
300 312.5 +4.17 0 NA - - NA - - NA - -
500NA- -NA- -NA- -NA- -
HIGH 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0
LOW 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255
BAUD
RATE
(K)
FOSC = 5.0688 MHz 4 MHz
SPBRG
value
(decimal)
3.579545 MHz
SPBRG
value
(decimal)
1 MHz
SPBRG
value
(decimal)
32.768 kHz
SPBRG
value
(decimal)KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1
1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 NA - -
2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 NA - -
9.6 9.9 +3.13 7 NA - - 9.322 -2.90 5 NA - - NA - -
19.2 19.8 +3.13 3 NA - - 18.64 -2.90 2 NA - - NA - -
76.8 79.2 +3.13 0 NA - - NA - - NA - - NA - -
96NA--NA--NA--NA--NA--
300NA- - NA- - NA- - NA- - NA- -
500NA- - NA- - NA- - NA- - NA- -
HIGH 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0
LOW 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 101
TABLE 9-5 BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 20 MHz SPBRG
value
(decimal)
16 MHz SPBRG
value
(decimal)
10 MHz SPBRG
value
(decimal)
7.16 MHz SPBRG
value
(decimal)KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46
19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22
38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11
57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7
115.2 113.636 -1.36 1 0 111.111 - 3.5 5 8 1 25 +8.51 4 111 .86 0 -2. 90 3
250 250 0 4 250 0 3 NA - - NA - -
625 625 0 1 NA - - 625 0 0 NA - -
1250 1250 0 0 NA - - NA - - NA - -
BAUD
RATE
(K)
FOSC = 5.068 MHz SPBRG
value
(decimal)
4 MHz SPBRG
value
(decimal)
3.579 MHz SPBRG
value
(decimal)
1 MHz SPBRG
value
(decimal)
32.768 kHz SPBRG
value
(decimal)KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR KBAUD %
ERROR
9.6 9.6 0 32 NA - - 9.727 +1.32 22 8.928 -6.99 6 NA - -
19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 NA - -
38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 NA - -
57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 NA - -
115.2 105.6 -8.33 2 19.231 +0.16 12 111.860 -2.90 1 NA - - NA - -
250 NA - - NA - - 223.721 -10.51 0 NA - - NA - -
625NA - - NA- - NA- - NA- - NA- -
1250 NA - - NA - - NA - - NA - - NA - -
PIC16C77X
DS30275A-page 102 Advance Information 1999 Microchip Technology Inc.
9.2 USART Asynchronous Mode
In this mode, the USART uses standard nonretur n-to-
zero (NRZ) format (one start bit, ei ght or nine data bits
and one stop bit). The most common data format is
8-bits. An on-chip dedicated 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LS b first. The USAR T’s trans mitter and recei ver are
functionally independent but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hard ware , b ut can be implemen ted in s oftware (and
stored as the ninth data bit). Asynchronous mode is
stopped duri ng SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important eleme nts:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
9.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 9-3. The hear t of the transmitter is the transmit
(serial) shift register (TSR). The shift reg ister obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXR EG re gi st er i s em pt y a nd
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
wa re. It will reset onl y when ne w data is load ed into the
TXREG register. While flag bit TXIF indicated the sta-
tus of the TXREG register, another bit TRMT
(TXSTA<1>) sho ws t he status of the TS R registe r . Sta-
tus bit TRMT is a read only bit which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
Steps to follow when setting up an Asynchronous
Transmission:
1. Initialize th e SPBRG re giste r for the ap pro priate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 9.1)
2. Enable t he a sy nc hro nou s s erial po rt by cle aring
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit tr an sm is si on is d esi red, then set tr ans m it
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 9-3: USART TRAN SMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
Note 2: Flag bit TXI F is set when ena bl e bit TXEN
is set.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG register
TSR register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
• • •
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 103
FIGURE 9-4: ASYNCHRONOUS TRANSMISSION
FIGURE 9-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 9-6 REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on :
POR,
BOR
Value on
all other
Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, alw ays maintain these bits clear.
WORD 1 Stop Bit
WORD 1
Transmit Shift Reg
Start Bit Bit 0 Bit 1 Bit 7/8
Write to TXREG Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT b it
(Transmi t shif t
reg. empty fl ag)
Transmit Shift Reg.
Write to TXREG
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bi t
(Transmit shift
reg. empty flag)
Word 1 Word 2
WORD 1 WORD 2
Start Bit Stop Bit Start Bit
Transmit Shift Reg.
WORD 1 WORD 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two consecutive transmissions.
PIC16C77X
DS30275A-page 104 Advance Information 1999 Microchip Technology Inc.
9.2.2 USART ASYNCHRONOUS RECEIVER
The recei ver b loc k diag ram is sho wn in Figure 9-6. The
data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recov ery block is actually
a high speed shifter operating at x16 times the baud
rate, whereas the main receive serial shifter operates at
the bit rate or at FOSC.
The USART module has a special provision for multi-
processor communication. When the RX9 bit is set in
the RCSTA register , 9-bits are rec eiv ed and the ninth bit
is placed in the RX9D status bit of the RSTA register.
The port can be programmed such that when the stop
bit is received, the serial port interrupt will only be acti-
vated if the RX9D bit = 1. This feature is enabled by
setting the ADDEN bit RCSTA<3> in the RCSTA regis-
ter. This fea ture c an be used in a mu lti- processor sys-
tem as follows:
A master processor intends to transmit a block of data
to one of many slav es. It must firs t send out an address
by te th at identifies the t arge t sl ave. A n ad dres s byte is
identifi ed by the R X9D bit being a ‘1’ (in stead of a ‘0’ for
a data byte). If the ADDEN bit is set in the slave’s
RCSTA register, all data bytes will be ignored. How-
ever, if the ninth received bit is equal to a ‘1’ , ind ic atin g
that the received byte is an address, the slave will be
inter rupted and the c ontent s of the R SR regis ter will b e
transferred into the receive buffer . This allows the slave
to be interrupted only by addresses, so that the slave
can e x amine the rece iv ed b y te to se e if it is addres sed.
The addressed slave will then clear its ADDEN bit and
prepare to receive data bytes from the master.
When ADDEN is set, all data bytes are ignored. Fol-
lowin g the ST O P bit, the data wil l not be loaded into the
receive buffer, and no interrupt will occur. If another
byte is shifted into the RSR register, the previous data
byte will be lost.
The ADDEN bit will only take effect when the receive r
is configured in 9-bit mode.
The receiver block diagram is shown in Figure 9-6.
Once Asynchronous mode is selected, reception is
enabled by se tting bit CREN (RCSTA<4>).
9.2.3 SETTING UP 9-BIT MODE W ITH ADDRESS
DETECT
Steps to follow when setting up an Asynchronous
Reception with Address Detect Enabled:
• Initialize the SPBRG register for the appropriate
baud r ate . If a high sp eed baud ra te is d esired, s et
bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
• Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if enable
bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit received data by reading the
RCREG register, to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If the device has been addressed, clear the
ADDEN bit to allow data bytes and address bytes
to be rea d into the receiv e b uffer , a nd int errupt the
CPU.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 105
FIGURE 9-6: USART RECEIVE BLOCK DIAGRAM
FIGURE 9-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
x64 B aud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR register
MSb LSb
RX9D RCREG register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷ 64
÷ 16
or Stop Start
(8) 710
RX9
• • •
RX9
ADDEN
RX9
ADDEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
Start
bit bit1bit0 bit8 bit0Stop
bit
Start
bit bit8 Stop
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
WORD 1
RCREG
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)
Bit8 = 0, Data Byte Bit8 = 1, Address Byte
because ADDEN = 1.
PIC16C77X
DS30275A-page 106 Advance Information 1999 Microchip Technology Inc.
FIGURE 9-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
TABLE 9-7 REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USAR T Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, alw ays maintain these bits clear.
Start
bit bit1bit0 bit8 bit0Stop
bit
Start
bit bit8 Stop
bit
RC7/RX/DT (pin)
Load RSR
Read
RCIF
WORD 1
RCREG
Bit8 = 1, Address Byte Bit8 = 0, Data Byte
Note: This timing diagram shows an address byte followed by a data byte. The data byte is not read into the RCREG (receive buffer)
because ADEN was not updated and still = 0.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 107
9.3 USART Synchronous Master Mode
In Sync hronous Maste r mode, t he data i s transmitte d in
a half-duplex manner i.e. transmission and reception
do not oc cur at the same time . Whe n tran smitt ing dat a,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
additio n enab le bit SPEN (RCSTA<7>) is set in ord er to
configure the RC6/TX/CK and RC7/RX/DT I/O pins to
CK (cloc k) and DT (data ) lines respec tively. The Master
mode i ndicates that the processor t ransmi ts the m aster
clock on the CK line. The Master mode is entered by
setting bit CSRC (TXSTA<7>).
9.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 9-3. The hear t of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit, TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
wa re. It will reset onl y when ne w data is load ed into the
TXREG register . While flag bit TX IF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
show s the status of the TSR register. TRMT is a read
only bit w hich is set whe n the T SR is empty. No inte r-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize th e SPBRG re giste r for the ap pro priate
baud rate (Section 9.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
TABLE 9-8 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Val ue on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, alw ays maintain these bits clear.
PIC16C77X
DS30275A-page 108 Advance Information 1999 Microchip Technology Inc.
FIGURE 9-9: SYNCHRONOUS TRANSMISSION
FIGURE 9-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Bit 0 Bit 1 Bit 7
WORD 1
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 2 Bit 0 Bit 1 Bit 7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
(Interrupt flag)
TRMT
TXEN bit ’1’ ’1’
Note: Sync master mode; SPBRG = ’0’. Continuous tra nsmission of two 8-b it words.
WORD 2
TRMT bit
Write word1 Write word2
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit0 bit1 bit2 bit6 bit7
TXEN b it
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 109
9.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enab led by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set
then CREN takes precedence.
Steps to follow when setting up a Sync hronous Master
Reception:
1. Initialize th e SPBRG re gi ste r fo r the ap pro priate
baud rate. (Section 9.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be se t when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 9-9 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Addr e s s Na me B it 7 Bit 6 Bit 5 Bit 4 B i t 3 Bit 2 Bit 1 B it 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unim plement ed read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, alw ays maintain these bits clear.
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'.
Q3 Q4Q1 Q2Q3 Q4Q1Q2 Q3Q4Q2 Q1Q2Q3Q4Q1Q2Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3Q4 Q1Q2 Q3Q4
'0'
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
'0'
Q1Q2Q3Q4
PIC16C77X
DS30275A-page 110 Advance Information 1999 Microchip Technology Inc.
9.4 USART Synchronous Sla ve Mode
Synchro nous sla v e mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/T X/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
9.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register .
c) Flag bit TXIF will not be set.
d) When the firs t word has been shi fted out of TSR ,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
Steps to follow when setting up a Synchronous Slave
Transmission:
1. Enable the synchron ous sla v e serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
9.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the synchronous master and slave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don’t care in slave mode.
If receive is enabled, by setting bit CREN, prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enab le bit RCIE bit is set, the interrupt gener ated
will wake the chip from SLEEP. If the global interrupt is
enabled, the p rog ram will br anch to the inte rrupt vector
(0004h).
Steps to follow when setting up a Synchronous Slave
Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, then set enable bit
RCIE.
3. If 9-bit reception is desired, then set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF wi ll b e se t w he n rec ept ion is com -
plete and an interrupt will be generated, if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, c lear the error by clearing
bit CREN.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 111
TABLE 9-10 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 9-11 REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unim plement ed read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, alw ays maintain these bits clear.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Register 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unim plement ed read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, alw ays maintain these bits clear.
PIC16C77X
DS30275A-page 112 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 113
10.0 VOLTAGE REFERENCE
MODULE AND LOW-VOLTAGE
DETECT
The V oltage Reference module provides reference volt-
ages fo r the Bro wn-out Res et circui try, the Lo w-v oltag e
Detect circuitry and the A/D converter.
The source for the reference voltages comes from the
bandgap ref erence ci rcu it. The band gap ci rcuit is en er-
gized anytime the reference voltage is required by the
other sub-modules, and is powered down when not in
use . The c ontrol regis ters f or this m odule are L VDCON
and REFCON, as shown in Figure 10-1 and
Figure 10-2.
FIGURE 10-1: LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER
U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
—— BGST L VDEN LV3 LV2 LV1 LV0 R = Readable bit
W =Wr itable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as '0'
bit 5: BGST: Bandgap Stable Status Fl ag bit
1 = Indicates that the bandgap voltage is stable, and LVD interrupt is reliable
0 = Indicates that the bandgap voltage is not stable, and LVD interrupt should not be enabled
bit 4: LVDEN: Low-voltage Detect Power Enable bit
1 = Enables LVD, powers up bandgap circuit and reference generator
0 = Disables LVD, powers down bandgap circuit if unused by BOR or VRH/VRL
bit 3-0: LV3:LV0: Low Voltage Detection Limit bits (1)
1111 = External analog input is used
1110 = 4.5V
1101 = 4.2V
1100 = 4.0V
1011 = 3.8V
1010 = 3.6V
1001 = 3.5V
1000 = 3.3V
0111 = 3.0V
0110 = 2.8V
0101 = 2.7V
0100 = 2.5V
Note 1: These are the minimum trip points for the LVD, see Table 15-3 for the trip point tolerances. Selection
of an unused setting may result in an inadvertant interrupt.
PIC16C77X
DS30275A-page 114 Advance Information 1999 Microchip Technology Inc.
FIGURE 10-2: REFCON: VOLTAGE REFERENCE CONTROL REGISTER
10.1 Bandgap Voltage Reference
The bandgap module gener at es a stable voltage refer-
ence of 1.22V over a range of temperatures and device
supply voltag es. This m odule is enab led an ytime any of
the following are enabled:
• Brown-out Reset
• Low-voltage Detect
• Either of the internal analog references (VRH,
VRL)
Whenever the above are all disabled, the bandgap
module is disabled and draws no current.
10.2 Internal VREF for A/D Converter
The bandgap output voltage is used to generate two
stab le referenc es f or the A/D c on v erter module . T hese
referenc es are enabled i n so ftw are to prov ide th e us er
with the m ean s to turn them on an d off in ord er to mi n-
imize current consumption. Each reference can be indi-
vidually enabled.
The 4.096 V referenc e (VRH ) is enab led with cont rol b it
VRHEN (REFCON<7>). When this bit is set, the gain
amplifier is enabled. After a specified star t-up time a
stable reference of 4.096V is generated and can be
use d by the A/D converter as the VRH input.
The 2.04 8V reference (VRL) is ena bled by s ett ing co n-
trol bit VRLEN (REFCON<6 >). Wh en th is bit i s set, th e
gain am plifier is ena bled. Af ter a specif ied start up time
a stable reference of 2.048V is generated and can be
used by the A/D converter as the VRL input.
Each voltage reference can source/sink up to 5 mA of
current.
Each reference, if enabled, can be presented on an
external pin by setting the VRHOEN (high reference
output enable) or VRLOEN (low reference output
enable) control bit. If the reference is not enabled, the
VRHOEN and VRLOEN bits will have no effect on the
correspo nding pin . The de vi ce speci fic pin ca n then be
used as general purpose I/O.
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
VRHEN VRLEN VRHOEN VRLOEN — — — — R = Readable bit
W =Writable bit
U = Unimplemented
bit, read as ‘0’
- n =Value at POR
reset
bit7 bit0
bit 7: VRHEN: Voltage Reference High Enable bit (VRH = 4.096V)
1 = Enabled, powers up reference generator
0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRL
bit 6: VRLEN: Voltage R eference Low Enable bit (VRL = 2.048V )
1 = Enabled, powers up reference generator
0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRH
bit 5: VRHOEN: High Voltage Reference Output Enable bit
1 = Enabled, VRH analog reference is presented on RA3 if enabled (VRHEN = 1)
0 = Disabled, analog reference is used internally only
bit 4: VRLOEN: Low Voltage Reference Output Enable bit
1 = Enabled, VRL analog reference is presented on RA2 if enabled (VRLEN = 1)
0 = Disabled, analog reference is used internally only
bit 3-0: Unimplemented: Read as '0’
Note: If VRH or VRL i s enab led a nd the other ref-
erence (VRL or VRH), the BOR, and the
LVD modules are not enabled, the band-
gap will require a star t-up time of no more
than 50 µs before the bandgap reference is
stable. Before using the internal VRH or
VRL reference, ensure that the bandgap
reference voltage is stable by monitoring
the BGST bit in the LVDCON register. The
voltage references will not be reliable until
the bandgap is stable as shown by BGST
being set.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 115
10.3 Low-voltage Detect (LVD)
This mo dule is used to generate an interrupt when t he
supply voltage falls below a specified “trip” voltage.
This module operates completely under software
control. This allows a user to power the module on
and off to periodi cally mo nitor the suppl y v ol tage , an d
thus minimize total current consumption.
FIGURE 10-3: BLOCK DIAGRAM OF LVD AND VOLTAGE REFERENCE CIRCUIT
The LVD m odule is enab led b y setting the LVDEN bit in
the LVDCON register. The “trip point” voltage is the
minimum supply volta ge level at wh ich the d evic e can
operate before the LVD module asserts an interrupt.
When the supp ly volt age is equal to or le ss than the trip
point, the module will generate an interrupt signal set-
ting interrupt flag bit LVDIF. If interrupt enab le bit LVDIE
was set, then an interrupt is generated. The LVD inter-
rupt can wake the device from sleep. The "trip point"
voltage is software programmable to any one of 16 val-
ues, five of which are reserved (See Figure 10-1). The
trip point is selected by programming the LV3:LV0 bits
(LVDCON<3:0>).
Once t he LV b its ha ve been pro gra mmed for the spec i-
fied trip voltage, the low-voltage detect circuitry is then
enabled by setting the LVDEN (LVDCON<4>) bit.
If the bandgap reference voltage is previously unused
by either the brown-out circuitry or the voltage refer-
ence ci rcuitry, then the bandgap circuit requires a time
to start-up and become stable before a low voltage con-
dition can be reliably detected. The low-voltage inter-
rupt flag is prevented from being set until the bandgap
has reached a stable reference voltage.
When the bandgap is stable the BGST (LVDCON<5>)
bit is s et indica ting th at the l ow-v o ltage interrupt fla g bit
is released to be set if VDD is equal to or less than the
LVD trip point.
10.3.1 EXTERNAL ANALOG VOLTAGE INPUT
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when
LV3:LV0 = 1111. When these bits are s et the comp ar-
ator input is multiplexed from an external input pin
(RB3/AN9/LVDIN.
VDD
LVD
16 to 1 MUX
BGAP
A/D Ref = 4.096V
A/D Ref = 2.048V
EN
LVDCON REFCON
BODEN
LVDEN VRxEN
RB3/AN9/LVDIN
VDD
Note: The LVDIF bit can not be cleared until the
supply voltage rises above the LVD trip
point. If interrupts are enabled, clear the
LVDIE bit once the first LVD interrupt
occurs to prevent reentering the interrupt
service routine immediately after exiting
the ISR.
PIC16C77X
DS30275A-page 116 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 117
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has six
inputs for the PIC16C773 and ten for the PIC16C774.
The analog-to-digital converter (A/D) allows conver-
sion of an analog input signal to a corresponding
12-bit digital number. The A/D module has up to 10
analog inputs, which are multiplexed into one sample
and hold. The output of the sample and hold is the
input into the conver ter, which generates the result via
successive approximation. The analog reference volt-
ages are software selectable to either the device’s
analog positive and negative supply voltages
(AVDD/AVSS), the voltage level on the VREF+ and
VREF- pins, or internal voltage references if available
(VRH, VRL).
The A/D conv erter has a unique fea ture of being able to
oper ate while the devic e is in SLEEP mode. To opera te
in sleep, the A/D conversion clock must be derived from
the A/D’s internal R C oscillator.
The A/D module has four registers. These registers
are: • A/D Result Register Low ADRESL
• A/D Result Register High ADRESH
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off and any
conversi on is abo rted.
11.1 Control Registers
The ADCON0 register, shown in Figure 11-1, controls
the operation of the A/D module. The ADCON1 regis-
ter, shown in Figure 11-2, configures the functions of
the port pins, the voltage reference configuration and
the result format. The port pins can be configured as
analog inputs or as digital I/O.
The combination of the ADRESH and ADRESL regis-
ters contai n the result of the A/D conversion. The reg-
ister pair is referred to as the ADRES register. When
the A/D conversion is complete, the result is loaded
into ADRES, the GO/DONE bit (ADCON0<2>) is
cleared, and the A/D interrupt flag ADIF is set. The
block diagram of the A/D module is shown in
Figure 11-3.
FIGURE 11-1: ADCON0 REGISTER (ADDRESS 1Fh).
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON R = Readab le bit
W = Writable bit
- n = Value at POR reset
bit7 bit 0
bit 7:6 ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = Fosc/2
01 = Fosc/8
10 = Fosc/32
11 = FRC (clock derived from an RC os cillator = 1 MHz max)
bit 5:3,1 CHS3:CHS0: Analog Channel Select bits
0000 = channel 00 (AN0)
0001 = channel 01 (AN1)
0010 = channel 02 (AN2)
0011 = channel 03 (AN3)
0100 = channel 04 (AN4) (Reserved on 28-pin devic es, do not use)
0101 = channel 05 (AN5) (Reserved on 28-pin devic es, do not use)
0110 = channel 06 (AN6) (Reserved on 28-pin devic es, do not use)
0111 = channel 07 (AN7) (Reserved on 28-pin devic es, do not use)
1000 = channel 08 (AN8)
1001 = channel 09 (AN9)
1010, 1011, 1100, 1101, 1110,1111 are reserved, do not select.
bit 2: GO/DONE: A/D Conversion Status bit
1 = A/D conv ersion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion com pleted/not in progress
bit 0: ADON: A/D On bit
1 = A/D converter mod ule is operating
0 = A/D converter is shutoff and consumes no operating current
PIC16C77X
DS30275A-page 118 Advance Information 1999 Microchip Technology Inc.
FIGURE 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCF G2 PCFG 1 PCFG0 R = R eadable bit
W = Writable bit
U = U nimplemented bit, read as ‘0’
- n = Value at POR reset
bit7 bit 0
bit 7: ADFM: A/D Result Format Select bit
1 = Right justif ied
0 = Left justified
bit 6:4 VCFG2:VCFG0: Voltage reference configuration bits
bit 3:0 PCFG3:PCFG0: A/D Port Configuration bits(1)
Note 1: Selection of an unimplemented channel produces a result of 0xFFFFFF.
A/D VREFH A/D VREFL
000 AVDD AVSS
001 External VREF+ Exter nal VREF-
010 Internal VRH Inter nal V RL
011 External VREF+AVSS
100 Internal VRH AVSS
101 AVDD External VREF-
110 AVDD Inter nal V RL
111 Internal VRL A VSS
AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000 AAAAAAAAAA
0001 AAAAAAAAAA
0010 AAAAAAAAAA
0011 AAAAAAAAAA
0100 AAAAAAAAAA
0101 AAAAAAAAAA
0110 DAAAAAAAAA
0111 DDAAAAAAAA
1000 DDDAAAAAAA
1001 DDDDAAAAAA
1010 DDDDDAAAAA
1011 DDDDDDAAAA
1100 DDDDDDDAAA
1101 DDDDDDDDAA
1110 DDDDDDDDDA
1111 DDDDDDDDDD
A = Analog input D= Digital I/O
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 119
The value that is in the ADRESH and ADRESL regis-
ters are not modified for a Power-on Reset. The
ADRESH and ADRESL registers will contain unknown
data after a Power-on Reset.
After the A/D module has been configured as desired,
the sele cte d c han nel must be acqui red b efo re the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 11.6.
After this acquisition time has elapsed the A/D conver-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversion:
11.2 Configuring the A/D Module
11.3 Configuring Analog Port Pins
The ADCON1 and TRIS regis ters control the oper ation
of the A/D port pins. The por t pins that are desired as
analog inputs must have their corresponding TRIS bit
set (in put ). If the TRIS bit is c le ared ( outp ut), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
11.3.1 CONFIGURING THE REFERENCE
VOLTAGES
The VCFG bits in the ADCON1 register configure the
A/D module reference inputs. The reference high
input can come from an internal reference (VRH) or
(VRL), an external reference (VREF+), or AVDD. The
low reference input can come from an internal refer-
ence (VRL), an ex ter nal reference (VREF-), or AVSS. If
an exter nal reference is chosen for the reference high
or reference low inputs, the port pin that multiplexes
the incoming external references is configured as an
analog input, regardless of the values contained in the
A/D port configuration bits (PCFG3:PCFG0).
After the A/D module has been configured as desired.
and the analog input channels have their correspond-
ing TRIS bits selected for port inputs, the selected
channel must be acquired before conversion is
started. The A/D conversion cycle can be initiated by
setting the GO/DONE bit. The A/D conversion begins,
and lasts for 13TAD. The following steps should be fol-
lowed for performing an A/D conversion:
1. Configure the A/D module
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if required)
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
3. Wait the required acquisition time (3TAD)
4. Start conversion
• Set GO/D ONE bit (ADCON0)
5. Wait 13TAD until A/D conversion is complete, by
either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH and
ADRESL), clear ADIF if required.
7. For next conversion, go to st ep 1, step 2 or step
3 as required.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRESH and
ADRESL registers WILL be updated with the par tially
completed A/D conversion value. T hat i s , t he AD RESH
and ADRESL registers WILL contain the value of the
current incomplete co nversion.
Note 1: When reading the PORTA or PORTE reg-
ister, all pins configured as analog input
channe ls will read as cleared (a lo w lev el).
When reading the PORTB register, all
pins configured as analog input channels
will read as set (a high level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
Note 2: Analog levels on an y pin that is defi ned as
a digital input (including the ANx pins),
may cause the input buffer to consume
current t hat is ou t of the devices speci fica-
tion.
Note: Do not set the ADON bit and the
GO/DONE bit in the same instruction.
Doing s o will cause the GO /DONE bit to be
automatically cleared.
PIC16C77X
DS30275A-page 120 Advance Information 1999 Microchip Technology Inc.
FIGURE 11-3: A/D BLOCK DIAGRAM
(Input voltage)
VAIN
VREFH
(Reference
voltage)
AVDD
VCFG2:VCFG0
CHS3:CHS0
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
RA5/AN4(1)
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
RA0/AN0
A/D
Converter
Note 1: Not available on 28-pin devices.
VREFL
(Reference
voltage) AVSS
VCFG2:VCFG0
RB2/AN8
RB3/AN9
VRH
VRL
VRL
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 121
11.4 Selecting the A/D Conversion Clock
The A/D conv ersion c ycle requires 13 TAD: 1 TAD for set-
tling ti me, and 12 TAD for conversion. The source of the
A/D conversion clock is software selected. The four
pos s ible opt ions for TAD are:
•2 T
OSC
•8 TOSC
•32 TOSC
• Internal RC os cillato r
Note that these options are the same as those of the
8-bit A/D.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs. Table 11-1 shows the resultant TAD times
derived from the device operating frequencies and the
A/D clock source selected.
The ADIF bit is set on the rising edge of the 14th TAD.
The GO/DONE bit is cleared on the falling edge of the
14th TAD.
TABLE 11-1 TAD vs. DEVICE OPERATING FREQUENCIES
11.5 A/D Conversions
Figure 11-5 shows an example that performs an A/D
conversion. The port pins are configured as analog
inputs. The analog reference VREF+ is the device A VDD
and the analog reference VREF- is the device A VSS. The
A/D interrupt is enabled, and the A/D conversion clock
is TRC. The conversion is performed on the AN0 chan-
nel.
FIGURE 11-4: PERFORMING AN A/D CONVERSION
BCF PIR1, ADIF ;Clear A/D Int Flag
BSF STATUS, RP0 ;Select Page 1
CLRF ADCON1 ;Configure A/D Inputs
BSF PIE1, ADIE ;Enable A/D interrupt
BCF STATUS, RP0 ;Select Page 0
MOVLW 0xC1 ;RC clock, A/D is on,
;Ch 0 is selected
MOVWF ADCON0 ;
BSF INTCON, PEIE ;Enable Peripheral
BSF INTCON, GIE ;Enable All Interrupts
;
; Ensure that the required sampling time for the
; selected input channel has lapsed. Then the
; conversion may be started.
BSF ADCON0, GO ;Start A/D Conversion
: ;The ADIF bit will be
;set and the GO/DONE bit
: ;cleared upon completion-
;of the A/D conversion.
AD Clock Source (TAD) Device Frequency
Operation ADCS<1:0> 20 MHz 5 MHz 4 MHz 1.25 MHz
2 TOSC 00 100 ns(2) 4 00 ns(2) 500 ns(2) 1.6 µs
8 TOSC 01 800 ns(2) 1.6 µs2.0 µs6.4 µs
32 TOSC 10 1.6 µs6.4 µs8.0 µs(3) 24 µs(3)
RC 11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4)
Note 1: The RC source has a typical TAD time of 4 µs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the RC A/D conversion clock source is only recommended if the conver-
sion will be performed during sleep.
PIC16C77X
DS30275A-page 122 Advance Information 1999 Microchip Technology Inc.
FIGURE 11-5: FLOWCHART OF A/D OPERATION
Sample
ADON = 0
ADON = 0?
GO = 0?
A/D Clock
GO = 0
ADIF = 0
Abort Conversion
SLEEP
Power down A/D Wait 2 TAD
Wake-up
Yes
No
Yes
No
No
Yes
Finish Conversion
GO = 0
ADIF = 1
SLEEP
No
Yes
Finis h Conversion
GO = 0
ADIF = 1
Wait 2 TAD
Stay in Sleep
Selected Channel
= RC?
Instruction?
SLEEP
No
Yes
Instruction?
Start of A/D
Conversion Delayed
1 Instruction Cycle
From Sleep?
Powerdown A/D
Yes
No
Wait 2 TAD
Finish Conversion
GO = 0
ADIF = 1
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 123
11.6 A/D Sample Requirements
11.6.1 RECOMMENDED SOURCE IMPEDANCE
The maximum recommended impedance for ana-
log sources is 2.5 kΩ. This value is ca lcu lated bas ed
on the maximum leakage current of the input pin. The
leakage current is 100 nA max., and the analog input
voltage cannot be vary by more than 1/4 LSb or
250 mV due to leakage. This places a requirement on
the input impedance of 250 µV/100 nA = 2.5 kΩ.
11.6.2 SAMPLING TIME CALCULATION
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-8. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device vo ltage
(VDD), see Figure 11-8. The maximum recom-
mended impedance for analog sources is 2.5 kΩ.
After the analog input channel is selected (changed)
this s a mp li ng mus t be d on e be f ore t h e c onversi on c an
be started.
To calculate the minimum sampling time,
Equation 11-6 may be used. This equation assumes
that 1/4 LSb error is used (16384 steps for the A/D).
The 1/4 LSb e rror is the m axim um error al lo wed for th e
A/D to meet its specified resolution.
The CHOLD is assumed to be 25 pF for the 12-bit
A/D.
FIGURE 11-6: A/D SAMPLING TIME EQUATION
VHOLD =(VREF - VREF/16384) = (VREF) • (1 -e (-TC/C (RIC +RSS + RS)) VREF(1 - 1/16384) = VREF • (1 -e (-TC/C (RIC +RSS + RS))
TC = -CHOLD (1kΩ + RSS + RS) In (1/16384)
Figure 11-7 sho ws the cal culati on of the minim um tim e
required to c harg e C HOLD. This ca lcula tion is ba se d on
the following system assumptions:
CHOLD = 25 pF
RS = 2.5 kΩ
1/4 LSb error
VDD = 5V → RSS = 10 kΩ (worst case)
Temp (system Max.) = 50°C
Note 1:The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
2:The charge holding capacitor (CHOLD) is
not discharged afte r each conversion.
3:The maximum recommended impedance
for analog sources is 2.5 kΩ. This is
required to meet the pin leakage specifi-
cation.
4:After a conversion has completed, 2 TAD
time must be waited before sampling can
begin again. During this time the holding
capacitor is not connected to the selected
A/D input channel.
PIC16C77X
DS30275A-page 124 Advance Information 1999 Microchip Technology Inc.
FIGURE 11-7: CALCULATING THE MINIMUM REQUIRED SAMPLE TIME
TACQ = Amplifier Settling Time
+ Holdin g Capacitor Charging Time
+Temperature Coefficient †
TACQ =5 µs
+ TC
+ [(Temp - 25°C)(0.05 µs/°C)] †
TC = + Holding Capacitor Chargin g Time
TC =(CHOLD) (RIC + RSS + RS) In (1/16384)
TC = -25 pF ( 1 kΩ +10 kΩ + 2.5 kΩ) In (1/16384)
TC = -25 pF (13.5 kΩ) In (1/16384)
TC = -0.338 (-9.704)µs
TC =3.3µs
TACQ =5 µs
+ 3.3 µs
+ [(50°C - 25°C)(0.05 µs / °C)]
TACQ =8.3 µs + 1.25 µs
TACQ = 9.55 µs
† The temperature coefficient is only required for
temperatures > 25°C.
FIGURE 11-8: ANALOG INPUT MODEL
CPIN
VA
Rs Port Pin
5 pF
VDD
VT = 0.6V
VT = 0.6V ILEAKAGE
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD = 25 pF
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
( kΩ )
VDD
± 100 nA
Legend CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 125
11.7 Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCPnM<3:0> bits be programmed as 1011b and that
the A/D module is enabled (ADON is set). When the
trigger occurs, the GO/DONE bit will be set on Q2 to
start the A/D conversion and the Timer1 counter will
be reset to zero. Timer1 is reset to automatically
repeat the A/D con version cyc le, with minim al s oftw are
overhead (moving the ADRESH and ADRESL to the
desired location). The appropriate analog input chan-
nel must be selected before the “special event trigger”
sets the GO/DONE bit (starts a conversion cycle).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
11.8 Effects of a RESET
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted. The value that is in the
ADRESH and ADRESL registers are not modified.
The ADRESH and ADRESL registers will contain
unknown data after a Power-on Reset.
11.9 Faster Conversion - Lower
Resolution Trade-off
Not all applications require a result with 12-bits of res-
olution, but may instead require a faster conversion
time. The A/D module allows users to make the
trade-off of conversion speed to resolution. Regard-
less of the resolution required, the acquisition time is
the same. To speed up the conversion, the A/D mod-
ule may be halted by clearing the GO/DONE bit after
the desi red n umber of bits in the res ul t have bee n co n-
verted. Once the GO/DONE bit has been cleared, all
of the remaining A/D result bits are ‘0’. The equation
to determine the time before the GO/DONE bit can be
switched is as follows:
Conversion time = N•TAD + 1TAD
Where: N = number of bits of resolution required,
and 1TAD is the amplifier settling time.
Since TAD is based from the device oscillator, the user
must use some me thod (a timer, software loop, etc.) to
determine when the A/D GO/DONE bit may be
cleared. Table 11-2 shows a comparison of time
required for a conversion with 4-bits of resolution, ver-
sus the normal 12-bit resolution conversion. The
example is for devices operating at 20 MHz. The A/D
clock is programmed for 32 TOSC.
TABLE 11-2 4-BIT vs. 12-BIT
CONVER SION TIMES
Freq.
(MHz)
Resolution
4-bit 12-bit
Tosc 20 50 ns 50 ns
TAD = 32 Tosc 20 1.6 µs1.6 µs
1TAD+N•TAD 20 8 µs20.8 µs
PIC16C77X
DS30275A-page 126 Advance Information 1999 Microchip Technology Inc.
11.10 A/D Operation During Sleep
The A/D mod ule can operate during SLEEP mode. This
requires that the A/D cl ock source be configured for RC
(ADCS1:ADCS0 = 11b). With the RC clock source
selected, when the GO/DONE bit is set the A/D mo dule
waits one instruction cycle before star ting the conver-
sion cycle. This allows the SLEEP i nst ruction to be ex e-
cuted, which eliminates all digital switching noise
during the sample and conversion. When the conver-
sion cycle is completed the GO/DONE bit is cleared,
and the result loaded into the ADRESH and ADRESL
register s. I f the A/D i nterrupt i s ena b led, t he device will
wake-up from SLEEP. If the A/D interrupt is not
enabled, the A/D module will then be turned off,
although the ADON bit will remain set.
When the A/D clo c k sou rce is a no ther clo c k opti on (not
RC), a SLEEP instruction causes the present conver-
sion to be aborted and the A/D module is turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
11.11 Connection Considerations
Since the analog inputs employ ESD protection, they
have diodes to VDD and VSS. This requires that the
analog input mus t be betwee n VDD and VSS. If the input
voltage exceeds this range by greater than 0.3V (either
direction), one of the diodes becomes forward biased
and it may damage the device if the inp ut curre nt spec -
ification is e x ce ede d.
An external RC filter is s ometim es a dde d for anti-alias-
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
ke pt under the 2.5 kΩ reco mmended specifi cation. An y
exter nal components connected (via hi-impedance) to
an analo g input pin (capacitor , zener diod e, etc.) shoul d
have v ery little leakage current at the pin.
TABLE 11-3 SUMMARY OF A/D REGISTERS
Note: For the A/D module to operate in SLEEP,
the A/D cl ock sou rce must be config ured to
RC (ADCS1:ADCS0 = 11b).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on all
other Resets
0Bh,8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuuu uuuu
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 0000 ----
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
05h PORTA ——PORTA5
(2) PORTA Data Latch when written: PORTA<4:0> pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx 11xx uuuu 11uu
09h(2) PORTE — — — — — RE2 RE1 RE0 ---- -000 ---- -000
85h TRISA ——bit5
(2) PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
89h(2) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
Legend: x = unknown, u = unc hanged, - = unimplemented read as ’0’. Shaded cells are not used for A/D conv ersion.
Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, alw ays maintain these bits clear.
2: These bits/registers are not implemented on the 28-pin devices, read as ’0’.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 127
12.0 SPECIAL FEATURES OF THE
CPU
These PICmicro devices have a host of features
intended to maximize system reliability, minimize cost
through elimination of external components, provide
power saving operating modes and offer code protec-
tion. Th ese are:
• Oscillator Selection
• Reset
- Power-on Reset (POR)
- P o wer-up Timer (PWR T)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Low -voltage detect ion
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
These devices have a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Star t-up Timer (OST), intended to keep
the chi p in rese t until th e crystal osci llator is stab le. Th e
other is the Power-u p Ti me r (P WRT), which provides a
fix ed d ela y of 72 m s (nomina l) on po we r-up typ e reset s
only (POR, BOR), designed to keep the part in reset
while the power supply stabilizes. With these two timers
on-chip, most applications need no external reset cir-
cuitr y.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Sever al oscillato r option s are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
Additional in formation on special features is avai lable in
the PICmicro™ Mid-Range Reference Manual,
(DS33023).
12.1 Configuration Bits
The con figur ati on bits c an be prog ra mmed (rea d as ' 0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), whic h can be accessed only dur ing program-
ming.
Some of the core features provided may not be neces-
sary to each application that a device may be used for.
The configuration word bits allow these features to be
configured/enabled/disabled as necessary. These fea-
tures include code protection, brown-out reset and its
trippoint, the power-up timer, the watchdog timer and
the devices oscillator mode. As can be seen in
Figure 12-1, some additional configuration word bits
have been pro vided for bro wn-ou t reset trippoi nt selec -
tion.
PIC16C77X
DS30275A-page 128 Advance Information 1999 Microchip Technology Inc.
FIGURE 12-1: CONFIGURATION WORD
12.2 Oscillator Configurations
12.2.1 OSCILLATOR TYPES
The PIC1 6C77X can be oper ated in four different os cil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
• LP Low Power Crysta l
• XT Crystal/Resonator
• HS High Speed Crystal/Resonator
• RC Resistor/Capacitor
12.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-2). The
PIC16C77 X o sc ill ato r d es ign re qui res th e use o f a p ar-
allel cut cr ystal. Use of a ser ies cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions.
A difference from the other mid-range devices may be
noted in that the device can be driven from an external
clock only when configured in HS mode (Figure 12-3).
CP1 CP0 BORV1 BORV0 CP1 CP0 - BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
Address 2007h
bit13 12 11 10 9 8 7 6 5 4 3 2 1 bit0
bit 13-12: CP1:CP 0: Co de Protectio n bits (2)
bit 9-8: 11 = Program memory code protection off
bit 5-4: 10 = 0800h-0FFFh code protected
01 = 0400h-0FFFh code protected
00 = 0000h-0FFFh code protected
bit 11-10: BORV1:BORV0: Brown-out Reset Voltage bits(3)
11 = VBOR set to 2.5V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 7: Unimplemented, Read as ’1’
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
3: These are the minimum trip points for the BOR, see Table 15-4 for the trip point tolerances. Selection of an unused
setting may result in an inadvertant interrupt.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 129
FIGURE 12-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
FIGURE 12-3: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
TABLE 12-1 CERAMIC RESONATORS
T ABLE 12-2 CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
Resonators Used:
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG ± 0.5%
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
8.0 MHz Murata Erie CSA8.00MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
All resonators used did not have built -in capacitors.
Note1: See Table 12-1 and Table 12-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen.
C1(1)
C2(1)
XTALOSC2
OSC1
RF(3)
SLEEP
To
logic
PIC16C77X
RS(2)
internal
OSC1
OSC2
Open
Clock from
ext. system PIC16C77X
Osc Type Crystal
Freq Cap. Range
C1 Cap . Ran ge
C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1 MHz 15 pF 15 pF
4 MHz 15 pF 15 pF
HS 4 MHz 15 pF 15 pF
8 MHz 15-33 pF 15-33 pF
20 MHz 15-33 pF 15-33 pF
These values are for design guidance only. See
notes at bottom of page.
Crystals Used
32 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz ST D XTL 200.000KHz ± 20 PPM
1 MHz ECS ECS-10-13-1 ± 50 PPM
4 MHz ECS ECS-40-20-1 ± 50 PPM
8 MHz EPSON CA-301 8.000M-C ± 30 PPM
20 MHz EPSO N CA-301 20.000M-C ± 30 PPM
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 12-1).
2: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manu facturer for appropri-
ate values of external components.
4: Rs may be required in HS mode as well as
XT mode to avoid overdriving crystals with
low drive level specification.
PIC16C77X
DS30275A-page 130 Advance Information 1999 Microchip Technology Inc.
12.2.3 RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequen c y is a function of the supply voltage, the resis-
tor (REXT) and c apacitor (CEXT) v alues , and th e ope rat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT value s. The se factors and the v ariation due to tol-
era nces of external R and C compo nents us ed nee d to
be taken into account for each application. Figure 12-4
shows how the R/C combination is connected to the
PIC16C77X.
FIGURE 12-4: RC OSCILLATOR MODE
OSC2/CLKOUT
Cext
Rext
PIC16C77X
OSC1
Fosc/4
Internal
clock
VDD
VSS
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 131
12.3 Reset
The PIC16C77X devices have several different resets.
These resets are grouped into two classifications;
pow er-up and non-p ower-u p. The power-up type resets
are th e power-on an d brown-o ut reset s whic h assume
the device VDD was below its normal operating range
for the device ’s configuration. The non-power up type
resets assume normal operating limits were main-
tained before/during and after the reset.
• Power-on Reset (POR)
• Brown-out Reset (BOR)
•MCLR
reset during normal operation
•MCLR
reset during SLEEP
• WDT Rese t (during normal operation)
Some registers are not affected in any reset condition.
Their status is unknown on a power-up reset and
unchanged in any other reset. Most other registers are
placed into an initia lized s tate upon rese t, howe v er they
are not affected by a WDT reset during sleep because
this i s c ons ide red a W DT Wakeup, which is vi ewed as
the resumption of normal operation.
Several status bits have been provided to indicate
which reset occurred (see Table 12-4). See Table 12-6
for a full description of reset states of all registers.
A simplifi ed b loc k diag ram of the on-ch ip res et circui t is
shown i n Figure 12-5.
These devices have a MCLR noise filter in the MCLR
reset path. The fil ter will detect and ignore small pulses.
It should be noted that a WDT Reset
does not drive
MCLR pin low.
FIGURE 12-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
On-chip
RC OSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Reset
Enable OST
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
Brown-out
Reset BODEN
(1)
PIC16C77X
DS30275A-page 132 Advance Information 1999 Microchip Technology Inc.
12.4 Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate e xternal RC components usual ly needed to create
a Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Spec ifications for details. For
a slow rise time, see Figure 12-6.
Two delay timers have been provided which hold the
device in reset after a POR (dependant upon device
configuration) so that all operational parameters have
been met pr ior to releasing to device to resume/begin
normal oper atio n.
When the device starts normal operation (exits the
reset co ndi tion), devic e op erating parameters (voltage,
frequency , temp erature,...) must be met to ensure op er-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brow n-out Re set ma y be used to meet t he sta rtup co n-
ditions, or if necessary an external POR circuit may be
implemented to delay end of reset for as long as
needed.
FIGURE 12-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
12.5 Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up type resets only. For a POR, the
PWRT is invoked when the POR pulse is generated.
F or a BOR, t he PWRT is in voked when t he device e xit s
the reset condition (VDD rises above BOR trippoint).
The Power-up Timer operates on an internal RC oscil-
lator. The chip is kept in reset as long as the PWRT is
activ e. The PWRT’s time dela y is designed to allo w VDD
to rise to an a cc ep table le vel. A configuration bit is p ro-
vided to enable/di sab le the PWR T for the POR only. F or
a BOR the PWRT is always available regardless of the
configuration bit setting.
The pow er- up time dela y will vary from chip to ch ip due
to VDD, temperature, and process variation. See DC
parame ters for details.
12.6 Oscillator Start- u p Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWR T dela y i s ov er . This e nsures that th e crystal osci l-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes a nd only on a power -up type reset or a w ake-u p
from SLEEP.
12.7 Brown-Out Reset (BOR)
The Brown-out Reset module is used to generate a
reset when the supply voltage falls below a specified
trip voltage. The trip voltage is configurable to any one
of four voltages provided by the BOR V1:BORV0 config-
uration word bits.
Configuration bit, BODEN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below the specified trippoint for
greater than parameter #35 in the electrical specifica-
tions se ction, the bro wn-out situation will reset the ch ip.
A reset m ay not occur if VDD falls b elow the trippoint for
less than parameter #35. The chip wi ll remain in Bro wn-
out Reset until VDD rises above BVDD. The Power-up
Timer w ill be in vok ed at that po int and will k eep the chi p
in RESET an additional 72 ms. If VDD drops below
BVDD while th e P ow er-up T imer is runnin g, the chi p will
go back into a Brown-out Reset and the Power-up
Timer will be re-initialized. Once VDD rises above
BVDD, the Power-up Timer will again begin a 72 ms
time delay. Even though the PWRT is always enabled
when brown-out is enabled, the PWRT configuration
word bit should be cleared (enab led) when brown- out is
enab led.
Note 1: External P ower-on Reset cir cuit is required
only if V DD power-up s lope is too slo w . The
diode D helps discharge the capacitor
quickl y when VDD powers down.
2: R < 40 k Ω is recommended to make sure
that voltag e drop across R does not vi olate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break -
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC16C77X
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 133
12.8 Time-out Sequence
On po wer-up the time-out seque nc e is as fol lo ws : Firs t
PWR T time -out is in v ok ed by the POR pulse . When th e
PWRT delay expires the Oscillator Start-up Timer is
activated. The total time-out will var y based on os cilla-
tor configuration and the status of the PWRT. For e xam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all. Figure 12-7, Figure 12-8, Figure 12-
9 and Figure 12-10 depict time-out sequences on
power-up.
Since the time-outs occu r from the POR pulse , if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 12-9). This is useful for testing purposes or to
synchronize more than one PICmicro microcontroller
operating in parallel.
Table 12-5 shows the reset conditions for some special
function registers, while Table 12-6 shows the reset
conditions for all the registers.
12.9 Power Control/Status Register
(PCON)
The P o wer Co ntrol/Status Reg ister , PCON has two st a-
tus bits that provide indication of which power-up type
reset occurred.
Bit0 is Bro wn-out Reset Status bit, BOR. Bit BOR is set
on a Power-on Reset. It must then be set by the user
and checked on subsequent resets to see if bit BOR
cleared, indicating a BOR occurred. However, if the
brown-out circuitry is disabled, the BOR bit is a "Don’t
Care" bit and is considered unknown upon a POR.
Bit1 is POR (P ower-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit follow ing a Power-on Reset.
TABLE 12-3 TIME-OUT IN VARIOUS SITUATIONS
TABLE 12-4 STATUS BITS AND THEIR SIGNIFICANCE
TABLE 12-5 RESET CONDITION FOR SPECIAL REGISTERS
Oscillator Co nfigu ration Power-up Brown-out Wake-up from
SLEEP
PWRTE = 0 PWRTE = 1
XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
RC 72 ms — 72 ms —
POR BOR TO PD
0111Power-on Reset
0x0xIllegal, TO is set on POR
0xx0Illegal, PD is set on POR
1011Brown-out Reset
1101WDT Reset
1100WDT Wake-up
11uuMCLR Reset during normal operation
1110MCLR Reset during SL EEP or interrupt wake-up from SLEEP
Condition Program
Counter STATUS
Register PCON
Register
Power-on Reset 000h 0001 1xxx ---- --01
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 1uuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-o ut Rese t 000h 0001 1uuu ---- --u0
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wak e-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
PIC16C77X
DS30275A-page 134 Advance Information 1999 Microchip Technology Inc.
TABLE 12-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS
Registe r Devices Power-on Reset,
Brown-out Reset MCLR Resets
WDT Reset Wake-up via WDT or
Interrupt
W 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
INDF 773 774 N/A N/A N/A
TMR0 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
PCL 773 774 0000h 0000h PC + 1(2)
STATUS 773 774 0001 1xxx 000q quuu(3) uuuq quuu(3)
FSR 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 773 774 --0x 0000 --0u 0000 --uu uuuu
PORTB 773 774 xxxx 11xx uuuu 11uu uuuu uuuu
PORTC 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
PORTE 773 774 ---- -000 ---- -000 ---- -uuu
PCLATH 773 774 ---0 0000 ---0 0000 ---u uuuu
INTCON 773 774 0000 000x 0000 000u uuuu uuuu(1)
PIR1 773 774 r000 0000 r000 0000 ruuu uuuu(1)
773 774 0000 0000 0000 0000 uuuu uuuu(1)
PIR2 773 774 0--- 0--0 0--- 0--0 u--- u--u(1)
TMR1L 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 773 774 --00 0000 --uu uuuu --uu uuuu
TMR2 773 774 0000 0000 0000 0000 uuuu uuuu
T2CON 773 774 -000 0000 -000 0000 -uuu uuuu
SSPBUF 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
SSPCON 773 774 0000 0000 0000 0000 uuuu uuuu
CCPR1L 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 773 774 --00 0000 --00 0000 --uu uuuu
RCSTA 773 774 0000 000x 0000 000x uuuu uuuu
TXREG 773 774 0000 0000 0000 0000 uuuu uuuu
RCREG 773 774 0000 0000 0000 0000 uuuu uuuu
CCPR2L 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2H 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 773 774 --00 0000 --00 0000 --uu uuuu
ADRESH 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 773 774 0000 0000 0000 0000 uuuu uuuu
OPTION_REG 773 774 1111 1111 1111 1111 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depen ds
on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the
interrupt v ec tor (000 4h).
3: See Table 12-5 for reset value for specific condition.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 135
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
TRISA 773 774 ---1 1111 ---1 1111 ---u uuuu
773 774 --11 1111 --11 1111 --uu uuuu
TRISB 773 774 1111 1111 1111 1111 uuuu uuuu
TRISC 773 774 1111 1111 1111 1111 uuuu uuuu
TRISD 773 774 1111 1111 1111 1111 uuuu uuuu
TRISE 773 774 0000 -111 0000 -111 uuuu -uuu
PIE1 773 774 r000 0000 r000 0000 ruuu uuuu
773 774 0000 0000 0000 0000 uuuu uuuu
PIE2 773 774 0--- 0--0 0--- 0--0 u--- u--u
PCON 773 774 ---- --qq ---- --uu ---- --uu
PR2 773 774 1111 1111 1111 1111 1111 1111
SSPADD 773 774 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 773 774 0000 0000 0000 0000 uuuu uuuu
TXSTA 773 774 0000 -010 0000 -010 uuuu -uuu
SPBRG 773 774 0000 0000 0000 0000 uuuu uuuu
REFCON 773 774 0000 ---- 0000 ---- uuuu ----
LVDCON 773 774 --00 0101 --00 0101 --uu uuuu
ADRESL 773 774 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 773 774 0000 000 0000 0000 uuuu uuuu
TABLE 12-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Registe r Devices Power-on Reset,
Brown-out Reset MCLR Resets
WDT Reset Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = v a lu e depen ds
on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the
interrupt v ec tor (000 4h).
3: See Table 12-5 for reset value for specific condition.
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PIC16C77X
DS30275A-page 136 Advance Information 1999 Microchip Technology Inc.
FIGURE 12-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 12-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 12-10: SLOW RISE TIME (MCLR TIED TO VDD)
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-O UT
INTERNAL RESET
0V 1V 5V
TPWRT
TOST
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 137
12.10 Interrupts
The PIC16C77X family has up to 14 sources of inter-
rupt. The interrupt control register (INTCON) records
indivi dual i nterrupt reques ts in fla g bits . I t al so ha s ind i-
vidual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interr upts or disables (if
cleared ) all in terrupts . W hen bit GIE is enab le d, and a n
inter rupt’s flag bit and ma sk bit are set, the inte rrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial fu nction regist ers PIR1 and PI R2. The co rrespond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bi t i s co nta ine d i n sp eci al function re g-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pu sh ed onto the stack and the PC is lo aded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive int errupt s.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the sam e for one or two c yc le ins tructi ons. Individua l
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit
FIGURE 12-11: INTERRUPT LOGIC
Note: Indiv id ual int errupt fla g bits are set regard-
les s of the status of their corresponding
mask bit or the GIE bit.
PSPIF
PSPIE ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake -up (If in SLEEP mode)
Interrupt to CPU
CCP2IE
CCP2IF
The following table shows which devices have which interrupts.
Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF LVDIF BCLIF CCP2IF
PIC16C773 Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
PIC16C774 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
LVDIF
LVDIE
BCLIE
BCLIF
PIC16C77X
DS30275A-page 138 Advance Information 1999 Microchip Technology Inc.
12.10.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be clea red in s oftware i n the in terrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can w ake-up the proces sor from SLEE P, if bit INTE w as
set prior to goin g into SLEEP. The status of gl obal inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 12.13 for details on SLEEP mode.
12.10.2 TMR0 INTERRUPT
An overf l ow (F F h → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0)
12.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
12.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on th e stack. Typically, users may wish to sa v e key re g-
isters during an interr upt, i.e., W register and STATUS
register. This will have to be implemented in software.
Example 12-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each ba nk and m ust be defin ed at the same off set from
the bank base address (i.e., if W_TEMP is defined at
0x20 i n bank 0, it m u st al so be defined at 0x A0 i n b an k
1).
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
d) Executes the interrupt service routine code
(User-generated).
e) Restores the STATUS register (and bank select
bit).
f) Restores the W and PCLATH registers.
EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3
MOVWF PCLATH_TEMP ;Save PCLATH into W
CLRF PCLATH ;Page zero, regardless of current page
BCF STATUS, IRP ;Return to Bank 0
MOVF FSR, W ;Copy FSR to W
MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP
:
:(ISR)
:
MOVF PCLATH_TEMP, W ;Restore PCLATH
MOVWF PCLATH ;Move W into PCLATH
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 139
12.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents . T his RC os cilla tor is s epar ate from the R C osci l-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During nor mal operation, a WDT time-out generates a
device RESET (Wat chdog Timer Reset). If the de vice is
in SLEEP m ode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer W ake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time- out.
The WDT can be permanently disabled by clearing
configur ation bit WDTE (Section 12.1).
WDT time-out period values may be f ound in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler may be assigned using the
OPTION_REG register.
.
FIGURE 12-12: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 12-13: SUMMARY OF WATCHDOG TIMER REGISTERS
Note: The CLRWDT and SLEEP instructions clear
the WDT an d th e postscaler, if assign ed to
the WDT, and prev ent it from timing out and
generating a device RESET condition.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
presc al er ass ig nme nt is not changed.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 12-1 for the full description of the configuration word bits.
From TMR0 Clock Source
(Figure 4-2)
To TMR0 (Section 4-2)
Postscaler
WDT Timer
WDT
Enable Bit
0
1M
U
X
PSA
8 - to - 1 MUX PS2:PS0
01
MUX PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
8
PIC16C77X
DS30275A-page 140 Advance Information 1999 Microchip Technology Inc.
12.13 P o wer-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
ke eps running , the PD bit (STATUS<3>) is clea red, th e
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pi ns at either VDD, or VSS, ensure no exter nal cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi -impedance i nputs, high or lo w e xternally to a v oid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
12.13.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change, or som e
Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is clea red if a WDT time-out occurred (and caused
wake-up).
The follo wing peripher al interrupts can wak e the de vice
from SLEEP:
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. CCP capture mode interrupt.
4. Special event trigger (Timer1 in asynchronous
mode using an external clock) .
5. SSP (Start/Stop) bit detect interrupt.
6. SSP transmit or receiv e in slav e mode (SPI/I2C).
7. USART RX or TX (synchronous slave mode).
8. A/D conversion (when A/D clock source is RC).
9. Low-v o lta ge det ect.
Other pe ripherals can not gener ate interrupts si nce dur-
ing SLEEP, no on-chip clocks are pres ent.
When th e SLEEP inst ruction is being ex ecuted, the ne xt
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
inte rrup t ena ble bit mus t be set (enabled ). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (dis abled), the device continues execution at the
instruction after the SLEEP instr uct ion . If t he GIE bi t is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
ru pt ad dress (00 04h ). In ca ses wh ere the execution of
the instruction following SLEEP is not desirable, the
user shoul d have a NOP after the SLEEP instruction.
12.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit se t, one of the follo wing will occur:
• If the interrupt occurs before the execution o f a
SLEEP instruction, the SLEEP inst ruct ion wi ll com -
plete as a NOP. Therefore, the WDT and WDT
pos tscaler will not be cl eare d, th e TO bit will not
be set and PD bits will not be cleare d.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction, t he device will imme-
diately wake up from slee p. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP ins truc tion exec uted, t est
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instr uc-
tion should be executed before a SLEEP instruction.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 141
FIGURE 12-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT
12.14 Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
12.15 ID Locations
F our memory locatio ns (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These loca tions are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
For ROM devices, these values are submitted along
with the ROM code.
12.16 In-Circuit Serial Programming
PIC16CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done wi th two lines fo r cloc k and data, a nd three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programme d.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
TOST(2)
PC+2
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-li ne.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
Note: Microchip does not recommend code pro-
tecting windowed devices.
PIC16C77X
DS30275A-page 142 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 143
13.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
oper at ion of the instructio n. The PIC 16CXX ins tructio n
set summary in Table 13-2 lists byte-oriented, bit-ori-
ented, and literal and contr ol operations. Table 13-1
shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file reg -
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ’d’ is ze ro, the result is
placed in the W registe r . If ’d ’ is one , the result i s placed
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
design ator which sele cts t he number of the b it affe cted
by the operation, while ’f’ represents the number of the
file in which the bit is located.
For literal and control operations, ’k’ represents an
eigh t or eleven bit constan t or literal value.
TABLE 13-1 OPCODE FIELD
DESCRIPTIONS
The ins truc ti o n se t is hig hl y orthog on a l an d is grou ped
into three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
All instructions are executed within one single instr uc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In thi s case, t he exe cut ion takes t wo ins tr ucti on cy cles
with the second cycle ex ecuted as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an osci llator frequ ency of 4 MHz, the normal instructio n
e xecution ti me is 1 µs . If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
Table 13-2 lists the instructions recognized by the
MPASM assembler .
Figure 13-1 sho ws th e genera l formats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 13-1: GENERAL FORMAT FOR
INSTRUCTIONS
A description of each instruction is available in the
PICmicro™ Mid-Range Reference Manual,
(DS33023).
Field Description
fRegister file address (0x00 to 0x7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon’t care location (= 0 or 1)
The assembler will generat e code with x = 0. I t is t he
recommended form of use for compatibility with all
Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
PC Program Counter
TO Time-out bit
PD Power-down bit
Note: To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTION and TRIS instructions.
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
PIC16C77X
DS30275A-page 144 Advance Information 1999 Microchip Technology Inc.
TABLE 13-2 PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-Bit Opcod e Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Compleme nt f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move lit eral to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low b y an external
devi ce , the data will be written back with a ’ 0’.
2: If this instruction is e x ecuted on the T MR0 register (and, where applicable , d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
1999 Microchip Technology Inc. DS30275A-page 145
PIC16C77X
14.0 DEVELOPMENT SUPPORT
14.1 Development Tools
The PICmicro microcontrollers are supported with a
full r an ge of hardw are and softw are d e velopment tools :
• MPLAB -ICE Real-Time In-Cir cuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
•PRO MATE
II Universal Programmer
• PICSTART Plus Entry -Level Prototype
Programmer
• SIMICE
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(
fuzzy
TECH−MP)
•KEELOQ® Evaluation Kits and Programmer
14.2 MPLAB-ICE: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
inte nded to provi de t he pr oduc t developm ent en gin eer
with a complete microcontroller design tool set for
PICmicro microcontroll ers (MCUs). M PLAB-ICE is su p-
plied with the MPLAB Integrated De velopment Environ-
ment (IDE), which allows editing, “make” and
download, and source debugging from a single envi-
ronment.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support all new Microchip micro-
controllers.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures t hat are gener ally found on more expen sive de vel-
opment tools. The PC compatible 386 (and higher)
machine platform and Microsoft Windows 3.x or
Windows 95 environment were chosen to best make
these features available to you, the end user.
MPLAB-ICE is available in two versions.
MPLAB-I CE 1000 is a basic , lo w-c ost em ulat or system
with si mple trac e capabili ties. It shares proce ssor mod-
ules with the MPLAB-ICE 2000. This is a full-featured
emul ator sys tem with e nhanced trace , trigger, and data
monitoring features. Both systems will operate across
the entire operating speed reange of the PICmicro
MCU.
14.3 ICEPIC: Low-Cost PICmicro
In-Circuit Emulator
ICEPIC is a low-cost in-ci rcu it emulator solutio n for th e
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
fam i lies of 8- bit OTP microcont rollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 386 through Pentium based
machines under Windows 3.x, Windows 95, or Win-
dow s NT environment. ICEPIC fe atu res real ti me, non-
intrusive emulation.
14.4 PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to ver ify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
gram PIC12CXXX, PIC14C000, PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
14.5 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is not
recommended for production programming.
PICSTART Plus supports all PIC12 CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be sup-
ported with an adapter socket. PICSTART Plus is CE
compliant.
PIC16C77X
DS30275A-page 146 1999 Microchip Technology Inc.
14.6 SIMICE Entry-Level Hardware
Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB™-SIM. Both SIM-
ICE and MPLAB-SIM run under Microchip Technol-
ogy’s MPLAB Integrated Development Environment
(IDE) softw are. Specific ally, SIMICE provides h ardware
simulation for Microchip’s PIC12C5XX, PIC12CE5XX,
and PIC16C5X families of PICmicro 8-bit microcontrol-
lers. SIMICE works in conjunction with MPLAB-SIM to
provide non-real-time I/O port emulation. SIMICE
enables a developer to run simulator code for driving
the target system. In addition, the target system can
provide input to the simulator code. This capability
allows for simple and interactive debugging without
having to manually generate MPLAB-SIM stimulus
files. SIMICE is a valuable debugging tool for entry-
level system development.
14.7 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a si mple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE em ulator and dow nlo a d t h e
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
14.8 PI CDEM - 2 Low-Cos t PIC16CX X
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICS TART- Plus , and eas ily tes t firmware .
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional ha rdware and connectin g it to the mic rocontroll er
soc ke t(s). Some of th e featur es include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C b us an d separ ate headers for connec -
tion to an LCD module and a keypad.
14.9 PI CDEM - 3 Low-Cos t PIC16CX XX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microc ont roll ers w ith a LCD Mo dul e . All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the P ICDE M- 3 boar d, on a PRO MAT E II pr ogra m-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Addit ional protot ype a rea h as been provided to
the use r f or a ddi ng ha rdwar e and c onn ect in g it to th e
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a k e y pad. Als o pro vide d on th e PICDEM -3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the we ek . Th e PICDEM-3 provides an add i-
tional RS-232 interface and Windows 3.1 software for
showing the demulti plex ed LCD signals on a PC . A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
1999 Microchip Technology Inc. DS30275A-page 147
PIC16C77X
14.10 MPLAB Integrated Development
Environme n t Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
-editor
-emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Exten si ve on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
proje ct inf ormation)
• Debug using:
- source files
- absolute listing file
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
14.11 Assembler (MPASM)
The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional a ssembl y, and se v eral source and listing f ormats .
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from MPLAB-
ICE, Microchip’s Univers al Emulator System.
MPASM has the following features to assist in develop-
ing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol, and
special) required for symbolic debu g with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programmin g of the PICmicro. Directives are helpful in
making the de velo pment of y our asse mble s ource code
shorter and more maintainable.
14.12 Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; si ngle step , e x ecute until break, or
in a trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPASM. The Software Simulator
offers the lo w co st fle xibilit y to de v elop and debug code
outside of the laboratory environment making it an
excellent multi-project software development tool.
14.13 MPLAB- C17 Compiler
The MPLAB-C17 Code Development System is a
complete ANSI ‘C’ compiler and integrated develop-
ment environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other co mpi le rs .
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.
14.14 Fuzzy Logic Dev elopment System
(
fuzzy
TECH-MP)
fuzzy
TECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working kno w ledge of fuz zy l ogic sys tem d esign ; and a
full-featured versio n,
fuzzy
TECH-MP, Edition for imple-
menting more complex systems.
Both versions include Microchip’s
fuzzy
LAB demon-
str ati on boa rd for han ds -on experien ce wit h fuzzy logic
system s im ple me nta tion .
14.15 SEEVAL Evaluation and
Prog ram ming Sys te m
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes ever ything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off ana lysi s and rel iabil ity ca lcula tions . The tota l kit ca n
significantly reduce time-to-market and result in an
optimized system.
PIC16C77X
DS30275A-page 148 1999 Microchip Technology Inc.
14.16 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microc hips HCS Secure D ata Product s. The HC S ev al-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
1999 Microchip Technology Inc. DS30275A-page 149
PIC16C77X
TABLE 14-1 DEVELOPMENT TOOLS FROM MICROCHIP
PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX 24CXX
25CXX
93CXX
HCS200
HCS300
HCS301
Emulat or Products
MPLAB™-ICE
á
á
á
á
á
á
á
á
á
á
ICEPIC Low-Cost
In-Cir c uit Emulator
á
á
á
á
á
á
Software Tools
MPLAB
Integrated
Development
Environment
á
á
á
á
á
á
á
á
á
á
MPLAB C17*
Compiler
á
á
fuzzy
TECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
á
á
á
á
á
á
á
á
á
Total En duranc e
Software Model
á
Programmers
PICSTARTPlus
Low-Cost
Universal Dev. Kit
á
á
á
á
á
á
á
á
á
á
PRO MATE II
Universal
Programmer
á
á
á
á
á
á
á
á
á
á
á
á
KEELOQ
Programmer
á
Demo Boards
SEEVAL
Designers Kit
á
SIMICE
á
á
PICDEM-14A
á
PICDEM-1
á
á
á
á
PICDEM-2
á
á
PICDEM-3
á
KEELOQ®
Evaluati on Kit
á
KEELOQ
Transponde r Kit
á
PIC16C77X
DS30275A-page 150 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 151
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltag e on any pin with resp ect to VSS (except VDD, MCLR. and RA4)..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +8.5V
Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin...........................................................................................................................300 mA
Maximum current into VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp cur rent, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA
Maximu m out put current sunk by any I/O pin................. ..... ...... ............................ ...... ............................................25 mA
Maximu m out put current sourced by an y I/O pin ...................... ...... ............................ ..... ...... .................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3)....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage s pikes be low VSS at the MCLR p in, inducing currents gr eater than 80 mA, may cause lat ch-up . Thus,
a series resist or of 50-100Ω s ho uld be used when ap ply in g a “l o w” level to the MCLR pin rat her tha n pullin g
this pin directly to VSS.
Note 3: PORTD and PORTE are not implemented on the PIC16C773.
TABLE 15-1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
† NOTICE: Stresses above those listed under “Absolute Maximum Rating s” may cause permanent damage to the
de vic e. Th is is a s tress r ating o nly and functional oper atio n of the device at thos e or an y ot her conditi ons abo v e those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
OSC PIC16C773-04
PIC16C774-04 PIC16C773-20
PIC16C774-20 PIC16LC773-04
PIC16LC774-04 JW Devices
RC
VDD: 4. 0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4. 5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 5.5V
IDD: 3.8 mA max. at 3.0V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
XT
VDD: 4. 0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4. 5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 5.5V
IDD: 3.8 mA max. at 3.0V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
HS
VDD: 4. 5V to 5.5V VDD: 4.5V to 5.5V
Not tested for functionality
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V IDD: 20 mA max. at 5.5V IDD: 20 mA max. at 5.5V
IPD: 1.5 µA typ. at 4.5V IPD:1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max. Freq: 20 MHz max. Freq: 20 MHz max.
LP
VDD: 4. 0V to 5.5V
IDD: 52.5 µA typ. at 32
kHz, 4.0V
IPD: 0.9 µA typ. at 4.0V
Freq: 200 kHz max.
Not tested for functionality
VDD: 2.5V to 5.5V
IDD: 48 µA max. at 32 kHz,
3.0V
IPD: 5.0 µA max. at 3.0V
Freq: 200 kHz max.
VDD: 2.5V to 5.5V
IDD: 48 µA max. at 32 kHz,
3.0V
IPD: 5.0 µA max. at 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
PIC16C77X
DS30275A-page 152 Advance Information 1999 Microchip Technology Inc.
15.1 DC Characteristics: PIC16C77X (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001
D001A Su ppl y Voltage VDD 4.0
4.5 —
—5.5
5.5 V
VXT, RC and LP osc configuration
HS osc configuration
D002* RAM Data Re tention
Voltage (Note 1) VDR —1.5—V
D003 VDD start voltage to
ensure in ternal Power- on
Reset signal
VPOR —VSS — V See section on Power-on Reset for details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 — — V/ms See secti on on P ow er-on Reset for details .
PWR T ena bled
D010
D013
Supply Current (Note 2) IDD —
—
2.7
13.5
5
30
mA
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
D020
D020A Power-down Current
(Not e 3) IPD —
—1.5
1.5 16
19 µA
µAVDD = 4.0V, -0°C to +70°C
VDD = 4.0V, -40°C to +85°C
Module Differential Cur-
rent (Note 5)
D021 Watchdog Timer ∆IWDT —6.020µAVDD = 4.0V
D023*
D023B*
Brown-out Reset Current
(Not e 5)
Bandgap voltage
generator
∆IBOR
∆IBG6
TBD
—
200
40µA
—
TBD
µA
µA
BOR enabled, VDD = 5.0V
D025* Timer1 oscill ator ∆IT1OSC —59µAVDD = 4.0V
D026* A/D Conve rter ∆IAD —300—µAVDD = 5.5V, A/D on, not co nverting
* These parameter s are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without lo sing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measuremen ts in act ive operati on mo de are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down cur r ent in SLEEP m od e do es no t de pen d o n th e os c ill ato r ty pe . Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: The ∆ current is the additional current consumed when the peripheral is enabled. This current should be
added to the base (IPD or IDD) current.
6: The bandg ap vol tate refer ence provi des 1.22V to the VRL, VRH, LVD and BOR circui ts. Whe n calculatin g cur-
rent cons umpti on use the f oll owin g formula: ∆IVRL + ∆IVRH + ∆ILVD + ∆IBOR + ∆IBG. An y of the ∆IVRL, ∆IVRH,
∆ILVD or ∆IBOR can be 0.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 153
15.2 DC Characteristics:PIC16LC77X-04 (Commercial, Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Ope rating temp erature -40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
Param
No. Characteristic Sym Min Typ† Max Units Conditions
D001 Supply Voltage VDD 2.5 —5.5 V LP, XT, RC osc co nfiguration (DC - 4
MHz)
D002* RAM Data Retention
Voltage (Note 1) VDR —1.5 —V
D003 VDD start voltage to
ensure i nternal Power-on
Reset si gna l
VPOR —VSS — V See section on Powe r-on Reset for
details
D004* VDD rise rate to ensure
internal Power-on Reset
signal
SVDD 0.05 — — V/ms See sectio n on Powe r-on Reset for
details. PWRT enabled
D010
D010A
Supply Current (Note 2) IDD —
—
2.0
22.5
3.8
48
mA
µA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc configu ration
FOSC = 32 kHz, VDD = 3.0V, WDT dis-
abled
D020
D020A Power-dow n Current
(Note 3) IPD —
—0.9
0.9 5
5µA
µAVDD = 3.0V, 0°C to +70°C
VDD = 3.0V, -40°C to +85°C
Module Differential Cur-
rent (note5)
D021 Watchdog Timer ∆IWDT —620µAVDD = 3.0V
D023* Brown-out Reset Current
(Note 5) ∆IBOR TBD 200 — µA BOR enabled, VDD = 5.0V
D025* Timer1 oscillator ∆IT1OSC —1.53µAVDD = 3.0V
D026* A/D Converter ∆IAD —300—µAVDD = 5.5V, A/D on, not converting
* These parameters are characterize d but not tes ted.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. T hese par amet ers are fo r design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The suppl y curren t is main ly a functio n of the oper at ing v olt age and fre quenc y. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: Fo r RC osc configuration , cur r ent th rou gh Rext is not included . The curre nt th roug h the res ist or ca n be est i-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: The ∆ current is the additional current consumed when the peripheral is enabled. This current should be
added to the base (IPD or IDD) current.
PIC16C77X
DS30275A-page 154 Advance Information 1999 Microchip Technology Inc.
15.3 DC Characteristics: PIC16C77X (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
Operating voltage VDD range as described in DC spec Section 15.1 and
Section 15.2.
Param
No. Characteristic Sym Min Typ† Max Units Conditions
Input Low Voltage
I/O ports VIL
D030 with TTL buffer VSS —0.15VDD V For entire VDD range
D030A VSS —0.8V V 4.5V ≤ VDD ≤ 5.5V
D031 with Schmitt Trigger buffer
RC3 and RC4
All others VSS
VSS
—
—0.3VDD
0.2VDD VI2C compliant
For entire VDD range
D032 MCLR, OSC1 (in RC mode) VSS —0.2VDD V
D033 OSC1 (in XT, HS and LP) VSS —0.3VDD VNote1
Input High Voltage
I/O ports VIH —
D040 with TTL buffer 2.0 —VDD V4.5V ≤ VDD ≤ 5.5V
D040A 0.25VDD
+ 0.8V —VDD V F or enti re VDD range
D041 with Schmitt Trigger buffer
RC3 and RC4
All others 0.7VDD
0.8VDD
—
—VDD
VDD V
VI2C compliant
For entire VDD range
D042 MCLR 0.8VDD —VDD V
D042A OSC1 (XT, HS and LP) 0.7VDD —VDD VNote1
D043 OSC1 (in RC mode) 0.9VDD —VDD V
D070 PORTB weak pull-up curr ent IPURB 50 250 400 µAVDD = 5V, VPIN = VSS
Input Leakage Current
(Notes 2, 3)
D060 I/O ports (digital) IIL ——±1µAVss ≤ VPIN ≤ VDD, Pin at hi-
impedance
D060A I/O ports (RA0-RA3, RA5, RB2,
RB3 analog) IIL ——
±100 nA Vss ≤ VPIN ≤ VDD, Pin at hi-
impedance
D061 MCLR, RA4/T0CKI ——±5µAVss ≤ VPIN ≤ VDD
D063 OSC1 ——±5µAVss ≤ VPIN ≤ VDD, XT, HS and LP
osc configurati on
Output Low Voltage
D080 I/O ports VOL ——
0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
D083 OSC2/CLKOUT (RC osc config) ——
0.6 V IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
* These parameters are characterized but not tested.
† Data in “Typ” col um n i s at 5V, 25°C unle ss oth erw is e s tat ed. These parameters are for desig n gu id anc e o nly
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C77X be driven with external clock in RC mode.
2: The leakag e curre nt on th e MCLR pin is strongly depend ent on the app lied v oltage le v el. The spe cified le v els
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as cu rrent sourced by the pin.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 155
Output High Voltage
D090 I/O por ts (Note 3) VOH VDD - 0.7 ——VIOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
D092 OSC2/CLKOUT (RC osc config) VDD - 0.7 ——VIOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
D150* Open-Drain High Voltage VOD ——
8.5 V RA4 pin
Capacitive Loading Specs on
Output Pins
D100 OSC2 pin COSC2 ——15 pF In XT, H S and LP modes when
external clock is used to drive
OSC1.
D101
D102 All I/O pins and OSC2 (in RC
mode) SCL, SDA in I2C mode CIO
CB—
——
—50
400 pF
pF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
Operating voltage VDD range as described in DC spec Section 15.1 and
Section 15.2.
Param
No. Characteristic Sym Min Typ† Max Units Conditions
* These parameters are characterized but not tested.
† Data in “Typ” col um n i s at 5V, 25°C unle ss oth erw is e s tat ed. These parameters are for desig n gu id anc e o nly
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C77X be driven with external clock in RC mode.
2: The leakag e curre nt on th e MCLR pin is strongly depend ent on the app lied v oltage le v el. The spe cified le v els
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as cu rrent sourced by the pin.
PIC16C77X
DS30275A-page 156 Advance Information 1999 Microchip Technology Inc.
15.4 DC Characteristics: VREF
TABLE 15-2 ELECTRICAL CHARACTERISTICS: VREF
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
Operat ing v oltag e VDD r ange a s describ ed in DC spe c Section 15.1 and Section 15.2.
Param
No. Characteristic Symbol Min Typ† Max Units Conditions
D400 Output Voltage VRL 2.0 2.048 2.1 V VDD ≥ 2.5V
VRH 4.0 4.096 4.2 V VDD ≥ 4.5V
D401A VRL Quiescent Supply Current ∆IVRL —70 TBD µA No load on VRL.
D401B VRH Quiescent Supply Current ∆IVRH —70 TBD µA No load on VRH.
D402 Ouput Voltage Drift TCVOUT —15* 50* ppm/°C Note 1
D404 External Load Source IVREFSO ——5* mA
D405 External Load Sink IVREFSI ——-5* mA
D406 Load Regulation ∆VOUT/
∆IOUT
—1TBD*
mV/mA
Isource = 0 mA to
5mA
—1 TBD* Isink = 0 mA to
5mA
D407 Line Regulation ∆VOUT/
∆VDD ——
50* µV/V
* These parameter s are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Production tested at TAMB = 25°C. Specifications over temp limits guaranteed by characterization.
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 157
FIGURE 15-1: LOW-VOLTAGE DETECT CHARACTERISTICS
TABLE 15-3 ELECTRICAL CHARACTERISTICS: LVD
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for c omme rcial
Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2.
Param
No. Characteristic Symbol Min Typ† Max Units Conditions
D420 LVD Voltage LVV = 01 00 2.5 2.58 2.66 V
LVV = 0101 2. 7 2.78 2.86 V
LVV = 0110 2. 8 2.89 2.98 V
LVV = 0111 3.0 3.1 3.2 V
LVV = 1000 3. 3 3.41 3.52 V
LVV = 1001 3. 5 3.61 3.72 V
LVV = 1010 3. 6 3.72 3.84 V
LVV = 1011 3. 8 3.92 4.04 V
LVV = 1100 4. 0 4.13 4.26 V
LVV = 1101 4. 2 4.33 4.46 V
LVV = 1110 4. 5 4.64 4.78 V
D421 Supply Current ∆ILVD —10 20 µA
D422* LVD Voltage Drift Temperature
coefficient TCVOUT —15 50 ppm/°C
D423* LVD Voltage Drift with respect to
VDD Regulation ∆VLVD/
∆VDD ——50 µV/V
D424* Low-voltage Detect Hysteresis VLHYS TBD —100 mV
* These parameter s are characterized but not tested.
Note 1: Production tested at Tamb = 25°C. Specifications over temp limits ensured by characterization.
VLVD VLHYS
LVDIF
VDD
(LVDIF set by hardware)
(LVDIF can be cleared i n software anytime during
the gray area)
PIC16C77X
DS30275A-page 158 Advance Information 1999 Microchip Technology Inc.
FIGURE 15-2: BROWN-OUT RESET CHARACTERISTICS
TABLE 15-4 ELECTRICAL CHARACTERISTICS: BOR
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
Operating voltage VDD range as described in DC spec Section 15.1 and
Section 15.2.
Param
No. Characteristic Symbol Min Typ Max Units Conditions
D005 BOR Voltage BORV1:0 = 11
VBOR
2.5 2.58 2.66
V
BORV1:0 = 10 2 .7 2.78 2.86
BORV1:0 = 01 4 .2 4.33 4.46
BORV1:0 = 00 4 .5 4.64 4.78
D006* BOR Voltage Drift Temperature coef-
ficient TCVOUT —15 50 ppm/°C
D006A* BOR Voltage Drift with respect to
VDD Regulation ∆VBOR/
∆VDD ——50 µV/V
D007 Brown-out Hysteresis VBHYS TBD —100mV
D022A Supply Current ∆IBOR —10 20 µA
* These parameter s are characterized but not tested.
Note 1: Production tested at TAMB = 25°C. Specifications over temp limits ensured by characterization.
VBOR VBHYS
RESET (due to BOR)
VDD
(device in Brown-out Reset)
(device not in Brown-out Rese t)
72 ms time out
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 159
15.5 AC Characteristics: PIC16C77X (Commercial, Industrial )
15.5.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TFFrequency TTime
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
SFFall PPeriod
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output acce ss High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
PIC16C77X
DS30275A-page 160 Advance Information 1999 Microchip Technology Inc.
FIGURE 15-3: LOAD CONDITIONS
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL=464Ω
CL= 50 pF for all pins e xcept OS C2, bu t includi ng POR TD and POR T E outputs as
ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16C773.
Load condition 1 Load condition 2
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 161
15.5.2 TIMING DIAG RAMS AND SPECIFICATIONS
FIGURE 15-4: EXTERNAL CLOCK TIMING
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
TABLE 15-5 EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
Fosc External CLKIN Frequency
(Note 1) DC — 4 MHz XT and RC osc mode
DC — 4 MHz HS osc mode (-04)
DC — 20 MH z HS osc mode (-20)
DC — 200 kHz LP osc mode
Oscillator Frequency
(Note 1) DC — 4 MHz RC osc mode
0.1 — 4 MHz XT osc mode
4
5—
—20
200 MHz
kHz HS osc mode
LP osc mode
1ToscExternal CLKIN Period
(Note 1) 250 — — ns X T and RC osc mode
250 — — ns HS osc mode (-04)
50 — — ns HS osc mode (-20)
5— —µs LP osc mode
Oscillator Period
(Note 1) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
250 — 250 ns HS osc mode (-04)
50 — 250 ns HS osc mode (-20)
5— —µs LP osc mode
2T
CY Instruction Cycle Time (Note 1) 200 TCY DC ns TCY = 4/F OSC
3* TosL,
TosH Exte rnal Clock in (OSC 1) High or
Low Time 100 — — ns XT oscillator
2.5 — — µs LP oscillator
15 — — ns HS oscillator
4* TosR,
TosF External Clock in (OSC1) Rise or
Fall Time — — 25 ns XT oscillator
— — 50 ns LP oscillator
— — 15 ns HS oscillator
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (T CY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device ex ecuting code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
PIC16C77X
DS30275A-page 162 Advance Information 1999 Microchip Technology Inc.
FIGURE 15-5: CLKOUT AND I/O TIMING
TABLE 15-6 CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1
11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1
12* TckR CLKOUT rise time — 35 100 ns Note 1
13* TckF CLKOUT fall time — 35 100 ns Note 1
14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1
15* TioV2ckH Port in valid before CLKOUT ↑ 0.25TCY + 25 — — ns Note 1
16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1
17* TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid — 50 150 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
PIC16C77X 100 — — ns
PIC16LC77X 200 — — ns
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns
20* TioR Port output rise time PIC16C77X —1025ns
PIC16LC77X — — 60 ns
21* TioF Port output fall time PIC16C77X —1025ns
PIC16LC77X — — 60 ns
22††* Tinp INT pin high or low time TCY ——ns
23††* Trbp RB7:RB4 change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 15-3 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12 16
old value new v alue
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 163
FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMI NG
FIGURE 15-7: BROWN-OUT RESET TIMING
TABLE 15-7 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER,POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
30* TmcL MCLR Pulse Width (low) 100 ——nsVDD = 5V, -40°C to +85°C
31* Twdt W atchdog Timer Time-out Period
(No Prescaler) 71833msV
DD = 5V, -40°C to +85°C
32* Tost Oscillation Start-up Timer Period — 1024TOSC ——TOSC = OSC1 period
33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
34* TIOZ I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset — — 100 ns
35* TBOR Brown-out Reset pulse width 100 — — µsVDD ≤ VBOR (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 15-3 for load conditions.
VDD BVDD
35
PIC16C77X
DS30275A-page 164 Advance Information 1999 Microchip Technology Inc.
FIGURE 15-8: BANDGAP START-UP TIME
TABLE 15-8 BANDGAP START-UP TIME
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
36* TBGAP Bandgap start-up time —30TBDµs Defined as the time between
the instant that the bandgap
is enabled and the moment
that the bandgap reference
voltage is s table.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
VBGAP = 1.2V
VBGAP
Enable Bandgap
Bandgap stable TBGAP
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 165
TABLE 15-9 A/D CONVERTER CHARACTERISTICS:
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 12 bits bit Min. resolution for A/D is 1 mV,
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A03 EIL Integral error — — +/-2 LSb — VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A04 EDL Differential error — — +2 LSb
-1 LSb — No m issing codes to 12-bits
VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A06 EOFF Offset error — — less than
±2 LSb —VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A07 EGN Gain Error — — +/- 2LSb LSb VREF+ = AVDD = 4.096V,
VREF- = AVSS = 0V,
VREF- ≤ VAIN ≤ VREF+
A10 — Monotonicity — guaranteed(3) ——AVSS ≤ VAIN ≤ VREF+
A20 VREF Reference voltage
(VREF+ VREF-) 4.096 — VDD +0.3V V Absolute minimum electrical spec to
ensure 12-bit accuracy.
A21 VREF+Reference V High
(AVDD or VREF+) VREF-— AVDD V Min. resolution for A/D is 1 mV
A22 VREF-Reference V Low
(AVSS or VREF-) AVSS —VREF+ V Min. resolution for A/D is 1 mV
A25 VAIN Analog input voltage VREFL —VREFH V
A30 ZAIN Recommended
impedance of analog
v oltage source
——2.5kΩ
A50 IREF VREF input current
(Note 2) ——10µA During VAIN acquisition.
Based on differential of VHOLD to VAIN.
To charge CHOLD see Section 11.0.
During A/D conversion cycle.
* These parameters are characterized but not tested.
† Dat a in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: When A/D is off, it will not consume any current other t han minor leakage current. The pow er down current spec includes any
such leakage from the A/D module.
2: VREF curr ent is from External VREF+, OR VREF-, or AVSS, or AVDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input volt age and has no missing codes.
PIC16C77X
DS30275A-page 166 Advance Information 1999 Microchip Technology Inc.
FIGURE 15-9: A/D CONVERSION TIMING (NORMAL MODE)
TABLE 15-10 A/D CONVERSION REQU IREMENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
130* TAD A/D clock period 1.6 ——µs Tosc based, VREF ≥ 2.5V
3.0 — — µs Tosc based, VREF full range
130* TAD A/D Internal RC
oscillator period 3.0 6.0 9.0 µsADCS1:ADCS0 = 11 (RC mode)
At VDD = 2.5V
2.0 4.0 6.0 µsAt V
DD = 5.0V
131* TCNV Conv ersion time (not
including
acquisition time)
(Note 1)
— 13TAD —TAD Set GO bit to new data in A/D result
register
132* TACQ Acquisition Time Note 2
5*
11.5
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134* TGO Q4 to A/D clock start — TOSC/2 — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock star ts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: ADRES register may be read on the following TCY cycle.
2: S ee Section 11.6 for minimum conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
987 3210
Note 1: I f the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1/2 Tcy
6
134
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 167
FIGURE 15-10: A/D CONVERSION TIMING (SLEEP MODE)
TABLE 15-11 A/D CONVERSION REQUIREM ENTS
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
130* TAD A/D clock period 1.6 ——µsVREF ≥ 2.5V
TBD — — µsV
REF full range
130* TAD A/D Internal RC
oscillator period 3.0 6.0 9.0 µsADCS1:ADCS0 = 11 (RC mode)
At VDD = 3.0V
2.0 4.0 6.0 µsAt V
DD = 5.0V
131* TCNV Conv ersion time (not
including acquisition
time)(Note 1)
— 13TAD ——
132* TACQ Acquisition Time Note 2
5*
11.5
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134* TGO Q4 to A/D clock start — TOSC/2 + TCY — — If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock star ts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: ADRES register may be read on the following TCY cycle.
2: S ee Section 11.6 for minimum conditions.
131
130
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
9 7 3210
Note 1: I f the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
134
6
8
132
PIC16C77X
DS30275A-page 168 Advance Information 1999 Microchip Technology Inc.
FIGURE 15-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIM INGS
TABLE 15-12 TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet
parameter 42
With Prescaler 10 — — ns
42* Tt 0P T0CK I Period No Prescaler TCY + 40 — — ns
With Prescaler Greater of:
20 or TCY + 40
N
— — ns N = prescale value
(2, 4, ..., 256)
45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C77X 15 — — ns
PIC16LC77X 25 — — ns
Asynchronous PIC16C77X 30 — — ns
PIC16LC77X 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
PIC16C77X 15 — — ns
PIC16LC77X 25 — — ns
Asynchronous PIC16C77X 30 — — ns
PIC16LC77X 50 — — ns
47* Tt1P T1CKI input period Synchronous PIC16C77X Greater of:
30 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
PIC16LC77X Great er of:
50 OR TCY + 40
N
— — ns N = prescale value
(1, 2, 4, 8)
Asynchronous PIC16C77X 60 — — ns
PIC16LC77X 100 — — ns
Ft1 Timer1 oscillator input freque ncy r ange
(oscillator enabled by setting bit T1OSCEN) DC — 50 kHz
48 TCKEZtmr1 Delay from external clock edg e to timer increment 2Tosc — 7Tosc —
* These parameters are characterized but not tested.
† Dat a in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and ar e not
tested.
Note: Refer to Figure 15-3 for load condi tio ns.
46
47
45
48
41
42
40
RA4/T0CKI
RC0/T1OSO/T1CKI
TMR0 or
TMR1
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 169
FIGURE 15-12: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 15-13 CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 and CCP2
input low time No Prescaler 0.5TCY + 20 ——ns
With Prescaler PIC16C77X 10 — — ns
PIC16LC77X 20 — — ns
51* TccH CCP1 and CCP2
input high time No Prescaler 0.5TCY + 20 — — ns
With Prescaler PIC16C77X 10 — — ns
PIC16LC77X 20 — — ns
52* TccP CCP1 and CCP2 input period 3TCY + 40
N— — ns N = prescale value
(1,4 or 16)
53* TccR CCP1 and CCP2 output fall time PIC16C77X —1025ns
PIC16LC77X —2545ns
54* TccF CCP1 and CCP2 output fall time PIC16C77X —1025ns
PIC16LC77X —2545ns
* Thes e parameters are character ized but not tested.
† Data in "Ty p" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 15-3 for load conditions.
and RC2/CCP1
(Capture Mode)
50 51
52
53 54
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
RC1/T1OSI/CCP2
PIC16C77X
DS30275A-page 170 Advance Information 1999 Microchip Technology Inc.
FIGURE 15-13: PARALLEL SLAVE PORT TIMING (PIC16C774)
TABLE 15-14 PARALLEL SLAVE PORT REQUIREMENTS (PIC16C774)
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
62* TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20
25 —
——
—ns
ns Extended
Temperature
Range Only
63* TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) PIC16C774 20 — — ns
PIC16LC774 35 — — ns
64* TrdL2dtV RD↓ and CS↓ to data–out vali d —
——
—80
90 ns
ns Extended
Temperature
Range Only
65* TrdH2dtI RD↑ or CS↓ to data–out invalid 10 — 30 ns
* These parameters are characterized but not tested.
† Data in "Ty p" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 15-3 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 171
FIGURE 15-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 15-15 USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 15-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 15-16 USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
120* TckH2dtV SYNC XMIT (MASTE R &
SLAVE)
Cloc k high to data out valid PIC16C774/773 — — 80 ns
PIC16LC774/773 — — 100 ns
121* Tc krf Cloc k out rise time and fall time
(Master Mode) PIC16C774/773 — — 45 ns
PIC16LC774/773 — — 50 ns
122* T dtrf Data out rise time and fall time PIC16C774/773 — — 45 ns
PIC16LC774/773 — — 50 ns
* These parameters are characterized but not tested.
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
125* TdtV2c k L SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time) 15 ——ns
126* TckL2dtl Data hold after CK ↓ (DT hold time) 15 — — ns
* These parameters are characterized but not tested.
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note: Refer to Figure 15-3 for load conditions.
121 121
122
RC6/TX/CK
RC7/RX/DT
pin
pin
120
Note: Refer to Figure 15-3 for load conditions.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
PIC16C77X
DS30275A-page 172 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 173
16.0 DC AND AC CHARACTERISTIC S GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. ’Typical’ represents the mean of the distribution at 25°C. ’Max’ or ’min’ represents
(mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.
Graphs and Tables not available at this time.
PIC16C77X
DS30275A-page 174 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 175
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXXXXXX
AABBCDE
Example
PIC16C773-20/SO
XXXXXXXXXXXXXXXXXXXX
AABBCDE
28-Lead PDIP (Skinny DIP) Example
PIC16C773-20/SP
9917HAT
9910SAA
AABBCAE
XXXXXXXXXXXX
XXXXXXXXXXXX
28-Lead SSOP
9817SBP
20I/SS
PIC16C773
Example
Legend: MM...M Microchip part number information
XX...X Customer speci fic information *
AA Year code (last 2 digi ts of calendar year)
BB Week code (week of January 1 is week ‘01’)
C Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D Mask revision number
E Assembly code of the plant or country of origin in which
part was assembled
Note: In the e ven t the ful l Micro chip pa rt number ca nno t be mark ed on one li ne , it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
28-Lead CERDIP Windowed
XXXXXXXXXXX
PIC16C774/JW
Example
9905HAT
XXXXXXXXXXX
PIC16C77X
DS30275A-page 176 Advance Information 1999 Microchip Technology Inc.
Package Marking Information (Cont’d)
XXXXXXXXXXXXXXXXXX
AABBCDE
40-Lead PDIP Example
PIC16C774-04/P
XXXXXXXXXXXXX
AABBCDE
40-Lead CERD IP Wi ndowed
XXXXXXXXXXXXX
PIC16C774/JW
Example
9912SAA
9905HAT
44-Lead TQFP
XXXXXXXXXXXX
AABBCDE
XXXXXXXXXXXX
XXXXXXXXXXXX
Example
-04/PT
PIC16C774
44-Lead PLC C
XXXXXXXXXXXX
AABBCDE
XXXXXXXXXXXX
XXXXXXXXXXXX
44-Lead MQ FP
Example
PIC16C774
-04/L
Example
-20/PQ
PIC16C774
9904SAT
9911HAT
9903SAT
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXX
XXXXXXXXXXXX
AABBCDE
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 177
17.2 K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil
* Controlling Parameter.
†Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
0.320
0.270
0.280
1.345
0.125
0.015
0.070
0.140
0.008
0.000
0.040
0.016
Mold Draft Angle Bottom
Mold Draft Angle Top
Overall Row Spacing
Radius to Radius Width
Molded Package Width
Tip to Seating Plane
Base to Seating Plane
Top of Lead to Seating Plane
Top to Seating Plane
Upper Lead Width
Lower Lead Width
PCB Row Spacing
Package Length
Lead Thickness
Shoulder Radius
Number of Pins
Dimension Limits
Pitch
Units
E‡
β
eB
E1
α
A1
A2
L
D‡
A
c
R
n
B1†
B
p
MIN MIN
0.2950.288
5
510
0.350
0.283
10 0.380
0.295
15
15
0.090
1.365
0.130
0.020
0.150
0.010
0.005
NOM
INCHES*
28
0.053
0.019
0.100
0.300
1.385
0.135
0.025
0.110
0.160
0.012
0.010
0.065
0.022
MAX
7.497.307.11
8.89
7.18
5
8.13
6.86
510
10 15
15
9.65
7.49
34.67
3.30
0.51
2.29
3.81
0.25
0.13
1.33
0.48
2.54
7.62
MILLIMETERS
1.78
34.16
3.18
0.38
3.56
0.20
0.00
1.02
0.41
NOM
2.79
35.18
3.43
0.64
4.06
0.30
0.25
MAX
28
1.65
0.56
n 1
2
R
D
E
c
eB
β
E1
α
p
L
A1
B
B1
A
A2
PIC16C77X
DS30275A-page 178 Advance Information 1999 Microchip Technology Inc.
17.3 K04-080 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil
* Controlling P arameter.
n 1
2
R
Overall Row Spacing
Radius to Radius Width
Package Length
Tip to Seating Plane
Base to Seating Plane
Top of Lead to Seating Plane
Top to Seating Plane
Shoulder Radius
Upper Lead Width
Lower Lead Width
PCB Row Spacing
Dimension Limits
Window Width
Window Length
Package Width
Lead Thickness
Pitch
Number of Pins
Units
0.170A
0.130W1
W2 0.290
D
E1
eB
E
A2
L
A1
1.430
0.345
0.255
0.285
0.135
0.015
0.107
B
R
c
B1
n
p0.016
0.008
0.010
0.050
0.098
MIN MILLIMETERS
4.320.1950.183
0.310
0.150
0.425
0.285
0.295
1.485
0.145
0.030
0.143
0.140
0.300
0.385
0.270
0.290
1.458
0.140
0.023
0.125
0.13
0.29
36.32
8.76
6.48
7.24
3.43
0.00
2.72
0.012
0.015
0.065
0.021
0.102
MAXNOM
0.010
0.013
0.058
0.019
0.100
0.300
28
INCHES*
0.41
0.20
0.25
1.27
2.49
MIN
4.954.64
0.31
0.15
10.80
7.24
7.49
37.72
3.68
0.76
3.63
0.14
0.3
37.02
6.86
9.78
7.37
0.57
3.56
3.18
0.30
0.38
1.65
0.53
2.59
NOM
28
0.47
0.32
0.25
1.46
2.54
7.62 MAX
D
W2
W1
E
c
E1
eB p
A1
L
B1
B
A2
A
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 179
17.4 K04- 052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil
MIN
pPitch
Mold Draft Angle Bottom
Mold Draft Angle Top
Lower Lead Width
Radius Centerline
Gull Wing Radius
Shoulder Radius
Chamfer Distance
Outside Dimension
Molded Package Width
Molded Package Length
Shoulder Height
Overall Pack . Height
Lead Thickness
Foot Angle
Foot Length
Standoff
Number of Pins
β
α
B†
c
φ
X
A2
A1
A
n
E1
L
L1
R1
R2
E‡
D‡
Dimension Limits
Units
1.270.050
8
12
12
0.017
0
0.014
00.019
15
15
0.011
0.015
0.016
0.005
0.005
0.020
0.407
0.296
0.706
0.008
0.058
0.099
28
0.394
0.011
0.009
0.010
0
0.005
0.005
0.010
0.292
0.700
0.004
0.048
0.093
0.419
0.012
0.020
0.021
0.010
0.010
0.029
48
0.299
0.712
0.011
0.068
0.104
0.36
0
012
12
0.42
15
15
0.48
10.33
17.93
10.01
0.23
0.25
0.28
0.13
0.13
0.25
0
7.42
0.10
1.22
2.36
17.78
10.64
0.41
4
0.27
0.38
0.13
0.13
0.50
0.53
0.30
0.51
0.25
0.25
0.74
7.51
0.19
28
2.50
1.47
18.08
7.59
0.28
2.64
1.73
NOM
INCHES* MAX NOM
MILLIMETERS
MIN MAX
n1
2
R1
R2
D
p
B
E1
E
L1
L
c
β
45°
X
φ
A1
α
A
A2
* Controlling Parameter.
†Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
PIC16C77X
DS30275A-page 180 Advance Information 1999 Microchip Technology Inc.
17.5 K04- 073 28- Lead Plastic Shrink Small Outline (SS) – 5.30 mm
Dimension Limits
Mold Draft Angle Bottom
Mold Draft Angle To p
Lower Lead Width
Lead Thickness
Radius Centerline
Gull Wing Radius
Shoulder Radius
Outside Dimension
Molded Pa ckage Width
Molded Pa ckage Length
Shoulder Height
Overall Pack. Height
Number of Pins
Foot Angle
Foot Length
Standoff
Pitch
β
α
B†
E‡
L
c
L1
φ
R1
R2
E1
A2
D‡
A1
A
n
p
Units MAXNOMMINMAXNOMMIN
10
10
0.38
0.22
0.25
0.64
0.25
0.25
7.90
5.38
10.33
0.21
1.17
1.99
0.012
0
0.010
05
510
0.015
10
0.007
0.005
0.020
0.005
0.005
0.306
0.208
0.402
0.005
0.036
0.073
0.026
0.205
0.015
0.005
0.000
0
0.005
0.005
0.301
0.396
0.002
0.026
0.068
0.212
40.025
0.009
0.010
8
0.010
0.010
0.311
28
0.407
0.008
0.046
0.078
0.25
0
05
0.32
5
5.20
0.13
0.00
0.38
0.13
0.13
7.65
0
10.07
0.05
0.66
1.73
5.29
0.51
0.18
0.13
4
0.13
0.13
7.78
10.20
0.13
0.91
1.86
0.65
28
8
INCHES MILLIMETERS*
n1
2
R1
R2
D
p
B
E
E1
L
L1
β
c
φ
α
A1
A2
A
* Controlling P arameter.
†Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 181
17.6 K04-016 40-Lead Plastic Dual In-line (P) – 600 mil
* Controlling Parameter.
†Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
n2
1
R
Top to Seating Plane
Mold Draft Angle Bottom
Mold Draft Angle Top
Overall Row Spacing
Radius to Radius Width
Molded Package Width
Tip to Seating Plane
Base to Seating Plane
Top of Lead to Seating Plane
Package Length
E1
β
eB
α
L
E‡
D‡
A2
A1
0.670
0.585
0.540
2.023
0.135
0.040
0.113
0.545
5
5
0.630
0.125
0.530
2.013
0.020
0.073
0.565
10
0.610
10
0.130
0.535
2.018
0.020
0.093
16.00
13.84
13.46
51.13
3.18
0.51
1.85
15
15
14.35
5
510
15.49
10
3.30
13.59
51.26
0.51
2.36
14.86
17.02
15
15
13.72
51.38
3.43
1.02
2.87
PCB Row Spacing
Lead Thickness
Shoulder Radius
Upper Lead Width
Lower Lead Width
Pitch
Number of Pins
Dimension Limits
Units
p
c
A
R
B
B1†
n
0.160
0.011
0.010
0.055
0.020
NOM
INCHES*
0.110
0.009
0.000
0.045
0.016
MIN
0.100
0.160
0.010
0.005
0.050
0.018
40
0.600 MAX
2.79
0.23
0.00
1.14
0.41
MIN
2.54
4.06
0.25
0.13
1.27
0.46
NOM
MILLIMETERS
15.24
40
4.06
0.28
0.25
1.40
0.51
MAX
A1
D
E
c
βeB
E1
α
p
L
B
B1
A
A2
PIC16C77X
DS30275A-page 182 Advance Information 1999 Microchip Technology Inc.
17.7 K04-014 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil
* Controlling Parameter.
n1
2
R
Window Diameter
Overall Row Spacing
Radius to Radius Width
Package Width
Package Length
Tip to Seating Plane
Base to Seating Plane
Top of Lead to Seating Plane
Top to Seating Plane
Lead Thickness
Shoulder Radius
Upper Lead Width
Lower Lead Width
Number of Pins
PCB Row Spacing
Dimension Limits
Pitch
E1
W
eB
D
E
L
A2
A1
A
c
p
B1
R
B
n
9.14
18.03
15.24
13.36
52.32
3.68
3.89
5.59
0.36
0.25
0.58
2.59
MAX
0.0140.0110.008
0.350
0.660
0.580
0.520
2.050
0.140
0.045
0.135
0.205
0.560
0.340
0.610
0.514
2.040
0.135
0.030
0.117
0.190
0.600
0.360
0.710
0.526
2.060
0.145
0.060
0.153
0.220
0.005
0.053
0.020
0.100
0.600
NOM
0.000
0.050
0.016
0.098
MIN
40 0.102
0.010
0.055
0.023
MAX
0.280.20
14.22
15.49
8.64
13.06
51.82
3.43
0.00
2.97
4.83
14.73
16.76
8.89
13.21
52.07
3.56
1.14
3.43
5.21
MIN
2.49
1.27
0.00
0.41 2.54
1.33
0.13
0.50
15.24
NOM
40
1.52
1.40
D
W
E
c
eB
E1
p
L
A1
B1
B
A
A2
Units INCHES* MILLIMETERS
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 183
17.8 K04-076 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form
0.025
0.390
0.390
0.463
0.463
0.012
0.004
0.003
0.005
0.003
0.003
0.002
0.015
0.039
p
Mold Draft Angle Bottom
Mold Draft Angle Top
Pin 1 Corner Chamfer
Molded Pack. Width
Molded Pack. Length
Outside Tip Width
Outside Tip Length
Lower Lead Width
Lead Thickness
Radius Centerline
Gull Wing Radius
Shoulder Radius
Shoulder Height
Ov erall Pack. Height
Pins along Width
Number of Pins
Foot Length
Foot Angle
Standoff
D‡
β
X
α
E‡
L
D1
E1
B†
c
L1
φ
A1
R1
R2
A2
n1
A
n
Dimension Limits
Pitch
Units MIN
0.3980.394
5
512
0.035
0.394
10 0.045
0.398
15
15
0.010
0
0.472
0.472
0.015
0.006
0.008
3.5
0.025
0.006
0.003
0.004
0.043
11
44
0.015
0.482
0.482
0.018
0.008
0.013
7
0.008
0.010
0.006
0.035
0.047
10.1010.009.90
12
10
0.89
10.00
5
0.64
9.90
515
15
1.14
10.10
12.00
12.00
0.38
0.15
0.20
3.5
0.25
0.14
0.08
0.10
0.64
1.10
11
44
0.13
11.75
11.75
0.30
0.09
0.08
0
0.38
0.08
0.08
0.05
1.00
0.38
12.25
12.25
0.45
0.20
0.33
7
0.89
0.20
0.25
0.15
1.20
MINNOM
INCHES
0.031 MAX 0.80
MILLIMETERS*
NOM MAX
X x 45°
n
1
2
R2
R1 L1
L
β
c
φ
D1D
B
p
# leads = n1
E
E1
α
A1
A2
A
* Controlling Parameter.
†Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MS-026 ACB
PIC16C77X
DS30275A-page 184 Advance Information 1999 Microchip Technology Inc.
17.9 K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form
* Controlling Parameter.
†Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MS-022 AB
0.025
0.390
0.390
0.510
0.510
0.012
0.005
0.011
0.015
0.005
0.005
0.002
0.032
0.079
pPitch
Mold Draft Angle Bottom
Mold Draft Angle Top
Pin 1 Corner Chamfer
Molded Pack. Width
Molded Pack. Length
Outside Tip Width
Outside Tip Length
Lower Lead Width
Radius Centerline
Gull Wing Radius
Shoulder Radius
Shoulder Height
Ov erall Pack . Hei ght
Pins along Width
Lead Thickness
Foot Angle
Foot Length
Standoff
Number of Pins
β
α
X
E‡
D‡
c
φ
A2
A1
A
n1
n
R2
E1
D1
B†
L1
L
R1
Dimension Limits
Units MIN 0.800.031
0.635
12.95
12.95
0.035
0.394
0.394
5
510
12 15
15
0.045
0.398
0.398
0.012
0.520
0.520
0.015
0.007
0.016
0.020
03.5
0.005
0.006
0.044
0.086
11
44
0.015
0.009
0.530
0.530
0.018
0.021
0.025
7
0.010
0.010
0.056
0.093
5
5
9.90
9.90
10
12
10.00
10.00
0.89 1.143
10.10
10.10
15
15
0.300.13
0.13
0.30
0
0.28
0.38
0.18
13.20
13.20
0.37
3.5
0.41
0.51
0.13
0.05
0.81
2.00
0.13
0.15
1.11
11
2.18
44
0.38
13.45
13.45
0.45
0.23
0.53
0.64
7
0.25
0.25
1.41
2.35
MINNOM
INCHES MAX MILLIMETERS*
NOM MAX
X x 45°
n
1
2
R2
R1
DD1
B
p
E1
E
# leads = n1
L1
L
c
βφ
α
A1
A
A2
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 185
17.10 K04-048 44-Lead Plastic Leaded Chip Carrier (L) – Square
* Controlling Parameter.
†Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimens ion “B1.”
‡Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent:MO-047 AC
0.015
0.003
0.050
0.015
0.026
0.008
0.610
0.610
0.650
0.650
0.685
0.685
0.000
0.040
0.024
0.015
0.095
0.165
MIN
pPitch
Mold Draft Angle Bottom
Mold Draft Angle Top
J-Bend Inside Radius
Shoulder Inside Radius
Upper Lead Length
Lower Lead Width
Upper Lead Width
Lead Thickness
Pins along Width
Footprint Length
Footprint Width
Molded Pack. Length
Molded Pack. Width
Overall Pack. Length
Overall Pack. Width
Corner Chamfer (other)
Corner Chamfer (1)
Side 1 Chamfer Dim.
Shoulder Height
Overall Pack . Height
Standoff
R2
R1
α
β
L
B
B1†
D2
E2
CH2
CH1
A3
A2
E1
c
n1
E‡
D‡
D1
A1
A
Number of Pins
Dimension Limits
Units
n1.270.050
0
0
0.005
0.025
5
5
0.058
0.018
0.029
0.035
0.010
0.065
0.021
0.032
10
10
0.690
0.620
0.010
0.620
11
0.653
0.653
0.690
0.005
0.045
0.029
0.023
0.103
0.173
0.695
0.012
0.630
0.630
0.656
0.656
0.695
0.010
0.050
0.034
0.030
0.110
0.180
0.64
0.13
1.46
0.46
0.74
0.08
0.38
0
0
1.27
0.38
0.66
5
5
0.25
0.89
10
10
1.65
0.53
0.81
0.25
15.75
15.75
16.59
16.59
17.53
17.53
0.13
1.14
0.74
0.57
2.60
4.38
17.40
15.49
0.20
15.49
16.51
16.51
17.40
0.00
1.02
0.61
0.38
2.41
4.19
17.65
11
16.00
0.30
16.00
16.66
16.66
17.65
0.25
1.27
0.86
0.76
2.79
4.57
INCHES*
NOM44 MAX MILLIMETERS
MIN NOM MAX
44
1
CH2 x 45°nCH1 x 45°
2
β
R2
A1
R1
c
E2
D1
D
# leads = n1
E1
E
α
p
L
A3
A2
A
35°
B1
B
D2
PIC16C77X
DS30275A-page 186 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 187
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for conv erting from pre vious versions of
de vices to the ones li sted in thi s data shee t are listed in
the following:
PIC16C774 vs. PIC16C74A
• RA2 Added VREF- and VRL
• RA3 Added VREF+ and VRH
• RA5 Removed SS
•Pin 11 AVDD vs. VDD
•Pin 12 AVSS vs. VSS
• RB1 Added SS, SS is now ST vs. TTL
• RB2 Added AN8
• RB3 Added AN9 and LVDIN
PIC16C773 vs. PIC16C73A
• RA2 Added VREF- and VRL
• RA3 Added VREF+ and VRH
•Pin 7 AVDD vs. removed RA5/SS/AN4
•Pin 8 AVSS vs. VSS
• RB1 Added SS, SS is now ST vs. TTL
• RB2 Added AN8
• RB3 Added AN9 and LVDIN
Program Memor y Differe nces
none
Data Memory Differences
1. Data memory size has increased to 256 from
192 by adding bank 2.
2. Bank 1 locations 0xF0 - 0xFF are now common
RAM locations across banks 0-3.
Peripheral Differences
1. 12-bit A/D replaces 8-bit A/D.
2. Master Synchronous Serial Port replace
Synchronous Serial Port.
3. USART adds 9-bit address mode to module.
4. Bandgap Voltage Reference added.
5. Low-voltage Detect Module added.
6. Selectable Brown-out Reset voltages added.
Version Date Revision Desc ri ption
A 99 This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the
PIC16C7X Data Sheet
, DS30390E.
TABLE B-1: DEVICE DIFFERENCES
Difference PIC16C773 PIC16C774
A/D 6 channels, 12 bits 10 channels, 12 bits
Parallel Slave Port no yes
Packages 28-pin PDIP, 28-pin windowed CERDIP,
28-pin SOIC, 28-pin SSOP 40-pin PDIP, 40-pin windowed CERDIP,
44-pin TQFP, 44-pin MQFP,
44-pin PLCC
PIC16C77X
DS30275A-page 188 Advance Information 1999 Microchip Technology Inc.
NOTES:
PIC16C77X
1999 Microchip Technology Inc. Preliminary DS30275A-page 189
INDEX
A
A/D ................................................................................... 117
A/D Converter Enable (ADIE Bit) ...............................19
A/D Converter Flag (ADIF Bit) ...................................20
ADCON0 Register ....................................................117
ADCON1 Register . ...........................................117, 118
ADRES Register ......................................................117
Analog Port Pins ......................................7, 8, 9, 36, 37
Block Diag ram ........ .......... ........... .......... ........... ........120
Configuring Analog Port ...........................................119
Conversion time .......................................................125
Conversions .............................................................121
converter characteristics ..................156, 157, 158, 165
Faster Conversion - Lower Resolution Tradeoff ......125
Internal Sampling Switch (Rss) Impedence .. ...........123
Operation During Sleep ...........................................126
Sampling Requirements .......................... .. ....... .. .... ..123
Sampli n g Time ....................... ........... .......... ........... ..123
Source Impedance ....... .... .... ......... .. .... .... .... ......... .. ..123
Special Event Trigger (CCP) ......................................49
A/D Conversion Clock ......................................................121
ACK ....................................................................................64
Acknowledge Data bit, AKD ...............................................56
Acknowledge Pulse ............................................................64
Acknowledge Sequence Enable bit, AKE ..........................56
Acknowledge Status bit, AKS ............................................56
ADCON0 Register ............................................................117
ADCON1 Register ....................................................117, 118
ADRES .............................................................................117
ADRES Register ..........................................13, 14, 117, 126
AKD ....................................................................................56
AKE ....................................................................................56
AKS ..............................................................................56, 79
Application Note AN578, "Use of the SSP
Module in the I2C Multi-Master Environment." . ..................63
Architecture
PIC16C63A/PIC16C73B Block Diagram ......................5
PIC16C65B/PIC16C74B Block Diagram ......................6
Assembler
MPASM Assembler ..................................................147
B
Banking, Data Memory ................................................11, 16
Baud Rate Generator .........................................................73
BF ....................................................................54, 64, 79, 82
Block Diagrams
Baud Rate Generator .................................................73
I2C Master Mode ........................................................71
I2C Module .................................................................63
SSP (I2C Mode) .. .......................................................63
SSP (SPI Mode) . . ..................... ..................... .............57
BOR.
See
Brown-out Reset
BRG ...................................................................................73
Brown-out Reset (BOR) ...................127, 131, 132, 133, 134
BOR Status (BO R Bit) ........ ............... .......... ...............23
Buffer Full bit, BF ...............................................................64
Buffer Full Status bit, BF ....................................................54
Bus Arbitration ..................... .......... ............... ........... ..........90
Bus Collision
Section .......................................................................90
Bus Collision During a RESTART Condition .......... ............93
Bus Collision During a Start Condition .... ............ ...............91
Bus Collision During a Stop Condition .... ............ ............. ..94
C
Capture (CCP Module) ................... .... .... .. ......... .... .. .... .... .. 48
Block Diag ram ........... ........... .......... ........... .......... ...... 48
CCP Pin Configuration .............................................. 48
CCPR1H:CCPR1L Registers .................................... 48
Changing Between Capture Prescalers .................... 48
Softwar e In terrupt ......................... ........... .......... ........ 48
Timer1 Mode Selection . ............................................. 48
Capture/Compar e /PWM (CCP) ......................... .......... ...... 47
CCP1 ......................................................................... 47
CCP1CON Register ........................................... 47
CCPR1H Register ........................... .................. 47
CCPR1L Register .............................................. 47
Enable (CCP1IE Bit) .......................................... 19
Flag (CCP1IF Bit) .............................................. 20
RC2/CCP1 Pin ................................................. 7, 9
CCP2 ......................................................................... 47
CCP2CON Register ........................................... 47
CCPR2H Register ........................... .................. 47
CCPR2L Register .............................................. 47
Enable (CCP2IE Bit) .......................................... 21
Flag (CCP2IF Bit) .............................................. 22
RC1/T1OSI/CCP2 Pin ..................................... 7, 9
Interaction of Two CCP Modules ............................... 47
Timer Resources ...... ................................................. 47
CCP1CON ......................................................................... 15
CCP1CON Regis te r ..... .......... ........... .......... ..................... .. 47
CCP1M3:CCP1 M0 Bits .................. ..................... ...... 47
CCP1X:CCP1Y Bits ....... ........... .......... ........... .......... .. 47
CCP2CON ......................................................................... 15
CCP2CON Regis te r ..... .......... ........... .......... ..................... .. 47
CCP2M3:CCP2 M0 Bits .................. ..................... ...... 47
CCP2X:CCP2Y Bits ....... ........... .......... ........... .......... .. 47
CCPR1H Register ........................................................ 13, 15
CCPR1L Register .............................................................. 15
CCPR2H Register ........................................................ 13, 15
CCPR2L Register ........................................................ 13, 15
CKE ................................................................................... 54
CKP ................................................................................... 55
Clock Polarity Select bit, CKP ............................................ 55
Code Examples
Loading the SSPBUF register ................................... 58
Code Protection ....................................................... 127, 141
Compare (CCP Module) ......................... .... ......... .. .... .... .... 49
Block Diag ram ........... ........... .......... ........... .......... ...... 49
CCP Pin Configuration .............................................. 49
CCPR1H:CCPR1L Registers .................................... 49
Softwar e In terrupt ......................... ........... .......... ........ 49
Special Event Trigger .......................................... 43, 49
Timer1 Mode Selection . ............................................. 49
Configuration Bits ............................................................ 127
Conversion Considerations .............................................. 187
D
D/A ..................................................................................... 54
Data Memor y ............. .......... ........... .......... ........... .......... .... 11
Bank Select (RP1:RP0 Bits) ................................ 11, 16
General Purpose Registers ....................................... 11
Register File Map ............. .......... ........... .......... .......... 12
Special Function Registers ........................................ 13
Data/Address bit, D/A ........................................................ 54
DC Characteristics
PIC16C73 ................................................................ 152
PIC16C74 ................................................................ 152
Development Support ...................................................... 145
Development Tools .......................................................... 145
Device Differences ........................................................... 187
Direct Add ressing ...... .......... ........... .......... ........... .......... .... 25
PIC16C77X
DS30275A-page 190 Preliminary 1999 Microchip Technology Inc.
E
Errata ...................................................................................4
External Power-on Reset Circuit ......................................132
F
Firmware Instructions .......................................................143
Flowcharts
Acknowledge ..............................................................86
Master Receiver .........................................................83
Master Transmit .........................................................80
Restart Condition ........................................ .. .... .........77
Start Condition .......................................... .... .... .. .......75
Stop Condition ............. .......... ........... .......... ........... ....88
FSR Register ..........................................................1 3, 14, 15
Fuzzy Logic Dev. System (
fuzzy
TECH-MP ) .... .. .... .. ... ...147
G
GCE ...................................................................................56
General Call Address Sequence ........................................69
General Call Address Support ...........................................69
General Call Enable bit, GCE ............................................56
I
I/O Ports ...................... ........... .......... ............... .......... .........27
I2C ...................................................................................... 63
I2C Master Mode Receiver Flowchart ................................83
I2C Master Mode Reception ...............................................82
I2C Master Mode Restart Condition ...................................76
I2C Mode Selection ............................................................63
I2C Module
Acknowledge Flowchart .............................................86
Acknowledge Sequence timing . .................................85
Addressing ................................................................. 64
Baud Rate Generator .................................................73
Block Diag ram .......................... ........... .......... ........... ..71
BRG Block Diagram ...................................................73
BRG Reset due to SDA Collision ...............................92
BRG Timing ...............................................................73
Bus Arbitration ..................... .......... ............... ........... ..90
Bus Collision ..............................................................90
Acknowledge ......................................................90
Restart Condition ...............................................93
Restart Condition Timing (Case1) ......................93
Restart Condition Timing (Case2) ......................93
Start Condition .............................. .... .... .... .. .......91
Start Condition Timing .................................91, 92
Stop Condition ............. .......... ........... .......... .......94
Stop Condition Timing (Case1) ..........................94
Stop Condition Timing (Case2) ..........................94
Transmit Timing ......... .......... ........... .......... .........90
Bus Collision timing ....................................................90
Clock Arbitration .........................................................89
Clock Arbitration Timing (Master Transmit) ................89
Conditions to not give ACK Pulse ..............................64
General Call Address Support ...................................69
Master Mode ..............................................................71
Master Mode 7-bit Reception timing ..........................84
Master Mode Operation .............................................72
Master Mode Start Condition .....................................74
Master Mode Transmission ........................................79
Master Mode Transmit Sequence ..............................72
Master Transmit Flowchart ........................................80
Multi-Master Communication .....................................90
Multi-master Mode .....................................................72
Operation ...................................................................63
Repeat Start Condition timing ....................... .. .. .. .......76
Restart Condition Flowchart ...................................... 77
Slave Mode ....................................... .... .. .... ......... .... .. 64
Slave Reception .... .......... ........... .......... ........... .......... 65
Slave Tra n smissio n ....... ........... .......... ........... .......... ..65
SSPBUF .................................................................... 64
Start Condition Flowchart .......................................... 75
Stop Condition Flowchart .......................... ......... .... .... 88
Stop Condition Receive or Transmit timing ............... 87
Stop Condition timing ...................... .... .. .... ....... .... .... .. 87
Waveforms for 7-bit Reception .................................. 65
Waveforms for 7-bit Transmission ............................. 66
I2C Module Address Register, SSPADD ........................... 64
I2C Slave Mode .................................................................. 64
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ......... 145
ID Locations ............................................................. 127, 141
In-Circuit Serial Programming (ICSP) ...................... 127, 141
INDF ..................................................................................15
INDF Register ..............................................................13, 14
Indire ct Addressing ............................................................ 25
FSR Register ............................................................. 11
Instru ction Format ............................................................ 143
Instru ction Set .................................................................. 143
Summary Ta b l e ......... .......... ........... .......... ........... .... 144
INTCON ............................................................................. 15
INTCON Register ............................................................... 18
GIE Bi t ...... ............... .............. ............... ............... ...... 18
INTE Bit ................... .......... ............... ............... .......... 18
INTF Bit ............... .......... ........... .......... ........... ............ 18
PEIE Bi t ...... ............... .......... ........... ............... .......... ..18
RBIE Bit ..................................................................... 18
RBIF Bit ............................................................... 18, 30
T0IE Bi t ..... ........... .......... ............... .......... ............... .... 18
T0IF Bit ................ .......... ........... .......... ........... ............ 18
Inter-Integrated Circuit (I2C) .............................................. 53
internal sampling switch (Rss) impedence ...................... 123
Interrupt Sources ..................................................... 127, 137
Block Diagram ......................................................... 137
Capture C omplete (CCP) ........................................... 48
Compare Complete (CCP) ......................................... 49
Interrupt on Change (RB7:RB4 ) ............................... 30
RB0/INT Pin, External ...................................... 7, 8, 138
TMR0 Overflow .................................................. 40, 138
TMR1 Overflow ....................................................41, 43
TMR2 to PR2 Match .................................................. 46
TMR2 to PR2 Match (PWM) ................................ 45, 50
USART Receive/Transmit Complete ......................... 97
Interrupts, Co ntext Saving During .................................... 138
Interrupts, Enable Bits
A/D Converter Enable (ADIE Bit) ............................... 19
CCP1 Enable (CCP1IE Bit) .................... .. .. ....... .. 19, 48
CCP2 Enable (CCP2IE Bit) .................... .. .. ....... .. .. .. .. 21
Global Interrupt Enable (GIE Bit) . ...................... 18, 137
Interrupt on Change (RB7:RB4) Enable
(RBIE Bit) ........................................................... 18, 138
Peripheral Interrupt Enable (PEIE Bit) . ...................... 18
PSP Read/Write Enable (PSPIE Bit) .......... ........... .... 19
RB0/INT Enable (INTE Bit) ........................................ 18
SSP Enable (SSPIE Bit) ............................................ 19
TMR0 Overflow Enable (T0IE Bit) ............................. 18
TMR1 Overflow Enable (TMR1IE Bit) ........................ 19
TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19
USART Receive Enable (RCIE Bit) ....................... .. .. 19
USART Transmit Enable (TXIE Bit) ........................... 19
PIC16C77X
1999 Microchip Technology Inc. Preliminary DS30275A-page 191
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) ...................................20
CCP1 Flag (CCP1IF Bit) ................................20, 48, 49
CCP2 Flag (CCP2IF Bit) ............................................22
Interrupt on Change (RB7:RB4) Flag
(RBIF Bit) .....................................................18, 30, 138
PSP Read/Write Flag (PSPIF Bit) ..............................20
RB0/INT Flag (INTF Bit) .............................................18
SSP Flag (SSPIF Bit) .................................................20
TMR0 Overflow Flag (T0IF Bit) ..........................18, 138
TMR1 Overflow Flag (TMR1IF Bit) ............................20
TMR2 to PR2 Match Flag (TMR2IF Bit) .....................20
USART Receive Flag (RCIF Bit) ................................20
USART Transmit Flag (TXIE Bit) ...............................20
K
KeeLoq Evaluation and Programming Tools . ................148
M
Master Clear (MCLR) .......................................................7, 8
MCLR Reset, Normal Operation ..............131, 133, 134
MCLR Reset, SLEEP ...............................131, 133, 134
Memory Organization
Data Memor y ....... .......... ........... .......... ........... .......... ..11
Program Memory .......................................................11
MPLAB Integrated Development Environment Software .147
Multi-Master Communication .............................................90
Multi-Master Mode .............................................................72
O
OPCODE Field Descriptions ............................................143
OPTION_R EG Re g i ster ....... .......... ........... .......... ........... ....17
INTEDG Bi t . ........... .......... ........... .......... ........... ..........17
PS2:PS0 Bits .......................................................17, 39
PSA Bit .................................................................17, 39
RBPU Bit .............. .......... ........... .......... ........... .......... ..17
T0CS Bit ...............................................................17, 39
T0SE Bit ...............................................................17, 39
OSC1/CLKIN Pin .............................................................7, 8
OSC2/CLKOUT Pin .........................................................7, 8
Oscillator Configuration ....................................................128
HS .................................................................... 128, 133
LP .....................................................................128, 133
RC ............................................................128, 130, 133
XT ....................................................................128, 133
Oscillato r, Timer1 .........................................................41, 43
Oscillat o r, WDT ............................................... .................139
P
P .........................................................................................54
Packaging ........................................................................175
Paging, Program Memory ............................................11, 24
Parallel Slave Port (PSP ) .........................................9, 34, 37
Block Diag ram ........ .......... ........... .......... ........... ..........37
RE0/RD/AN5 Pin ..............................................9, 36, 37
RE1/WR/AN6 Pin .............................................9, 36, 37
RE2/CS/AN7 Pin ..............................................9, 36, 37
Read Waveforms .......................................................38
Read/Write Enable (PSPIE Bit) ..................................19
Read/Write Flag (PSPIF Bit) ......................................20
Select (PSPMODE Bit) ..................................3 4, 35, 37
Write Waveforms .......................................................37
PCL Register ................................................................13, 14
PCLATH Register ..................................................13, 14, 15
PCON Register .......................................................... 23, 133
BOR Bit ...................................................................... 23
POR Bit ...................................................................... 23
PICDEM-1 Low-Cost PICmicro Demo Board .................. 146
PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 146
PICDEM-3 Low-Cost PIC16CXXX Demo Board ............. 146
PICSTART Plus Entry Level Development System ...... 145
PIE1 Register .................................................................... 19
ADIE Bit ..................................................................... 19
CCP1IE Bit ........ .......... ........... .......... ............... .......... 19
PSPIE Bit ................................................................... 19
RCIE Bit ..................................................................... 19
SSPIE Bit ................................................................... 19
TMR1IE Bit ................................................................ 19
TMR2IE Bit ................................................................ 19
TXIE Bit ..................................................................... 19
PIE2 Register .................................................................... 21
CCP2IE Bit ........ .......... ........... .......... ............... .......... 21
Pinout Descriptions
PIC16C63A/PIC16C73B .............................................. 7
PIC16C65B/PIC16C74B .............................................. 8
PIR1 Register .................................................................... 20
ADIF Bi t .... ........... ............... .......... ........... .............. .... 20
CCP1IF Bit ................. ........... .............. ........... .......... .. 20
PSPIF Bit ................................................................... 20
RCIF Bit ..................................................................... 20
SSPIF Bit ................................................................... 20
TMR1IF Bit ................................................................ 20
TMR2IF Bit ................................................................ 20
TXIF Bit ...................................................................... 20
PIR2 Register .................................................................... 22
CCP2IF Bit ................. ........... .............. ........... .......... .. 22
Pointer, FSR ...................................................................... 25
POR.
See
Power-on Reset
PORTA ...................................................................... 7, 8, 15
Analog Port Pins ...................................................... 7, 8
Initialization ................................................................ 27
PORTA Register ........................................................ 27
RA3:RA0 and RA5 Port Pins ..................................... 28
RA4/T0CKI Pin .................................................. 7, 8, 28
RA5/SS/AN4 Pin .......................................................... 8
TRISA Register .......................................................... 27
PORTA Register ........................................................ 13, 126
PORTB ...................................................................... 7, 8, 15
Initialization ................................................................ 29
PORTB Register ........................................................ 29
Pull-up Enable (RBPU Bit) ......................................... 17
RB0/INT Edge Select (INTEDG Bit) .......................... 17
RB0/INT Pin, External ..................................... 7, 8, 138
RB3:RB0 Port Pins .................................................... 29
RB7:RB4 Interrupt on Change ....................... .... .. .. .. 138
RB7:RB4 Interrupt on Change Enable (RBIE Bit) .... 18,
138
RB7:RB4 Interrupt on Change Flag (RBIF Bit) ... 18, 30,
138
RB7:RB4 Port Pins .................................................... 30
TRISB Register .......................................................... 29
PORTB Register ........................................................ 13, 126
PORTC ...................................................................... 7, 9, 15
Block Diag ram ........... ........... .......... ........... .......... ...... 32
Initialization ................................................................ 32
PORTC Register ........................................................ 32
RC0/T1OSO/T1CKI Pin ........................................... 7, 9
RC1/T1OSI/CCP2 Pin ............................................. 7, 9
RC2/CCP1 Pin ......................................................... 7, 9
RC3/SCK/SCL Pin ................................................... 7, 9
PIC16C77X
DS30275A-page 192 Preliminary 1999 Microchip Technology Inc.
RC4/SDI/SDA Pin ....................................................7, 9
RC5/SDO Pin ...........................................................7, 9
RC6/TX/CK Pin ..................................................7, 9, 98
RC7/RX/DT Pin ............................................7, 9, 98, 99
TRISC Register ....................................................32, 97
PORTC Register ................................................................13
PORTD .....................................................................9, 15, 37
Block Diag ram .......................... ........... .......... ........... ..34
Parallel Slave Port (PSP ) Function ............................34
PORTD Register ........................................................34
TRISD Regist e r ................ ..................... .......... ...........34
PORTD Register ................................................................13
PORTE ...........................................................................9, 15
Analog Port Pins ..............................................9, 36, 37
Block Diag ram .......................... ........... .......... ........... ..35
Input Buffer Full Status (IBF Bit) ................................35
Input Buffer Overflow (IBOV Bit) ................................35
Output Buffer Full Status (OBF Bit) ............................35
PORTE Register ........................................................35
PSP Mode Select (PSPM ODE Bit) .. ..............34, 35, 37
RE0/RD/AN5 Pin ..............................................9, 36, 37
RE1/WR/AN6 Pin .............................................9, 36, 37
RE2/CS/AN7 Pin ..............................................9, 36, 37
TRISE Register ..........................................................35
PORTE Register ........................................................13, 126
Postscaler, Timer2
Select (TOUTPS3:TOUTPS0 Bit s ) ............... ........... ..45
Postscaler, WDT ................................................................39
Assignment (PSA Bit) ..........................................17, 39
Block Diag ram .......................... ........... .......... ........... ..40
Rate Select (PS2:PS0 Bits) .................................17, 39
Switching Between Timer0 and WDT ........................40
Power-on Reset (POR) ....................127, 131, 132, 133, 134
Oscillator Start-up Timer (OST) .......................127, 132
POR Status (PO R Bit) ................ ........... .......... ...........23
Power Control (PCON) Register ..............................133
Power-down (PD Bit) .................................................16
Power-on R eset Circuit, External .............................132
Power-up Timer (PWRT) ............. ......... .... .... ...127, 132
Time-out (TO Bit) ...... ........... .......... ........... .......... .......16
Time-out Sequence ........................ ....... .. .... .... .. .......133
Time-out Sequence on Power-up ....................135, 136
PR2 Register ......................................................................14
Presca le r, Capture .. .......... ........... .......... ..................... .......48
Presca le r, Timer0 ........................... ........... .......... ........... ....39
Assignment (PSA Bit) ..........................................17, 39
Block Diag ram .......................... ........... .......... ........... ..40
Rate Select (PS2:PS0 Bits) .................................17, 39
Switching Between Timer0 and WDT ........................40
Presca le r, Timer1 ........................... ........... .......... ........... ....42
Select (T1CKPS1:T1CKPS0 Bits) ....... .......... ........... ..41
Presca le r, Timer2 ........................... ........... .......... ........... ....50
Select (T2CKPS1:T2CKPS0 Bits) ....... .......... ........... ..45
PRO MA TE II Universal Programmer ............................145
Product Identification System ...........................................199
Program Counter
PCL Register ..............................................................24
PCLATH Register ..............................................24, 138
Reset Conditions .............. ..................... .......... .........133
Program Memory ...............................................................11
Inter rupt Vector ....... ........... ............... .......... ...............11
Paging ..................................................................11, 24
Program Memory Map ...............................................11
Reset Vec to r ............. ........... .......... ............... ........... ..11
Program Verification .........................................................141
Programm ing Pin (Vpp) ....................................................7, 8
Programming, Device Instructions ................................... 143
PWM (CCP Module) .......................................................... 50
Block Diagram ........................................................... 50
CCPR1H:CCPR1L Registers ..................................... 50
Duty Cycle ...... ..................... ........... .......... ........... ...... 50
Example Frequencies/Resolutions ............................ 51
Output Diagram ................... ............... ........... .......... ..50
Period ........................................................................ 50
Set-Up for PWM Operation ........................................ 51
TMR2 to PR2 Match ............................................ 45, 50
TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19
TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 20
Q
Q-Clock ..............................................................................50
R
R/W .................................................................................... 54
R/W bit ............................................................................... 64
R/W bit ............................................................................... 65
RCE,Receive Enable bit, RCE .............. .. .. .... .. .. .. ..... .. .... .. .. 56
RCREG ..............................................................................15
RCSTA Register .......................................................... 15, 98
CREN Bit ........................... ............... .......... ........... .... 98
FERR Bit .................................................................... 98
OERR Bit ................................................................... 98
RX9 Bit ......................................................................98
RX9D Bit .......................... ........... .............. ........... ...... 98
SPEN Bit .............................................................. 97, 98
SREN Bit ............... .......... ........... .......... ............... ...... 98
Read/Write bit, R/W ...........................................................54
Receive Overflow Indicator bit, SS POV ............................. 55
Register File ........................... ........... .......... ........... .......... .. 11
Register File Map ................. ..................... .......... ........... .... 12
Registers
FSR Summary ........................................................... 15
INDFSummary ........................................................... 15
INTCON
Summary ........................................................... 15
PCL Summary ........................................................... 15
PCLATH
Summary ........................................................... 15
PORTB
Summary ........................................................... 15
SSPSTAT .................................................................. 54
STATUS
Summary ........................................................... 15
Summary ................................................................... 13
TMR0
Summary ........................................................... 15
TRISB
Summary ........................................................... 15
Reset ....................................................................... 127, 131
Block Diagram ......................................................... 131
Reset Conditions for All Registers . .......................... 134
Reset Conditions for PCON Register ...................... 133
Reset Conditions for Program Counter .................... 133
Reset Conditions for STATUS Register ................... 133
Restart Condition Enabled bit, RSE ................................... 56
Revision History ............................................................... 187
RSE ................................................................................... 56
PIC16C77X
1999 Microchip Technology Inc. Preliminary DS30275A-page 193
S
SAE ....................................................................................56
SCK ....................................................................................57
SCL .................................................................................... 64
SDA ....................................................................................64
SDI ..................................................................................... 57
SDO ...................................................................................57
SEEVAL Evaluation and Programming System . ...........147
Serial Clock, SCK ..............................................................57
Serial Clock, SCL ...............................................................64
Serial Data Address, SDA ..................................................64
Serial Data In, SDI .............................................................57
Serial Data Out, SDO .........................................................57
Slave Select Synchronization ............................................60
Slave Select, SS ................................................................ 57
SLEEP .............................................................127, 131, 140
SMP ...................................................................................54
Softwa re Simulator (MPLAB-SIM) ...... .......... ........... ........147
SPBRG Register ................................................................14
SPE ....................................................................................56
Special Features of the CPU ...........................................127
Special Function Registers ................................................13
PIC16C73 ..................................................................13
PIC16C73A ................................................................ 13
PIC16C74 ..................................................................13
PIC16C74A ................................................................ 13
PIC16C76 ..................................................................13
PIC16C77 ..................................................................13
Speed, Operating ............. .. .. .... .. .. ....... .. .... .. .. .... .. ....... .. .. .... ..1
SPI Master Mode ..............................................................59
Serial Clock ................................................................57
Serial Data In .............................................................57
Serial Data Out ..........................................................57
Serial Peripheral Interface (SPI) ................................53
Slave Select ...............................................................57
SPI clock ....................................................................59
SPI Mode ...................................................................57
SPI Clock Edge Select, CKE .............................................54
SPI Data Input Sample Phase Select, SM P ......................54
SPI Master/Slave Connection . ...........................................58
SPI Module
Master/Slave Connection .................... .... .. .. ....... .... .. ..58
Slave Mode ................................................................60
Slave Select Synchronization ....................................60
Slave Synch Timnig ...................................................60
SS ......................................................................................57
SSP ....................................................................................53
Block Diagram (SPI Mode) ................................ ...... ..57
Enable (SSPIE Bit) .....................................................19
Flag (S SPIF Bit) .........................................................20
RA5/SS/AN4 Pin ...... .......... ........... .......... ........... ..........8
RC3/SCK/SCL Pin ...................................................7, 9
RC4/SDI/SDA Pin ....................................................7, 9
RC5/SDO Pin ...........................................................7, 9
SPI Mode ...................................................................57
SSPADD .................................................................... 64
SSPBUF ...............................................................59, 64
SSPCON1 ..................................................................55
SSPCON2 ..................................................................56
SSPSR .................................................................59, 64
SSPSTAT .............................................................54, 64
TMR2 Output for Clock Shift ................................45, 46
SSP I2C
SSP I2C Operation ............................ .......... ........... ....63
SSP Module
SPI Master Mode ....................................................... 59
SPI Master./Slave Connection ................................... 58
SPI Slave Mode ......................................................... 60
SSPCON1 Register ................................................... 63
SSP Overflow Detect bit, SSPOV ...................................... 64
SSPADD Regis ter .............................................................. 14
SSPBUF ...................................................................... 15, 64
SSPBUF Register .............................................................. 13
SSPCON Register ............................................................. 13
SSPCON1 ................................................................... 55, 63
SSPCON2 ......................................................................... 56
SSPEN .............................................................................. 55
SSPIF ................................................................................ 65
SSPM3:SSPM0 ................................................................. 55
SSPOV .................................................................. 55, 64, 82
SSPSTAT .................................................................... 54, 64
SSPSTAT Register ............................................................ 14
Stack .................................................................................. 24
Start bit (S) ........................................................................ 54
Start Condition Enabled bit, SAE ....................................... 56
STATUS Register ...................................................... 16, 138
C Bit ........................................................................... 16
DC Bit ........................................................................ 16
IRP Bit ......................... ............... ........... .......... .......... 16
PD Bit ........................................................................ 16
RP1:RP0 Bits ....... .......... ........... .......... ........... .......... .. 16
TO Bit ........................................................................ 16
Z Bit ........................... ........... .......... ............... .......... .. 16
Stop bit (P ) ................. .......... ........... .......... ........... .............. 54
Stop Condition Enable bit ........................... ....... .. .... .. .... .. .. 56
Synchronous Serial Port .................................................... 53
Synchronous Serial Port Enable bit, SSPEN ..................... 55
Synchronous Serial Port Mode Select bits,
SSPM3:SSPM0 ................................................................. 55
T
T1CON .............................................................................. 15
T1CON Register .......................................................... 15, 41
T1CKPS1:T1CKPS0 Bits ....................... .......... .......... 41
T1OSCEN Bi t ......................... .......... ............... .......... 41
T1SYNC Bit ... .......... ............... .......... ............... .......... 41
TMR1CS Bit ............... ........... .......... ........... .......... ...... 41
TMR1ON Bit .............................................................. 41
T2CON Register .......................................................... 15, 45
T2CKPS1:T2CKPS0 Bits ....................... .......... .......... 45
TMR2ON Bit .............................................................. 45
TOUTPS3:TOUTPS0 Bits ......................................... 45
Timer0 ............................................................................... 39
Block Diag ram ........... ........... .......... ........... .......... ...... 39
Clock Source Edge Select (T0SE Bit) ................. 17, 39
Clock Source Select (T 0CS Bit) .......................... 17, 39
Overflow Enable (T0IE Bit) ......... .... ............. ...... ...... .. 18
Overflow Flag ( T0IF Bit) .................................... 18, 138
Overflow Interrupt .............................................. 40, 138
RA4/T0CKI Pin, External Clock ............................... 7, 8
Timer1 ............................................................................... 41
Block Diag ram ........... ........... .......... ........... .......... ...... 42
Capacitor Selection ................................................... 43
Clock Source Select (TMR1CS Bit) ........................... 41
External Clock Input Sync (T1SYNC Bit) .. .. ...... .. ...... . 41
Module On/Off (TMR1ON Bit) ................................... 41
Oscillator .............................................................. 41, 43
Oscillato r Enabl e (T1OSCEN Bit) ..... ......................... 41
Overflow Enable (TMR1IE Bit) .................................. 19
Overflow Flag ( TMR1IF Bit) ....................................... 20
PIC16C77X
DS30275A-page 194 Preliminary 1999 Microchip Technology Inc.
Overflo w Interrupt ................................................41, 43
RC0/T1OSO/T1CKI Pin ...........................................7, 9
RC1/T1OSI/CCP2 Pin ..............................................7, 9
Special Event Trigger (CCP) ................................43, 49
T1CON Regis ter ..... ........... .......... ........... ...................41
TMR1H Register ........................................................41
TMR1L Register .........................................................41
Timer2
Block Diag ram .......................... ........... .......... ........... ..46
PR2 Register ........................................................45, 50
SSP Clock Shift ....................................................45, 46
T2CON Regis ter ..... ........... .......... ........... ...................45
TMR2 Register ...........................................................45
TMR2 to PR2 Match Enable (TMR2IE Bit) ................19
TMR2 to PR2 Match Flag (TMR2IF Bit) .....................20
TMR2 to PR2 Match Interrupt ........................45, 46, 50
Timing Diagrams
Acknowledge Sequence Timing .................................85
Baud Rate Generator with Clock Arbitration ..............73
BRG Reset Due to SDA Collision ..............................92
Brown-out Reset ......................................................163
Bus Collision
Start Condition Timing .......................................91
Bus Collision During a Restart Condition (Case 1) ....93
Bus Collision During a Restart Condition (Case2) .....93
Bus Collision During a Start Condition (SCL = 0) ......92
Bus Collision During a Stop Condition ................ .......94
Bus Collision for Transmit and Acknowledge ........... ..90
Capture/Compare/PWM ...........................................169
CLKOUT and I/O ......................................................162
External Clock Timing ..............................................161
I2C Master Mode First Start bit timing ........................74
I2C Master Mode Reception timing . . ..........................84
I2C Master Mode Transmission timing .......................81
Master Mode Transmit Clock Arbitration ....................89
Power-up Timer ...... ........... .......... ........... .................163
Repeat Start Condition ............. .. .... ..... .. .. .... .. .. .. .. .......76
Reset ........................................................................163
Slave Synchronization ...............................................60
Start- u p Timer ....... ........... .......... ........... .......... .........163
Stop Condition Receive or Transmit ..........................87
Time-out Sequence on Power-up ....................135, 136
Timer0 ...................................................................... 168
Timer1 ...................................................................... 168
USART Asynch ronous Mas ter Transm ission ...........103
USART Synchronous Receive .................................171
USART Synchronous Reception ..............................109
USART Synchronous Tran smiss ion ................108, 171
USART, Asynchronous Reception ... ........................105
Wake-up from SLEEP via Interrupt ..........................141
Watchdog Timer ................... .... .. .... ..... .... .. .... .. .. .......163
TMR0 .................................................................................15
TMR0 Register ...................................................................13
TMR1H ...............................................................................15
TMR1H Register ................................................................13
TMR1L ...............................................................................15
TMR1L Register .................................................................13
TMR2 .................................................................................15
TMR2 Register ...................................................................13
TRISA Register ..........................................................14, 126
TRISB Register ..........................................................14, 126
TRISC Regist e r ... .......... ..................... ........... .......... ...........14
TRISD Regist e r ... .......... ..................... ........... .......... ...........14
TRISE Register ....................................................14, 35, 126
IBF Bit ........................................................................35
IBOV Bit .....................................................................35
OBF Bit .......................... .............. ........... .......... .........35
PSPMODE Bit ................................................ 34, 35, 37
TXREG .............................................................................. 15
TXSTA Register ................................................................. 97
BRGH Bit ............................................................. 97, 99
CSRC Bit ................. .......... ........... .......... ........... ........ 97
SYNC Bit ...... ........... .......... ........... .......... ................... 97
TRMT Bit .................................................................... 97
TX9 Bit ....................................................................... 97
TX9D Bit .................................................................... 97
TXEN Bit ...... .......... .......... ........... .............. ............... .. 97
U
UA ...................................................................................... 54
Universal Synchronous Asynchronous Receiver Transmitter
(USART)
Asynchronous Receiver
Setting Up Reception ....................................... 104
Timing Dia g ram ........... ........... .......... ........... .... 105
Update Address, UA ..................................... .... .. ......... .... .. 54
USART ............................................................................... 97
Asynchronous Mode ................................................ 102
Master Transmission ....................................... 103
Receive Block Diagram ................................... 105
Transmit Block Diagram .................................. 102
Baud Rate Generator (BRG) ..................................... 99
Baud Rate Error, Calculating ............................. 99
Baud Rate Formula ........................................... 99
Baud Rates, Asynchronous Mode (B RG H=0) . 100
Baud Rates, Asynchronous Mode (B RG H=1) . 101
Baud Rates, Synchronous Mode ..................... 100
High Baud Rate Select (BRGH Bit) ............. 97, 99
Sampling ............................................................ 99
Clock Source Select (CSRC Bit) ................................ 97
Continuous Receive Enable (CREN Bit) .................... 98
Framing Error (FERR Bit) .......................................... 98
Mode Select (SYNC Bit) ............................................ 97
Overrun Error (OERR Bit) .......................................... 98
RC6/TX/CK Pin ........................................................ 7, 9
RC7/RX/DT Pin ........................................................ 7, 9
RCSTA Regist e r ....................... .......... ........... .......... .. 98
Receive Data, 9th bit (RX9D Bit) ............................... 98
Receive Enable (RCIE Bit) ........................................ 19
Receive Enable, 9-bit (RX9 Bit) . ................................ 98
Receive Flag ( R CI F Bit) ............ .......... ..................... .. 20
Serial Port Enable (SPEN Bit) ............................. 97, 98
Single Receive Enable (SREN Bit) ............................ 98
Synchronous Master Mode ...................................... 107
Reception ........................................................ 109
Transmission ................................................... 108
Synchronous Slave Mode ......................... ......... .... .. 110
Transmit Data, 9th Bit (TX9D) ................................... 97
Transmit Enable (TXEN Bit) ...................................... 97
Transmit Enable (TXIE Bit) ................................ .. .... ..19
Transmit Enable, Nine-bit (TX9 Bit) . .......................... 97
Transmit Flag (TXIE Bit) ............................................ 20
Transmit Shift Register Status (TRMT Bit) ................ 97
TXSTA Register ......................................................... 97
PIC16C77X
1999 Microchip Technology Inc. Preliminary DS30275A-page 195
W
W Register .......................................................................138
Wake-up from SLEEP ..............................................127, 140
Interrupts ..........................................................133, 134
MCLR Reset .................. ........... .......... ........... ..........134
Timing Dia g r a m ......................... .......... ........... ..........141
WDT Reset ................ .......... ........... .......... ........... ....134
Watchdog Timer (WDT) ............................ .... .... .......127, 139
Block Diag ram ........ .......... ........... .......... ........... ........139
Enable (WDTE Bit) ...................................................139
Programming Considerations ..................................139
RC Oscillator ............................................................139
Time-o u t Pe riod ..................... ............... ........... ........139
WDT Reset, Normal Operation ................131, 133, 134
WDT Reset, SLEEP . .. ........ ............... ...... .........133, 134
Waveform for General Call Address Seque nce .................69
WCOL ..................................................55, 74, 79, 82, 85, 87
WCOL Status Flag .............................................................74
Write Collision Detect bit, WC OL .......................................55
WWW, On-Line Support ......................................................4
PIC16C77X
DS30275A-page 196 Preliminary 1999 Microchip Technology Inc.
BIT/REGISTER CROSS-REFERENCE
LIST
ADCS1:ADCS0 ..................................ADCON0<7:6>
ADIE ...................................................PIE1<6>
ADIF ...................................................PIR1<6>
ADON .................................................ADCON0<0>
BF .......................................................SSPSTAT<0>
BOR ...................................................PCON<0>
BRGH .................................................TXSTA<2>
C .........................................................STATUS<0>
CCP1IE ..............................................PIE1<2>
CCP1IF ..............................................PIR1<2>
CCP1M3:CCP1M0 .............................CCP1CON<3:0>
CCP1X:CCP1Y ..................................CCP1CON<5:4>
CCP2IE ..............................................PIE2<0>
CCP2IF ..............................................PIR2<0>
CCP2M3:CCP2M0 .............................CCP2CON<3:0>
CCP2X:CCP2Y ..................................CCP2CON<5:4>
CHS2:CHS0 .......................................ADCON0<5:3>
CKE ....................................................SSPSTAT<6>
CKP ....................................................SSPCON<4>
CREN .................................................RCSTA<4>
CSRC .................................................TXSTA<7>
D/A .....................................................SSPSTAT<5>
DC ......................................................STATUS<1>
FERR .................................................RCSTA<2>
GIE .....................................................INTCON<7>
GO/DONE ..........................................ADCON0<2>
IBF ......................................................TRISE<7>
IBOV ...................................................TRISE<5>
INTE ...................................................INTCON<4>
INTEDG ..............................................OPTION_REG<6>
INTF ...................................................INTCON<1>
IRP .....................................................STATUS<7>
OBF ....................................................TRISE<6>
OERR .................................................RCSTA<1>
P .........................................................SSPSTAT<4>
PCFG2:PCFG0 ..................................ADCON1<2:0>
PD ......................................................STATUS<3>
PEIE ...................................................INTCON<6>
POR ...................................................PCON<1>
PS2:PS0 .............................................OPTION_REG<2:0>
PSA ....................................................OPTION_REG<3>
PSPIE .................................................PIE1<7>
PSPIF .................................................PIR1<7>
PSPMODE .........................................TRISE<4>
R/W ....................................................SSPSTAT<2>
RBIE ...................................................INTCON<3>
RBIF ...................................................INTCON<0>
RBPU .................................................OPTION_REG<7>
RCIE .... ............................................... PIE1<5>
RCIF ...................................................PIR1<5>
RP1:RP0 ............................................STATUS<6:5>
RX9 ....................................................RCSTA<6>
RX9D ..................................................RCSTA<0>
S .........................................................SSPSTAT<3>
SMP ...................................................SSPSTAT<7>
SPEN .................................................RCSTA<7>
SREN .................................................RCSTA<5>
SSPEN ...............................................SSPCON<5>
SSPIE .................................................PIE1<3>
SSPIF .................................................PIR1<3>
SSPM3:SSPM0 ..................................SSPCON<3:0>
SSPOV ...............................................SSPCON<6>
SYNC .................................................TXSTA<4>
T0CS ..................................................OPTION_REG<5>
T0IE ...................................................INTCON<5>
T0IF ...................................................INTCON<2>
T0SE ..................................................OPTION_REG<4>
T1CKPS1:T1CKPS0 ..........................T1CON<5:4>
T1OSCEN .......................................... T1CON<3>
T1SYNC .............................................T 1CON<2>
T2CKPS1:T2CKPS0 ..........................T2CON<1:0>
TMR1CS ............................................ T1CON<1>
TMR1IE ..............................................PIE1<0>
TMR1IF .............................................. PIR1<0>
TMR1ON ............................................T1CON<0>
TMR2IE ..............................................PIE1<1>
TMR2IF .............................................. PIR1<1>
TMR2ON ............................................T2CON<2>
TO ...................................................... STATUS<4>
TOUTPS3:TOUTPS0 ......................... T2CON<6:3>
TRMT ................................................. TXSTA<1>
TX9 ....................................................TXSTA<6>
TX9D ..................................................TXSTA <0>
TXEN .................................................TXSTA<5>
TXIE ................................................... PIE1<4>
TXIF ................................................... PIR1<4>
UA ...................................................... SSPSTAT<1>
WCOL ................................................SSPCON<7>
Z .........................................................STATUS<2>
1998 Microchip Technology Inc. DS30275A-page 197
PIC16C77X
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides infor mation on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the wor ld.
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTA RT, PICMASTER and PRO MATE are registered
trademarks of Microchip Technology Incor porated in the
U.S.A. and other countries.
Flex
ROM, MPLAB and
fuzzy-
LAB are trademarks and SQTP is a service mark of Micro-
chip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World W ide Web (WWW) si te.
The we b site is used b y Mic rochi p as a mean s to mak e
files and information easily available to customers. To
vie w the site , the user must ha v e access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
•Device Errata
• Job Postings
• Mi crochip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
981103
PIC16C77X
DS30275A-page 198 1998 Microchip Technology Inc.
READER RESPONSE
It is our i ntention to pro vi de you with the bes t d ocu me ntation possible to ensure suc ce ss ful us e of your Microc hi p pro d-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
1. Wha t are the be st fe atures of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to fo llow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
To: Technical Publications Manager
RE: Reader Response Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _______ __ - _____ ____
DS30275A
PIC16C77X
PIC16C77X
1999 Microchip Technology Inc. Advance Information DS30275A-page 199
PIC16C77X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factor y or the listed sales office.
* JW Dev ices are UV erasable and can be programmed to any device configuration. JW Dev ices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
PART NO. -XX X/XX XXX
PatternPackageTemperature
Range
Frequency
Range
Device
Device PIC16C77X(1), PIC16C77XT(2);VDD range 4.0V to 5.5V
PIC16LC77X(1), PIC16LC77XT(2);VDD range 2.5V to 5.5V
Frequency Range 04 = 4 MHz
20 = 20 MHz
Temperature Range b(3) = 0°C to 70°C (Commercial)
I= -40°C to +85°C (Industrial)
Pac kage JW = Windowed CERDIP/Ceramic
PQ = MQFP (Met ric PQFP)
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Ski n ny plastic dip
P=PDIP
L=PLCC
SS = SSOP
Pattern QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
g) PIC16C774 -04/P 301 = Commercial temp.,
PDI P pa ckage , 4 MH z, no rm al V DD limits, QTP
pattern #301.
h) PIC16LC773 - 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
i) PIC16C774 - 20I/P = Industrial temp., PDIP
package, 20MHz, normal VDD limits.
Note 1: C = CMOS
LC = Low Power CMOS
T = in tape and reel - SOIC, SSOP,
PLCC,
MQFP, TQFP packages only.
2: b= blank
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a par ticular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.m icrochip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Inco rporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or oth er intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorpora ted in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Note the following details of the code protection feature on PICmicro® MCUs.
•The PICmicro family meets the specifications contained in the Microchip Data Sheet.
•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in t he data sheet.
The person doing so may be engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter , please contact the local sales office nearest to you.
2002 Microchip Technology Inc.
M
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://ww w.microchip .com
Rocky Mountain
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Atlanta
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 -6 40- 003 4 Fax: 770- 640 -03 07
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978 -6 92- 384 8 Fax: 978- 692 -38 21
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 7500 1
Tel: 972 -8 18- 742 3 Fax: 972- 818 -29 24
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Los A n ge les
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949 -2 63- 188 8 Fax: 949- 263 -13 38
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631 -2 73- 530 5 Fax: 631- 273 -53 35
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 -4 36- 795 0 Fax: 408- 436 -79 55
Toronto
6285 Northam Drive, Suite 108
Mississ aug a, Ontario L4V 1X5, C ana da
Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 212 1, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
China - Be ijing
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wa n Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
China - Chengdu
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Cheng du 610 016 , Chi na
Tel: 86-28-6766200 Fax: 86-28-6766599
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd. , Fuzhou Liaison Of fice
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East Internationa l Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 1315, 13/F, Shenzhen Kerry Centre,
Renminnan Lu
Shenzhen 518001, China
Tel: 86-755-2350361 Fax: 86-755-2366086
Hong Kong
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
India
Microchip Technology Inc.
India Liaiso n Office
Divyasree Chambers
1 Floor , Wing A (A3 /A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Microchip Technology Japan K.K.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Microc hip Technolo gy Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Ko re a 135- 88 2
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Midd le Ro ad
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fa x: 65-334-8850
Taiwan
Microc hip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Microc hip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Et age
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Microc hip Technology Gmb H
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Microc hip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berksh ire, E ngla nd RG 41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02
WORLDWIDE SALES AND SERVICE
