HD 74 LS 77 oe-ricsisiavie tarches The HD74LS77 is ideally suited for use as temporary storage for binary information between processing units and input/ output or indicator units. Information present at a data(D) input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low the informa- tion (that was present at the data input at the time the transi- tion occurred) is retained at the Q output until the enable is permitted to go high. BLOCK DIAGRAM DATA To ober latch ENABLE MRECOMMENDED OPERATING CONDITIONS [~~ __d P Q MPIN ARRANGEMENT 1 lafig [ia] 29 Lz) sy DP] GND 10] NC BE ra] (Top View) M@FUNCTION TABLE xmypryo xX Output Q L H Qo Inputs Notes) H; high level, L; low level, X; irrelevant Q, i level of Q before the indicated steady-state input condi- Item Symbol | min typ | max | Unit tions were established. Pulse width te 20 - - ns Setup time bw 20 - - ns Hold time tr 5 - - ns MELECTRICAL CHARACTERISTICS ( Tae=20~+75C) Item Symbol Test Conditions min typ* max Unit Vin 2.0 - - v Input voltage Vit - - 0.8 Vv Vou Vec=4.75V, Vin=2V, Vit=0.8V, lon= 400KA 2.7 - _ Vv Output voltage Vec=4.75V, Vin=2V, foc =4mA - - 0.4 y OL Vit=0.8V foc=8mA - - 0.5 p I Vec=5.28V, Wi=2.7V = et uA 1 co=5.25V, Vi=2. G - [| - ao] * D - - 0.4 Input current tit Vec=5.25V, Vi=0.4V mA G - - -1.6 D - > 0.1 i Vec=5.25V, Vi=7V mA G - - 0.4 Short-circuit output current los Vec=5.25V 20 - 100 | mA Supply current e Icc Vec=5.25V - 6.9 13} mA Input clamp voltage Vix Vec=4.75V. in=18mA - - -1.5 Vv * Voc#5V, Ta=25C ** Icc is measured with all outputs open and all inputs grounded. 70 @ HITACHI Hitachi America Ltd. 2210 O Toole Ave. San Jose, CA 95131 (408) 435-8300 HD74LS77 MSWITCHING CHARACTERISTICS (Vcc=5V, Ta=25C ) Item Symbol Input Output Test Conditions min typ max Unit t - 11 19 PLH D Q ion di . tPHL C.=15pF - 9 W ns Propagation delay time pun C Q Ri=2kO = 10 18 tPHL _ 10 18 MTESTING METHOD 1) Test Circuit Input Vee Outpus PG. Ri. Zeus =500 D Input Q T ae i t Notes)1. Test is put into the each latch 2. All diodes are 182074 . 3. Cz includes probe and jig capacitance. Waveform lus lus tT LH tran 3V 1} 90%, 90%, / 13V 13V4 13V 10% 10% av tow ta bow ta iTLa t THLE - 3V C 90% 90% / \ , 13V 13V y / \ 10% ov te tern Q 1.3V iPLi Notes)1. Input pulse; TL HS! 5ns, t 777, <6ns. 2. When measuring propagation delay times from the D input, the corresponding G input must be held high. @ HITACHI Hitachi America Ltd. * 2210 O'Toole Ave. San Jose, CA 95131 (408) 435-8300 71 HITACHI/ LOGIC/ZARRAYS/MEM eFE D Mm 4496203 0014913 0 PACKAGING INFORMATIONS 7-90-20 Factory orders for circuits described in this databook should include a three-part type number as explained in the follow- ing exampte. BPlastic DIP HD 74LSOO P Lo Package ; Plastic DIP ; letters P Cerdip ; non-letters Circuit description Prefix : HD; Hitachi Digital IC @14 Pin @16 Pin OP-14 OP-16 5.06max 2.54 min TAmax 5.06max ,2.54min 7 Amax Stminta.76) | 0.51 63-4 4 ts he-6.3: meal hy? He ts is pis 3 fs {= 24998 bes 2 3 12 Lets 4 wel 2 3 By i $ a nd go H 4 As z : ef 7 a < si 5 wes | al 5 0 4 6 il | pot pe 4 ? Ww T ? 8 U x $i y 3 7,62: | Ls | F alien o*~ 15" O15 u.ese8 hs @20 Pin @24 Pin OP-20 OP-24 fom 14.6maxa4 5.7max 5 5tmi Prd pd B mn pA . 91min 5 1 24 m ie i. 2 23 g 3 22 4a uw 4 at 3 a G 2a 5 ws 6 ys = - - = 7 a 6 6s 8 71s 4 7 ui 4 16 so 8 ia to 15 2 q 12 Hl rr 3 la ut 2 13 i hase @ HITACHI 11 Hitachi America Ltd. * 2210 O'Toole Ave. * San Jose, CA 95131 (408) 435-8300 HITACHI/ LOGIC/ARRAYS/MEM 29 D mm 44%6203 OOLNI14 2 a T-90-20 PACKAGING INFORMATIONS Bcerdip @14 Pin @16 Pin DG-14 0G-16 4 4 5.06max 2.8max 1 Pid = 3 a DI (2 3 eg < 4 Bus 5 [eto # 6 > 9 e 7 [p 8 = -P 0.20~0.38 4 O~1s" 0.20~0.38 @20 Pin @24 Pin 06-20 ear 5.5tear 28a DG-24 13.24 28min Fiscnia { 0.5 min 1 baa 1 3 4 his a 2 = a jin a ' W d 3 a 3 673 8 3 h KOS i 3 7 u | 9 x B 10 ht | i 1a ta - PoP 3 f=1s.2a I ~/ FH \ 20~93q FIP O'~ 15* ono 2 @ HITACHI Hitachi America Ltd. * 2210 O'Toole Ave. San Jose, CA 95131 (408) 435-8300