UCC3580DTR-1G4 - Texas Instruments

UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

SLUS292D- FEBRUARY 1999 - REVISED FEBRUARY 2007

FEATURES

Provides Auxiliary Switch Activation

Complementary to Main Power

Switch Drive

Programmable deadtime (Turn-on

Delay) Between Activation of Each

Switch

Voltage Mode Control with

Feedforward Operation

Programmable Limits for Both

Transformer Volt- Second Product

and PWM Duty Cycle

High Current Gate Driver for Both

Main and Auxiliary Outputs

Multiple Protection Features with

Latched Shutdown and Soft Restart

Low Supply Current (100 mA Startup,

1.5 mA Operation)

BLOCK DIAGRAM

DESCRIPTION

The UCC3580 family of PWM controllers is designed to implement a variety

of active clamp/reset and synchronous rectifier switching converter topolo-

gies. While containing all the necessary functions for fixed frequency, high

performance pulse width modulation, the additional feature of this design is

the inclusion of an auxiliary switch driver which complements the main

power switch, and with a programmable deadtime or delay between each

transition. The active clamp/reset technique allows operation of single

ended converters beyond 50% duty cycle while reducing voltage stresses

on the switches, and allows a greater flux swing for the power transformer.

This approach also allows a reduction in switching losses by recovering en-

ergy stored in parasitic elements such as leakage inductance and switch

capacitance.

The oscillator is programmed with two resistors and a capacitor to set

switching frequency and maximum duty cycle. A separate synchronized

ramp provides a voltage feedforward pulse width modulation and a pro-

grammed maximum volt-second limit. The generated clock from the oscilla-

tor contains both frequency and maximum duty cycle information.

(continued)

Single Ended Active Clamp/Reset PWM

UDG-95069-2

Pin Numbers refer to DIL-16 and SOIC-16 packages

UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

VDD...........................................16V

IVDD..........................................25mA

LINE, RAMP ........................ 0.3V to VDD + 1V

ILINE,I

RAMP .....................................5mA

DELAY ........................................5.3V

IDELAY ........................................ 5mA

IOUT1 (tpw < 1 s and Duty Cycle < 10%)....... 0.6A to 1.2A

IOUT2 (tpw < 1 s and Duty Cycle < 10%)....... 0.4A to 0.4A

ICLK................................ 100mA to 100mA

OSC1, OSC2, SS, SHTDWN, EAIN ..... 0.3V to REF + 0.3V

IEAOUT.................................. 5mAto5mA

IREF......................................... 30mA

PGND.................................. 0.2V to 0.2V

Storage Temperature .................. -65°C to +150°C

Junction Temperature.................. -55°C to +150°C

Lead Temperature (Soldering, 10 sec.).............+300°C

All voltages are with respect to ground unless otherwise stated.

Currents are positive into, negative out of the specified termi-

nal. Consult Packaging Section of Databook for thermal limita-

tions and considerations of packages.

ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS

DIL-16, SOIC-16 (Top View)

J, N, or D Packages

ORDER INFORMATION

The main gate drive output (OUT1) is controlled by the

pulse width modulator. The second output (OUT2) is in-

tended to activate an auxiliary switch during the off time

of the main switch, except that between each transition

there is deadtime where both switches are off, pro-

grammed by a single external resistor. This design offers

two options for OUT2, normal and inverted. In the -1 and

-2 versions, OUT2 is normal and can be used to drive

PMOS FETs. In the -3 and -4 versions, OUT2 is inverted

and can be used to drive NMOS FETs. In all versions,

both the main and auxiliary switches are held off prior to

startup and when the PWM command goes to zero duty

cycle. During fault conditions, OUT1 is held off while

OUT2 operates at maximum duty cycle with a guaran-

teed off time equal to the sum of the two deadtimes.

Undervoltage lockout monitors supply voltage (VDD), the

precision reference (REF), input line voltage (LINE), and

the shutdown comparator (SHTDWN). If after any of

these four have sensed a fault condition, recovery to full

operation is initiated with a soft start. VDD thresholds, on

and off, are 15V and 8.5V for the -2 and -4 versions, 9V

and 8.5V for the -1 and -3 versions.

The UCC1580-x is specified for operation over the mili-

tary temperature range of -55°C to 125°C. The

UCC2580-x is specified from -40°C to 85°C. The

UCC3580-x is specified from 0°C to 70°C. Package op-

tions include 16-pin surface mount and dual in-line.

DESCRIPTION (cont.)

UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

ELECTRICAL CHARACTERISTICSUnless otherwise stated, all specifications are over the full temperature range, VDD =

12V, R1 = 18.2 kW, R2 = 4.41 kW,C

T= 130 pF, R3 = 100 kW,C

OUT1 =0F,C

OUT2 =0F.T

A= 0°C to 70°C for the UCC3580,

-40°C to 85°C for the UCC2580, -55°C to 125°C for the UCC1580, TA=T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Oscillator Section

Frequency 370 400 430 kHz

CLK Pulse Width 650 750 850 ns

CLK VOH ICLK = 3 mA 4.3 4.7 V

CLK VOL ICLK = 3 mA 0.3 0.5 V

Ramp Generator Section

Ramp VOL IRAMP = 100 mA 50 100 mV

Flux Comparator Vth 3.16 3.33 3.50 V

Pulse Width Modulator Section

Minimum Duty Cycle OUT1, EAOUT = VOL 0 %

Maximum Duty Cycle OUT1, EAIN = 2.6 V 63 66 69 %

PWM Comparator Offset 0.1 0.4 0.9 V

Error Amplifier Section

EAIN EAOUT = EAIN 2.44 2.5 2.56 V

IEAIN EAOUT = EAIN 150 400 nA

EAOUT, VOL EAIN = 2.6 V, IEAOUT = 100 mA 0.3 0.5 V

EAOUT, VOH EAIN = 2.4 V, IEAOUT = 100 mA 4 5 5.5 V

AVOL 70 80 dB

Gain Bandwidth Product f = 100 kHz (Note 1) 2 6 MHz

Softstart/Shutdown Section

Start Duty Cycle EAIN = 2.4 V 0 %

SS VOL ISS = 100 mA 100 350 mV

SS Restart Threshold 400 550 mV

ISS –20 –35 mA

SHTDWN VTH 0.4 0.5 0.6 V

ISHTDWN 50 150 nA

Undervoltage Lockout Section

VDD On UCC3580-2,-4 14 15 16 V

UCC3580-1,-3 8 9 10 V

VDD Off 7.5 8.5 9.5 V

LINE On 4.7 5 5.3 V

LINE Off 4.2 4.5 4.8 V

ILINE LINE=6V 50 150 nA

Supply Section

VDD Clamp IVDD =10mA 14 15 16 V

IVDD Start VDD < VDD On 160 250 A

IVDD Operating No Load 2.5 3.5 mA

Output Drivers Section

OUT1 VSAT High IOUT1 = 50 mA 0.4 1.0 V

OUT1 VSAT Low IOUT1 =100 mA 0.4 1.0 V

OUT2 VSAT High IOUT2 = 30 mA 0.4 1.0 V

OUT2 VSAT Low IOUT2 = 30 mA 0.4 1.0 V

OUT1 Fall Time COUT1 = 1nF, RS=3W20 50 ns

OUT1 Rise Time COUT1 = 1nF, RS=3W40 80 ns

OUT2 Fall Time COUT2 = 300pF, RS=10W20 50 ns

OUT2 Rise Time COUT2 = 300pF, RS=10W20 40 ns

UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

ELECTRICAL CHARACTERISTICSUnless otherwise stated, all specifications are over the full temperature range, VDD =

12V, R1 = 18.2 kW, R2 = 4.41 kW,C

T= 130 pF, R3 = 100 kW,C

OUT1 =0F,C

OUT2 =0F.T

A= 0°C to 70°C for the UCC3580,

-40°C to 85°C for the UCC2580, -55°C to 125°C for the UCC1580, TA=T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Output Drivers Section (cont.)

Delay 1 OUT2 to OUT1 R3 = 100 kW,C

OUT1 =C

OUT2 = 15 pF 90 120 160 ns

TA=T

J= 25°C 100 120 140 ns

Delay 2 OUT1 to OUT2 R3 = 100 kW,C

OUT1 =C

OUT2 = 15 pF 110 170 250 ns

TA=T

J= 25°C 140 170 200 ns

Reference Section

REF IREF = 0 4.875 5 5.125 V

Load Regulation IREF =0mAto1mA 1 20 mV

Line Regulation VDD = 10 V to 14 V 1 20 mV

Note 1: Guaranteed by design. Not 100% tested in production.

CLK: Oscillator clock output pin from a low impedance

CMOS driver. CLK is high during guaranteed off time.

CLK can be used to synchronized up to five other

UCC3580 PWMs.

DELAY: A resistor from DELAY to GND programs the

nonoverlap delay between OUT1 and OUT2. The delay

times, Delay1 and Delay2, are shown in Figure 1 and are

as follows:

Delay pF R111 3=·.

Delay2 is designed to be larger than Delay1 by a ratio

shown in Figure 2.

EAIN: Inverting input to the error amplifier. The

noninverting input of the error amplifier is internally set to

2.5V. EAIN is used for feedback and loop compensation.

EAOUT: Output of the error amplifier and input to the

PWM comparator. Loop compensation components

connect from EAOUT to EAIN.

GND: Signal Ground.

LINE: Hysteretic comparator input. Thresholds are 5.0V

and 4.5V. Used to sense input line voltage and turn off

OUT1 when the line is low.

OSC1 & OSC2: Oscillator programming pins. A resistor

connects each pin to a timing capacitor. The resistor

connected to OSC1 sets maximum on time. The resistor

connected to OSC2 controls guaranteed off time. The

combined total sets frequency with the timing capacitor.

Frequency and maximum duty cycle are approximately

given by:

()( )

Frequency 1.44

R1 R CT

=+· +227pF

Maximum Duty Cycle R1

R1 R2

Maximum Duty Cycle for OUT1 is slightly less due to

Delay1 which is programmed by R3.

OUT1: Gate drive output for the main switch capable of

sourcing up to 0.5A and sinking 1A.

OUT2: Gate drive output for the auxiliary switch with

0.3A drive current capability.

PGND: Ground connection for the gate drivers. Connect

PGND to GND at a single point so that no high frequency

components of the output switching currents are in the

ground plane on the circuit board.

RAMP: A resistor (R4) from RAMP to the input voltage

and a capacitor (CR) from RAMP to GND programs the

feedforward ramp signal. RAMP is discharged to GND

when CLK is high and allowed to charge when CLK is

low. RAMP is the line feedforward sawtooth signal for the

PWM comparator. Assuming the input voltage is much

greater than 3.3V, the ramp is very linear. A flux

comparator compares the ramp signal to 3.3V to limit the

maximum allowable volt-second product:

Volt-Second Product Clamp = 3.3 • R4 • CR.

REF: Precision 5.0V reference pin. REF can supply up to

5mA to external circuits. REF is off until VDD exceeds 9V

(–1 and –3 versions) or activates the 15V clamp (–2 and

–4 versions) and turns off again when VDD droops below

8.5V. Bypass REF to GND with a 1mF capacitor.

SHTDWN: Comparator input to stop the chip. The

threshold is 0.5V. When the chip is stopped, OUT1 is low

and OUT2 continues to oscillate with guaranteed off time

equal to two non-overlap delay times. OUT2 continues to

switch after SHTDWN is asserted until the voltage on

VDD falls below VCS (typically 4 V) in order to discharge

the clamp capacitor.

PIN DESCRIPTIONS

UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

UVLO and Startup

For self biased off-line applications, -2 and -4 versions

(UVLO on and off thresholds of 15V and 8.5V typical)

are recommended. For all other applications, -1 and -3

versions provide the lower on threshold of 9V. The IC re-

quires a low startup current of only 160mA when VDD is

under the UVLO threshold, enabling use of a large trickle

charge resistor (with corresponding low power dissipa-

tion) from the input voltage. VDD has an internal clamp

at 15V which can sink up to 10mA. Measures should be

taken not to exceed this current. For -2 and -4 versions,

this clamp must be activated as an indication of reaching

the UVLO on threshold. The internal reference (REF) is

brought up when the UVLO on threshold is crossed. The

startup logic ensures that LINE and REF are above and

SHTDWN is below their respective thresholds before

outputs are asserted. LINE input is useful for monitoring

actual input voltage and shutting off the IC if it falls be-

low a programmed value. A resistive divider should be

used to connect the input voltage to the LINE input. This

feature can protect the power supply from excessive

currents at low line voltages.

Figure 1. Output time relationships.

APPLICATION INFORMATION

UDG-95070-2

Note: Waveforms are not to scale.

SS: A capacitor from SS to ground programs the soft

start time. During soft start, EAOUT follows the amplitude

of SS’s slowly increasing waveform until regulation is

achieved.

VDD: Chip power supply pin. VDD should be bypassed

to PGND. The –1 and –3 versions require VDD to ex-

ceed 9V to start and remain above 8.5V to continue run-

ning. A shunt clamp from VDD to GND limits the supply

voltage to 15V. The –2 and –4 versions do not start until

PIN DESCRIPTIONS (cont.)

UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

The soft start pin provides an effective means to start

the IC in a controlled manner. An internal current of

20 A begins charging a capacitor connected to SS once

the startup conditions listed above have been met. The

voltage on SS effectively controls maximum duty cycle

on OUT1 during the charging period. OUT2 is also con-

trolled during this period (see Figure 1). Negation of any

of the startup conditions causes SS to be immediately

discharged. Internal circuitry ensures full discharge of

SS (to 0.3V) before allowing charging to begin again,

provided all the startup conditions are again met.

Oscillator

Simplified oscillator block diagram and waveforms are

shown in Figure 3. OSC1 and OSC2 pins are used to

program the frequency and maximum duty cycle. Capac-

itor CT is alternately charged through R1 and discharged

through R2 between levels of 1.67 V and 3.3 V. The

charging and discharging equations for CT are given by

VC(cha rge ) = • 1 • e -t

REF -

çö

VC(dis c h a rg e ) = V e

REF

-t

23··

where t1=R1•CT andt2= R2 • CT. The charge time

and discharge time are given by

tCH = 0.69 • R1 • CTand tDIS =0.69•R2•CT

The CLK output is high during the discharge period. It

blanks the output to limit the maximum duty cycle of

OUT1. The frequency and maximum duty cycle are

given by

()

Frequency = 1.44

(R1+ R2)• CT+ 27 pF

Maximum Duty Cycle = R1

R1+ R2

Maximum Duty Cycle for OUT1 will be slightly less due

to Delay1 which is programmed by R3.

Voltage Feedforward and Volt-Second Clamp

UCC3580 has a provision for input voltage feedforward.

As shown in Figure 3, the ramp slope is made propor-

tional to input line voltage by converting it into a charging

current for CR. This provides a first order cancellation of

the effects of line voltage changes on converter perfor-

mance. The maximum volt-second clamp is provided to

protect against transient saturation of the transformer

core. It terminates the OUT1 pulse when the RAMP volt-

age exceeds 3.3V. If the feedforward feature is not used,

the ramp can be generated by tying R4 to REF. How-

ever, the linearity of ramp suffers and in this case the

maximum volt-second clamp is no longer available.

Figure 3. Oscillator and ramp circuits.

UDG-96016-1

Delay Times

200

400

600

800

1000

1200

1400

0 100 200 300 400 500 600 700 800 900 1000

R3 ProgrammingResistor k

Delay ns

1.10

1.20

1.30

1.40

1.50

1.60

1.70

1.80

Delay2/Delay1 Ratio

DelayRatio

Delay1

Delay2

Figure 2. Delay times.

APPLICATION INFORMATION (cont.)

UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

Output Configurations

The UCC3580 family of ICs is designed to provide con-

trol functions for single ended active clamp circuits. For

different implementations of the active clamp approach,

different drive waveforms for the two switches (main and

auxiliary) are required. The -3 and -4 versions of the IC

supply complementary non-overlapping waveforms

(OUT1 and OUT2) with programmable delay which can

be used to drive the main and auxiliary switches. Most

active clamp configurations will require one of these out-

puts to be transformer coupled to drive a floating switch

(e.g. Figure 5). The -1 and -2 versions have the phase of

OUT2 inverted to give overlapping waveforms. This con-

figuration is suitable for capacity coupled driving of a

ground referenced p-channel auxiliary switch with the

OUT2 drive while OUT1 is directly driving an n-channel

main switch (e.g. Figure 4).

The programmable delay can be judiciously used to get

zero voltage turn-on of both the main and auxiliary

switches in the active clamp circuits. For the UCC3580,

a single pin is used to program the delays between

OUT1 and OUT2 on both sets of edges. Figure 1 shows

the relationships between the outputs. Figure 2 gives the

ratio between the two delays. During the transition from

main to auxiliary switch, the delay is not very critical for

ZVS turn-on. For the first half of OUT1 off-time, the body

diode of the auxiliary switch conducts and OUT2 can be

turned on any time. The transition from auxiliary to main

switch is more critical. Energy stored in the parasitic in-

ductance(s) at the end of the OUT2 pulse is used to dis-

charge the parasitic capacitance across the main switch

during the delay time. The delay (Delay 1) should be op-

timally programmed at 1/4 the resonant period deter-

mined by parasitic capacitance and the resonant

inductor (transformer leakage and/or magnetizing induc-

tances, depending on the topology). However, depend-

ing on other circuit parasitics, the resonant behavior can

change, and in some cases, ZVS turn-on may not be ob-

tainable. It can be shown that the optimum delay time is

independent of operating conditions for a specific circuit

and should be determined specifically for each circuit.

APPLICATION INFORMATION (cont.)

Figure 4. Active clamp forward converter.

UDG-95071-2

UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

Figure 5. Off-line active clamp flyback converter.

APPLICATION INFORMATION (cont.)

UDG-96017-1

The use of active reset in a flyback power converter topology may be covered by U.S. Patent No. 5,402,329 owned by Technical

Witts, Inc., and for which Unitrode offers users a paid up license for application of the UCC1580 product family.

UCC1580-1,-2,-3,-4

UCC2580-1,-2,-3,-4

UCC3580-1,-2,-3,-4

Figure 6. UCC3580 used in a synchronous rectifier application.

APPLICATION INFORMATION (cont.)

UDG-96018-1

REVISION DATE COMMENT

SLUS292B MAY 2005 Updated OSC frequency and maximum duty cycle, CT charge and discharge

equations.

Updated SHTDWN pin description.

Updated typical CT value used for measurements in electrical characteristics

table.

SLUS292C MAY 2005 Removed Q package from datasheet.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

UCC1580J-2 OBSOLETE UTR TBD Call TI Call TI

UCC1580J-4 OBSOLETE CDIP J 16 TBD Call TI Call TI

UCC2580D-1 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580D-1G4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580D-2 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580D-2G4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580D-3 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580D-3G4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580D-4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580D-4G4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580DTR-1 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580DTR-1G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580DTR-2 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580DTR-2G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580DTR-3 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580DTR-3G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580DTR-4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580DTR-4G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC2580N-1 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC2580N-1G4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC2580N-2 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC2580N-2G4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC2580N-3 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC2580N-3G4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC2580N-4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC2580N-4G4 ACTIVE PDIP N 16 25 Green (RoHS & CU NIPDAU N / A for Pkg Type

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 1

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

no Sb/Br)

UCC3580D-1 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580D-1G4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580D-2 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580D-2G4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580D-3 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580D-3G4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580D-4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580D-4G4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580DTR-1 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580DTR-1G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580DTR-2 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580DTR-2G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580DTR-3 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580DTR-3G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580DTR-4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580DTR-4G4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

UCC3580N-1 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC3580N-1G4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC3580N-2 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC3580N-2G4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC3580N-3 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC3580N-3G4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC3580N-4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

UCC3580N-4G4 ACTIVE PDIP N 16 25 Green (RoHS &

no Sb/Br) CU NIPDAU N / A for Pkg Type

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 2

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

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information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 3

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

UCC2580DTR-1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC2580DTR-2 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC2580DTR-3 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC2580DTR-4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC3580DTR-1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC3580DTR-2 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC3580DTR-3 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

UCC3580DTR-4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UCC2580DTR-1 SOIC D 16 2500 333.2 345.9 28.6

UCC2580DTR-2 SOIC D 16 2500 333.2 345.9 28.6

UCC2580DTR-3 SOIC D 16 2500 333.2 345.9 28.6

UCC2580DTR-4 SOIC D 16 2500 333.2 345.9 28.6

UCC3580DTR-1 SOIC D 16 2500 333.2 345.9 28.6

UCC3580DTR-2 SOIC D 16 2500 333.2 345.9 28.6

UCC3580DTR-3 SOIC D 16 2500 333.2 345.9 28.6

UCC3580DTR-4 SOIC D 16 2500 333.2 345.9 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 19-Mar-2008

Pack Materials-Page 2

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