VN920D-B5 VN920DSO High-side driver Features Type RDS(on) IOUT VCC VN920D-B5 VN920DSO 18 m 30 A 36 V P2PAK CMOS-compatible input On-state open load detection Off-state open load detection Shorted load protection Under-voltage and over-voltage shutdown Protection against loss of ground Very low standby current Reverse battery protected (see Application schematic ) SO-16L Description The VN920D-B5 and VN920DSO are monolithic devices designed in STMicroelectronics VIPower M0-3 technology. The VN920D-B5 and VN920DSO are intended for driving any type of load with one side connected to ground. The active VCC pin voltage clamp protects the devices against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the devices against overload. The devices detect the open load condition in both the on and off-state. In the off-state the devices detect if the output is shorted to VCC. The devices automatically turn-off in the case where the ground pin becomes disconnected. Table 1. Device summary Order codes Package Tube Tape and reel P2PAK VN920D-B5 VN920D-B513TR SO-16L VN920DSO VN920DSO13TR December 2008 Rev 3 1/32 www.st.com 32 Contents VN920D-B5 / VN920DSO Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 4 5 6 2/32 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 16 3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 17 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 P2PAK maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . 18 3.5 SO-16L maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . 19 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 SO-16L thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 P2PAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 P2PAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 SO-16L packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4 P2PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VN920D-B5 / VN920DSO List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching (VCC=13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SO-16L thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 P2PAK thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-16L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 P2PAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3/32 List of figures VN920D-B5 / VN920DSO List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. 4/32 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 On-state resistance Vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 On-state resistance Vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Over-voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input high-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input low-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ilim Vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 P2PAK maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SO-16L maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SO-16L PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO-16L Rthj-amb Vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . 20 SO-16L thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . 21 Thermal fitting model of a single channel HSD in SO-16L . . . . . . . . . . . . . . . . . . . . . . . . . 21 P2PAK PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 P2PAK Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . 23 P2PAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal fitting model of a single channel HSD in P2PAK. . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-16L package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 P2PAK package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO-16L tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SO-16L tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 P2PAK tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 P2PAK tape and reel (suffix "13TR"). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VN920D-B5 / VN920DSO 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC OVER-VOLTAGE DETECTION VCC CLAMP UNDER-VOLTAGE DETECTION GND Power CLAMP DRIVER INPUT OUTPUT LOGIC CURRENT LIMITER ON-STATE OPEN LOAD DETECTION STATUS OVER-TEMPERATURE DETECTION Figure 2. OFF-STATE OPEN LOAD AND OUTPUT SHORTED TO VCC DETECTION Configuration diagram (top view) 1 VCC OUTPUT STATUS VCC INPUT GND 5 4 3 2 1 16 VCC N.C. OUTPUT GND OUTPUT INPUT OUTPUT STATUS N.C. OUTPUT OUTPUT OUTPUT N.C. 8 VCC 9 VCC P2PAK SO-16L Table 2. Suggested connections for unused and not connected pins Connection / pin Status N.C. Output Input Floating X X X X To ground X Through 10K resistor 5/32 Electrical specifications 2 VN920D-B5 / VN920DSO Electrical specifications Figure 3. Current and voltage conventions IS VF IIN VCC INPUT ISTAT IOUT STATUS VCC OUTPUT GND VIN VSTAT 2.1 VOUT IGND Absolute maximum ratings Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality document. Table 3. Absolute maximum ratings Value Symbol Parameter P2PAK SO-16L VCC 41 V - VCC Reverse DC supply voltage - 0.3 V - Ignd DC reverse ground pin current - 200 mA IOUT DC output current Internally limited A - 25 A DC input current +/- 10 mA ISTAT DC Status current +/- 10 mA VESD Electrostatic discharge (human body model: R = 1.5K; C = 100pF) - INPUT - STATUS - OUTPUT - VCC 4000 4000 5000 5000 V V V V - IOUT IIN 6/32 DC supply voltage Unit Reverse DC output current VN920D-B5 / VN920DSO Table 3. Electrical specifications Absolute maximum ratings (continued) Value Symbol EMAX Ptot Unit SO-16L P2PAK Maximum switching energy (L = 0.25mH; RL= 0; Vbat = 13.5V; Tjstart = 150C; IL = 45A) 352 364 mJ Power dissipation TC = 25C 8.3 96.1 W Tj Junction operating temperature Tc Tstg 2.2 Parameter Internally limited C Case operating temperature - 40 to 150 C Storage temperature - 55 to 150 C Thermal data Table 4. Thermal data Max. value Symbol Parameter SO-16L P2PAK Unit Rthj-case Thermalresistance junction-case - 1.3 C/W Rthj-lead Thermalresistance junction-lead 15 - C/W Rthj-amb Thermalresistance junctionambient 65 (1) 51.3(2) C/W 1. When mounted on FR4 printed circuit board with 0.5cm2 of Cu (at least 35m thick) connected to all VCC pins. 2. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick). 7/32 Electrical specifications 2.3 VN920D-B5 / VN920DSO Electrical characteristics Values specified in this section are for 8V < VCC < 36V; -40C < Tj < 150C, unless otherwise stated. Table 5. Power Symbol Parameter VCC Min. Typ. Operating supply voltage 5.5 13 36 V VUSD Under-voltage shutdown 3 4 5.5 V VUSDhyst Under-voltage shutdown hysteresis VOV Over-voltage shutdown RON On-state resistance IS Supply current Test conditions 0.5 V 36 V IOUT = 10A; Tj = 25C; IOUT = 10A; IOUT = 3A; VCC = 6V 18 36 50 m m m Off-state; VCC = 13V; VIN = VOUT = 0V 10 25 A Off-state; VCC = 13V; VIN = VOUT = 0V; Tj = 25C 10 20 A 3.5 mA 0 50 A -75 0 A On-state; VCC = 13V; VIN = 5V; IOUT = 0A IL(off1) Off-state output current VIN = VOUT = 0V IL(off2) Off-state output current VIN = 0V; VOUT = 3.5V IL(off3) Off-state output current VIN = VOUT = 0V; VCC = 13V; Tj = 125C 5 A IL(off4) Off-state output current VIN = VOUT = 0V; VCC = 13V; Tj = 25C 3 A Table 6. Symbol 8/32 Max. Unit Switching (VCC=13V) Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 1.3 50 s td(off) Turn-off delay time RL = 1.3 50 s dVOUT/dt(on) Turn-on voltage slope RL = 1.3 See Figure 20. V/s dVOUT/dt(off) Turn-off voltage slope RL = 1.3 See Figure 21. V/s VN920D-B5 / VN920DSO Table 7. Symbol Electrical specifications Input pin Parameter VIL Input low-level IIL Low-level input current VIH Input high-level IIH High-level input current Vhyst Input hysteresis voltage VICL Input clamp voltage Table 8. Test conditions Min. VIN = 1.25V Unit 1.25 V A 3.25 V 10 0.5 IIN = 1mA IIN = -1mA A V 6 6.8 - 0.7 8 V V Max. Unit 0.7 V Max. Unit VCC output diode Parameter Test conditions VF Forward on voltage - IOUT = 5.5A; Tj = 150C Symbol Max. 1 VIN = 3.25V Symbol Table 9. Typ. Min. Typ. Status pin Parameter Test conditions Min. Typ. VSTAT Status low output voltage ISTAT = 1.6mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5V 10 A CSTAT Status pin input capacitance Normal operation; VSTAT = 5V 100 pF VSCL Status clamp voltage 8 V V Table 10. Protections(1) Symbol Parameter 6 ISTAT = 1mA ISTAT = - 1mA Min. Typ. Max. Unit Shutdown temperature 150 175 200 C TR Reset temperature 135 Thyst Thermal hysteresis 7 tSDL Status delay in overload condition Ilim Current limitation TTSD Vdemag Turn-off output clamp voltage Test conditions 6.8 - 0.7 C 15 Tj > Tjsh 30 5.5V < VCC < 36V IOUT = 2 A; VIN = 0V; L = 6mH 45 C 20 ms 75 75 A A VCC - 41 VCC - 48 VCC - 55 V 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles. 9/32 Electrical specifications Table 11. Symbol VN920D-B5 / VN920DSO Open load detection Parameter Test conditions Min. Typ. Max. Unit 300 500 700 mA 250 s 3.5 V 1000 s IOL Open load on-state detection threshold VIN = 5V tDOL(on) Open load on-state detection delay IOUT = 0A VOL Open load off-state voltage detection threshold VIN = 0V tDOL(off) Open load detection delay at turn-off Figure 4. 1.5 Status timings OPEN LOAD STATUS TIMING (with external pull-up) IOUT< IOL VOUT > VOL OVER-TEMP STATUS TIMING Tj > Tjsh VIN VIN VSTAT VSTAT tDOL(off) Figure 5. 2.5 tDOL(on) tSDL tSDL Switching time waveforms VOUT 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% t VIN td(on) td(off) t 10/32 VN920D-B5 / VN920DSO Table 12. Electrical specifications Truth table Conditions Input Output Status Normal operation L H L H H H Current limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Over-temperature L H L L H L Under-voltage L H L L X X Over-voltage L H L L H H Output voltage > VOL L H H H L H Output current < IOL L H L H H L Table 13. Electrical transient requirements Test level ISO T/R 7637/1 Test pulse I II III IV Delays and impedance 1 - 25V(1) - 50V(1) - 75V(1) - 100V(1) 2ms, 10 2 (1) + 50V(1) 75V(1) + 100V(1) 0.2ms, 10 - 50V(1) - 150V(1) 0.1s, 50 + 50V(1) + 100V(1) 0.1s, 50 3a 3b + 25V - 25V(1) + 25V (1) + - 100V(1) + 75V(1) 4 - 4V(1) - 5V(1) - 6V(1) - 7V(1) 5 26.5V(1) 46.5V(2) 66.5V(2) 86.5V(2) + + + + 100ms, 0.01 400ms, 2 1. All functions of the device are performed as designed after exposure to disturbance. 2. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 11/32 Electrical specifications Figure 6. VN920D-B5 / VN920DSO Waveforms NORMAL OPERATION INPUT LOAD VOLTAGE STATUS UNDER-VOLTAGE VUSDhyst VCC VUSD INPUT LOAD VOLTAGE STATUS undefined OVER-VOLTAGE VCC<VOV VCC > VOV VCC INPUT LOAD VOLTAGE STATUS OPEN LOAD with external pull-up INPUT VOUT > VOL LOAD VOLTAGE VOL STATUS OPEN LOAD without external pull-up INPUT LOAD VOLTAGE STATUS Tj INPUT LOAD CURRENT STATUS 12/32 TTSD TR OVER-TEMPERATURE VN920D-B5 / VN920DSO 2.4 Electrical specifications Electrical characteristics curves Figure 7. Off-state output current IL(off1) (A) Figure 8. Iih (uA) 5 5 4.5 4.5 Off state Vcc=36V Vin=Vout=0V 4 3.5 High-level input current Vin=3.25V 4 3.5 3 3 2.5 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C ) Figure 9. 50 75 100 125 150 175 Tc (C ) Input clamp voltage Figure 10. Status leakage current Vicl (V) Ilstat(A) 8 0.05 7.8 0.045 Iin=1mA 7.6 Vstat=5V 0.04 7.4 0.035 7.2 0.03 7 0.025 6.8 0.02 6.6 0.015 6.4 0.01 6.2 0.005 0 6 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (C ) Tc (C ) Figure 11. Status low output voltage Figure 12. Status clamp voltage Vscl (V) Vstat (V) 8 0.8 7.8 0.7 Istat=1.6mA Istat=1mA 7.6 0.6 7.4 0.5 7.2 7 0.4 6.8 0.3 6.6 0.2 6.4 0.1 6.2 0 6 -50 -25 0 25 50 75 Tc (C ) 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) 13/32 Electrical specifications VN920D-B5 / VN920DSO Figure 13. On-state resistance Vs Tcase Figure 14. On-state resistance Vs VCC Ron (mOhm) Ron (mOhm) 50 50 45 45 Iout=10A Vcc=8V; 36V 40 Iout=10A 40 35 35 30 30 25 25 20 20 15 15 10 10 5 5 0 Tc=150C Tc=25C Tc=-40C 0 -50 -25 0 25 50 75 100 125 150 175 5 10 15 20 Tc (C ) 25 30 35 40 Vcc (V) Figure 15. Over-voltage shutdown Figure 16. Input high-level Vov (V) Vih (V) 50 3.6 48 3.4 46 3.2 44 3 42 40 2.8 38 2.6 36 2.4 34 2.2 32 2 30 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (C ) Tc (C ) Figure 17. Input low-level Figure 18. Input hysteresis voltage Vil (V) Vhyst (V) 2.6 1.5 1.4 2.4 1.3 2.2 1.2 2 1.1 1.8 1 0.9 1.6 0.8 1.4 0.7 1.2 0.6 1 0.5 -50 -25 0 25 50 75 Tc (C ) 14/32 100 125 150 175 -50 -25 0 25 50 75 Tc (C ) 100 125 150 175 VN920D-B5 / VN920DSO Electrical specifications Figure 19. Ilim Vs Tcase Figure 20. Turn-on voltage slope Ilim (A) dVout/dt(on) (V/ms) 100 700 90 650 Vcc=13V 80 Vcc=13V Rl=1.3Ohm 600 70 550 60 500 50 450 40 400 30 20 350 10 300 0 250 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) -50 -25 0 25 50 75 100 125 150 175 Tc (C ) Figure 21. Turn-off voltage slope dVout/dt(off) (V/ms) 550 500 Vcc=13V Rl=1.3Ohm 450 400 350 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) 15/32 Application information 3 VN920D-B5 / VN920DSO Application information Figure 22. Application schematic +5V +5V VCC Rprot STATUS Dld C Rprot INPUT OUTPUT GND VGND RGND DGND 3.1 GND protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (RGND only) This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. RGND 600mV / (IS(on)max). 2. RGND (- VCC) / (- IGND) where - IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC < 0: during reverse battery situations) is: PD= (- VCC)2/ RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high-side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 16/32 VN920D-B5 / VN920DSO 3.1.2 Application information Solution 2: diode (DGND) in the ground line A resistor (RGND = 1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift ( 600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.3 MCU I/Os protection If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended values: Rprot =10k . 17/32 Application information 3.4 VN920D-B5 / VN920DSO P2PAK maximum demagnetization energy (VCC = 13.5V) Figure 23. P2PAK maximum turn-off current versus inductance ILMAX (A) 100 A B C 10 1 0.01 0.1 1 10 100 L(mH) A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t Note: 18/32 Values are generated with RL =0 .In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. VN920D-B5 / VN920DSO 3.5 Application information SO-16L maximum demagnetization energy (VCC = 13.5V) Figure 24. SO-16L maximum turn-off current versus inductance A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL =0 .In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. 19/32 Package and PCB thermal data VN920D-B5 / VN920DSO 4 Package and PCB thermal data 4.1 SO-16L thermal data Figure 25. SO-16L PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 41mm x 48mm, PCB thickness = 2mm, Cu thickness = 35m, Copper areas: 0.5cm2, 6cm2). Figure 26. SO-16L Rthj-amb Vs PCB copper area in open box free air condition 70 RTH j-amb (C/W) 65 60 55 50 45 40 0 1 2 3 4 5 PCB Cu heatsink area (cm^2) 20/32 6 7 VN920D-B5 / VN920DSO Package and PCB thermal data Figure 27. SO-16L thermal impedance junction ambient single pulse Equation 1: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tp T Figure 28. Thermal fitting model of a single channel HSD in SO-16L Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb 21/32 Package and PCB thermal data Table 14. 4.2 VN920D-B5 / VN920DSO SO-16L thermal parameters Area / island (cm2) Footprint R1 (C/W) 0.02 R2 (C/W) 0.1 R3 (C/W) 2.2 R4 (C/W) 12 R5 (C/W) 15 R6 (C/W) 35 C1 (W.s/C) 0.0015 C2 (W.s/C) 7E-03 C3 (W.s/C) 1.5E-02 C4 (W.s/C) 0.14 C5 (W.s/C) 1 C6 (W.s/C) 5 6 20 8 P2PAK thermal data Figure 29. P2PAK PC board Note: 22/32 Layout condition of Rth and Zth measurements (PCB FR4 area = 60mm x 60mm, PCB thickness = 2 mm, Cu thickness = 35m , Copper areas: 0.97cm2, 8cm2). VN920D-B5 / VN920DSO Package and PCB thermal data Figure 30. P2PAK Rthj-amb Vs. PCB copper area in open box free air condition RTHj_amb (C/W) 55 Tj-Tamb=50C 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) Figure 31. P2PAK thermal impedance junction ambient single pulse ZTH (C /W) 1000 100 0.97 cm2 6 cm2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 23/32 Package and PCB thermal data VN920D-B5 / VN920DSO Equation 2: pulse calculation formula Z TH = R TH +Z THtp ( 1 - ) where = tP/T Figure 32. Thermal fitting model of a single channel HSD in P2PAK Table 15. 24/32 P2PAK thermal parameters Area/island (cm2) 0.97 R1 (C/W) 0.02 R2 (C/W) 0.1 R3 (C/W) 0.22 R4 (C/W) 4 R5 (C/W) 9 R6 (C/W) 37 C1 (W*s/C) 0.0015 C2 (W*s/C) 0.007 C3 (W*s/C) 0.015 C4 (W*s/C) 0.4 C5 (W*s/C) 2 C6 (W*s/C) 3 6 22 5 VN920D-B5 / VN920DSO Package and packing information 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 33. SO-16L package dimensions Table 16. SO-16L mechanical data mm. DIM. Min. Typ. A a1 Max. 2.65 0.1 0.2 a2 2.45 b 0.35 0.49 b1 0.23 0.32 C 0.5 c1 45 (typ.) 25/32 Package and packing information Table 16. VN920D-B5 / VN920DSO SO-16L mechanical data (continued) mm. DIM. Min. Typ. D 10.1 10.5 E 10.0 10.65 e 1.27 e3 8.89 F 7.4 7.6 L 0.5 1.27 M S 26/32 Max. 0.75 8 (max.) VN920D-B5 / VN920DSO 5.2 Package and packing information P2PAK mechanical data Figure 34. P2PAK package dimensions P010R 27/32 Package and packing information VN920D-B5 / VN920DSO P2PAK mechanical data Table 17. mm Dim. Min. Max. A 4.30 4.80 A1 2.40 2.80 A2 0.03 0.23 b 0.80 1.05 c 0.45 0.60 c2 1.17 1.37 D 8.95 9.35 D2 E 8.00 10.00 E1 10.40 8.50 e 3.20 3.60 e1 6.60 7.00 L 13.70 14.50 L2 1.25 1.40 L3 0.90 1.70 L5 1.55 2.40 0.40 R V2 Package weight 28/32 Typ. 0 8 1.40 Gr (typ) VN920D-B5 / VN920DSO 5.3 Package and packing information SO-16L packing information Figure 35. SO-16L tube shipment (no suffix) Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) C B 50 1000 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 36. SO-16L tape and reel shipment (suffix "TR") Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 16 4 12 1.5 1.5 7.5 6.5 2 End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 29/32 Package and packing information 5.4 VN920D-B5 / VN920DSO P2PAK packing information Figure 37. P2PAK tube shipment (no suffix) Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) B C 50 1000 532 18 33.1 1 All dimensions are in mm. A Figure 38. P2PAK tape and reel (suffix "13TR") REEL DIMENSIONS All dimensions are in mm. Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 60 30.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 24 4 12 1.5 1.5 11.5 6.5 2 End Start Top cover tape No components Components 500mm min Empty components pockets saled with cover tape. User direction of feed 30/32 No components 500mm min VN920D-B5 / VN920DSO 6 Revision history Revision history Table 18. Document revision history Date Revision 09-Sep-2004 1 Initial release. 03-May-2006 2 Suggested connections for unused and n.c.pins correction (page 2). 3 Document reformatted and restructured. Added content, list of figures and tables. Added ECOPACK(R) packages information. Updated Figure 38.: P2PAK tape and reel (suffix "13TR"): changed component spacing (P) in tape dimensions table from 16 mm to 12 mm. 19-Dec-2008 Changes 31/32 VN920D-B5 / VN920DSO Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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