December 2008 Rev 3 1/32
32
VN920D-B5
VN920DSO
High-side driver
Features
■CMOS-compatible input
■On-state open load detection
■Off-state open load detection
■Shorted load protection
■Under-voltage and over-voltage shutdown
■Protection against loss of ground
■Very low standby current
■Reverse battery protected (see Application
schematic )
Description
The VN920D-B5 and VN920DSO are monolithic
devices designed in STMicroelectronics VIPower
M0-3 technology. The VN920D-B5 and
VN920DSO are intended for driving any type of
load with one side connected to ground. The
active VCC pin voltage clamp protects the devices
against low energy spikes (see ISO7637 transient
compatibility table).
Active current limitation combined with thermal
shutdown and automatic restart protects the
devices against overload. The devices detect the
open load condition in both the on and off-state. In
the off-state the devices detect if the output is
shorted to VCC. The devices automatically turn-off
in the case where the ground pin becomes
disconnected.
Type RDS(on) IOUT VCC
VN920D-B5
VN920DSO 18 mΩ30 A 36 V
P2PAK SO-16L
Table 1. Device summary
Package
Order codes
Tube Tape and reel
P2PAK VN920D-B5 VN920D-B513TR
SO-16L VN920DSO VN920DSO13TR
www.st.com
Contents VN920D-B5 / VN920DSO
2/32
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 16
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 17
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 P2PAK maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . 18
3.5 SO-16L maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . 19
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 SO-16L thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 P2PAK thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 P2PAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 SO-16L packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.4 P2PAK packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VN920D-B5 / VN920DSO List of tables
3/32
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Switching (VCC=13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. VCC output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 9. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 11. Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 13. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 14. SO-16L thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. P2PAK thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. SO-16L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. P2PAK mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of figures VN920D-B5 / VN920DSO
4/32
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. On-state resistance Vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. On-state resistance Vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. Over-voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Input high-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. Input low-level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Ilim Vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. P2PAK maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 24. SO-16L maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 25. SO-16L PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. SO-16L Rthj-amb Vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . 20
Figure 27. SO-16L thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 28. Thermal fitting model of a single channel HSD in SO-16L . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 29. P2PAK PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. P2PAK Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . 23
Figure 31. P2PAK thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. Thermal fitting model of a single channel HSD in P2PAK. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 33. SO-16L package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 34. P2PAK package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 35. SO-16L tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. SO-16L tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 37. P2PAK tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 38. P2PAK tape and reel (suffix “13TR”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VN920D-B5 / VN920DSO Block diagram and pin description
5/32
1 Block diagram and pin description
Figure 1. Block diagram
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Status N.C. Output Input
Floating X X X X
To ground X Through 10KΩ resistor
UNDER-VOLTAGE
OVER-TEMPERATURE
VCC
GND
INPUT
OUTPUT
OVER-VOLTAGE
CURRENT LIMITER
LOGIC
DRIVER
Power CLAMP
STATUS
VCC
CLAMP
ON-STATE OPEN LOAD
OFF-STATE OPEN LOAD
AND OUTPUT SHORTED TO VCC
DETECTION
DETECTION
DETECTION
DETECTION
DETECTION
OUTPUT
STATUS
V
CC
INPUT
GND
5
4
3
2
1
P2PAK
V
CC
OUTPUT
OUTPUT
OUTPUT
OUTPUT
V
CC
OUTPUT
OUTPUT
V
CC
N.C.
N.C.
STATUS
INPUT
V
CC
GND
N.C.
1
89
16
SO-16L
Electrical specifications VN920D-B5 / VN920DSO
6/32
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics sure
program and other relevant quality document.
INPUT
IS
IIN
VIN
VCC
STATUS
ISTAT
VSTAT
GND
VCC
IOUT
VOUT
IGND
OUTPUT
V
F
Table 3. Absolute maximum ratings
Symbol Parameter
Value
Unit
SO-16L P2PAK
VCC DC supply voltage 41 V
- VCC Reverse DC supply voltage - 0.3 V
- Ignd DC reverse ground pin current - 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse DC output current - 25 A
IIN DC input current +/- 10 mA
ISTAT DC Status current +/- 10 mA
VESD
Electrostatic discharge
(human body model: R = 1.5KΩ; C = 100pF)
- INPUT
- STATUS
- OUTPUT
- VCC
4000
4000
5000
5000
V
V
V
V
VN920D-B5 / VN920DSO Electrical specifications
7/32
2.2 Thermal data
Symbol Parameter
Value
Unit
SO-16L P2PAK
EMAX
Maximum switching energy
(L = 0.25mH; RL= 0Ω; Vbat = 13.5V;
Tjstart = 150ºC; IL = 45A)
352 364 mJ
Ptot Power dissipation TC = 25°C 8.3 96.1 W
TjJunction operating temperature Internally limited °C
TcCase operating temperature - 40 to 150 °C
Tstg Storage temperature - 55 to 150 °C
Table 3. Absolute maximum ratings (continued)
Table 4. Thermal data
Symbol Parameter
Max. value
Unit
SO-16L P2PAK
Rthj-case Thermalresistance junction-case - 1.3 °C/W
Rthj-lead Thermalresistance junction-lead 15 - °C/W
Rthj-amb
Thermalresistance junction-
ambient 65 (1)
1. When mounted on FR4 printed circuit board with 0.5cm2 of Cu (at least 35µm thick) connected to all VCC
pins.
51.3(2)
2. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick).
°C/W
Electrical specifications VN920D-B5 / VN920DSO
8/32
2.3 Electrical characteristics
Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless otherwise
stated.
Table 5. Power
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC Operating supply voltage 5.5 13 36 V
VUSD Under-voltage shutdown 3 4 5.5 V
VUSDhyst
Under-voltage shutdown
hysteresis 0.5 V
VOV Over-voltage shutdown 36 V
RON On-state resistance
IOUT = 10A; Tj = 25°C;
IOUT = 10A;
IOUT = 3A; VCC = 6V
18
36
50
mΩ
mΩ
mΩ
ISSupply current
Off-state; VCC = 13V;
VIN = VOUT = 0V
Off-state; VCC = 13V;
VIN = VOUT = 0V; Tj = 25°C
On-state; VCC = 13V; VIN = 5V;
IOUT = 0A
10
10
25
20
3.5
µA
µA
mA
IL(off1) Off-state output current VIN = VOUT = 0V 0 50 µA
IL(off2) Off-state output current VIN = 0V; VOUT = 3.5V -75 0 µA
IL(off3) Off-state output current VIN = VOUT = 0V; VCC = 13V;
Tj = 125°C 5µA
IL(off4) Off-state output current VIN = VOUT = 0V; VCC = 13V;
Tj = 25°C 3µA
Table 6. Switching (VCC=13V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time RL = 1.3Ω 50 µs
td(off) Turn-off delay time RL = 1.3Ω50 µs
dVOUT/dt(on) Turn-on voltage slope RL = 1.3ΩSee Figure 20. V/µs
dVOUT/dt(off) Turn-off voltage slope RL = 1.3ΩSee Figure 21. V/µs
VN920D-B5 / VN920DSO Electrical specifications
9/32
Table 7. Input pin
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low-level 1.25 V
IIL Low-level input current VIN = 1.25V 1 µA
VIH Input high-level 3.25 V
IIH High-level input current VIN = 3.25V 10 µA
Vhyst Input hysteresis voltage 0.5 V
VICL Input clamp voltage IIN = 1mA
IIN = -1mA
66.8
- 0.7
8V
V
Table 8. VCC output diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
VFForward on voltage - IOUT = 5.5A; Tj = 150°C 0.7 V
Table 9. Status pin
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSTAT Status low output voltage ISTAT = 1.6mA 0.5 V
ILSTAT Status leakage current Normal operation; VSTAT = 5V 10 µA
CSTAT Status pin input capacitance Normal operation; VSTAT = 5V 100 pF
VSCL Status clamp voltage ISTAT = 1mA
ISTAT = - 1mA
66.8
- 0.7
8V
V
Table 10. Protections(1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device operates under
abnormal conditions this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature 135 °C
Thyst Thermal hysteresis 7 15 °C
tSDL
Status delay in overload
condition Tj > Tjsh 20 ms
Ilim Current limitation 5.5V < VCC < 36V
30 45 75
75
A
A
Vdemag
Turn-off output clamp
voltage
IOUT = 2 A;
VIN = 0V;
L = 6mH
VCC - 41 VCC - 48 VCC - 55 V
Electrical specifications VN920D-B5 / VN920DSO
10/32
Figure 4. Status timings
Figure 5. Switching time waveforms
Table 11. Open load detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
IOL
Open load on-state
detection threshold VIN = 5V 300 500 700 mA
tDOL(on)
Open load on-state
detection delay IOUT = 0A 250 µs
VOL
Open load off-state
voltage detection
threshold
VIN = 0V 1.5 2.5 3.5 V
tDOL(off)
Open load detection
delay at turn-off 1000 µs
V
IN
V
STAT
t
DOL(off)
OPEN LOAD STATUS TIMING
(with external pull-up) OVER-TEMP STATUS TIMING
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
T
j
> T
jsh
V
IN
V
STAT
t
SDL
t
SDL
t
t
VOUT
VIN
80%
10%
dVOUT/dt(on)
td(off)
90%
dVOUT/dt(off)
td(on)
VN920D-B5 / VN920DSO Electrical specifications
11/32
Table 12. Truth table
Conditions Input Output Status
Normal operation L
H
L
H
H
H
Current limitation
L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Over-temperature L
H
L
L
H
L
Under-voltage L
H
L
L
X
X
Over-voltage L
H
L
L
H
H
Output voltage > VOL
L
H
H
H
L
H
Output current < IOL
L
H
L
H
H
L
Table 13. Electrical transient requirements
ISO T/R
7637/1
Test pulse
Test level
I II III IV Delays and impedance
1- 25V
(1)
1. All functions of the device are performed as designed after exposure to disturbance.
- 50V(1) - 75V(1) - 100V(1) 2ms, 10Ω
2 + 25V(1) + 50V(1) + 75V(1) + 100V(1) 0.2ms, 10Ω
3a - 25V(1) - 50V(1) - 100V(1) - 150V(1) 0.1µs, 50Ω
3b + 25V(1) + 50V(1) + 75V(1) + 100V(1) 0.1µs, 50Ω
4- 4V
(1) - 5V(1) - 6V(1) - 7V(1) 100ms, 0.01Ω
5+ 26.5V
(1) + 46.5V(2)
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
proper operation without replacing the device.
+ 66.5V(2) + 86.5V(2) 400ms, 2Ω
Electrical specifications VN920D-B5 / VN920DSO
12/32
Figure 6. Waveforms
OPEN LOAD without external pull-up
STATUS
INPUT
NORMAL OPERATION
UNDER-VOLTAGE
V
CC
V
USD
V
USDhyst
INPUT
OVER-VOLTAGE
V
CC
V
CC
> V
OV
STATUS
INPUT
STATUS
STATUS
INPUT
STATUS
INPUT
OPEN LOAD with external pull-up
undefined
LOAD VOLTAGE
V
CC
<V
OV
LOAD VOLTAGE
LOAD VOLTAGE
LOAD VOLTAGE
LOAD VOLTAGE
OVER-TEMPERATURE
INPUT
STATUS
T
TSD
T
R
T
j
LOAD CURRENT
V
OUT
> V
OL
V
OL
VN920D-B5 / VN920DSO Electrical specifications
13/32
2.4 Electrical characteristics curves
Figure 7. Off-state output current Figure 8. High-level input current
Figure 9. Input clamp voltage Figure 10. Status leakage current
Figure 11. Status low output voltage Figure 12. Status clamp voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC )
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IL(off1) (µA )
Off state
Vcc=36V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iih (u A )
Vin=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vicl (V)
Ii n =1 m A
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC )
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0.045
0.05
Il s ta t(µA)
Vstat=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
V s tat (V )
Is tat=1.6mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vscl (V)
Is t a t =1 m A
Electrical specifications VN920D-B5 / VN920DSO
14/32
Figure 13. On-state resistance Vs Tcase Figure 14. On-state resistance Vs VCC
Figure 15. Over-voltage shutdown Figure 16. Input high-level
Figure 17. Input low-level Figure 18. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC )
0
5
10
15
20
25
30
35
40
45
50
Ron (mOhm)
Io u t =1 0 A
Vc c =8V; 36V
5 10152025303540
Vcc (V)
0
5
10
15
20
25
30
35
40
45
50
Ron (mOhm)
Io u t =10 A
Tc=150ºC
Tc=25ºC
Tc= -40ºC
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
30
32
34
36
38
40
42
44
46
48
50
Vov (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vil (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Vhyst (V)
VN920D-B5 / VN920DSO Electrical specifications
15/32
Figure 19. Ilim Vs Tcase Figure 20. Turn-on voltage slope
Figure 21. Turn-off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
10
20
30
40
50
60
70
80
90
100
Ilim (A )
Vcc=13V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC )
250
300
350
400
450
500
550
600
650
700
dVout/dt(on) (V/ms)
Vcc=13V
Rl=1.3Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
450
500
550
dVout/dt(off) (V/ms)
Vcc=13V
Rl=1.3Ohm
Application information VN920D-B5 / VN920DSO
16/32
3 Application information
Figure 22. Application schematic
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600mV / (IS(on)max).
2. RGND ≥ (- VCC) / (- IGND)
where - IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC < 0: during reverse battery situations) is:
PD= (- VCC)2/ RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high-side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
V
CC
GND
OUTPUT
D
GND
R
GND
D
ld
µ
C
+5V
R
prot
V
GND
STATUS
INPUT
+5V
R
prot
VN920D-B5 / VN920DSO Application information
17/32
3.1.2 Solution 2: diode (DGND) in the ground line
A resistor (RGND = 1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
Series resistor in INPUT and STATUS lines are also required to prevent that, during battery
voltage transient, the current exceeds the absolute maximum rating.
Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended values: Rprot =10kΩ .
Application information VN920D-B5 / VN920DSO
18/32
3.4
P
2
PAK
maximum demagnetization energy (VCC = 13.5V)
Figure 23.
P
2
PAK
maximum turn-off current versus inductance
Note: Values are generated with RL =0 Ω. In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
C: Tjstart = 125°C repetitive pulse
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
Demagnetization Demagnetization Demagnetization
t
VIN, IL
1
10
100
0.01 0.1 1 10 100
L(mH)
I
LMAX (A)
A
B
C
VN920D-B5 / VN920DSO Application information
19/32
3.5 SO-16L maximum demagnetization energy (V
CC
= 13.5V)
Figure 24. SO-16L maximum turn-off current versus inductance
Note: Values are generated with RL =0 Ω. In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
C: Tjstart = 125°C repetitive pulse
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
Demagnetization Demagnetization Demagnetization
t
VIN, IL
Package and PCB thermal data VN920D-B5 / VN920DSO
20/32
4 Package and PCB thermal data
4.1 SO-16L thermal data
Figure 25. SO-16L PC board
Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 41mm x 48mm, PCB
thickness = 2mm, Cu thickness = 35µm, Copper areas: 0.5cm2, 6cm2).
Figure 26. SO-16L Rthj-amb Vs PCB copper area in open box free air condition
40
45
50
55
60
65
70
01234567
PC B Cu heatsink area (cm^2)
RTH j-amb (°C/W)
VN920D-B5 / VN920DSO Package and PCB thermal data
21/32
Figure 27. SO-16L thermal impedance junction ambient single pulse
Equation 1: pulse calculation formula
Figure 28. Thermal fitting model of a single channel HSD in SO-16L
ZTHδRTH δZTHtp 1δ–()+⋅=
where
δtpT⁄=
T_amb
C1
R1 R2
C2
R3
C3
R4
C4
R5
C5
R6
C6
Pd
Tj
Package and PCB thermal data VN920D-B5 / VN920DSO
22/32
4.2 P2PAK thermal data
Figure 29. P2PAK PC b oard
Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 60mm x 60mm, PCB
thickness = 2 mm, Cu thickness = 35µm , Copper areas: 0.97cm2, 8cm2).
Table 14. SO-16L thermal parameters
Area / island (cm2) Footprint 6
R1 (°C/W) 0.02
R2 (°C/W) 0.1
R3 (°C/W) 2.2
R4 (°C/W) 12
R5 (°C/W) 15
R6 (°C/W) 35 20
C1 (W.s/°C) 0.0015
C2 (W.s/°C) 7E-03
C3 (W.s/°C) 1.5E-02
C4 (W.s/°C) 0.14
C5 (W.s/°C) 1
C6 (W.s/°C) 5 8
VN920D-B5 / VN920DSO Package and PCB thermal data
23/32
Figure 30. P2PAK Rthj-amb Vs. PCB copper area in open box free air condition
Figure 31. P2PAK thermal impedance junction ambient single pulse
30
35
40
45
50
55
024681
0
PCB Cu heatsink area
(
cm^2
)
RTHj_amb (°C/W)
Tj-Tamb=50°C
0.01
0.1
1
10
100
1000
0.0001 0.001 0.01 0.1 1 10 100 1000
Time (s)
ZT H (°C /W)
0.97 cm2
6 cm2
Package and PCB thermal data VN920D-B5 / VN920DSO
24/32
Equation 2: pulse calculation formula
where δ = tP/T
Figure 32. Thermal fitting model of a single channel HSD in P2PAK
Table 15. P2PAK thermal parameters
Area/island (cm2)0.976
R1 (°C/W) 0.02
R2 (°C/W) 0.1
R3 (°C/W) 0.22
R4 (°C/W) 4
R5 (°C/W) 9
R6 (°C/W) 37 22
C1 (W·s/°C) 0.0015
C2 (W·s/°C) 0.007
C3 (W·s/°C) 0.015
C4 (W·s/°C) 0.4
C5 (W·s/°C) 2
C6 (W·s/°C) 3 5
ZTHδRTH δZTHtp 1δ–()+⋅=
VN920D-B5 / VN920DSO Package and packing information
25/32
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 33. SO-16L package dimensions
Table 16. SO-16L mechanical data
DIM.
mm.
Min. Typ. Max.
A2.65
a1 0.1 0.2
a2 2.45
b 0.35 0.49
b1 0.23 0.32
C0.5
c1 45° (typ.)
Package and packing information VN920D-B5 / VN920DSO
26/32
DIM.
mm.
Min. Typ. Max.
D 10.1 10.5
E 10.0 10.65
e1.27
e3 8.89
F7.4 7.6
L 0.5 1.27
M0.75
S 8° (max.)
Table 16. SO-16L mechanical data (continued)
VN920D-B5 / VN920DSO Package and packing information
27/32
5.2 P2PAK mechanical data
Figure 34. P2PAK package dimensions
P010R
Package and packing information VN920D-B5 / VN920DSO
28/32
Table 17. P2PAK mechanical data
Dim.
mm
Min. Typ. Max.
A 4.30 4.80
A1 2.40 2.80
A2 0.03 0.23
b 0.80 1.05
c 0.45 0.60
c2 1.17 1.37
D 8.95 9.35
D2 8.00
E 10.00 10.40
E1 8.50
e 3.20 3.60
e1 6.60 7.00
L 13.70 14.50
L2 1.25 1.40
L3 0.90 1.70
L5 1.55 2.40
R0.40
V2 0º 8º
Package weight 1.40 Gr (typ)
VN920D-B5 / VN920DSO Package and packing information
29/32
5.3 SO-16L packing information
Figure 35. SO-16L tube shipment (no suffix)
Figure 36. SO-16L tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 50
Bulk Q.ty 1000
Tube length (± 0.5) 532
A3.5
B13.8
C (± 0.1) 0.6
A
C
B
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Reel dimensions
Package and packing information VN920D-B5 / VN920DSO
30/32
5.4 P2PAK packing information
Figure 37. P2PAK tube shipment (no suffix)
Figure 38. P2PAK tape and reel (suffix “13TR”)
All dimensions are in mm.
Base Q.ty 50
Bulk Q.ty 1000
Tube length (± 0.5) 532
A18
B33.1
C (± 0.1) 1
C
B
A
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
REEL DIMENSIONS
All dimensions are in mm.
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4
VN920D-B5 / VN920DSO Revision history
31/32
6 Revision history
Table 18. Document revision history
Date Revision Changes
09-Sep-2004 1 Initial release.
03-May-2006 2 Suggested connections for unused and n.c.pins correction (page 2).
19-Dec-2008 3
Document reformatted and restructured.
Added content, list of figures and tables.
Added ECOPACK® packages information.
Updated Figure 38.: P2PAK tape and reel (suffix “13TR”): changed
component spacing (P) in tape dimensions table from 16 mm to 12 mm.
VN920D-B5 / VN920DSO
32/32
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