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M34D64, M 34D 32
transition, and the data must change
only
when
the SCL line is lo w .
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type
Identifier, and a 3-bit Chip Enable “Address” (E2,
E1 , E0) .
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
If all three chip enable inputs are connected, up to
eight memory devices can be connected on a
single I2C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Dev ice
Select Code is received on the SDA bus, the
memory o nly responds if the Chip Select Code is
the same as the patt ern applied to its Chip Enable
pins.
The 8th b it is the R W bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding
memory gives an acknowledgment on the SDA
bus during the 9th bit time. If the memory does not
match the Device Select Code, it deselects itself
from t he bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte
(Table 4) is sent first, followed by the Least
significant By te (Table 5). B its b 15 to b0 form the
address of the byte in memory. Bits b15 to b13 are
treated as a Don’t Care bit on the M34D64
memory. Bits b15 to b12 are treated as Don’t Care
bits on the M34D3 2 memory.
Write Operations
Following a ST ART con dition t he master sen ds a
Device Select Code with the R W bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory
responds to each address byte with an
acknowledge bit, and then waits for t he data byt e.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the contents of the top quarter of
t he memo r y.
Table 3. Device Select Code 1
No te : 1 . The m ost sign ifican t bit, b7, is sent firs t.
Device Type Identifier Chip Enable RW
b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 E2 E1 E 0 RW
Table 4. Mos t Significant Byte
Note: 1. b15 to b13 are Don’t Car e on the M3 4D64 seri es.
b15 to b12 are Don’t Car e on the M3 4D32 seri es.
Table 5. Least Significant Byte
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4 b3 b2 b1 b0
Table 6. Operating Modes
No te: 1 . X = VIH or VIL.
Mode RW bit WC 1 Bytes Initial Sequence
Current Address Read 1 X 1 START, Device Select, RW = ‘1’
Random Address Read 0X1
START, Device Select, RW = ‘0’, Address
1 X reSTART, Device Select, RW = ‘1’
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0 VIL 1 START, Device Select, RW = ‘0’
Page Write 0 VIL ≤ 32 START, Device Select, RW = ‘0’