TQP3M9035 High Linearity LNA Gain Block Applications Repeaters Mobile Infrastructure LTE / WCDMA / CDMA / GSM General Purpose Wireless TDD or FDD systems 2x2mm 8-lead DFN plastic package Product Features Functional Block Diagram 50-4000 MHz 0.66 dB Noise Figure @ 1.9 GHz 16.5 dB Gain @ 1.9 GHz +37.0 dBm Output IP3 +22.5 dBm P1dB Shut-down capability Unconditionally stable 50 Ohm Cascadable Gain Block +5V Single Supply, 110 mA Current 2x2mm 8-lead DFN plastic package RF In General Description 1 8 2 7 RF Out 3 6 Shutdown 4 5 Pin Configuration The TQP3M9035 is a high linearity low noise gain block amplifier in a low-cost surface-mount package. At 1.9 GHz, the amplifier typically provides 16.5 dB gain, +37.0 dBm OIP3, and 0.66 dB Noise Figure. The LNA is also designed to be broadband without the requirement for external matching. The device is housed in a leadfree/green/RoHS-compliant industry-standard 2x2mm package. The TQP3M9035 has the benefit of having high linearity while also providing very low noise across a broad range of frequencies. This allows the device to be used in both receive and transmit chains for high performance systems. The amplifier is internally matched using a high performance E-pHEMT process and only requires an external RF choke and blocking/bypass capacitors for operation from a single +5V supply. The low noise amplifier integrates a shut-down biasing capability to allow for operation for TDD applications. Pin # Symbol 1,3,4,5,8 2 N/A RF Input 6 7 SD (Shutdown) RF Output Ordering Information The TQP3M9035 covers the 0.05 - 4 GHz frequency band and is targeted for wireless infrastructure or other applications requiring high linearity and/or low noise figure. Part No. Description TQP3M9035 TQP3M9035-PCB High Linearity LNA Gain Block 0.5-4 GHz Evaluation Board Standard T/R size = 2500 pieces on a 7" reel. Data Sheet: Rev B 09/24/12 (c) 2012 TriQuint Semiconductor, Inc. - 1 of 7 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network (R) TQP3M9035 High Linearity LNA Gain Block Specifications Absolute Maximum Ratings Recommended Operating Conditions Parameter Rating Parameter Storage Temperature Device Voltage,Vdd Max RF Input Power (continuous) -55 to +150 oC +6 V +23 dBm Vdd Tcase Tj (for>106 hours MTTF) Operation of this device outside the parameter ranges given above may cause permanent damage. Min Typ Max Units +5 -40 +5.25 85 190 V o C o C Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions. Electrical Specifications Test conditions unless otherwise noted: +25C, +5V Vsupply, 50 system. Parameter Conditions Operational Frequency Range Test Frequency Gain Min Typical 50 15 Input Return Loss Output Return Loss Output P1dB Output IP3 See Note 1. Noise Figure Vdd On state Off state Vsd > 3 V Current, Idd Shutdown pin current, Isd Thermal Resistance (jnc to case) jc +20 +32.5 1900 16.5 15 10 +22.5 +37.0 0.66 +5 Max Units 4000 MHz MHz dB 18 0.9 110 3.0 100 50 dB dB dBm dBm dB V mA mA A o C/W Notes 1. OIP3 measured with two tones at an output power of +4 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the OIP3 using 2:1 rule. Power Shutdown Control State Pin 6 Bias Condition On state 0.8 V Power down 3.0 V Data Sheet: Rev B 09/24/12 (c) 2012 TriQuint Semiconductor, Inc. - 2 of 7 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network (R) TQP3M9035 High Linearity LNA Gain Block Application Circuit Configuration C4 J3 VDD J4 J5 J3 1 uF J4 GND C3 R 3 100 pF L1 68 nH (0603) C2 C4 C3 RF Input L1 C1 C1 J1 C2 U1 2 7 Q1 6 100 pF 100 pF J2 RF Output 1,3,4,5,8 R2 R2 R1 33k C5 J5 PD R1 10k C6 Notes: 1. See PC Board Layout, page 5 for more information. 2. Components shown on the silkscreen but not on the schematic are not used. 3. R3 (0 jumper) may be replaced with copper trace in the target application layout. 4. All components are of 0402 size unless stated on the schematic. 5. C1, C2, and C3 are non-critical values. The reactive impedance should be as low as possible at the frequency of operation for optimal performance. 6. The L1 value is non-critical and needs to provide high reactive impedance at the frequency of operation. 7. R1 and R2 are optional and do not need to be loaded if the shut-down functionality is not needed; i.e. FDD applications. If R1 and R2 are not loaded, the LNA will operate in its standard "ON" state. 8. A through line is included on the evaluation board to de-embed the board losses. Bill of Material Reference Des. Value Description U1 R1 R2 R3 L1 C4 C1, C2, C3, C5, C6 J3, J4, J5 n/a 10K 33K 0 68 nH 1.0 uF 100 pF n/a TQP3M9035 Amplifier, 2x2 mm Package Resistor, Chip, 0402, 5%, 1/16W Resistor, Chip, 0402, 5%, 1/16W Resistor, Chip, 0402, 5%, 1/16W Inductor, 0603, 5%, Ceramic Cap., Chip, 0402, 10%, 10V, X5R Cap., Chip, 0402, 5%, 50V, NPO/COG Solder Turret Data Sheet: Rev B 09/24/12 (c) 2012 TriQuint Semiconductor, Inc. - 3 of 7 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network (R) TQP3M9035 High Linearity LNA Gain Block Typical Performance TQP3M9035-PCB Test conditions unless otherwise noted: +25C, +5V, 110 mA, 50 system. The data shown below is measured on TQP3M9035-PCB. Frequency MHz 900 1900 2600 dB 22.0 16.5 14.0 dB dB dBm 14 13 +22.6 15 10 +22.5 15 8 +22.5 dBm +37.2 +37.0 +37.3 dB 0.55 0.66 1.0 Gain Input Return Loss Output Return Loss Output P1dB OIP3 [1] Noise Figure [2] Notes: 1. OIP3 measured with two tones at an output power of +4 dBm / tone separated by 1 MHz. The suppression on the largest IM3 product is used to calculate the OIP3 using 2:1 rule. 2. Noise figure data shown in the table above is de-embedded to the device leads and removes PCB losses. RF Performance Plots Gain vs. Frequency 30 Input Return Loss vs. Frequency 0 Input Return Loss (dB) Gain (dB) 25 20 15 10 5 0 -10 500 1000 1500 2000 2500 3000 3500 -15 -15 -20 4000 -20 -25 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 Frequency (MHz) P1dB vs. Frequency 23 -5 -10 Frequency (MHz) 1500 2000 2500 3000 3500 4000 Frequency (MHz) OIP3 vs. Pout/tone 50 22 Noise Figure vs. Frequency 2 900 MHz 45 1900 MHz 1.5 21 20 NF (dB) 2600 MHz OIP3 (dBm) P1dB (dBm) Temp.=+25C -5 -25 0 Output Return Loss vs. Frequency 0 Temp.=+25C Output Return Loss (dB) Temp.=+25C 40 35 1 0.5 19 30 18 0 25 0 500 1000 1500 2000 2500 3000 3500 4000 0 1 2 Frequency (MHz) 3 4 5 6 7 8 0 500 1000 1500 2000 2500 3000 3500 4000 Frequency (MHz) Pout/Tone (dBm) Idd vs. Shutdown Voltage 140 120 +85 C Idd (mA) 100 +25 C - 40 C 80 60 40 20 0 -20 0 1 2 3 4 5 Shutdown Voltage (V) Data Sheet: Rev B 09/24/12 (c) 2012 TriQuint Semiconductor, Inc. - 4 of 7 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network (R) TQP3M9035 High Linearity LNA Gain Block Pin Configuration and Description RF In Pin 1 8 2 7 RF Out 3 6 Shutdown 4 5 Symbol Description 2 RF IN RF Input, DC Block Required 6 SD 7 RF OUT/BIAS Shut-down pin. A high voltage turns off the device. If the pin is not connected or is less than 1V, then the device will operate under its normal operating condition. RF Output, 5V DC Bias N/A Ground or No-connect. No internal connection. 1,3,4,5,8 Evaluations Board PCB Specifications Matirial Stack-Up and Layout 0.010" 0.062" 0.006" Finished Board Thickness Rogers 4350B r=3.7 typ. 1 oz. Cu top layer 1 oz. Cu inner layer Rogers 4450F 1 oz. Cu inner layer 0.010" Rogers 4350B 1 oz. Cu bottom layer The pad pattern shown has been developed and tested for optimized assembly at TriQuint Semiconductor. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from supplier to supplier, careful process development is recommended. Data Sheet: Rev B 09/24/12 (c) 2012 TriQuint Semiconductor, Inc. - 5 of 7 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network (R) TQP3M9035 High Linearity LNA Gain Block Mechanical Information Package Information and Dimensions 935 XXX This package is lead-free/RoHScompliant. The plating material on the backside and leads is annealed matte tin. The component will be marked with a "935" designator with an alphanumeric lot code on the top surface of package. The "XXX" is an auto generated number. PCB Mounting Pattern All dimensions are in millimeters (inches). Angles are in degrees. 3 Notes: 1. Ground / thermal vias are critical for the proper performance of this device. Vias should use a .35mm (#80 / .0135") diameter drill and have a final plated thru diameter of .25 mm (.010"). 2. Add as much copper as possible to inner and outer layers near the part to ensure optimal thermal performance. 3. RF trace width depends upon the PC board material and construction. 4. Use 1 oz. Copper minimum. Data Sheet: Rev B 09/24/12 (c) 2012 TriQuint Semiconductor, Inc. - 6 of 7 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network (R) TQP3M9035 High Linearity LNA Gain Block Product Compliance Information ESD Information Solderability Compatible with the latest version of J-STD-020, Lead free solder, 260 ESD Rating: Value: Test: Standard: Class 0 Passes 100V on SD pin (6) Passes 250V on RF pins (2, 7) Human Body Model (HBM) JEDEC Standard JESD22-A114 ESD Rating: Value: Test: Standard: Class IV Passes 100V Charged Device Model (CDM) JEDEC Standard JESD22-C101 This part is compliant with EU 2002/95/EC RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and Electronic Equipment). This product also has the following attributes: Lead Free Halogen Free (Chlorine, Bromine) Antimony Free TBBP-A (C15H12Br402) Free PFOS Free SVHC Free MSL Rating The part is rated Moisture Sensitivity Level 1 at 260C per JEDEC standard IPC/JEDEC J-STD-020. Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: info-sales@tqs.com Tel: Fax: +1.503.615.9000 +1.503.615.8902 For technical questions and application information: Email: sjcapplications.engineering@tqs.com Important Notice The information contained herein is believed to be reliable. TriQuint makes no warranties regarding the information contained herein. TriQuint assumes no responsibility or liability whatsoever for any of the information contained herein. TriQuint assumes no responsibility or liability whatsoever for the use of the information contained herein. The information contained herein is provided "AS IS, WHERE IS" and with all faults, and the entire risk associated with such information is entirely with the user. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for TriQuint products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. TriQuint products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Data Sheet: Rev B 09/24/12 (c) 2012 TriQuint Semiconductor, Inc. - 7 of 7 - Disclaimer: Subject to change without notice Connecting the Digital World to the Global Network (R)