MT16LSDF32264HG-133B1 - Micron Technology, Inc.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

SMALL-OUTLINE

SDRAM MODULE

MT16LSDF3264(L)H – 256MB

MT16LSDF6464(L)H – 512MB

For the latest data sheet, please refer to the Micron® Web

site: www.micron.com/products/modules

Features

• PC100- and PC133-compliant, 144-pin, small-

outline, dual in-line memory module (SODIMM)

• Utilizes 100 MHz and 133 MHz SDRAM components

• Unbuffered

• 256MB (32 Meg x 64) and 512MB (64 Meg x 64)

• Single +3.3V power supply

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal SDRAM banks for hiding row access/

precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge and auto refresh modes

• Self refresh mode: standard and low-power

• 256MB module: 64ms, 4,096-cycle refresh (15.625µs

refresh interval); 512MB: 64ms, 8,192-cycle refresh

(7.81µs refresh interval)

• LVTTL-compatible inputs and outputs

• Serial presence-detect (SPD)

• Gold edge connectors

Figure 1: 144-Pin SODIMM (MO-190)

NOTE: 1. Contact Micron for product availability.

Table 1: Timing Parameters

CL = CAS (READ) latency

MODULE

MARKING

CLOCK

FREQUENCY

ACCESS TIME SETUP

TIME

HOLD

TIMECL = 2 CL = 3

-13E 133 MHz 5.4ns – 1.5ns 0.8ns

-133 133 MHz – 5.4ns 1.5ns 0.8ns

-10E 100 MHz 6ns – 2ns 1ns

Options Marking

• Self refresh current

Standard None

Low power L1

•Package

144-pin SODIMM (standard) G

144-pin SODIMM (lead-free) Y1

• Memory Clock/CL

7.5ns (133 MHz)/CL = 2 -13E

7.5ns (133 MHz)/CL = 3 -133

10ns (100 MHz)/CL = 2 -10E

•PCB

Height 1.25in (31.75mm) See page 2 note

PCB height: 1.25in (31.75mm)

Table 2: Address Table

256MB 512MB

Refresh count 4K 8K

Device banks 4 (BA0, BA1) 4 (BA0, BA1)

Device configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8)

Row addressing 4K (A0–A11) 8K (A0–A12)

Column addressing 1K (A0–A9) 1K (A0–A9)

Module ranks 2 (S0#, S1#) 2 (S0#, S1#))

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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NOTE:

1. The designators for component and PCB revision are the last two characters of each part number Consult factory for

current revision codes. Example: MT16LSDF32264(L)HG-133B1.

Table 3: Part Numbers

PART NUMBER

MODULE DENSITY CONFIGURATION

SYSTEM

BUS SPEED

MT16LSDF3264(L)HG-13E_ 256MB 32 Meg x 64 133 MHz

MT16LSDF3264(L)HY-13E_ 256MB 32 Meg x 64 133 MHz

MT16LSDF3264(L)HG-133_ 256MB 32 Meg x 64 133 MHz

MT16LSDF3264(L)HY-133_ 256MB 32 Meg x 64 133 MHz

MT16LSDF3264(L)HG-10E_ 256MB 32 Meg x 64 100 MHz

MT16LSDF3264(L)HY-10E_ 256MB 32 Meg x 64 100 MHz

MT16LSDF6464(L)HG-13E_ 512MB 64 Meg x 64 133 MHz

MT16LSDF6464(L)HY-13E_ 512MB 64 Meg x 64 133 MHz

MT16LSDF6464(L)HG-133_ 512MB 64 Meg x 64 133 MHz

MT16LSDF6464(L)HY-133_ 512MB 64 Meg x 64 133 MHz

MT16LSDF6464(L)HG-10E_ 512MB 64 Meg x 64 100 MHz

MT16LSDF6464(L)HY-10E_ 512MB 64 Meg x 64 100 MHz

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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NOTE:

1. Pin 70 is No Connect for 256MB modules, or A12 for 512MB modules.

Figure 2: Pin Locations (144-Pin SODIMM)

Table 4: Pin Assignment

(144-Pin SODIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VSS 37 DQ8 73 NC 109 A9

3DQ039DQ975 Vss 111 A10

5 DQ1 41 DQ10 77 NC 113 VDD

7DQ243 DQ11 79 NC 115 DQMB2

9DQ345 VDD 81 VDD 117 DQMB3

11 VDD 47 DQ12 83 DQ16 119 VSS

13 DQ4 49 DQ13 85 DQ17 121 DQ24

15 DQ5 51 DQ14 87 DQ18 123 DQ25

17 DQ6 53 DQ15 89 DQ19 125 DQ26

19 DQ7 55 VSS 91 VSS 127 DQ27

21 VSS 57 NC 93 DQ20 129 VDD

23 DQMB0 59 NC 95 DQ21 131 DQ28

25 DQMB1 61 CK0 97 DQ22 133 DQ29

27 VDD 63 VDD 99 DQ23 135 DQ30

29 A0 65 RAS# 101 VDD 137 DQ31

31 A1 67 WE# 103 A6 139 VSS

33 A2 69 S0# 105 A8 141 SDA

35 VSS 71 S1# 107 VSS 143 VDD

Table 5: Pin Assignment

(144-Pin SODIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

2Vss38 DQ40 74 CK1 110 BA1

4 DQ32 40 DQ41 76 VSS 112 A11

6 DQ33 42 DQ42 78 NC 114 VDD

8 DQ34 44 DQ43 80 NC 116 DQMB6

10 DQ35 46 VDD 82 VDD 118 DQMB7

12 VDD 48 DQ44 84 DQ48 120 VSS

14 DQ36 50 DQ45 86 DQ49 122 DQ56

16 DQ37 52 DQ46 88 DQ50 124 DQ57

18 DQ38 54 DQ47 90 DQ51 126 DQ58

20 DQ39 56 VSS 92 VSS 128 DQ59

22 VSS 58 NC 94 DQ52 130 VDD

24 DQMB4 60 NC 96 DQ53 132 DQ60

26 DQMB5 62 CKE0 98 DQ54 134 DQ61

28 VDD 64 VDD 100 DQ55 136 DQ62

30 A3 66 CAS# 102 VDD 138 DQ63

32 A4 68 CKE1 104 A7 140 VSS

34 A5 70 NC/A121106 BA0 142 SCL

36 VSS 72 NC 108 VSS 144 VDD

U1 U2 U17 U10 U9

U3 U4 U5 U6 U7 U8 U16 U15 U14 U13 U12 U11

Back View

Front View

PIN 1 PIN 143

(all odd pins) PIN 2

PIN 144 (all even pins)

Indicates a V

DD or VDDQ pin Indicates a VSS pin

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Table 6: Pin Descriptions

Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

65, 66, 67 RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define

the command being entered.

61, 74 CK0, CK1 Input Clock: CK is driven by the system clock. All SDRAM input

signals are sampled on the positive edge of CK. CK also

increments the internal burst counter and controls the output

registers.

62, 68 CKE0, CKE1 Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the

CK signal. Deactivating the clock provides PRECHARGE power-

down and SELF REFRESH operation (all device banks idle),

ACTIVE power-down (row ACTIVE in any device bank), or

CLOCK SUSPEND operation (burst access in progress). CKE is

synchronous except after the device enters power-down and

self refresh modes, where CKE becomes asynchronous until

after exiting the same mode. The input buffers, including CK,

are disabled during power-down and self refresh modes,

providing low standby power.

69, 71 S0#,S1# Input Chip select: S# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are

masked when S# is registered HIGH. S# is considered part of

the command code.

23, 24, 25, 26, 115, 116, 117,

118

DQMB0–DQMB7 Input Input/output mask: DQMB is an input mask signal for write

accesses and an output enable signal for read accesses. Input

data is masked when DQMB is sampled HIGH during a WRITE

cycle. The output buffers are placed in a High-Z state (two-

clock latency) when DQMB is sampled HIGH during a READ

cycle.

106, 110 BA0, BA1 Input Bank address: BA0 and BA1 define to which device bank the

ACTIVE, READ, WRITE, or PRECHARGE command is being

applied.

29, 30, 31, 32, 33, 34,

70 (512MB), 103, 104, 105,

109, 111, 112

A0–A11

(256MB)

A0–A12

(512MB)

Input Address inputs: Provide the row address for ACTIVE commands

and the column address and auto precharge bit (A10) for

READ/WRITE commands, to select one location out of the

memory array in the respective device bank. A10 sampled

during a PRECHARGE command determines whether the

PRECHARGE applies to one device bank (A10 LOW, device

bank selected by BA0, BA1) or all device banks (A10 HIGH).

The address inputs also provide the op-code during a MODE

142 SCL Input Serial clock for presence-detect: scl is used to synchronize the

presence-detect data transfer to and from the module.

141 SDA Input/

Output

Serial presence-detect data: sda is a bidirectional pin used to

transfer addresses and data into and data out of the presence-

detect portion of the module.

3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15,

16, 17, 18,19, 20, 37, 38, 39,

40, 41, 42, 43, 44, 47, 48, 49,

50, 51, 52, 53, 54, 83, 84, 85,

86, 87, 88, 89, 90, 93, 94, 95,

96, 97, 98, 99, 100, 121, 122,

123, 124, 125, 126, 127, 128,

131, 132, 133, 134, 135, 136,

137, 138

DQ0–DQ63 Input/

Output

Data I/O: Data bus.

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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11, 12, 27, 28, 45, 46, 63, 64,

81, 82, 101, 102, 113, 114, 129,

130, 143, 144

VDD Supply Power supply: +3.3V ±0.3V.

1, 21, 35, 55, 75, 91, 107, 119,

139, 2, 22, 36, 56, 76, 92, 108,

120, 140

VSS Supply Ground.

57, 58, 59, 60, 70 (256MB), 72,

73, 77, 78, 79, 80

NC – Not connected: These pins should be left unconnected.

Table 6: Pin Descriptions (Continued)

Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Figure 3: Functional Block Diagram

RAS#

CAS# CAS#: SDRAMs

WE#: SDRAMs

A0-A11: SDRAMs

A0-A12: SDRAMs

BA0, BA1: SDRAMs

(256MB) A0–A11

(512MB) A0–A12

BA0, BA1

SDRAMs

CLK (U6, U7, U14, U15)

CLK (U2, U8, U10, U16)

CS# DQM

RAS#: SDRAMs

WE#

SERIAL PD

SDA

SCL

A0 A1 A2

CLK (U1, U3, U9, U11)

CLK (U4, U5, U12, U13)

CK0

CK1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB0

U11

DQM CS#

U13

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

CKE0 CKE0 (U1–U8)

U17

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB3

U15

U16

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U12

U14

U10

DQMB1

DQM CS#

CS# DQM

S0#

CS# DQM

DQMB2

DQM CS#

CS# DQM DQM CS#

DQMB4

DQM CS#

CS# DQM

DQMB5

DQM CS#

CS# DQM

DQMB6

DQM CS#

CS# DQM

DQMB7

DQM CS#

CS# DQM

CKE1 CKE1 (U9–U16)

0Ω

S1#

0Ω

0Ω0Ω

0Ω

NOTE:

1. All resistor values are 10Ω unless otherwise specified.

2. Per industry standard, Micron utilizes various component speed grades

as referenced in the module part numbering guide at www.micron.com/

support/numbering.html.

Standard modules use the following SDRAM devices:

MT48LC16M8A2FB (256MB); MT48LC32M8A2FB (512MB)

Lead-free modules use the following SDRAM devices:

MT48LC16M8A2BB (256MB); MT48LC32M8A2BB (512MB)

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

pdf: 09005aef807924d2, source: 09005aef807924f1 Micron Technology, Inc., reserves the right to change products or specifications without notice.

General Description

The MT16LSDF3264(L)H and MT16LSDF6464(L)H

are high-speed CMOS, dynamic random-access

256MB and 512MB unbuffered memory modules,

organized in x64 configurations. These modules use

internally configured quad-bank SDRAMs with a syn-

chronous interface (all signals are registered on the

positive edge of the clock signal CK).

Read and write accesses to the SDRAM modules are

burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a

programmed sequence. Accesses begin with the regis-

tration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the device bank and row to be

accessed (BA0, BA1 select the device bank, A0–A11

[256MB] or A0–A12 [512MB] select the device row).

The address bits A0–A9 (for both 256MB and 512MB

modules) registered coincident with the READ or

WRITE command are used to select the starting device

column location for the burst access.

These modules provide for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

page, with a burst terminate option. An auto precharge

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst

sequence.

These modules use an internal pipelined architec-

ture to achieve high-speed operation. This architec-

ture is compatible with the 2n rule of prefetch

architectures, but it also enables the column address

to be changed on every clock cycle to achieve a high-

speed, fully random access. Precharging one device

bank while accessing one of the other three device

banks will hide the precharge cycles and provide

seamless, high-speed, random-access operation.

These modules are designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is pro-

vided, along with a power-saving, power-down mode.

All inputs and outputs are LVTTL-compatible.

SDRAM modules offer substantial advances in

DRAM operating performance, including the ability to

synchronously burst data at a fast data rate with auto-

matic column-address generation, the ability to inter-

leave between internal banks in order to hide

precharge time and the capability to randomly change

column addresses on each clock cycle during a burst

access. For more information regarding SDRAM opera-

tion, refer to the 128Mb or 256Mb SDRAM component

data sheets.

Serial Presence Detect Operation

These modules incorporate serial presence-detect

(SPD). The SPD function is implemented using a

2,048-bit EEPROM. This nonvolatile storage device

contains 256 bytes. The first 128 bytes are programmed

by Micron to identify the module type, SDRAM charac-

teristics and module timing parameters. The remain-

ing 128 bytes of storage are available for use by the

customer. System READ/WRITE operations between

the master (system logic) and the slave EEPROM

device (DIMM) occur via a standard I2C bus using the

DIMM’s SCL (clock) and SDA (data) signals, together

with SA[2:0], which provide eight unique DIMM/

EEPROM addresses. Write protect (WP) is tied to

ground on the module, permanently disabling hard-

ware write protect.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other

than those specified may result in undefined opera-

tion. When power is applied to VDD and VDDQ (simul-

taneously), and the clock is stable (stable clock is

defined as a signal cycling within timing constraints

specified for the clock pin), the SDRAM requires a

100µs delay prior to issuing any command other than a

COMMAND INHIBIT or NOP. Starting at some point

during this 100µs period and continuing at least

through the end of this period, COMMAND INHIBIT

or NOP commands should be applied.

When the 100µs delay has been satisfied with at

least one COMMAND INHIBIT or NOP command hav-

ing been applied, a PRECHARGE command should be

applied. All device banks must then be precharged,

thereby placing the device in the all banks idle state.

When in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles

are complete, the SDRAM is ready for mode register

programming. Because the mode register will power

up in an unknown state, it should be loaded prior to

applying any operational command.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the SDRAM. This definition

includes the selection of a burst length, a burst type, a

CL, an operating mode, and a write burst mode, as

shown in Figure 4 on page 8. The mode register is pro-

grammed via the LOAD MODE REGISTER command

and will retain the stored information until it is pro-

grammed again or the device loses power.

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Mode register bits M0–M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-

leaved), M4–M6 specify the CL, M7 and M8 specify the

operating mode, M9 specifies the write burst mode,

and M10 and M11 are reserved for future use. For the

256MB and 512MB, M12 (A12) is undefined, but

should be driven LOW during loading of the mode reg-

ister.

The mode register must be loaded when all device

banks are idle, and the controller must wait the speci-

fied time before initiating the subsequent operation.

Violating either of these requirements will result in

unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as

shown in Figure 4. The burst length determines the

maximum number of column locations that can be

accessed for a given READ or WRITE command. Burst

lengths of 1, 2, 4, or 8 locations are available for both

the sequential and the interleaved burst types, and a

full-page burst is available for the sequential type. The

full-page burst is used in conjunction with the BURST

TERMINATE command to generate arbitrary burst

lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached, as shown in Table 7 on

page 9. The block is uniquely selected by A1–A9 when

the burst length is set to two; by A2–A9 when the burst

length is set to four; and by A3–A9 when the burst

length is set to eight. The remaining (least significant)

address bit(s) is (are) used to select the starting loca-

tion within the block. Full-page bursts wrap within the

page if the boundary is reached, as shown in Table 7 on

page 9.

Figure 4: Mode Register Definition

Diagram

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

512MB Module

256MB Module

Burst LengthCAS LatencyBT

A9 A7 A6A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9765438210

M6-M0

M8 M7

Op Mode

A10

A11

1011

Reserved*WB

Write Burst Mode

Programmed burst length

Single location access

*Should program

M12, M11, and

M10 = “0, 0, 0”

to ensure

compatibility with

future devices.

*Should program

M11 and M10 = “0, 0”

to ensure compatibility

with future devices.

A12

Burst LengthCAS LatencyBT

A9 A7 A6A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9765438210

Op Mode

A10

A11

1011

Reserved*

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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NOTE:

1. For full-page accesses: y = 1,024 (both 256MB and

512MB modules)

2. For a burst length of two, A1–A9 select the block-of-

two burst; A0 selects the starting column within the

block.

3. For a burst length of four, A2–A9 select the block-of-

four burst; A0–A1 select the starting column within the

block.

4. For a burst length of eight, A3–A9 select the block-of-

eight burst; A0–A2 select the starting column within

the block.

5. For a full-page burst, the full row is selected and A0–A9

select the starting column.

6. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps

within the block.

7. For a burst length of one, A0–A9 select the unique col-

umn to be accessed, and mode register bit M3 is

ignored.

Figure 5: CL Diagram

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type, and the

starting column address, as shown in Table 7.

CAS Latency (CL)

CL is the delay, in clock cycles, between the registra-

tion of a READ command and the availability of the

first piece of output data. The latency can be set to two

or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

by clock edge n + m. The DQ will start driving as a

result of the clock edge one cycle earlier (n + m - 1),

and provided that the relevant access times are met,

the data will be valid by clock edge n + m. For example,

assuming that the clock cycle time is such that all rele-

vant access times are met, if a READ command is regis-

tered at T0 and the latency is programmed to two

clocks, the DQ will start driving after T1 and the data

will be valid by T2, as shown in Figure 4 on page 8.

Table 8 on page 10 indicates the operating frequencies

at which each CL setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Table 7: Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES

WITHIN A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

00-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full

Page

(y)

n = A0-A9

(location

0-y)

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

…Cn - 1, Cn…

Not supported

CLK

T2T1 T3T0

CAS Latency = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CAS Latency = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values

for M7 and M8 are reserved for future use and/or test

modes. The programmed burst length applies to both

READ and WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with

future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-

M2 applies to both READ and WRITE bursts; when

M9 = 1, the programmed burst length applies to READ

bursts, but write accesses are single-location (non-

burst) accesses.

Table 8: CL Table

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHz)

SPEED CL = 2 CL = 3

-13E ≤ 133 < 143

-133 ≤ 100 < 133

-10E ≤ 100 ≤ NA

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Commands

The Truth Table provides a quick reference of avail-

able commands. This is followed by written descrip-

tion of each command. For a more detailed

description of commands and operations, refer to the

128Mb or 256Mb SDRAM component data sheet.

NOTE:

1. A0–A11 (256MB) or A0–A12 (512MB) provide device row address, and BA0, BA1 determine which device bank is made

active.

2. A0–A9 (256MB and 512MB) provide device column address; A10 HIGH enables the auto precharge feature (nonpersis-

tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or

written to.

3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and

BA0, BA1 are “Don’t Care.”

4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

6. A0–A11 define the op-code written to the mode register; for the 256MB and 512MB, A12 should be driven low.

7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

Table 9: Truth Table – SDRAM Commands and DQMB Operation

CKE is HIGH for all commands shown except SELF REFRESH

NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQ NOTES

COMMAND INHIBIT (NOP) HXXX X X X

NO OPERATION (NOP) LHHH X X X

ACTIVE (select bank and activate row) L L H H X Bank/Row X 1

READ (select bank and column, and start READ burst) LH L H

L/H8Bank/Col X 2

WRITE (select bank and column, and start WRITE burst) LH L LL/H8Bank/Col Valid 2

BURST TERMINATE LH H L X X Active

PRECHARGE (deactivate row in bank or banks) LL H L X Code X 3

AUTO REFRESH or SELF REFRESH

(enter self refresh mode)

LL L H X X X 4, 5

LOAD MODE REGISTER LLLL XOp-codeX 6

Write enable/output enable –––– L –Active7

Write inhibit/output High-Z –––– H –High-Z7

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

Voltage on VDD Supply,

Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to VSS . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Operating Temperature,

TOPR (Commercial - ambient) . . . . . .0°C to +65°C

Storage Temperature (plastic) . . . . . . -55°C to +125°C

Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1, 5, 6; notes appear on page 16; VDD, VDDQ = +3.3V ±0.3V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply voltage VDD, VDDQ3 3.6 V

Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22

Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 22

Input leakage current:

Any input 0V ≤ VIN ≤ VDD

(All other pins not under test = 0V)

Command and

Address Inputs

–80 80

µA 33

CK, CKE, S# –40 40

DQMB –10 10

Output leakage current: DQ pins are disabled;

0V ≤ VOUT ≤ VDDQ

DQ IOZ –10 10 µA 33

Output levels:

Output High Voltage (IOUT = -4mA)

Output Low Voltage (IOUT = 4mA)

VOH 2.4 – V

VOL –0.4V

Table 11: IDD Specifications and Conditions – 256MB

Notes: 1, 5, 6, 11, 13; SDRAM components only; notes appear on page 16; VDD, VDDQ = +3.3V ±0.3V

MAX

PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES

Operating current: Active mode; Burst = 2; READ or WRITE;

tRC = tRC (MIN)

IDD1a1,296 1,216 1,136 mA 3, 17, 19, 32

Standby current: Power-down mode; All device banks idle;

CKE = LOW IDD2b32 32 32 mA 32

Standby current: Active mode;

CKE = HIGH; CS# = HIGH; All device banks active after tRCD

met; No accesses in progress

IDD3a416 416 336 mA 3, 12, 19, 32

Operating current: Burst mode; Continuous burst; READ or

WRITE; All device banks active IDD4a1,336 1,216 1,136 mA 3, 18, 19, 32

Auto refresh current

CKE = HIGH; S# = HIGH

tRFC = tRFC (MIN) IDD5b5,280 4,960 4,320 mA 3, 12, 18, 19,

32,30

tRFC = 15.625µs IDD6b48 48 48 mA

Self refresh current: CKE ≤ 0.2V Standard IDD7b32 32 32 mA 4

Low power (L) IDD7b16 16 16 mA

a - Value calculated as one module rank in this operating condition, and all other ranks in power-down mode.

b - Value calculated reflects all module ranks in this operation condition.

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Table 12: IDD Specifications and Conditions – 512MB

Notes: 1, 5, 6, 11, 13; SDRAM components only; notes appear on page 16; VDD, VDDQ = +3.3V ±0.3V

MAX

PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES

Operating current: Active mode; Burst = 2; READ or WRITE;

tRC = tRC (MIN) IDD1a1,096 1,016 1,016 mA 3, 17,19, 32

Standby current: Power-down mode; All device banks idle;

CKE = LOW IDD2b32 32 32 mA 32

STANDBY CURRENT: Active mode;

CKE = HIGH; CS# = HIGH; All device banks active after tRCD

met; No accesses in progress

IDD3a336 336 336 mA 3, 12, 19, 32

OPERATING CURRENT: Burst mode; Continuous burst; READ

or WRITE; All device banks active IDD4a1,096 1,096 1,096 mA 3, 18, 19, 32

Auto refresh current

CKE = HIGH; S# = HIGH

tRFC = tRFC (MIN) IDD5b4,560 4,320 4,320 mA 3, 12, 18, 19,

32,30

tRFC = 7.8125µs IDD6b56 56 56 mA

Self refresh current: CKE < 0.2V Standard IDD7b40 40 40 mA 4

Low power (L) IDD7b24 24 24 mA

a - Value calculated as one module rank in this operating condition, and all other ranks in power-down mode.

b - Value calculated reflects all module ranks in this operation condition.

Table 13: Capacitance

Note 2; notes appear on page 16

PARAMETER SYMBOL MIN MAX UNITS

Input capacitance: Address and command CI1 40 60.8 pF

Input capacitance: CK CI2 20 28 pF

Input capacitance: CKE, S# CI3 20 30.4 pF

Input capacitance: DQMB CI4 57.6pF

Input/output capacitance: DQ CIO 812pF

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Table 14: Electrical Characteristics and Recommended AC Operating Conditions

Notes: 5, 6, 8, 9, 11, 31; notes appear on page 16; comply with PC100 and PC133 specifications, based on SDRAM device

AC CHARACTERISTICS -13E -133 -10E

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Access time from

CLK (positive edge)

CL = 3 tAC(3) 5.4 5.4 6 ns 27

CL = 2 tAC(2) 5.4 6 6 ns

Address hold time tAH 0.8 0.8 1 ns

Address setup time tAS 1.5 1.5 2 ns

CLK high-level width tCH 2.5 2.5 3 ns

CLK low-level width tCL 2.5 2.5 3 ns

Clock cycle time CL = 3 tCK(3) 77.58 ns23

CL = 2 tCK(2) 7.5 10 10 ns 23

CKE hold time tCKH 0.8 0.8 1 ns

CKE setup time tCKS 1.5 1.5 2 ns

CS#, RAS#, CAS#, WE#, DQM hold

time

tCMH 0.8 0.8 1 ns

CS#, RAS#, CAS#, WE#, DQM setup

time

tCMS 1.5 1.5 2 ns

Data-in hold time tDH 0.8 0.8 1 ns

Data-in setup time tDS 1.5 1.5 2 ns

Data-out High-Z time CL = 3 tHZ(3) 5.4 5.4 6 ns 10

CL = 2 tHZ(2) 5.4 6 6 ns 10

Data-out Low-Z time tLZ 111 ns

Data-out hold time (load) tOH 333 ns

Data-out hold time (no load) tOHN 1.8 1.8 1.8 ns 28

ACTIVE-to-PRECHARGE command tRAS 37 120,000 44 120,000 50 120,000 ns 32

ACTIVE-to-ACTIVE command period tRC 60 66 70 ns

ACTIVE-to-READ or WRITE delay tRCD 15 20 20 ns

Refresh period tREF 64 64 64 ms

AUTO REFRESH period tRFC 66 66 70 ns

PRECHARGE command period tRP 15 20 20 ns

ACTIVE bank a to ACTIVE bank b

command

tRRD 14 15 20 ns

Transition time tT0.3 1.2 0.3 1.2 0.3 1.2 ns 7

WRITE recovery time tWR 1 CLK

+ 7ns

1 CLK +

7.5ns

1 CLK

+ 7ns

ns 24

14 15 15 ns 25

Exit SELF REFRESH to ACTIVE

command

tXSR 67 75 80 ns 20

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Table 15: AC Functional Characteristics

Notes: 5, 6, 7, 8, 9, 11, 31; notes appear on page 16; comply with PC100 and PC133 specifications, based on SDRAM device

PARAMETER SYMBOL -13E -133 -10E UNITS NOTES

READ/WRITE command to READ/WRITE command tCCD 111

tCK 17

CKE to clock disable or power-down entry mode tCKED 111

tCK 14

CKE to clock enable or power-down exit setup mode tPED 11 1

tCK 14

DQM to input data delay tDQD 000

tCK 17

DQM to data mask during WRITEs tDQM 000

tCK 17

DQM to data High-Z during READs tDQZ 222

tCK 17

WRITE command to input data delay tDWD 000

tCK 17

Data-in to ACTIVE command tDAL 454

tCK 15, 21

Data-in to PRECHARGE command tDPL 222

tCK 16, 21

Last data-in to burst STOP command tBDL 111

tCK 17

Last data-in to new READ/WRITE command tCDL 11 1

tCK 17

Last data-in to PRECHARGE command tRDL 222

tCK 16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH

command

tMRD 222

tCK 26

Data-out to High-Z from PRECHARGE command CL = 3 tROH(3) 333

tCK 17

CL = 2 tROH(2) 222

tCK 17

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144-PIN SDRAM SODIMM

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Notes

1. All voltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V; f =

1 MHz, TA = 25°C; pin under test biased at 1.4V.

3. IDD is dependent on output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to

indicate cycle time at which proper operation

over the full temperature range is ensured (0°C ≤

TA ≤ +70°C).

6. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,

before proper device operation is ensured. (VDD

and VDDQ must be powered up simultaneously.

VSS and VSSQ must be at same potential.) The two

AUTO REFRESH-command wake-ups should be

repeated any time the tREF refresh requirement is

exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between

VIH and VIL (or between VIL and VIH) in a mono-

tonic manner.

9. Outputs measured at 1.5V with equivalent load:

10. tHZ defines the time at which the output achieves

the open circuit condition; it is not a reference to

VOH or VOL. The last valid data element will meet

tOH before going High-Z.

11. AC timing and IDD tests have VIL = 0V and VIH = 3V,

with timing referenced to 1.5V crossover point. If

the input transition time is longer than 1ns, then

the timing is referenced at VIL (MAX) and VIH

(MIN) and no longer at the 1.5V crossover point.

12. Other input signals can change no more than

once every two clocks and are otherwise at valid

VIH or VIL levels.

13. IDD specifications are tested after the device is

properly initialized.

14. Timing actually specified by tCKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

15. Timing actually specified by tWR plus tRP; clock(s)

specified as a reference only at minimum cycle

rate.

16. Timing actually specified by tWR.

17. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-

eter.

18. The IDD current will increase or decrease propor-

tionally according to the amount of frequency

alteration for the test condition.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on tCK = 10ns for -10E, and tCK = 7.5ns for -

133 and -13E.

22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse

width ≤ 3ns, and the pulse width cannot be greater

than one third of the cycle rate. VIL undershoot:

VIL (MIN) = -2V for a pulse width ≤ 3ns.

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing

constraints specified for the clock pin) during

access or precharge states (READ, WRITE, includ-

ing tWR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only. The precharge time

(tRP) begins at 7ns for -13E; 7.5ns for -133 and 7ns

for -10E after the first clock delay, after the last

WRITE is executed. May not exceed limit set for

precharge mode.

25. Precharge mode only.

26. JEDEC and PC100 specify three clocks.

27. tAC for -133/-13E at CL = 3 with no load is 4.6ns

and is guaranteed by design.

28. Parameter guaranteed by design.

29. For -10E, CL = 2 and tCK = 10ns; for -133, CL = 3

and tCK = 7.5ns; for -13E, CL = 2 and tCK = 7.5ns.

30. CKE is HIGH during refresh command period

tRFC (MIN), else CKE is LOW. The IDD6 limit is

actually a nominal value and does not result in a

fail value.

31. Refer to device data sheet for timing waveforms.

32. The value of tRAS used in -13E speed grade mod-

ule SPDs is calculated from tRC - tRP = 45ns.

33. Leakage number reflects the worst case leakage

possible through the module pin, not what each

memory device contributes.

50pF

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (see

Figures 6, and 7).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has been

met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (see Figure 8).

The SPD device will always respond with an

acknowledge after recognition of a start condition and

its slave address. If both the device and a WRITE oper-

ation have been selected, the SPD device will respond

with an acknowledge after the receipt of each subse-

quent eight bit word. In the read mode the SPD device

will transmit eight bits of data, release the SDA line and

monitor the line for an acknowledge. If an acknowl-

edge is detected and no stop condition is generated by

the master, the slave will continue to transmit data. If

an acknowledge is not detected, the slave will termi-

nate further data transmissions and await the stop

condition to return to standby power mode.

Figure 6: Data Validity Figure 7: Definition of Start and Stop

Figure 8: Acknowledge Response From Receiver

SCL

SDA

Data stable

Data change

Data stable

SCL

SDA

Start

bit

Stop

bit

SCL from master

Data output

from transmitter

Data output

from receiver

Acknowledge

(

)(

)

(

)(

)

(

)(

)

(

)(

)

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Figure 9: SPD EEPROM Timing Diagram

Table 16: EEPROM Device Select Code

Most significant bit (b7) is sent first

DEVICE TYPE IDENTIFIER CHIP ENABLE RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory area select code (two arrays) 1010SA2SA1SA0RW

Protection register select code 0110SA2SA1SA0RW

Table 17: EEPROM Operating Modes

MODE RW# BIT WC BYTES INITIAL SEQUENCE

Current address READ 1V

IH or VIL 1START, device select, RW = 1

Random address READ 0VIH or VIL 1START, device select, RW = 0, Address

IH or VIL RESTART, device select, RW = 1

Sequential READ 1VIH or VIL ≥1similar to current or random address READ

Byte WRITE 0V

IL 1START, device select, RW = 0

Page WRITE 0VIL ≤16 START, device select, RW# = 0

SCL

SDA In

SDA Out

tLOW

tSU:STA tHD:STA

tFtHIGHtR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

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144-PIN SDRAM SODIMM

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NOTE:

1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising

edge of SDA.

2. This parameter is sampled.

3. For a restart condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA

remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 18: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VSS; VDDSPD = 2.3V to 3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

Supply voltage VDD 33.6V

Input high voltage: Logic 1; All inputs VIH VDD × 0.7 VDD × 0.5 V

Input low voltage: Logic 0; All inputs VIL –1 VDD × 0.3 V

Output low voltage: IOUT = 3mA VOL –0.4V

Input leakage current: VIN = GND to VDD ILI –10µA

Output leakage current: VOUT = GND to VDD ILO –10µA

Standby current: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10% ISB –30µA

Power supply current: SCL clock frequency = 100 KHz ICC –2mA

Table 19: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to VSS; VDDSPD = 2.3V to 3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 µs

Data-out hold time tDH 200 ns

SDA and SCL fall time tF300ns2

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 0.6 µs

Clock HIGH period tHIGH 0.6 µs

Noise suppression time constant at SCL, SDA inputs tI50ns

Clock LOW period tLOW 1.3 µs

SDA and SCL rise time tR0.3µs2

SCL clock frequency fSCL 400 KHz

Data-in setup time tSU:DAT 100 ns

Start condition setup time tSU:STA 0.6 µs 3

Stop condition setup time tSU:STO 0.6 µs

WRITE cycle time tWRC 10 ms 4

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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Table 20: Serial Presence-Detect Matrix

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; VDD = +3.3V ±0.3V

BYTE DESCRIPTION ENTRY (VERSION) MT16LSDF3264H MT16LSDF6464H

0Number of bytes used by Micron 128 80 80

1Total number of SPD memory bytes 256 08 08

2Memory type SDRAM 04 04

3Number of row addresses 12 or 13 0C 0D

4Number of column addresses 10 0A 0A

5Number of banks 202 02

6Module data width 64 40 40

7Module data width (continued) 000 00

8Module voltage interface levels LVTTL 01 01

9SDRAM cycle time, tCK

(CL = 3)

7ns (-13E)

7.5ns (-133)

8ns (-10E)

10 SDRAM access from clock, tAC

(CL = 3)

5.4ns (-13E/-133)

6ns (-10E)

11 Module configuration type NONE 00 00

12 Refresh rate/type 15.6µs

or 7.81µs/self

80 82

13 SDRAM width (primary SDRAM) 808 08

14 Error-checking SDRAM data width 00 00

15 MIN clock delay from back-to-back random

column addresses, tCCD

101 01

16 Burst lengths supported 1, 2, 4, 8, page 8F 8F

17 Number of banks on SDRAM device 404 4

18 CAS latencies supported 2, 3 06 6

19 CS latency 001 01

20 WE latency 001 01

21 SDRAM module attributes Unbuffered 00 00

22 SDRAM device attributes: General 14 0E 0E

23 SDRAM cycle time, tCK

(CL = 2)

7.5ns (13E)

10ns (-133/-10E)

24 SDRAM access from CLK, tAC

(CL = 2)

5.4ns (-13E)

6ns (-133/-10E)

25 SDRAM cycle time, tCK

(CL = 1)

–00 00

26 SDRAM access from CLK, tAC

(CL = 1)

–00 00

27 MIN row precharge time, tRP 15ns (-13E)

20ns (-133/-10E)

28 MIN row active-to-row active, tRRD 14ns (-13E)

15ns (-133)

20ns (-10E)

29 MIN RAS#-to-CAS# delay, tRCD 15ns (-13E)

20ns (-133/-10E)

30 MIN RAS# pulse width, tRAS 45ns (-13E)

44ns (133)

50ns (-10E)

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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NOTE:

1. The value of tRAS used for the -13E module is calculated from tRC - tRP. Actual device spec value is 37ns.

31 Module rank density 128MB or 256MB 20 40

32 Command and address setup time, tAS, tCMS 1.5ns (-13E/-133)

2ns (-10E)

33 Command and address hold time, tAH, tCMH 0.8ns (-13E/-133)

1ns (-10E)

34 Data signal input setup time, tDS 1.5ns (-13E/-133)

2ns (-10E)

35 Data signal input hold time, tDH 0.8ns (-13E/-133)

1ns (-10E)

36–40 Reserved 00 00

41 Device MIN ACTIVE/AUTO-REFRESH time, tRC 66ns (-13E)

71ns (-133)

66ns (-10E)

42–61 Reserved 00 00

62 SPD revision REV. 2.0 02 02

63 Checksum for bytes 0-62 (-13E)

(-133)

(-10E)

64 Manufacturer’s JEDEC ID code MICRON 2C 2C

65–71 Manufacturer’s JEDEC ID code (continued) FF FF

72 Manufacturing location 1–12 01–0C 01– 0C

73–90 Module part number (ASCII) Variable Data Variable Data

91 PCB identification code 1–9 01–09 01–09

92 Identification code (continued) 000 00

93 Year of manufacture in BCD Variable Data Variable Data

94 Week of manufacture in BCD Variable Data Variable Data

95-98 Module serial number Variable Data Variable Data

99–125 Manufacturer-specific data (RSVD)

126 System frequency 100 MHz/133 MHz

(-13E/-133/-10E)

64 64

127 SDRAM component and clock detail CF CF

Table 20: Serial Presence-Detect Matrix (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; VDD = +3.3V ±0.3V

BYTE DESCRIPTION ENTRY (VERSION) MT16LSDF3264H MT16LSDF6464H

256MB, 512MB (x64, DR)

144-PIN SDRAM SODIMM

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8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 10: 144-Pin SODIMM Dimensions

NOTE:

All dimensions in inches (millimeters); or typical where noted.

Data Sheet Designation

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete

power supply and temperature range for production

devices. Although considered final, these specifica-

tions are subject to change, as further product devel-

opment and data characterization sometimes occur.

U1 U2 U17

U10 U9

U3 U4 U5 U6 U7 U8

U16 U15 U14 U13 U12 U11

0.150 (3.80)

MAX

0.043 (1.10)

0.035 (0.90)

PIN 1

2.666 (67.72)

2.655 (67.45)

0.787 (20.00)

TYP

0.071 (1.80)

(2X)

2.386 (60.60)

0.0315 (0.80)

TYP

83.82 (3.30)

0.024 (0.60)

TYP

0.079 (2.00) R

(2X)

PIN 143

PIN 144 PIN 2

FRONT VIEW

BACK VIEW

0.079 (2.00)

0.236 (6.00)

2.504 (63.60)

0.100 (2.55)

0.059 (1.50)

TYP

0.157 (4.00)

1.255 (31.88)

1.245 (31.62)

MAX

MIN

512MB SDRAM: MT16LSDF6464HY-133

Illustration Only. See data sheet for product specifications.

The narrow SODIMM form factor (67.6mm long) is designed for applications where board space is at a

remium.

MT16LSDF6464HY-133D2

Production orders are being taken, parts are shipping.

Contact a Sales Representative

Distributor Stock

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