18-Bit Registered Transceiver
ax id: 7047
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Au
ust 19994 – Revised October 30
1997
H501
Features
• Low pow er, pin-compatible replacement for ABT
functions
• FCT-E speed at 3.8 ns
• Power-off disable outputs permits live insertion
• Edge-rate control cir cuit ry for signif icant ly improved
noise characteristics
• Typical out put skew < 250 ps
• ESD > 2000V
• TSSOP (19.6 mil pitch) and SSOP (25-mil pitc h)
packages
• Industrial temperature range of −40°C to +85°C
•V
CC = 5V ± 10%
CY74FCT16501T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25°C
CY74FCT162501T Features:
• Balanced 24 mA output dri vers
• Red uced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 2 5° C
CY74FCT162H501T Features:
• Bus hold ret ains last active state
• Eliminat es the need for exter nal pull-up or pul l- down
resistors
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (C LKAB and CLKBA). For
A-to-B data flow , the device operates in transparent mode when
LEAB is HIGH. When LEAB is LOW, the A data is latched if
CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW,
the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transiti on of CL KAB. OEAB performs the output
enable function on the B por t. Data flow from B-to-A is similar
to t hat of A-to-B and is cont rolled b y OEBA, LEBA, an d CLKBA.
The output buffers are designed with a power-off disable fea-
ture to allo w li ve i nsertion of boards.
The CY74FCT16501T is ideally suited for driving
high-capacitance loads and low-impedance bac kplane s.
THE CY74FCT162501T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need f or ext ernal te rminating resistors a nd provides f or minimal
undershoot and reduced ground bounce. The
CY74FCT162501T is ideal for driving transmissio n li nes.
The CY74FCT16 2H501T is a 24-mA balanced output part, that
has “b us hold” on the data i nputs. The de vice retains t he input’ s
last state whenever the input goes to high impedance. This
eliminates the need for pull-up/down resistors and prevents
floating inputs.
GND
Functional Block Diagram Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
OEAB
SSOP/TSSOP
Top Vie w
13
14
15
16
17
18
19
20
21
22
23
24
LEAB
A1
GND
GND
VCC
GND
GND
FCT16501-1
A2
A3
A4
A5
A6
A7
A8
A9
GND
25
26
27
28
GND
A10
A11
A12
VCC
A13
A14
A15
A16
A17
A18
OEBA
LEBA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
B13
B14
B15
VCC
B16
B17
B18
CLKBA
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
D
C
D
C
D
A1B1
C
D
TO 17 OTHER CHANNELS
FCT16501-2