IDT CMOS ASYCHRONOUS FIFO 256 x 9, 512 x 9, 1,024 x 9 (DT7200L IDT7201LA IDT7202LA FEATURES: * First-In/First-Out dual-port memory * 256 x 9 organization (IDT7200) * 512 x 9 organization (IDT7201) * 1,024 x 9 organization (IDT7202) + Lowpowerconsumption Active: 440mW (max.) Power-down: 2.75mW (max.) * Ultra high speedt2ns access time | * Asynchronous and simultaneous read and write Fully expandable by both word depth and/or bit width * Pin and functionally compatible with 720X family * Status Flags: Empty, Half-Full, Full * Auto-retransmit capability + High-performance CEMOS technology * Military product compliant to MIL-STD-883, Class B Standard Military Drawing #5962-87531, 5962-89666, 5962-89863 and 5962-89536 are listed on this function * Dual versions available in the TSSOP package. For more informa- tion, see IDT7280/7281/7282 data sheet (3208.pdf) 1DT7280 = 2 x IDT7200 1DT7281 = 2 x 1DT7201 1DT7282 = 2 x IDT7202 Industrial temperature range (-40C to +85C) is available (plastic packages only) DESCRIPTION: The IDT7200/7201/7202 are dual-port memories that load and empty data on a first-inffirst-out basis, The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. . The devices utilize a 9-bit wide data array to allow for control and parity bitsatthe user's option. This featureis especially usefulin data communications applications where itis necessary to use a parity bit for transmission/reception error checking. Italso features a Retransmit(RT) capability that allows forreset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using IDTs high-speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Military grade productis manufacturedin compliance with the latestrevision of MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM Ort edi W WRITE CONTROL DOT rrr a | $ e WRITE LX) RAM [AT Reap POINTER >] ARRAY KOI pointer z 256 x9 LL 512x9 1,024 x9 e e e THREE. MPU STATE an . s* _ BUFFERS <> RS ==ap DATA OUTPUTS t Qo-Qe8 R~)"} CONTROL | Pen 4 5 t FLAG == a EF FURT ore > EF EXPANSION xI-| _ Locic [KM XO/HF 2679 drw 01 NOVEMBER 1998 1998 Integrated Device Technology, Inc. OSC-2679/7IDT7200L/7201LA/7202LA ony PIN CONFIGURATIONS 6 LS eX 8Se28as wht 28 voc Y~ UUUQUUN \ pel_] 2 27|_] ps 4 3 2 7 323130 D3 CI 3 26 Y Ds De 15 20L_] De Del_] 4 25|_] De p: (le 28] pr ots 24{|] pz po 17 at NC Dol_] 6 23|_] FURT x CIs ae(_| FLAT xiL 7 22|_] RS FF LJ o5L_] AS FFL_| 8 21|_] EF Qo [J 10 2aL_} EF QoL] 9 20] XO/AF Qn =" za XO aL 10 19 @ eS. eso Qe 13 21 Qs Col 11 tf 14 15 16 17 18 19 20 Qs 4 12 171\ Qs \ DODO ael_] 13 16|_] as OQ ole i J 8 6629" 66 GND 14 15 R Oo 2679 drw 02b 2679 drw 02a Reference Order Reference Order Package Type identifier Code Package Type Identifier Code PLASTIC DIP P28-1 P Lec L32-1 L PLASTIC THIN DIP P28-2 TP PLCC 532-1 J CERDIP D28-1 D TOP VIEW THIN CERDIP D28-3 TD soc $028-3 so CERPACK E282 XE TOP VIEW NOTE: 1. The 600-mil-wide DIP (P28-1 and D28-1), CERPACK and LCC are not available for the IDT7200. RECOMMENDED DC OPERATING ABSOLUTE MAXIMUM RATINGS CONDITIONS Symbol Rating Com & Indl Mil. Unit Symbol Parameter Min. | Typ. | Max.| Unit VTERM | TerminalVohage -0.5t0+7.0 -0.5t0+7.0 | V Vcc | Supply Voltage 45 150 | 55 | V with Respect Commercial/industria/Military to GND GND Supply Voltage 0 0 0 V Ts1G Storage -5to+125 -65to+155 | C ViH | InputHigh Voltage 20 | tIv Temperature Commercial/industrial louT DC Output -50to +50 -50to +50 mA vin) Input High Voltage 22 | _ V Current Military NOTE: 2679 thi 01 (2) _ _ 1, Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause | VIL" | InputLowVoltage = 8 | V permanent damage to the device. This is a stress rating only and functional operation of Commercial/industria/Miltary the device at these or any other conditions above those indicated in the operational TA Operating Temperature 0 - 7% | C sections of this specification is not implied. Exposure to absolute maximum rating Commercial conditions for extended periods may affect reliability. TA Operating Temperature 4 | 8 | c industial_ TA Operating Temperature 5 | | 12 7 C Military NOTES: 1. For RT/RS/XI input, Vin = 2.6V (commercial). For RT/RS/XI input, Vin = 2.8V (miftary). 2. 1.5V undershoots are allowed for 10ns once per cycle. 2679 thi 03IDT7200L/7201LA/7202LA DC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5V + 10%, TA=0C to +70C; Industrial: Vcc = SV + 10%, TA=40C to +85C; Miltary: Vcc = SV + 10%, TA=-55C to +125C) IDT IDT7200L. IDT7200L IDT7201LA IDT7201LA IDT7202LA IDT7202LA Com' & ind Military ta= 12, 15, 20, 25, 35, 50 ns ta = 20, 30, 40, 50, 65, 80,120ns__ Symbol Parameter Min. Max. Min. Max. Unit we input Leakage Current (Any Input) -1 1 -10 10 HA no) Output Leakage Current -10 10 -10 10 WA Vou Output Logic 1 Voltage lon = -2mA 2.4 _ 24 _ V VoL Output Logic "0" Voltage lo. = 8mA _ 0.4 _ 0.4 V icc) Active Power Supply Current _ 80 100 mA Icc2* Standby Current (R-W=RS-FL/RT=Vin) _ 5 _ 5 mA NOTES: 2679 tht 05 Measurements with 0.4 < VIN < Vcc. R > Vin, 0.4 < Vout < Vcc. Tested with outputs open (louT = 0). Tested at f = 20 MHz. A APwnr load (in pF). 7. All Inputs = Vcc - 0.2V or GND + 0.2V. CAPACITANCE (1a = +25C, f= 1.0 MHz) Symbol Parameter Condition Max. | Unit CIN Input Capacitance Vin = OV 8 pF Cout Output Capacitance Vout = 0V 8 pF NOTE: 2679 tbl 02 1. Characterized values, not currently tested. AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 1 2679 thi 08 Industrial temperature range product for the 25 ns speed grade is available as a standard device. All other speed grades are available by special order. Typical Icc1 = 15 + 2fs + 0.02Ci'fs (in mA) with Vcc = SV, Ta = 25C, fs = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fs/2, C. = capacitive 5V J 1.1K > TO OUTPUT PIN L . 6802 =~ 30pF = 2679 drw 03 or equivalent circuit Figure 1. Output Load * Includes scope and jig capacitances.IDT7200L/7201LA/7202LA AC ELECTRICAL CHARACTERISTICS (Commercial: Voc = 5V + 10%, Ta=0Cto+70C; Industrial: Vcc = 5V + 10%, TA=~40C 10 +85C; Miltary: Vcc = 5V + 10%, TA=-55Cto+125C) Commercial Com'l & Mil._| Com1&indt? | Military Com! T200L12 | | 7200L15 7200120 7200.25 7200L30 | 7200135 7201LA12 | 7201LA1S | 7201LA20 T201LAZS T2O1LA30 | 7201LA35 22021812 | _ 72021, A15 T2021, A20 T2021,A25_ | 7207, ASD | 7 ASS | [Symbol Parameter Min._| Max. | Min.| Max | Nin. | Max | Min. | Max | Min.| Max| Min.| Max | Unit is Shift Frequency | 0] | o] { 33] | 25 |] { 3] ~ | 22 | MHz IRC Read Cycle Time aj]| s||]|] 3 |#|--|] 45 | | os tA Access Time | 2] ] 6] 2 _ 25 | DX] - 35 | ns RR Read Recovery Time 8 | 0] | 10 _ 10 _ 10 | | 10 | os irew _| Read Pulse Width) 2{/-]| 6/-|a]| oa | 9} -]| 5] | os IRLZ Read Pulse Lowto Data Bus atLow 22) 3 - 3} - 3 _ 3 - 3] | 3 - ns twiz_| Write Pulse Highto Data Bus at Low 2") 5|-|5}/-]5/)--|5 |.-]5{/-[s]| os tv Data Valid from Read Pulse High 5 - 5] - 5 - 5 _ 5] |] 5 | os IRHZ Read Pulse High to Data Bus at High 2 /2yj-/{/s6]/] 6] we | |a] | a] os two Write Cycie Time 2a || a|{ | = 3 = 4 | | 45 | 0s twew _| WritePusewWiath z2/|] 6}/--|a]-] 2 |x] -] 3] | os twR Write Recovery Time 8 |] 0); -] 1 - 10 _ 10 | |] 10 | ns tos Data Set-up Time 9 - Wy} 74 = 15 - 13 | ] 18 | ns {DH Data Hold Time 0 ~~ Oo}; - 0 _ 0 o}; 0 - ns tRSC Reset Cycle Time ao j]| oa] | - 35 _ 4] ] 4 | ns IRS Reset Pulse Width) z{[-|] 6] --|a]|] a | }] | 3 | | os trss Reset Set-up Time 2]/| 6] -| a] ]} 2 |x] ] 3] ] os IRSR Reset Recovery Time 8 - 10] 10 _ 10 10 | | 10 | ns tRIC Retransmit Cycle Time o]-| oa] -] wv _ 35 _ 4 | ] 4 | ns RT Retransmit Pulse Width) z2f]| 6{/-|a]|2a - |x] -] 3 | | os IRTS Retransmit Set-up Time? z||] 6|--|]a]| 2 - |x] ]| 3 | | os tRTR Retransmit Recovery Time 8 | Ww] ] 0 _ 10 _ 10 | | 10 a (EFL Reset to Empty Flag Low - 2] | 2 - Ki - 3 -| #] 45 | ns tHFHFFH | ResettoHalf-Fulland Full Flag High -|7/-|}a/]/|{ ] - 3 | | 0] |] 4] os (RIF Retransmit Lowto Flags Valid | oa] -|] So] - wv - 35 | 0] 45 | ns (REF Read Low to Empty Flag Low | 2), -])] by] - 2 ~ a -| xD] - x | ns tRFF Read High to Full Flag High | 4] -) by] - 20 - 28 -| dD] x |] ns wReE__| ReadPulse Widthafter EF High z2l|-|s/|oa]-|o |-/[x|-|sl|os IWEF Write High to Empty Flag High ~|2z}-|}6]--] a] 3a || o] ] | os twrF Write Low to Full Flag Low |u}]-| 6] - a] oa |-|] ) |] DO | os (WHF Write Low to Half-Fult Flag Low --|vi}-|}a]/] wo] - BS |-] of; ] 4 | os (RHF Read Highto Half-Full Flag High -|vwf-|a] of] 3 | ] 40] | 45] os twPr Write Pulse Width after FF High 2]/| 6] ]| @ | 2 |x] -| 3 | | ns 1XOL Read/Write to XO Low {| wz} -[| 6] na} a | | 0] | 35] 2s 1KOH Read/Writeto XO High | 2] | 6] - a] 5 || 0] | 3 | ns bu X1Putse Wiath) 2z2{]| 6} -|oa] -]|] 2 - |x] | 3 | |] os DOR XI Recovery Time 8 |}| 0} | m0] |{ 0 | ow] ] mo] | os bus X1Set-up Time 8 |] | 0} ] | 10 | 0] ] 0 | |] ns NOTES: 2679 tbh 06 1. Timings referenced as in AC Test Conditions. 2. Industrial temperature range is available by special order for speed grades faster than 25ns. 3. Pulse widths fess than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode.IDT7200L/7201LA/7202LA aE AC ELECTRICAL CHARACTERISTICS (Continued) (Commercial: Vcc = 5V + 10%, TA=0C to + 70C; Industrial: Vcc = 5V + 10%, TA=-40C to +85C; Military: Vcc =5V + 10%, TA=-55C to+125C) Military Com'l & Mil. Miltary?) 7200 L40 7200150 7200165 7200.80 7200L.120 7201LA40 7201LA50 7201LAG5 7201LA80 7201LA120 7202LA40 7202LA50 7202LA65 7202LA80 7202LA120 Symbol Parameter Min. | Max.| Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit ts Shift Frequency = 20} 15 | 125 | 10 = 7 MHz IRC Read Cycle Time 50 | 6 = 80 | 0] 140 ns ta Access Time = 40 | 50 = 65 | 80 = 120 ns IRR Read Recovery Time 10 - 15 - 15 - 20 20 _ ns tRPW Read Pulse Width 40 | 50 _ 6 | | 8 | | 10 |] ns tRLZ Read Pulse Low to Data Bus at Low 2") 3 | 3 - 3 3 = 3 - ns twiz Write Pulse High to Data Bus at Low 2 5 5 | 5 5 5 - 5 ns tov Data Valid from Read Pulse High 5 = 5 ~ 5 = 5 = 5 ns (RHZ Read Pulse High to Data Bus at High Z' 23 | 30 ~ | 3 | | 30 35 ns two Write Cycle Time 50 - 65 _ 80 _ 100 140 ns twew _| Write Pulse Width 40 ~ | 50 | | 6 | | | | | 120 | ~ ns twR Write Recovery Time 10 _ 15 _ 15 _ 20 _ 20 ns tos Data Set-up Time 20 - 30 _ 30 _ 40 40 = ns (OH Data Hold Time 0 = 5 _ 10 _ 10 _ 10 = ns IRSC Reset Cycle Time 50 _ 65 _ 80 _ 100 _ 140 ns RS Reset Pulse Width) 40 | 50 65 | oF - 120 | ns IRSS Reset Set-up Time) 40 _ 50 _ 65 _ 80 _ 120 ns IRSR Reset Recovery Time 10 15 _ 15 20 _ 20 ns (RTC Retransmit Cycle Time 50 _ 65 _ 80 _ 100 _ 140 - ns tRT Retransmit Pulse Width) 40 | 50 = 65 _ 80 | 120 = ns tats Retransmit Set-up Time 40 | 50 ~ 6 | | 80 | | 120 | ns tRTR Retransmit Recovery Time 10 _ 15 _ 15 _ 20 = 20 - ns tEFL Reset to Empty Flag Low _ 50 _ 65 ~ 80 _ 100 _ 140 ns tHFH.FFH | Reset to Half-Full and Full Flag High _ 50 _ 65 _ 80 _ 100 _ 140 ns tRIF Retransmit Low to Flags Valid - 50 | 65 ~ 80 | 100 = 140 ns {REF Read Low to Empty Flag Low _ 30 _ 45 _ 60 _ 60 60 ns IRFF Read High to Full Flag High = 35 | 45 = 60 | 6 - 60 ns IRPE Read Pulse Width after EF High 40 | 50 _ 65 = 80 = 120 _ ns tWeEF Write High to Empty Flag High = 3) 45 ~ 60 | 6 60 ns twrF Write Low to Full Flag Low _ 3 45 _ 60 _ 60 _ 60 ns tWHE Write Low to Half-Ful Flag Low = 5 | 65 = 80 | 100 - 140 ns IRHF Read High to Half-Full Flag High _ so | 65 - 80 | 100 = 140 ns twer Write Pulse Width after FF High 40 | 50 _ 65 _ 80 _ 120 ns OL ReadWite to XO Low - 40] 50 - 65 _ 80 _ 120 ns ea ReadMWrite to XO High _ 40 _ 50 - 65 - 80 - 120 ns tl XI Pulse Width 40 | 50 _ 6 | | #0 | | 120] - ns aR Xi Recovery Time 10 | 10 = 10 - mo} 10 ns bus Xi Set-up Time 10 | 3% - 15 = 15 ~ 5 _ ns NOTES: 2679 thi O7 . Timings referenced as in AC Test Conditions Speed grades 65, 80 and 120 not available in the CERPACK Pulse widths less than minimum value are not alowed. Values guaranteed by design, not currently tested. Only applies to read data flow-through mode. newnoIDT7200L/7201LA/7202LA SIGNAL DESCRIPTIONS INPUTS: DATA IN (Do - Ds) Data inputs for 9-bit wide data. CONTROLS: RESET (RS) Resetis accomplished whenever the Reset (RS) inputis taken to aLOW state. During reset, both internal read and write pointers are set to the first location. Aresetis required after power up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2, ((.e., tkss before the rising edge of RS) and should not change until trsr after the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after Reset (RS). WRITE ENABLE (W) A write cycle is initiated on the falling edge of this input if the Full Flag (FF)is notset. Data set-up and hold times must be adhered to with respect to the rising edge of the Write Enable (W). Datais stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be setto LOW and will remain setuntil the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. Topreventdata overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after trFF, allowing a valid write to begin. When the FIF Ois full, theinternal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full READ ENABLE (R) A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First- In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Qo Qe) will return to a high impedance condition until the next Read operation. When all data has been read fromthe FIFO, the Empty Flag (EF) will go LOW, allowing the "final" read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after twer anda valid Read canthen begin. When the FIFO is empty, the internal read pointeris blocked from R so external changes in R will not affect the FIFO when it is empty. FIRST LOAD/RETRANSMIT (FLIRT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate thatitis the firstloaded (see Operating Modes). Inthe Single Device Mode, this pinacts as the retransmitinput. The Single Device Madeis initiated by grounding the Expansion In (XI). The 1DT7200/7201A/7202A can be made to retransmit data when the Retransmit Enable control (RT) inputis pulsed LOW. Aretransmit operation will setthe internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (VW) must be in the HIGH state during retransmit. This feature is useful when less than 256/512/1,024 writes are performed between resets. Theretransmitfeature is notcompatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), dependingon the refative locations of the read and write pointers. EXPANSION IN (X1) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. OUTPUTS: FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. Ifthe read pointer is not moved after Reset (RS), the Full-Flag (FF) will go LOW after 256 writes for |DT 7200, 512 writes for the IDT7201A and 1,024 writes for the IDT7202A. EMPTY FLAG (EF) __ The Empty Flag (EF) willgo LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is emply. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XIis grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set LOW and will remain set until the difference between the write pointer and read pointer is less than or equal toone half of the total memory of the device. The Half-Full Flag (HF) is then Teset by using rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This outputacts asa signal tothe next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the lastlocation of memory. DATA OUTPUTS (Qo - Qa) Data outputs for 9-bit wide data. This data isin a highimpedance condition whenever Read (FR) is in a HIGH state.IDT7200L/7201LA/7202LA =| wl 1 Fl al = 5 . ma S: m =| tHFH , tFFH F, FF, HF may change status during Reset, but flags will be valid at trsc. and R = Vin around the rising edge of RS. Figure 2. Reset tRc tRR >=_ ta tDv ( DATA ouT VA Toa y be tRHZ \, DATA out VALID two ~ * twew >\+ twR* oN 7 wW Ko cK tbs 1+ {DH Do-Ds DATA in VALID DATA IN VALID 2679 drw 05 Figure 3. Asynchronous Write and Read Operation LAST WRITE IGNORED FIRST READ ADDITIONAL FIRST WRITE READS WRITE _ a F 7 Ww \_/ \_/ 7 wre 7, tRFF FF ! 2679 drw 06 Figure 4. Full Flag From Last Write to First Read 7IDT7200L/7201LA/7202LA Te LASTREAD | IGNORED] = FIRSTWAITE | ADDITIONAL| FIRST READ READ WRITES _ J W 7 A \ \/ L.<s7 tREF 7 Wer EF L s tA \/ / \/ \/ DATAOQUT XK vaLin XX XX vauin XX) = Figure 5. Empty Flag From Last Read to First Write tATC a {RT ~ /\ 4h N\ r__________ tres ss tRrR qa ar XXXKX Y tATF ~t- | mere XXX KKK KK KKK III KT VA 2679 drw 08 Figure 6. Retransmit wtCO 7 WEF r WA sero ause Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse ON | 7 tRFF WIMLNTITANL NNN a Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse =|IDT7200L/7201LA/7202LA Ww tRHF | L tWHF HF HALF-FULL OR LESS MORE THAN HALF-FULL HALF-FULL OR LESS 2679 drw 11 Figure 9. Half-Full Flag Timing WRITE TO LAST PHYSICAL LOCATION W READ FROM LAST PHYSICAL LOCATION R YO 2679 drw 12 xO iw Figure 10. Expansion Out + txt m+ txIR ~ Xi Kx / s KIS write To FIRST PHYSICAL LOCATION =I 7, tas a READ FROM FIRST PHYSICAL LOCATION 2679 drw 13 Figure 17. Expansion In OPERATING MODES: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where Ris used). For additional information, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. SINGLE DEVICE MODE A single |DT7200/7201A/7202A may be used when the application requirements are for 256/512/1,024 words or less. These devices are ina Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 12). DEPTH EXPANSION The IDT7200/7201A/7202A can easily be adapted to applications when the requirements are for greater than 256/512/1,024 words. Figure 14 demonstrates Depth Expansion using three IDT7200/7201A/7202As. Any depthcan be attained by adding additional |DT7200/7201A/7202As. These FIFOs operate in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. Allother devices musthave FL in the HIGH state. The Expansion Out (XO) pin of each device must be tied to the Expansion In (Xi) pin of the next device. See Figure 14. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (ie. all must be set to generate the correct composite FF or EF). See Figure 14. The Retransmit (RT} function and Hall-Full Flag (HF) are notavailable in the Depth Expansion Mode. 2. 3. 4, For additional information, refer to Tech Note 9: Cascading FIFOs or FIFO Modules.IDT7200L/7201LA/7202LA USAGE MODES: WIDTH EXPANSION Word width may be increased simply by connecting the corresponding inputcontrol signals of multiple devices. Status fags (EF, FF and HF) can be detected from any one device. Figure 13 demonstrates an 18-bit word width by using two IDT7200/7201A/7202As. Any word width can be attained by adding additional IDT7200/7201A/7202As (Figure 13). BIDIRECTIONAL OPERATION Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing 1DT7200/7201A/7202As as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. DATA FLOW-THROUGH Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow-through mode (Figure 17), (HALF-FULL FLAG) (HF) on the FIFO permits areading of a single word after writing one word of data into anempty FIFO. The datais enabled on the bus in (tweF + ta) ns after the rising edge of W, called the first write edge, andit remains on the bus until the Filine israised from LOW-to-HIGH, after which the bus would go into a three-state mode after tRHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. Inthe write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO, The Rline causes the FF tobe deasserted but the Wine beingLOW causes itto be asserted again in anticipation of anew data word. Ontherising edge of W, the new word is loaded in the FIFO. The W line must be toggled when FF is notasserted to write newdatain the FIFO andtoincrementthe write pointer. COMPOUND EXPANSION The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15). WRITE (W) g DATA IN of FULL FLAG (FF) RESET (RS) IDT 7200/ 7201A/ 7202A ++. READ (R) 9 _a DATA OUT (Q) [-*_ EMPTY FLAG (EF) + RETRANSMIT (RT) EXPANSION IN (XI) I 2679 drw 14 Figure 12. Block Diagram of Single 256 x 9, 512x 9, 1,024 x 9 FIFO DATAIN (D) WRITE (W) FULL FLAG (FF) RESET (RS) READ (R) EMPTY FLAG (EF) RETRANSMIT (RT) DATA our (Q) 2679 drw 15 Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion ModeIDT7200L/7201LA/7202LA ea TABLE IRESET AND RETRANSMIT Single Device Configuration Width Expansion Mode Internal Status Reset Location Zero Location Zero Retransmit Location Zero Read/Write NOTE: 2679 tbl 09 1, Pointer will increment if flag is HIGH. TABLE IIRESET AND FIRST LOAD TRUTH TABLE Depth Expansion/Compound Expansion Mode Internal Status All Other 0 1 Location Zero Location Zero Read/Write 1 X Xx Xx NOTE: 2679 thi 10 1, Xt is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/AT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output Ww R D Q Vcc FULL EMPTY RS 2679 dew 16 xl Figure 14. Block Diagram of 768 x 9, 1,536 x 9, 3,072 x 9 FIFO Memory (Depth Expansion)IDT7200L/7201LA/7202LA DATA ouT ONE Qo-Q8 Q9-Q17 Q(N-8)-Q eee Qo0-Q8 Qs-Q17 Qin-8)-Qn IDT7200/ IDT7200/ IDT7200/ IDT7201A/ IDT7201A/ IDT7201A/ IiDT7202A IDT7202A IDT7202A R, Ww, RS DEPTH - DEPTH iH eee > DEPTH EXPANSION EXPANSION EXPANSION BLOCK BLOCK BLOCK 4 * Do-Ds 4 * Dog-D17 4 } D(n-8)-DN Do-DN ese Do-DN Dis-DN D(N-8)-DN 2679 dew 17 NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13. Figure 15. Compound FIFO Expansion Wa * FFa x ] IDT 7200/ ec 7201A/ - HFe 7202A DAo-8 SYSTEM A < Q QB 0-8 > SYSTEMB TT A. 0-8 Ra] HFA EFa IDT 7200/ 7201A/ 7202A A_DB 0-8 \ *_ We | * FFB 2679 drw 18 Figure 16. Bidirectional FIFO Mode DATA IN x *___ tRPE : Z| + twEF >[-** tREF I a DATA OUTVALID 2679 drw 19 Figure 17. Read Data Flow-Through ModetwPF w J) tRFF }+ twFF 7 tOH DATA IN DATA IN VALID * tbs al N DATA OUT 2679 dew 20 Figure 18. Write Data Flow-Through Mode ORDERING INFORMATION IDT XXXX X XXX x xX Device Type Power Speed Package Process/ Temperature Range | | Blank Commercial (0C to +70C) 1) Industrial (-40C to +85C) B Military (-55C to +125C) Compliant to MIL-STD-883, Class B P Plastic DIP P28-1 = (7201 & 7202 Only) TP Plastic Thin DIP P28-2 D CERDIP D28-1 (7201 & 7202 Only) TD Thin CERDIP D28-3 J Plastic Leaded Chip Carrier PLCC J32-1 so SOIC S$028-3 L Leadless Chip Carrier LCC =L32-1 (7201 & 7202 Only) XE CERPACK E28-2 (7201 & 7202 Only) 12 Commercial Only 15 Commercial Only 20 Commercial and Military 25 Commercial and Industrial 30 Military On 35 Commerce, Only Access Time (ta) Speed 40 Military Only in Nanoseconds 50 Commercial and Military 65 Military only-- 80 except XE 120 package | La) Low Power 7200 4256 x 9-Bit FIFO 7201 512 x 9-Bit FIFO 7202 = 1,024 x 9-Bit FIFO 7280 256 x 9-Bit DUAL FIFO See 7280/7281/7282 7281 512x9-Bit DUAL FIFO data sheet for details 7282 1,024 x 9-Bit DUAL FIFO (3208. pdf) NOTES: 2679 dew 21 1. Industrial temperature range is available for plastic packages by special order for speed grades faster than 25ns. 2. A to be included for 7201 and 7202 ordering part number. 2975 Stender Way 800-345-7015 i DT Santa Clara, CA 95054 fax: 408-492-8674 www. idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.