FM3565 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID General Description The serial port is an IIC compatible slave-only interface and supports both 100kbit and 400kbit modes of operation. The port is used to read the I-Port and to write data to the internal nonvolatile registers. The FM3565 is fabricated with advanced CMOS technology to achieve high density and low power operation. The Fairchild FM3565 replaces the PC motherboard's CPU configuration switches with an electronic implementation, consisting of a 5-bit multiplexed port, standard 2-wire bus interface, and non-volatile latches with external hardware control. Features The FM3565 multiplexes the I-port input signals with two internal non-volatile registers that can be loaded through the serial port. The multiplexer output is under hardware control, and is determined by the inputs OVRD, MUXSEL, and A/B. Pull-up resistors are provided on the input port to accommodate connections to open drain outputs and to eliminate the need for external resistors. The device has open-drain outputs for easy interface to devices with different VDD Levels. Extended Operating Voltage Range 3.0V-5.5V IIC Compatible Slave Interface. ESD performance: Human body model > 2000V Open-Drain Outputs Block Diagram I [4:0] Y [4:0] Mux1 SOPRA Mux2 SOPRB MXSB, MXSA IIC Read Logic Mux3 MUXSEL A/B OVRD Control Logic SDA SCL IIC Interface Shift Register Slave Address Register Comparator ASEL Start/Stop Logic (c) 2001 Fairchild Semiconductor Corporation FM3565 Rev. A.1 1 www.fairchildsemi.com FM3565 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID Preliminary March 2001 FM 3565 XXXX Order Number X Blank X Tube Tape & Reel M20 MT20 20-Pin SO Package Option 20-Pin TSSOP Package Option Package Number Package Description FM3565MT20 MTC20 20-Pin TSSOP FM3565MT20X MTC20 20-Pin TSSOP T & R FM3565M20 M20B 20 Pin SO FM3565M20X M20B 20 Pin SO T & R For all other combinations, check with Fairchild Marketing/Sales Pin Connection Diagram Pin Description Pin Name 20-Pin Packages FM3565 I [0:4] Data Inputs w/Pullups (10K-40K) Y [0:4] Open-Drain Data Outputs WP SCL Serial Port Clock Input (120K pullup) 17 NC OVRD Override Input. Sets all outputs to 0 16 MUXSEL 6 15 Y0 WP Write Protect Input I3 7 14 Y1 NC No Connect I4 8 13 Y2 A/B 9 12 Y3 MUXSEL Multiplex Select Input 10 11 Y4 A/B Level Select Input ASEL Address Select Input SDA Serial Port Data I/O (120K pullup) SCL 1 20 VCC SDA 2 19 ASEL OVRD 3 18 I0 4 I1 5 I2 GND 2 FM3565 Rev. A.1 Description www.fairchildsemi.com FM3565 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID Ordering Code Serial Output Port Register (SOPR) The FM3565 block diagram is shown in Figure 1. (Address 000b and 001b) Operational Modes MXSB MXSA During standard operation, the device will pass data to the Y-Port either from the I-Port or from one of the internally stored NonVolatile Register values. Data Field 0 0 I5 0 I3 I2 I1 I0 b7 b6 b5 b4 b3 b2 B1 b0 b7-b6 - Multiplexer Select Bits (MXSB,MXSA) The I-port values are generated from the motherboard of the system and may be hardwired or driven by another device. Pullup resistors are provided on the device to accommodate this device being driven by open-drain output drivers. The device expects standard CMOS input signals. The outputs (Y0-Y4) operate in the open-drain mode. The OVRD (override) input, when set to 0, will cause all the outputs to be set to 0. The WP signal, if set to logic 1, will prevent data from being written to the non-volatile register. 00 - Multiplexer passes the SOPR(A). 01 - Multiplexer passer the SOPR(B). 10 - Multiplexer defaults to passing the I-Port Value. b5, b3-b0 - Data Field. New value to be output through the multiplexer. Parallel Input Port Register (PIPR) (Address 002b) The functioning of this device is described by the truth table in Table 1. Address Field Output Port: Y0-Y4 The output port is an open-drain output to allow for easy connection to devices running at different voltage levels. The port is always active and either passes the value on the I-Port or data from one of the internal non-volatile registers (SOPRA/B). Changing the Mux Path is accomplished using the external hardware controls - OVRD, MUXSEL, and A/B. Data Field 0 0 0 I4 I3 I2 I1 I0 b7 b6 b5 b4 b3 b2 B1 b0 b7-b5 - Address field. Value is always 000 b4-b0 - Data Field. Value is equal to the value on the I-Port. The external Port Register captures the value on the I-Port. Data is latched into this register on the first clock after a start condition is seen. This insures that a valid value will always be in this register if it is read. This register is a-read only register with respect to the IIC port. Register Description The FM3550/60 has 3 registers in total. These registers are made up of a combination of read-only, write-only and read/write bits. The two registers are listed below. Serial Output Port Register A(SOPRA) Address: 00H - A read/ write register that contains the new value of SOPRA. Serial Output Port Register B(SOPRB) Address: 01H - A read/ write register that contains the new value for SOPRB. Parallel Input Port Register (PIPR) Address: 02H - A read-only register that is loaded with the 5-bit value of the I-Port. 3 FM3565 Rev. A.1 www.fairchildsemi.com FM3565 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID Functional Description MUXSEL A/B Mux_outputs 0 0 X all 0's 0 1 X Mux_inputs 1 0 0 From Non-volatile register (SOPRB) 1 0 1 From Non-volatile register (SOPRA) (1) SOPRA: Serial Output Port Register A (2) SPORB: Serial Output Port Register B 1 1 X Mux_inputs (3) PIPR: PORT-I Value Data can be read from both of the internal registers. All reads are non-destructive and do not change the value in the register or the internal state of the device. When a start condition is received with a read request, both registers can be read out in the following sequence: If so desired, only the SOPRA register can be read. This is accomplished by issuing a stop command after the acknowledge bit for the first byte is read. If no stop is issued, the device will output the registers in the above sequence. Table 1. Multiplexer Control Options Multiplexer Logic The output multiplexer logic determines what value is actually output to the Y-port. The above table describes all the combinations. Writing to the Registers Data is written to the SOPR registers through the serial port interface. When a write request is received with the Start Address, it is assumed that the intent is to write to the SOPR registers. The value placed in the least 6 significant bits of the register contain the new code to be placed in the SOPR A/B registers. The value of the two most significant bits must contain the address of the destination register SOPRA or SOPRB. Serial Interface The IIC Interface is a standard slave interface. As such, the device will not generate its own clock. Data can be read from and written into the device. Commands for reading and writing the registers are generated by the Master. START and STOP Conditions The internal non-volatile latch takes about 10 ms to update its data. Register Read Sequence SDA Slave SOPRA SOPRB PIPR S Address R A Register A Register A Register A P SCL S START Condition STOP Condition 1001110 1 A 00bbbbbb A 00bbbbbb A 00bbbbbb A P Register Write Sequence This protocol uniquely defines START and STOP conditions. A START condition is defined as a HIGH to LOW transition of the SDA signal while SCL is HIGH. A STOP condition is defined as a LOW to HIGH transition of the SDA signal while SCL is HIGH. These are shown in Figure 2. Slave SOPRx S Address W A Register A S S 1001110 0 A xxbbbbbb A S xx = Register Selection bits (MXSB and MXSA) xx = 00 selects SOPRA, 01 selects SOPRB Device Addressing The device uses 7-bit addressing. The address has been defined as 1001 110 if the ASEL input is `1' and 0110 111 if the ASEL input is `0'. The address byte is the first byte of data sent after a start condition. This is the only address that this device will respond to. The device will not respond to the general call address 0000 000. Register Write Sequence using Repeated Start Condition Slave SOPRA Slave SOPRx S Address R A Register A S Address W A Register A P S 1001110 1 A 00bbbbbb A S 1001110 0 A xxbbbbbb A P Figure 4 4 FM3565 Rev. A.1 www.fairchildsemi.com FM3565 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID Reading from the Registers OVRD Recommended Operating Conditions Supply Voltage (VCC ) -0.5V to +6.5V (Note 3) DC Input Voltage (VI) -0.5V to +6.5V Power Supply 3.0V to 5.5V Input Voltage -0.3V to 5.5V Output Voltage (VO) Outputs 3-stated Outputs Active (Note 2) -0.5V to +6.5V -0.5 to VCC+0.5V DC Input Diode Current (IIK) VI < 0V 3mA Free Air Operating Temperature(TA) -50mA +50mA DC Output Source/Sink Current (IOH/IOL) 50mA Storage Temperature Range (TSTG) 0V to VCC Output Current IOL -50mA DC Output Diode Current (IOK) VO < 0V VO > Vcc DC VCC or Ground Current per Supply Pin (ICC or Ground) Output Voltage (VO) -0C to +70C Minimum Input Edge Rate (dt/dv) VIN = 0.8V to 2.0V, VCC = 3.0V 10ns/V 100mA -65C to +150C Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Floating or unused pins (inputs or I/O's) must be held HIGH or LOW. DC Electrical Characteristics (4.5V < VCC 5.5V unless stated otherwise) Symbol Parameter Conditions VIH High Level Input Voltage VIL Low Level Input Voltage VOL Low Level Output Voltage IOL = 100A IOL = 3mA IIR Input Leakage Current VI=VIL, VCC = 5.5V ICC Quiescent Supply Current VI = VCC or GND VCC (VI, VO) 3.6V Min Max Units VCC x 0.7 V VCC x 0.3 V 0.2 0.4 V -10 +10 A 300 975 A Max Units DC Electrical Characteristics Extended (3.0V VCC 5.5V unless stated otherwise) Symbol Parameter Conditions VIH High Level Input Voltage VIL Low Level Input Voltage VOL Low Level Output Voltage IOL = 100A IOL = 3mA VOH Output High Voltage Fixed output mode, ('S' grade samples, or FM3560 with LEVEL input = logical `0') 1 TTL load, 50pF capacitance IIR Input Leakage Current ICC Quiescent Supply Current V VCC x 0.3 V 0.2 0.4 V 2.3 2.5 V VI=VIL, VCC = 5.5V -10 +10 A VCC (VI, VO) 3.6V 300 975 A 5 FM3565 Rev. A.1 Min VCC x 0.7 www.fairchildsemi.com FM3565 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID Absolute Maximum Ratings (Note 1) Symbol TA = 0C to +70C, CL = 30pF, RL = 500 VCC = 5.0V 0.5V VCC = 3.3V 0.3V Parameter Min Max Min Units Max tPHL Prop Delay I to Y 50 50 ns tPLH Prop Delay I to Y 50 50 ns tPHL Prop Delay to Y (from OVRD or MUXSEL) 50 50 ns tPLH Prop Delay to Y (from OVRD or MUXSEL) 50 50 ns IIC AC Characteristics Symbol TA = 0C to +70C,CL = 30pF, RL = 500 100kHz 400kHz Parameter Min fSCL Max Min Units Max SCL Clock Frequency 100 400 kHz T1 Noise Supression Time Constant 100 50 nS tAA SCL Low to SDA Data Out Valid 0.3 0.9 S tBUF Time the Bus must be free before a new Transmission can start 4.7 1.3 S Start Condition Hold Time 4.0 0.6 S tLOW Clock Low Period 4.7 0.6 S tHIGH Clock High Period 4.0 0.6 S tSU:STA Start Condition Setup Time (For a repeated Start Condition) 4.7 0.6 tHD:DAT Data in Hold Time 0 0 S tSU:DAT Data in Setup Time 250 100 nS tHD:STA 3.5 0.1 tR SDA and SCL Rise Time 1000 300 nS tF SDA and SCL Fall Time 300 300 nS tSU:STO Stop Condition Setup Time 4.7 S 0.6 Capacitance Symbol Parameter TA = +25C Typical Conditions Units CIN Input Capacitance (I4-I0) VI =0V or VCC, VCC=3.3 or 5.0 6 pF CI/O Input/Output Capacitance (SDA) VI=0V or VCC, VCC=3.3 or 5.0 7 pF COUT Output Capacitance (Y4-Y0) 7 pF Non-Volatile Memory Characteristics Parameter Specification Data Retention 10 years minimum Number of writes 1,000,000 cycles 6 FM3565 Rev. A.1 www.fairchildsemi.com FM3565 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID AC Characteristics FM3565 CPU CONFIGURATION CONTROLLER Register/Multiplexer for Microprocessor VID Physical Dimensions inches (millimeters) unless otherwise noted Order Number FM3565MT Package Number MTC20 Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 7 FM3565 Rev. A.1 www.fairchildsemi.com