MB95110A - Fujitsu - Datasheet.Directory

DS07-12602-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

8-bit Proprietary Microcontrollers

CMOS

F2MC-8FX MB95110A Series

MB95116A/F118AS/F118AW/FV100A-101

■DESCRIPTION

The MB95110A series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,

the microcontrollers contain a variety of peripheral functions.

■FEATURES

• F2MC-8FX CPU core

Instruction set that is optimum to the controllers

• Multiplication and division instructions

• 16-bit arithmetic operation

• Bit test branch instruction

• Bit manipulation instructions etc.

• Clock

• Main clock

• Main PLL clock

• Subclock (for dual clock product)

• Sub PLL clock (for dual clock product) (Continued)

■PACKAGES

48-pin plastic BCC 48-pin plastic-LQFP

(LCC-48P-M09) (FPT-48P-M26)

MB95110A Series

(Continued)

• Timer

• 8/16-bit compound timer × 2 channels

• 8/16-bit PPG × 2 channels

• 16-bit PPG

• Timebase timer

• Watch prescaler (for dual clock product)

• LIN-UART

• Full duplex double buffer

• Clock asynchronous or synchronous serial transfer capable

• UART/SIO

• Clock asynchronous or synchronous serial transfer capable

• I2C*

• Built-in wake-up function

• External interrupt

• Interrupt by edge detection (rising, falling, or both edges can be selected)

• Can be used to recover from low-po wer consumption modes.

• 10-bit A/D converter

• 10-bit resolution

• Low-power consumption (standby mode)

• Stop mode

• Sleep mode

• Watch mode (for dual clock product)

• Timebase timer mode

• I/O port: Max 40

• General-purpose I/O ports (Nch open drain) : 2 ports

• General-purpose I/O ports (CMOS) : 38 ports

* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these com-

ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by

Philips.

MB95110A Series

■PRODUCT LINEUP

(Continued)

Part number

Parameter MB95116A MB95F118AS MB95F118AW MB95FV100A-101

Type MASK product FLASH product EVA product

ROM capacity 32 Kbytes 60 Kbytes

RAM capacity 1 Kbytes 2 Kbytes 3.75 Kbytes

Reset output No

Option Selectable

single/dual

-system*2Single-system Dual-system Selectable

single/dual

-system*1

CPU functions

Number of basic instructions : 136

Instruction bit length : 8 bits

Instruction length : 1 to 3 bytes

Data bit length : 1, 8, and 16 bits

Minimum instruction execution time : 0.1 µs (at internal 10 MHz)

Interrupt processing time : 0.9 µs (at internal 10 MHz)

Ports

(Max 40 ports) General-purpose I/O port (Nch open drain) : 2 ports

General-purpose I/O port (CMOS) : 38 ports

Timebase timer Interrupt cycle : 0.5 ms, 2.05 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)

Watchdog timer Reset generated cycle

At main oscillation clock 10 MHz : Minimum 105 ms

At sub oscillation clock 32.768 kHz (for dual clock product) : Minimum 250 ms

Wild register Capable of replacing 3 bytes of data

I2C bus

Master/slave sending and receiving

Bus error function and arbitration function

Detecting transmitting direction function

Start condition repeated generation and detection functions

Built-in wake-up function

UART/SIO

Data transfer capable in UART/SIO

Full duple x double b uffer, variable data length (5/6/7/8-bit), b uilt-in baud rate generator

Transfer rate : 2400 bps to 125000 bps (at machine clock 10 MHz)

NRZ type transfer format, error detected function

LSB-first or MSB-first can be selected.

Clock synchronous (SIO) or clock asynchronous (UART) data transfer capable

LIN-UART Dedicated reload timer allowing a wide range of communication speeds to be set.

Capable of data transfer synchronous or asynchronous to clock signal.

LIN functions available as the LIN master or LIN slave.

A/D converter

(8 channels) 8-bit or 10-bit resolution can be selected.

8/16-bit

compound timer

(2 channels)

Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer ×

1 channel”.

Built-in timer function, PWC function, PWM function, capture function and square

waveform output

Count clock : 7 internal clocks and external clock can be selected.

Peripheral functions

MB95110A Series

(Continued)

*1 : Change by the switch on MCU board.

*2 : Specify clock mode when ordering MASK ROM.

Part number

Parameter MB95116A MB95F118AS MB95F118AW MB95FV100A-101

16-bit PPG PWM mode or one-shot mode can be selected.

Counter operating clock : Eight selectable clock sources

Support for external trigger start

8/16-bit PPG

(2 channels)

Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG ×

1 channel”.

Counter operating clock : Eight selectable clock sources

Watch counter

(for dual cloc k product) Count clock : Four selectable clock sources (125ms, 250ms, 500ms, or 1s)

Counter value can be set from 0 to 63. (Capable of counting for 1 minute)

Watch prescaler

(for dual cloc k product) Four selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)

External interrupt

(8 channels) Interrupt by edge detection (rising, falling, or both edges can be selected)

Can be used to recover from standby modes.

Standby mode Sleep, stop, watch, and timebase timer

Peripheral functions

MB95110A Series

■SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK PRODUCT ONLY)

F or the MASK product, you can set the mask option when ordering MASK ROM to select the initial v alue of main

clock oscillation stabilization wait time from among the following four values.

Note that the EVA and FLASH products are fix ed their initial value of main cloc k oscillation stabilization wait time

at the maximum value.

■PACKAGES AND CORRESPONDING PRODUCTS

: Available

: Unavailable

Selection of oscillation stabilization wait time Remarks

(22 − 2) /FCH 0.5 µs (at main oscillation clock 4 MHz)

(212 − 2) /FCH Approx. 1.02 ms (at main oscillation clock 4 MHz)

(213 − 2) /FCH Approx. 2.05 ms (at main oscillation clock 4 MHz)

(214 − 2) /FCH Approx. 4.10 ms (at main oscillation clock 4 MHz)

Part number

Package MB95116A MB95F118AS MB95F118AW MB95FV100A-101

LCC-48P-M09

FPT-48P-M26

BGA-224P-M08

MB95110A Series

■DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS

• Notes on Using EVA Products

The EVA product has not only the functions of the MB95110A series but also those of other products to support

software development for multiple series and products of F2MC-8FX family. The I/O addresses for peripheral

resources not used by the MB95110A series are therefore access-barred. Read/write access to these access-

barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected

malfunctions of hardware or software.

Take par ticular care not to use word, long word, or similar access to read or write odd numbered bytes in the

prohibited areas.

Note that the values read from barred addresses are different between the EVA product and the FLASH or MASK

product. Therefore, the data must not be used for software processing.

The EV A product does not support the functions of some bits in single-byte registers. Read/write access to these

bits does not cause hardware malfunctions. Since the EV A, FLASH, and MASK products are designed to behave

completely the same wa y in terms of hardwa re and software, y ou do not hav e to pa y special attention to specific

products.

• Difference of Memory Spaces

If the amount of memory on the EVA product is different from that of the FLASH or MASK product, carefully

check the difference in the amount of memory from the product to be actually used when developing software.

• Current Consumption

• The current consumption of FLASH product is typically greater than for MASK product.

• For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.

• Package

For details of information on each package, see “■ PACKAGE DIMENSIONS”.

• Operating voltage

The operating voltage are different among the EVA, FLASH and MASK products.

For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”

• Difference between RST and MOD pins

The RST and MOD pins are hysteresis inputs on the MASK product. A pull-down resistor is provided for the

MOD pin of the MASK product.

MB95110A Series

■PIN ASSIGNMENTS

P65/SCK

P66/SOT

P67/SIN

37/AN07

36/AN06

35/AN05

34/AN04

33/AN03

32/AN02

31/AN01

30/AN00

AVss

P06/INT0

P05/INT0

P04/INT0

P03/INT0

P02/INT0

P01/INT0

P00/INT0

RST

PG1/X0A

PG2/X1A

PG0

Vcc

1413 15 16 17 18 19 20 21 22 23 24 25

48 47 46 45 44 43 42 41 40 39 38

TOP VIEW

AVcc

P24/EC0

P23/TO01

P22/TO00

21/PPG01

20/PPG00

P51/SDA0

P50/SCL0

MOD

Vss

P64/EC1

P63/TO11

P62/TO10

P61/PPG11

P60/PPG10

P15

P14/PPG0

P13/TRG0/ADT

P12/UCK0

P11/UO0

P10/UI0

P07/INT07

(LCC-48P-M09)

MB95110A Series

17 18 19 20 21 22 23 24

TOP VIEW

P65/SCK

P66/SOT

P67/SIN

37/AN07

36/AN06

35/AN05

34/AN04

33/AN03

32/AN02

31/AN01

30/AN00

AVss

AVcc

P24/EC0

P23/TO01

P22/TO00

21/PPG01

20/PPG00

P51/SDA0

P50/SCL0

MOD

Vss

P06/INT0

P05/INT0

P04/INT0

P03/INT0

P02/INT0

P01/INT0

P00/INT0

RST

PG1/X0A

PG2/X1A

PG0

Vcc

P64/EC1

P63/TO11

P62/TO10

P61/PPG11

P60/PPG10

P15

P14/PPG0

P13/TRG0/ADT

P12/UCK0

P11/UO0

P10/UI0

P07/INT07

(FPT-48P-M26)

MB95110A Series

■PIN DESCRIPTION

(Continued)

Pin no. Pin name Circuit type Description

1 P65/SCK K

General-purpose I/O port.

The pin is shared with LIN-UART clock I/O.

2 P66/SOT General-purpose I/O port.

The pin is shared with LIN-UART data output.

3 P67/SIN L General-purpose I/O port.

The pin is shared with LIN-UART data input.

4 P37/AN07

JGeneral-purpose I/O port.

The pins are shared with A/D analog input.

5 P36/AN06

6 P35/AN05

7 P34/AN04

8 P33/AN03

9 P32/AN02

10 P31/AN01

11 P30/AN00

12 AVss ⎯A/D power supply pin (GND)

13 AVcc ⎯A/D power supply pin

14 P24/EC0

General-purpose I/O port.

The pin is shared with 8/16-bit compound timer ch0 clock input.

15 P23/TO01 General-purpose I/O port.

The pins are shared with 8/16-bit compound timer ch0 output.

16 P22/TO00

17 P21/PPG01 General-purpose I/O port.

The pins are shared with 8/16-bit PPG ch0 output.

18 P20/PPG00

19 P51/SDA0 I

General-purpose I/O port.

The pin is shared with I2C ch0 data I/O.

20 P50/SCL0 General-purpose I/O port.

The pin is shared with I2C ch0 clock I/O.

21 MOD B Operating mode designation pin

22 X0 A Crystal oscillation pin

23 X1

24 Vss ⎯Power supply pin (GND)

25 Vcc ⎯Power supply pin

26 PG0 H General-purpose I/O port.

27 PG2/X1A H/A Single-system product is general-purpose port.

Dual-system product is Crystal oscillation pin (32 kHz).

28 PG1/X0A

29 RST B’ Reset pin

MB95110A Series

(Continued)

Pin no. Pin name Circuit type Description

30 P00/INT00

CGeneral-purpose I/O port.

The pins are shared with external interrupt input. Large current port.

31 P01/INT01

32 P02/INT02

33 P03/INT03

34 P04/INT04

35 P05/INT05

36 P06/INT06

37 P07/INT07

38 P10/UI0 G General-purpose I/O port.

The pin is shared with UART/SIO ch0 data input.

39 P11/UO0

General-purpose I/O port.

The pin is shared with UART/SIO ch0 data output.

40 P12/UCK0 General-purpose I/O port.

The pin is shared with UART/SIO ch0 clock I/O.

41 P13/TRG0/

ADTG

General-purpose I/O port.

The pin is shared with 16-bit PPG ch0 trigger input (TRG0) and A/D

trigger input (ADTG).

42 P14/PPG0 General-purpose I/O port.

The pin is shared with 16-bit PPG ch0 output.

43 P15 General-purpose I/O port.

44 P60/PPG10

General-purpose I/O port.

The pins are shared with 8/16-bit PPG ch1 output.

45 P61/PPG11

46 P62/TO10 General-purpose I/O port.

The pins are shared with 8/16-bit compound timer ch1 output.

47 P63/TO11

48 P64/EC1 General-purpose I/O port.

The pin is shared with 8/16-bit compound timer ch1 clock input.

MB95110A Series

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

• Oscillation circuit

• High-speed side

Feedback resistance value : approx. 1 MΩ

• Low-speed side

Feedback resistance : approx. 24 MΩ

(EVA product : approx. 10 MΩ)

Dumping resistance : approx. 144 kΩ

(EVA product : without dumping resistance)

• Only for input

• Hysteresis input only for MASK product

• With pull-down resistor only for MASK

product

B’ • Hysteresis input only for MASK product

• CMOS output

• Hysteresis input

• CMOS output

• CMOS input

• Hysteresis input

• With pull-up control

0 (X0A)

X1 (X1A)

Standby control

Pch

Nch

Standby control

External

interrupt enable

Pch

Nch

Pull-up control

Standby control

MB95110A Series

(Continued)

Type Circuit Remarks

•CMOS output

• Hysteresis input

• With pull-up control

• Nch open drain output

•CMOS input

• Hysteresis input

•CMOS output

• Hysteresis input

• Analog input

• With pull-up control

•CMOS output

• Hysteresis input

•CMOS output

•CMOS input

• Hysteresis input

Pch

Nch

R Pull-up control

Standby control

Nch

Standby control

Pch

Nch

Pull-up control

Analog input

A/D control

Standby control

Pch

Nch

Standby control

Pch

Nch

Standby control

MB95110A Series

■HANDLING DEVICES

• Preventing Latchup

Care must be taken to ensure that maximum voltage ratings are not exceeded when it is used.

Latchup ma y occur on CMOS ICs if v oltage higher than VCC or low er than VSS is applied to input and output pins

other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC

and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements.

Also, take care to prevent the analog power supply v oltage (AVCC) and analog input voltage from e xceeding the

digital power supply voltage (VCC) when the analog system power supply is turned on or off.

• Stable Supply Voltage

Supply voltage should be stabilized.

A sudden change in pow er-supply voltage ma y cause a malfunction ev en within the guaranteed operating r ange

of the Vcc power-supply voltage.

For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range

(50 Hz to 60 Hz) not to exceed 10% of the Vcc value and suppress the voltage variation so that the transient

variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.

• Treatment of Unused Input Pin

An unused input pin may cause a malfunction if it is left open. It should be connected to a pull-up or pull-down

resistor.

• Treatment of Power Supply Pins on A/D Converter

Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.

• Precautions for Use of External Clock

Even when an external clock is used, oscillation stabilization wait time is required for powe r-on reset, wake-up

from subclock mode or stop mode.

• Precaution against Noise to the External Reset Pin (RST)

An input of a reset pulse below the specified level to the external reset pin (RST) may cause malfunctions. Be

sure not to allow an input of a reset pulse below the specified level to the external reset pin (RST).

MB95110A Series

■PROGRAMMING FLASH MICROCONTROLLERS USING PARALLEL PROGRAMMER

• Supported Parallel Programmers and Adapters

The following table lists supported parallel programmers and adapters.

Notes: • Set all of the J1 to J3 switches on the adapter to "95F108".

• For information on applicable adapter models and parallel programmers, contact the following:

Flash Support Group, Inc. TEL: 053-428-8380

• Sector Configuration

The individual sectors of flash memory correspond to addresses used fo r CPU access and programming b y the

parallel programmer as follows:

• Programming Method

1) Set the type code of the parallel programmer to 17226.

2) Load program data to programmer addresses 71000H to 7FFFFH.

3) Programmed by parallel programmer

Package Applicable adapter model Parallel programmers

FPT-48P-M26 TEF110-108F37AP AF9708 (Ver 02.35G or more)

AF9709/B (Ver 02.35G or more)

AF9723+AF9834 (Ver 02.08E or more)

LCC-48P-M09 TEF100-108F41AP

*: Programmer addresses are equivalent to CPU addresses, used when the parallel programmer programs

data into flash memory.

These programmer addresses are used for the parallel programmer to program or erase data in flash memory

Flash memory CPU address Writer address*

SA1 (4 Kbytes) 1000H71000H

1FFFH71FFFH

SA2 (4 Kbytes) 2000H72000H

2FFFH72FFFH

SA3 (4 Kbytes) 3000H73000H

3FFFH73FFFH

SA4 (16 Kbytes) 4000H74000H

7FFFH77FFFH

SA5 (16 Kbytes) 8000H78000H

BFFFH7BFFFH

SA6 (4 Kbytes) C000H7C000H

CFFFH7CFFFH

SA7 (4 Kbytes) D000H7D000H

DFFFH7DFFFH

SA8 (4 Kbytes) E000H7E000H

EFFFH7EFFFH

SA9 (4 Kbytes) F000H7F000H

FFFFH7FFFFH

Lower bank

Upper bank

MB95110A Series

■BLOCK DIAGRAM

P15

P65/SCK

P67/SIN

AVCC

AVSS

P50/SCL0

P51/SDA0

P30/AN00 to P37/AN07

P12/UCK0 P62/TO10

P61/PPG1

P60/PPG1

P63/TO11

00/INT00 to P07/INT07

P10/UI0

P64/EC1

P66/SOT

RST

X0,X1

P14/PPG0

P13/TRG0/ADTG

P20/PPG00

P21/PPG01

P22/TO00

P23/TO01

P24/EC0

P11/UO0 UART/SIO

16-bit PPG

8/16-bit PPG ch0

10-bit A/D

converter

I2C

8/16-bit PPG ch1

ROM

RAM

F2MC-8FX CPU

Port Port

8/16-bit compound

timer ch0

8/16-bit compound

timer ch1

Interrupt control

Wild register

Reset control

Clock control

Watch prescaler

Watch counter

External interrupt

Internal bus

PG2/X1A*

PG1/X0A*

PG0

LIN-UART

MOD, VCC, VSS

* : Single-system product is general-purpose port, and dual-system product is subclock oscillation.

Other pins

MB95110A Series

■CPU CORE

1. Memory space

Memor y space of the MB95110A series is 64 Kbytes and consists of I/O area, data area, and program area.

The memory space includes special-purpose areas such as the general-purpose registers and vector table.

Memory map of the MB95110A series shown in below.

0000H

0080H

0100H

0200H

0880H

0F80H

1000H

FFFFH

FLASH 60 KB

MB95F118A

I/O

RAM 2 KB

I/O

0000H

0080H

0100H

0200H

0F80H

1000H

FFFFH

I/O

FLASH 60 KB

RAM 3.75 KB

MB95FV100A-10

I/O

000H

080H

100H

200H

480H

F80H

000H

FFFH

ROM 32 KB

MB95116A

I/O

RAM 1 KB

I/O

000H

Access

prohibited

Access

prohibited

Access

prohibited

• Memory Map

MB95110A Series

2. Register

The MB95110A series has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The dedicated registers are as follows:

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer

(DP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)

Program counter (PC) :A 16-bit register to indicate locations where instructions are stored.

Accumulator (A) :A 16-bit register for temporary storage of arithmetic operations. In the case of

an 8-bit data processing instruction, the lower one byte is used.

Temporary accumulator (T) :A 16-bit register which performs arithmetic operations with the accumulator.

In the case of an 8-bit data processing instruction, the lower one byte is used.

Index register (IX) :A 16-bit register for index modification

Extra pointer (EP) :A 16-bit pointer to point to a memory address.

Stack pointer (SP) :A 16-bit register to indicate a stack area.

Program status (PS) :A 16-bit register for storing a register bank pointer, a direct bank pointer, and

a condition code register

16-bit : Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

Initial Value

FFFDH

0000H

0030H

RP CCR

15 14 13 12 11 10 9 8

DP2 DP1 DP0

76543210

R4 R3 R2 R1 R0 H I IL1 IL0 N Z VC

• Structure of the program status

MB95110A Series

The RP indicates the address of the register bank currently being used. The relationship between the content

of RP and the real address conforms to the conversion rule illustrated below:

The DP specifies the area for mapping instr uctions (16 different instr uctions such as MOV A, dir) using direct

addresses to 0080H to 00FFH.

The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that

control CPU operations at interrupt.

Direct bank pointer (DP2 to DP0) Specified address area Mapping area

Don’t care 0000H to 007FH0000H to 007FH (without mapping)

000B (initial value)

0080H to 00FFH

0080H to 00FFH (without mapping)

001B0100H to 017FH

010B0180H to 01FFH

011B0200H to 027FH

100B0280H to 02FFH

101B0300H to 037FH

110B0380H to 03FFH

111B0400H to 047FH

H flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to “0” otherwise. This flag is for decimal adjustment instructions.

I flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.

The flag is set to “0” when reset.

IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level

is higher than the value indicated by this bit.

IL1 IL0 Interrupt level Priority

00 0 High

Low = no interruption

01 1

10 2

11 3

N flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the

bit is set to “0”.

Z flag : Set to “1” when an arithmetic operation results in 0. Cleared to “0” otherwise.

V flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”

otherwise.

C flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared

to “0” otherwise. Set to the shift-out value in the case of a shift instruction.

"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 b1 b0

A7 A6 A5 A4 A3 A2 A1 A0

A15 A14 A13 A12 A11 A10 A9 A8

• Rule for Conversion of Actual Addresses in the General-purpose Register Area

Generated address

RP upper OP code lower

MB95110A Series

The following general-purpose registers are provided:

General-purpose registers: 8-bit data storage registers

The general-purpose registers are 8 bits and located in the register banks on the memory. One bank contains

eight registers. Up to a total of 32 banks can be used on the MB95110A series. The bank currently in use is

indicated by the register bank pointer (RP).

This address = 0100H + 8 x (RP)

32 banks

Memory area

• Register Bank Configuration

MB95110A Series

■I/O MAP

(Continued)

Address Register

abbreviation Register name R/W Initial value

0000HPDR0 Port 0 data register R/W 00000000B

0001HDDR0 Port 0 direction register R/W 00000000B

0002HPDR1 Port 1 data register R/W 00000000B

0003HDDR1 Port 1 direction register R/W 00000000B

0004H⎯ (Vacancy) ⎯⎯

0005HWATR Oscillation stabilization wait time setting register R/W 11111111B

0006HPLLC PLL control register R/W 00000000B

0007HSYCC System clock control register R/W 1010X011B

0008HSTBC Standby control register R/W 00000000B

0009HRSRR Reset source register R XXXXXXXXB

000AHTBTC Timebase timer control register R/W 00000000B

000BHWPCR Watch prescaler control register R/W 00000000B

000CHWDTC Watchdog timer control register R/W 00000000B

000DH⎯ (Vacancy) ⎯⎯

000EHPDR2 Port 2 data register R/W 00000000B

000FHDDR2 Port 2 direction register R/W 00000000B

0010HPDR3 Port 3 data register R/W 00000000B

0011HDDR3 Port 3 direction register R/W 00000000B

0012H⎯ (Vacancy) ⎯⎯

0013H

0014HPDR5 Port 5 data register R/W 00000000B

0015HDDR5 Port 5 direction register R/W 00000000B

0016HPDR6 Port 6 data register R/W 00000000B

0017HDDR6 Port 6 direction register R/W 00000000B

0018H

0029H

⎯ (Vacancy) ⎯⎯

002AHPDRG Port G data register R/W 00000000B

002BHDDRG Port G direction register R/W 00000000B

002CH⎯ (Vacancy) ⎯⎯

002DHPUL1 Port 1 pull-up register R/W 00000000B

002EHPUL2 Port 2 pull-up register R/W 00000000B

002FHPUL3 Port 3 pull-up register R/W 00000000B

0030H

0034H

⎯ (Vacancy) ⎯⎯

MB95110A Series

(Continued)

Address Register

abbreviation Register name R/W Initial value

0035HPULG Port G pull-up register R/W 00000000B

0036HT01CR1 8/16-bit compound timer 01 control status register 1 ch0 R/W 00000000B

0037HT00CR1 8/16-bit compound timer 00 control status register 1 ch0 R/W 00000000B

0038HT11CR1 8/16-bit compound timer 11 control status register 1 ch1 R/W 00000000B

0039HT10CR1 8/16-bit compound timer 10 control status register 1 ch1 R/W 00000000B

003AHPC01 8/16-bit PPG1 control register ch0 R/W 00000000B

003BHPC00 8/16-bit PPG0 control register ch0 R/W 00000000B

003CHPC11 8/16-bit PPG1 control register ch1 R/W 00000000B

003DHPC10 8/16-bit PPG0 control register ch1 R/W 00000000B

003EH

0041H

⎯ (Vacancy) ⎯⎯

0042HPCNTH0 16-bit PPG status control register (Upper byte) ch0 R/W 00000000B

0043HPCNTL0 16-bit PPG status control register (Lower byte) ch0 R/W 00000000B

0044H

0047H

⎯ (Vacancy) ⎯⎯

0048HEIC00 External interrupt circuit control register ch0/1 R/W 00000000B

0049HEIC10 External interrupt circuit control register ch2/3 R/W 00000000B

004AHEIC20 External interrupt circuit control register ch4/5 R/W 00000000B

004BHEIC30 External interrupt circuit control register ch6/7 R/W 00000000B

004CH

004FH

⎯ (Vacancy) ⎯⎯

0050HSCR LIN-UART serial control register R/W 00000000B

0051HSMR LIN-UART serial mode register R/W 00000000B

0052HSSR LIN-UART serial status register R/W 00001000B

0053HRDR/TDR LIN-UART reception/transmission data register R/W 00000000B

0054HESCR LIN-UART extended status control register R/W 00000100B

0055HECCR LIN-UART extended communication control register R/W 000000XXB

0056HSMC10 UART/SIO serial mode control register 1 ch0 R/W 00000000B

0057HSMC20 UART/SIO serial mode control register 2 ch0 R/W 00100000B

0058HSSR0 UART/SIO serial status register ch0 R/W 00000001B

0059HTDR0 UART/SIO serial output data register ch0 R/W 00000000B

005AHRDR0 UART/SIO serial input data register ch0 R 00000000B

005BH

005FH

⎯ (Vacancy) ⎯⎯

MB95110A Series

(Continued)

Address Register

abbreviation Register name R/W Initial value

0060HIBCR00 I2C bus control register 0 ch0 R/W 00000000B

0061HIBCR10 I2C bus control register 1 ch0 R/W 00000000B

0062HIBSR0 I2C bus status register ch0 R 00000000B

0063HIDDR0 I2C data register ch0 R/W 00000000B

0064HIAAR0 I2C address register ch0 R/W 00000000B

0065HICCR0 I2C clock control register ch0 R/W 00000000B

0066H

006BH

⎯ (Vacancy) ⎯⎯

006CHADC1 A/D control register 1 R/W 00000000B

006DHADC2 A/D control register 2 R/W 00000000B

006EHADDH A/D data register (Upper byte) R/W 00000000B

006FHADDL A/D data register (Lower byte) R/W 00000000B

0070HWCSR Watch counter status register R/W 00000000B

0071H⎯ (Vacancy) ⎯⎯

0072HFSR Flash memory status register R/W 000X0000B

0073HSWRE0 Flash memory sector writing control register 0 R/W 00000000B

0074HSWRE1 Flash memory sector writing control register 1 R/W 00000000B

0075H⎯ (Vacancy) ⎯⎯

0076HWREN Wild register address compare enable register R/W 00000000B

0077HWROR Wild register data test setting register R/W 00000000B

0078H⎯ (Mirror of register bank pointer (RP) and direct bank

pointer (DP) ) ⎯⎯

0079HILR0 Interrupt level setting register 0 R/W 11111111B

007AHILR1 Interrupt level setting register 1 R/W 11111111B

007BHILR2 Interrupt level setting register 2 R/W 11111111B

007CHILR3 Interrupt level setting register 3 R/W 11111111B

007DHILR4 Interrupt level setting register 4 R/W 11111111B

007EHILR5 Interrupt level setting register 5 R/W 11111111B

007FH⎯ (Vacancy) ⎯⎯

0F80HWRARH0 Wild register address setting register (Upper byte) ch0 R/W 00000000B

0F81HWRARL0 Wild register address setting register (Lower byte) ch0 R/W 00000000B

0F82HWRDR0 Wild register data setting register ch0 R/W 00000000B

0F83HWRARH1 Wild register address setting register (Upper byte) ch1 R/W 00000000B

0F84HWRARL1 Wild register address setting register (Lower byte) ch1 R/W 00000000B

0F85HWRDR1 Wild register data setting register ch1 R/W 00000000B

MB95110A Series

(Continued)

Address Register

abbreviation Register name R/W Initial value

0F86HWRARH2 Wild register address setting register (Upper byte) ch2 R/W 00000000B

0F87HWRARL2 Wild register address setting register (Lower byte) ch2 R/W 00000000B

0F88HWRDR2 Wild register data setting register ch2 R/W 00000000B

0F89H

0F91H

⎯ (Vacancy) ⎯⎯

0F92HT01CR0 8/16-bit compound timer 01 control status register 0 ch0 R/W 00000000B

0F93HT00CR0 8/16-bit compound timer 00 control status register 0 ch0 R/W 00000000B

0F94HT01DR 8/16-bit compound timer 01 data register ch0 R/W 00000000B

0F95HT00DR 8/16-bit compound timer 00 data register ch0 R/W 00000000B

0F96HTMCR0 8/16-bit compound timer 00/01 timer mode control

0F97HT11CR0 8/16-bit compound timer 11 control status register 0 ch1 R/W 00000000B

0F98HT10CR0 8/16-bit compound timer 10 control status register 0 ch1 R/W 00000000B

0F99HT11DR 8/16-bit compound timer 11 data register ch1 R/W 00000000B

0F9AHT10DR 8/16-bit compound timer 10 data register ch1 R/W 00000000B

0F9BHTMCR1 8/16-bit compound timer 10/11 timer mode control

0F9CHPPS01 8/16-bit PPG1 cycle setting buffer register ch0 R/W 11111111B

0F9DHPPS00 8/16-bit PPG0 cycle setting buffer register ch0 R/W 11111111B

0F9EHPDS01 8/16-bit PPG1 duty setting buffer register ch0 R/W 11111111B

0F9FHPDS00 8/16-bit PPG0 duty setting buffer register ch0 R/W 11111111B

0FA0HPPS11 8/16-bit PPG1 cycle setting buffer register ch1 R/W 11111111B

0FA1HPPS10 8/16-bit PPG0 cycle setting buffer register ch1 R/W 11111111B

0FA2HPDS11 8/16-bit PPG1 duty setting buffer register ch1 R/W 11111111B

0FA3HPDS10 8/16-bit PPG0 duty setting buffer register ch1 R/W 11111111B

0FA4HPPGS 8/16-bit PPG starting register R/W 00000000B

0FA5HREVC 8/16-bit PPG output inversion register R/W 00000000B

0FA6H

0FA9H

⎯ (Vacancy) ⎯⎯

0FAAHPDCRH0 16-bit PPG down counter register (Upper byte) ch0 R 00000000B

0FABHPDCRL0 16-bit PPG down counter register (Lower byte) ch0 R 00000000B

0FACHPCSRH0 16-bit PPG cycle setting buffer register (Upper byte) ch0 R/W 11111111B

0FADHPCSRL0 16-bit PPG cycle setting buffer register (Lower byte) ch0 R/W 11111111B

0FAEHPDUTH0 16-bit PPG duty setting buffer register (Upper byte) ch0 R/W 11111111B

0FAFHPDUTL0 16-bit PPG duty setting buffer register (Lower byte) ch0 R/W 11111111B

MB95110A Series

(Continued)

• Read/write access symbols

• Initial value symbols

Address Register

abbreviation Register name R/W Initial value

0FB0H

0FBBH

⎯ (Vacancy) ⎯⎯

0FBCHBGR1 LIN-UART baud rate generator register 1 R/W 00000000 B

0FBDHBGR0 LIN-UART baud rate generator register 0 R/W 00000000 B

0FBEHPSSR0 UART/SIO prescaler selection register ch0 R/W 00000000B

0FBFHBRSR0 UART/SIO baud rate setting register ch0 R/W 00000000B

0FC0H

0FC2H

⎯ (Vacancy) ⎯⎯

0FC3HAIDRL A/D input disable register (Lower byte) R/W 00000000B

0FC4H

0FE2H

⎯ (Vacancy) ⎯⎯

0FE3HWCDR Watch counter data register R/W 00111111B

0FE4H

0FEDH

⎯ (Vacancy) ⎯⎯

0FEEHILSR Input level select register R/W 00000000B

0FEFHWICR Interrupt pin control register R/W 01000000B

0FF0H

0FFFH

⎯ (Vacancy) ⎯⎯

R/W : Readable and Writable

R : Read only

W : Write only

0 : The initial value of this bit is “0”.

1 : The initial value of this bit is “1”.

X : The initial value of this bit is undefined.

MB95110A Series

■INTERRUPT SOURCE TABLE

Interrupt source Interrupt

request

number

Vector table address Bit name of

interrupt level

setting register

Same level

priority order

(at simultaneous

occurrence)

Upper Lower

External interrupt ch0 IRQ0 FFFAHFFFBHL00 [1 : 0] High

External interrupt ch4

External interrupt ch1 IRQ1 FFF8HFFF9HL01 [1 : 0]

External interrupt ch5

External interrupt ch2 IRQ2 FFF6HFFF7HL02 [1 : 0]

External interrupt ch6

External interrupt ch3 IRQ3 FFF4HFFF5HL03 [1 : 0]

External interrupt ch7

UART/SIO ch0 IRQ4 FFF2HFFF3HL04 [1 : 0]

8/16-bit compound timer ch0

(Lower) IRQ5 FFF0HFFF1HL05 [1 : 0]

8/16-bit compound timer ch0

(Upper) IRQ6 FFEEHFFEFHL06 [1 : 0]

LIN-UART (reception) IRQ7 FFECHFFEDHL07 [1 : 0]

LIN-UART (transmission) IRQ8 FFEAHFFEBHL08 [1 : 0]

8/16-bit PPG ch1 (Lower) IRQ9 FFE8HFFE9HL09 [1 : 0]

8/16-bit PPG ch1 (Upper) IRQ10 FFE6HFFE7HL10 [1 : 0]

(Unused) IRQ11 FFE4HFFE5HL11 [1 : 0]

8/16-bit PPG ch0 (Upper) IRQ12 FFE2HFFE3HL12 [1 : 0]

8/16-bit PPG ch0 (Lower) IRQ13 FFE0HFFE1HL13 [1 : 0]

8/16-bit compound timer ch1

(Upper) IRQ14 FFDEHFFDFHL14 [1 : 0]

16-bit PPG ch0 IRQ15 FFDCHFFDDHL15 [1 : 0]

I2C ch0 IRQ16 FFDAHFFDBHL16 [1 : 0]

(Unused) IRQ17 FFD8HFFD9HL17 [1 : 0]

10-bit A/D converter IRQ18 FFD6HFFD7HL18 [1 : 0]

Timebase timer IRQ19 FFD4HFFD5HL19 [1 : 0]

Watch prescaler/counter IRQ20 FFD2HFFD3HL20 [1 : 0]

(Unused) IRQ21 FFD0HFFD1HL21 [1 : 0]

8/16-bit compound timer ch1

(Lower) IRQ22 FFCEHFFCFHL22 [1 : 0]

FLASH IRQ23 FFCCHFFCDHL23 [1 : 0] Low

MB95110A Series

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximu m Ratings

(Continued)

Parameter Symbol Rating Unit Remarks

Min Max

Power supply voltage*1Vcc,

AVcc Vss − 0.3 Vss + 4.0 V*2

AVR Vss − 0.3 Vss + 4.0 *2 MB95FV100A-101 only

Input voltage*1VI1 Vss − 0.3 Vss + 4.0 VOther than P50, P51*3

VI2 Vss − 0.3 Vss + 6.0 P50, P51

Output voltage*1VOVss − 0.3 Vss + 4.0 V *3

Maximum clamp current ICLAMP − 2.0 + 2.0 mA Applicable to pins*4

Total maximum clamp current Σ|ICLAMP|⎯20 mA Applicable to pins*4

“L” level maximum

output current IOL1 ⎯15 mA Other than P00 to P07

IOL2 15 P00 to P07

“L” level average current

IOLAV1

⎯

Other than P00 to P07

Average output current =

operating current × operating ratio

(1 pin)

IOLAV2 12

P00 to P07

Average output current =

operating current × operating ratio

(1 pin)

“L” level total maximum

output current ΣIOL ⎯100 mA

“L” level total average

output current ΣIOLAV ⎯50 mA Total average output current =

operating current × operating ratio

(total of pins)

“H” level maximum

output current IOH1 ⎯ − 15 mA Other than P00 to P07

IOH2 − 15 P00 to P07

“H” level average current

IOHAV1

⎯

− 4

Other than P00 to P07

Average output current =

operating current × operating ratio

(1 pin)

IOHAV2 − 8

P00 to P07

Average output current =

operating current × operating ratio

(1 pin)

“H” level total maximum

output current ΣIOH ⎯ − 100 mA

“H” level total average

output current ΣIOHAV ⎯ − 50 mA Total average output current =

operating current × operating ratio

(total of pins)

Power consumption Pd ⎯320 mW

Operating temperature TA − 40 + 85 °C Other than MB95FV100A-101

Storage temperature Tstg − 55 + 150 °C

MB95110A Series

(Continued)

*1 : The parameter is based on AVCC = VSS = 0.0 V.

*2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V.

*3 : VI1 and VO should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum

current to/from an input is limited by some means with external components, the I CLAMP r ating supersedes the

VI1 rating.

*4 : •Applicable to pins : P00 to P07, P10 to P15, P20 to P24, P30 to P37, PG0

•Use within recommended operating conditions.

•Use at DC voltage (current).

•The + B signal should always be applied a limiting resistance placed between the + B signal and the

microcontroller.

•The value of the limiting resistance should be set so that when the + B signal is applied the input current

to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

•Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the VCC pin, and this may

affect other devices.

•Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power

supply is provided from the pins, so that incomplete operation may result.

•Note that if the + B input is applied during power-on, the power supply is provided from the pins and the

resulting power supply voltage may not be sufficient to operate the power-on reset.

•Care must be taken not to leave the + B input pin open.

•Sample recommended circuits :

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Pch

Nch

Vcc

• Input/Output Equivalent Circuits

+ B input (0 V to 16 V)

Limiting

resistance

Protective diode

MB95110A Series

2. Recommended Operating Conditions (AVSS = VSS = 0.0 V)

*1 : The values vary with the operating frequency.

*2 : Consult Fujitsu separately for a guarantee of a maximum value of 3.6 V.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Value Unit Remarks

Min Max

Power supply voltage VCC,

AVCC

1.8*13.3*2

At normal operating, FLASH product,

TA = −10 °C to +85 °C

1.8*13.6 At normal operating, MASK product,

TA = −10 °C to +85 °C

2.0*13.3*2At normal operating, FLASH product,

TA = −40 °C to +85 °C

2.0*13.6 At normal operating, MASK product,

TA = −40 °C to +85 °C

2.6 3.6 MB95FV100A-101

1.5 3.3*2Retain status of stop operation, FLASH product

1.5 3.6 Retain status of stop operation, MASK product

Operating temperature TA − 40 + 85 °C Other than MB95FV100A-101

MB95110A Series

3. DC Characteristics

(Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C [MB95FV100A-101 is TA = +25 °C])

(Continued)

Parameter Sym

bol Pin name Condi-

tions Value Unit Remarks

Min Typ Max

“H” level input

voltage

VIH1 P10, P67 *1 0.7 Vcc ⎯Vcc + 0.3 V At selecting of

CMOS input level

(hysteresis input)

VIH2 P50, P51 *1 0.7 Vcc ⎯Vss + 5.5 V At selecting of

CMOS input level

(hysteresis input)

VIHS1

P00 to P07,

P10 to P15,

P20 to P24,

P30 to P37,

P60 to P67, PG0,

PG1*2, PG2*2

*1 0.8 Vcc ⎯Vcc + 0.3 V Hysteresis input

VIHS2 P50, P51 *1 0.8 Vcc ⎯Vss + 5.5 V Hysteresis input

VIHM RST, MOD ⎯0.7 Vcc ⎯Vcc + 0.3 V CMOS input

(FLASH product)

⎯0.8 Vcc ⎯Vcc + 0.3 V Hysteresis input

(MASK product)

“L” level input

voltage

VIL P10, P50, P51,

P67 *1 Vss − 0.3 ⎯0.3 Vcc V At selecting of

CMOS input level

(hysteresis input)

VILS

P00 to P07,

P10 to P15,

P20 to P24,

P30 to P37, P50,

P51, P60 to P67,

PG0, PG1*2,

PG2*2

*1 Vss − 0.3 ⎯0.2 Vcc V Hysteresis input

VILM RST, MOD ⎯Vss − 0.3 ⎯0.3 Vcc V CMOS input

(FLASH product)

⎯Vss − 0.3 ⎯0.2 Vcc V Hysteresis input

(MASK product)

Open drain

output application

voltage VDP50, P51 ⎯Vss − 0.3 ⎯Vss + 5.5 V

“H” level output

voltage

VOH1 Output pin other

than P00 to P07 IOH =

− 4.0 mA 2.4 ⎯⎯VMB95FV100A-101

a conditional :

IOH = − 2.0 mA

VOH2 P00 to P07 IOH =

− 8.0 mA 2.4 ⎯⎯VMB95FV100A-101

a conditional :

IOH = − 5.0 mA

MB95110A Series

(Continued) (Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C [MB95FV100A-101 is TA = +25 °C])

(Continued)

Parameter Sym-

bol Pin name Conditions Value Unit Remarks

Min Typ Max

“L” level output

voltage

VOL1 Output pin

other than

P00 to P07

IOL =

4.0 mA ⎯⎯0.4 V MB95FV100A-

101 a conditional :

IOL = 3.0 mA

VOL2 P00 to P07 IOL = 12 mA ⎯⎯0.4 V MB95FV100A-

101 a conditional :

IOL = 8.0 mA

Input leakage

current (High-Z

output leakage

current)

ILI Port other

than P50,

P51 0.0 V < VI < Vcc − 5 ⎯ + 5 µAWhen no pull-up

resistor is

specified

Open drain

output leakage

current ILIOD P50, P51 0.0 V < VI < Vss +

5.5 V ⎯⎯ + 5 µA

Pull-up resistor RPULL

P10 to P15,

P20 to P24,

P30 to P37,

PG0, PG1*2,

PG2*2

VI = 0.0 V 25 50 100 kΩWhen pull-up

resistor is

specified

Pull-down

resistor RMOD MOD VI = Vcc 50 100 200 kΩMASK product

only

Power supply

current*3

ICC

VCC

(external

clock

operation)

FCH = 20 MHz

fmp = 10 MHz

Main clock mode

(divided by 2)

⎯11 14 mA FLASH product

⎯7.3 10 mA MASK product

⎯30 35 mA FLASH product

(at FLASH writing

and erasing)

ICCS

FCH = 20 MHz

fmp = 10 MHz

Main Sleep mode

(divided by 2)

⎯4.5 6 mA

ICCL

FCL = 32 kHz

fmpl = 16 kHz

Subclock mode

(divided by 2) ,

TA = + 25 °C

⎯25 35 µA

ICCLS

FCL = 32 kHz

fmpl = 16 kHz

Sub sleep mode

(divided by 2) ,

TA = + 25 °C

⎯715µA

MB95110A Series

(Continued) (Vcc = AVcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C [MB95FV100A-101 is TA = +25 °C])

*1 : P10, P50, P51, and P67 can s witch the input le v el to either the “CMOS input le v el” or “h ysteresis input level”.

The switching of the input level can be set by the input level selection register (ILSR).

*2 : Single-clock products only

*3 : The power-supply current is determined by the external clock.

•Refer to “4. AC characteristics (1) Clock Timing” for FCH and FCL.

•Refer to “4. AC characteristics (2) Source Clock/Machine Clock” for fmp and fmpl.

Parameter Sym-

bol Pin name Conditions Value Unit Remarks

Min Typ Max

Power supply

current*3

ICCT

VCC

(external

clock

operation)

FCL = 32 kHz

Watch mode

Main stop mode

TA = + 25 °C

⎯210 µA FLASH product

⎯15 µA MASK product

ICCMPLL

FCH = 4 MHz

fmp = 10 MHz

Main PLL mode

(multiplied by 2.5)

⎯10 14 mA FLASH product

⎯6.7 10 mA MASK product

ICCSPLL

FCL = 32 kHz

fmpl = 128 kHz

Sub PLL mode

(multiplied by 4) ,

TA = + 25 °C

⎯190 250 µA

ICTS FCH = 10 MHz

Timebase timer mode

TA = + 25 °C⎯0.4 0.5 mA

ICCH Substop mode

TA = + 25 °C⎯15µA

AVcc

FCH = 10 MHz

At A/D converting ⎯1.3 2.2 mA

IAH FCH = 10 MHz

At A/D converting stop

TA = + 25 °C⎯15µA

Input

capacitance CIN Other than

AVcc, AVss,

Vcc, and Vss ⎯⎯515pF

MB95110A Series

4. AC Characteristics

(1) Clock Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)

Parameter Sym-

bol Pin Condi-

tions Value Unit Remarks

Min Typ Max

Clock frequency

FCH X0, X1

⎯

1⎯10 MHz When using Main oscilla-

tion circuit

1⎯20 MHz When using external clock

3⎯10 MHz Main PLL multiplied by 1

3⎯5 MHz Main PLL multiplied by 2

3⎯4 MHz Main PLL multiplied by 2.5

FCL X0A,

X1A

⎯32.768 ⎯kHz When using Sub oscilla-

tion circuit

⎯32.768 ⎯kHz

When using sub PLL

FLASH product :

Vcc = 2.3 V to 3.3 V

MASK product :

Vcc = 2.3 V to 3.6 V

Clock cycle time tHCYL X0, X1 100 ⎯1000 ns When using Main oscilla-

tion circuit

50 ⎯1000 ns When using Sub oscilla-

tion circuit

tLCYL X0A,

X1A ⎯30.5 ⎯µs Subclock

Input clock pulse width

tWH1

tWL1 X0 10 ⎯⎯ns When using external clock

Duty ratio is about 30% to

70%.

tWH2

tWL2 X0A ⎯15.2 ⎯µs

Input clock rise time and

fall time tCR

tCF X0,

X0A ⎯⎯ 5 ns When using external clock

MB95110A Series

tHCYL

tWH1

tCR

0.2 VCC

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tCF

tWL1

X0 X1

FCH

• X0 and X1 Timing and Applying Conditions

• Main Clock Applying Conditions

When using a crystal or

ceramic oscillator When using external clock

Open

tLCYL

tWH2

tCR

0.1 VCC

0.8 VCC 0.8 VCC

0.1 VCC 0.1 VCC

tCF

tWL2

X0A X1A

FCL

X0A

FCL

X1A

• X0A and X1A Timing and Applying Conditions

• Subclock Applying Conditions

When using a crystal or

ceramic oscillator When using external clock

Open

MB95110A Series

(2) Source Clock/Machine Clock (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)

*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This

source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes

the machine clock. Further, the source clock can be selected as follow.

•Main clock divided by 2

•PLL multiplication of main clock (select from 1, 2, 2.5 multiplication)

•Subclock divided by 2

•PLL multiplication of subclock (select from 2, 3, 4 multiplication)

*2 : Operation clock of the microcontroller. Machine clock can be selected as follow.

•Source clock (no division)

•Source clock divided by 4

•Source clock divided by 8

•Source clock divided by 16

Parameter Sym-

bol Pin

name Value Unit Remarks

Min Typ Max

Source clock*1

(Clock before setting

division) SCLK ⎯

100 ⎯2000 ns When using Main clock

Min : FCH = 10 MHz, PLL multiplied by 1

Max : FCH = 1 MHz, divided by 2

7.6 ⎯61.0 µsWhen using Subclock

Min : FCL = 32 kHz, PLL multiplied by 4

Max : FCL = 32 kHz, divided by 2

Source clock frequency fsp ⎯0.5 ⎯10.0 MHz When using Main clock

fspl ⎯16.384 ⎯131.072 kHz When using Subclock

Machine clock*2

(Minimum instruction

execution time) MCLK ⎯

100 ⎯32000 ns When using Main clock

Min : SLCK = 10 MHz, no division

Max : SLCK = 0.5 MHz, divided by 16

7.6 ⎯976.5 µsWhen using Subclock

Min : SLCK = 131 kHz, no division

Max : SLCK = 16 kHz, divided by 16

Machine clock

frequency fmp ⎯0.031 ⎯10.000 MHz When using Main clock

fmpl 1.024 ⎯131.072 kHz When using Subclock

MB95110A Series

• MASK product

• FLASH product

Note: In operating by 2.0 V or less, only “TA = -10 °C to +85 °C” is guaranteed.

10 MHz0.5 MHz

1.0

3.6

2.2

1.8

5 MHz3 MHz

2.0

Sub PLL operation guarantee range

(2.3 V to 3.6 V) A/D converter accuracy

guarantee range

Operating voltage (V)

Source clock frequency (fsp)

Main PLL operation guarantee range

10 MHz0.5 MHz

1.0

3.3

2.2

1.8

5 MHz3 MHz

2.0

Sub PLL operation guarantee range

(2.3 V to 3.3 V)

A/D converter accuracy

guarantee range

Operating voltage (V)

Source clock frequency (fsp)

Main PLL operation guarantee range

• Operating voltage − Operating frequency

MB95110A Series

10 MH

4 MHz3 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz

3 MHz

4 MHz

5 MHz

6 MHz

7 MHz

8 MHz

9 MHz

10 MHz

.5 MHz

• Main PLL operation frequency

Main clock frequency

Source clock frequency (fsp)

× 2.5

× 2

× 1

MB95110A Series

(3) Reset Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)

*1 : Refer to “ (2) Source Clock/Machine Clock” for MCLK.

*2 : Oscillation time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator , the oscillation

time is between several ms and tens of ms. In F AR/ceramic oscillators, the oscillation time is between hundreds

of µs and several ms. In the external clock, the oscillation time is 0 ms.

Parameter Symbol Value Unit Remarks

Min Max

RST “L” level pulse

width tRSTL

2 MCLK*1⎯ns At normal operating

Oscillation time of oscillator*2

+ 2 MCLK*1⎯ns At stop mode, subclock mode,

Sub sleep mode, and watch mode

tRSTL

0.2 VCC

RST

0.2 VCC

tRSTL

0.2 VCC 0.2 VCC

2 MCLK

RST

Oscillation stabilization wait time

Execute instruction

Oscillation time

of oscillator

90% of

amplitude

Internal

operating

clock

nternal reset

• At normal operating

• At stop mode, subclock mode, sub sleep mode, and watch mode

MB95110A Series

(4) Power-on Reset (AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)

Note : The power supply must be turned on within the selected oscillation stabilization time.

Parameter Symbol Conditions Value Unit Remarks

Min Max

Power supply rising time tR⎯⎯36 ms

Power supply cutoff time tOFF ⎯1⎯ms Due to repeated

operations

0.2 V0.2 V

OFF

1.5 V

0.2 V

.5 V

Sudden change of power supply voltage may activate the power-on reset function.

When changing power supply voltages during operation, set the slope of rising within

20 mV/ms as shown below. In this case, do not use PLL clock. However, if voltage

drop is 1V/s or less, use of PLL clock is allowed during operation.

Limiting the slope of rising within

20 mV/ms is recommended.

RAM data hold period

MB95110A Series

(5) Peripheral Input Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)

* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.

Parameter Symbol Pin name Value Unit Remarks

Min Max

Peripheral input “H” pulse

width tILIH INT00 to INT07, EC0,

EC1, TRG0/ADTG

2 MCLK* ⎯ns

Peripheral input “L” pulse

width tIHIL 2 MCLK* ⎯ns

tILIH

NT00 to INT07,

C0, EC1,

RG0/ADTG

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

tIHIL

MB95110A Series

(6) UART/SIO, Serial I/O Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)

* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.

Parameter Symbol Pin name Conditions Value Unit Remarks

Min Max

Serial clock cycle time tSCYC UCK0 Internal

clock

operation

4 MCLK* ⎯ns

UCK ↓ → UO time tSLOV UCK0, UO0 − 190 190 ns

Valid UI → UCK ↑tIVSH UCK0, UI0 2 MCLK* ⎯ns

UCK ↑ → valid UI hold time tSHIX UCK0, UI0 2 MCLK* ⎯ns

Serial clock “H” pulse width tSHSL UCK0

External

clock

operation

4 MCLK* ⎯ns

Serial clock “L” pulse width tSLSH UCK0 4 MCLK* ⎯ns

UCK ↓ → UO time tSLOV UCK0, UO0 ⎯190 ns

Valid UI → UCK ↑tIVSH UCK0, UI0 2 MCLK* ⎯ns

UCK ↑ → valid UI hold time tSHIX UCK0, UI0 2 MCLK* ⎯ns

tSCYC

tIVSH

VIH

VIL VIH

VIL

tSHIX

tSLOV

0.8 V 2.4 V 0.8 V

2.4 V

CK0

0.8 V

tSLSH

tIVSH

VIH

VIL VIH

VIL

tSHIX

tSLOV

0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC

tSHSL

2.4 V

CK0

0.8 V

• Internal shift clock mode

• External shift clock mode

MB95110A Series

(7) LIN-UART Timing

ESCR : SCES = 0, ECCR : SCDE = 0 (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)

* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.

Parameter Sym-

bol Pin name Conditions Value Unit

Min Max

Serial clock cycle time tSCYC SCK

Internal clock

operation output pin :

CL = 80 pF + 1 TTL.

5 MCLK* ⎯ns

SCK ↑ → SOT delay time tSLOVI SCK, SOT −95 95 ns

Valid SIN → SCK ↑tIVSHI SCK, SIN MCLK* +

190 ⎯ns

SCK ↑→ valid SIN hold time tSHIXI SCK, SIN 0 ⎯ns

Serial clock “L” pulse width tSLSH SCK

External clock

operation output pin :

CL = 80 pF + 1 TTL.

3 MCLK* −

tR⎯ns

Serial clock “H” pulse width tSHSL SCK MCLK* + 95 ⎯ns

SCK ↓ → SOT delay time tSLOVE SCK, SOT ⎯2 MCLK* +

95 ns

Valid SIN → SCK↑tIVSHE SCK, SIN 190 ⎯ns

SCK ↑ → Valid SIN hold time t SHIXE SCK, SIN MCLK* + 95 ⎯ns

SCK fall time tFSCK ⎯10 ns

SCK rise time tRSCK ⎯10 ns

MB95110A Series

0.8 V

2.4 V

SLOVI

IVSHI

SHIXI

2.4 V

0.8 V

SCYC

SLOVE

IVSHE

SHIXE

2.4 V

0.8 V

SLSH

SHSL

• Internal shift clock mode

• External shift clock mode

MB95110A Series

ESCR : SCES = 1, ECCR : SCDE = 0 (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)

* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.

Parameter Sym-

bol Pin name Conditions Value Unit

Min Max

Serial clock cycle time tSCYC SCK

Internal clock

operation output pin :

CL = 80 pF + 1 TTL.

5 MCLK* ⎯ns

SCK ↑ → SOT delay time tSHOVI SCK, SOT −95 95 ns

Valid SIN → SCK ↓tIVSLI SCK, SIN MCLK* +

190 ⎯ns

SCK ↓ → Valid SIN hold time tSLIXI SCK, SIN 0 ⎯ns

Serial clock “H” pulse width tSHSL SCK

External clock

operation output pin :

CL = 80 pF + 1 TTL.

3 MCLK* −

tR⎯ns

Serial clock “L” pulse width tSLSH SCK MCLK* +

95 ⎯ns

SCK ↑ → SOT delay time tSHOVE SCK, SOT ⎯2 MCLK* +

95 ns

Valid SIN → SCK ↓tIVSLE SCK, SIN 190 ⎯ns

SCK ↓ → Valid SIN hold time tSLIXE SCK, SIN MCLK* +

95 ⎯ns

SCK fall time tFSCK ⎯10 ns

SCK rise time tRSCK ⎯10 ns

MB95110A Series

0.8 V

2.4 V

SHOVI

IVSLI

SLIXI

2.4 V

0.8 V

SCYC

SHOVE

IVSLE

SLIXE

2.4 V

0.8 V

SHSL

SLSH

• Internal shift clock mode

• External shift clock mode

MB95110A Series

ESCR : SCES = 0, ECCR : SCDE = 1 (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)

* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.

Parameter Sym-

bol Pin

name Conditions Value Unit

Min Max

Serial clock cycle time tSCYC SCK

Internal clock

operation output pin :

CL = 80 pF + 1 TTL.

5 MCLK* ⎯ns

SCK ↑ → SOT delay time tSHOVI SCK,

SOT −95 95 ns

Valid SIN→SCK↓tIVSLI SCK,

SIN MCLK* +

190 ⎯ns

SCK ↓ → valid SIN hold time tSLIXI SCK,

SIN 0⎯ns

SOT → SCK ↓ delay time tSOVLI SCK,

SOT ⎯4 MCLK* ns

SCK

SOT

SIN

2.4 V

0.8 V

SHOVI

2.4 V

0.8 V

VIH

VIL

2.4 V

0.8 V

SCYC

SOVLI

tIVSLI tSLIXI

MB95110A Series

ESCR : SCES = 1, ECCR : SCDE = 1 (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)

* : Refer to “ (2) Source Clock/Machine Clock” for MCLK.

Parameter Sym-

bol Pin name Conditions Value Unit

Min Max

Serial clock cycle time tSCYC SCK

Internal clock

operation output pin :

CL = 80 pF + 1 TTL.

5 MCLK* ⎯ns

SCK ↓ → SOT delay time tSLOVI SCK, SOT −95 95 ns

Valid SIN → SCK ↑tIVSHI SCK, SIN MCLK* +

190 ⎯ns

SCK ↑ →valid SIN hold time tSHIXI SCK, SIN 0 ⎯ns

SOT → SCK ↑ delay time tSOVHI SCK, SOT ⎯4 MCLK* ns

SCK

SOT

SIN

2.4 V 2.4 V

0.8 V t

SLOVI

2.4 V

0.8 V

2.4 V

0.8 V

SCYC

SOVHI

IVSHI

SHIXI

MB95110A Series

(8) I2C Timing (Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 85 °C)

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.

*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement

tSU;DAT ≥ 250 ns must then be met.

Parameter Symbol Conditions

Value

Unit Remarks

Standard-

mode Fast-mode

Min Max Min Max

SCL clock frequency fSCL

R = 1.7 kΩ,

C = 50 pF*1

01000400kHz

(Repeat) Start condition hold time

SDA ↓ → SCL ↓ tHD;STA 4.0 ⎯0.6 ⎯µs

SCL clock “L” width tLOW 4.7 ⎯1.3 ⎯µs

SCL clock “H” width tHIGH 4.0 ⎯0.6 ⎯µs

(Repeat) Start condition setup time

SCL ↑ → SDA ↓tSU;STA 4.7 ⎯0.6 ⎯µs

Data hold time SCL ↓ → SDA ↓ ↑tHD;DAT 0 3.45*200.9*

3µs

Data setup time SDA ↓ ↑ → SCL ↑tSU;DAT 0.25 ⎯0.1 ⎯µs

Stop condition setup time SCL ↑ →

SDA ↑tSU;STO 4⎯0.6 ⎯µs

Bus free time between stop

condition and start condition tBUF 4.7 ⎯1.3 ⎯µs

DA0

CL0

tWAKEUP

tHD;STA tHD;DAT

tHD;STA

tSU;STA

tLOW tSU;DAT tHIGH

tSU;STO

tBUF

MB95110A Series

(Vcc = 3.3 V, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)

(Continued)

Parameter Sym-

bol I/O Timing Unit Remarks

Min Max

SCL clock “L” width tLOW (2 + nm*2 / 2)

MCLK*1 − 20 ⎯ns Master mode

SCL clock “H” width tHIGH (nm*2 / 2)

MCLK*1 − 20 (nm*2 / 2 )

MCLK*1 + 20 ns Master mode

Start condition hold time tHD;STA (−1 + nm*2 / 2)

MCLK*1 − 20 (−1 + nm*2)

MCLK*1 + 20 ns

Master mode

Maximum value is applied when

m, n = 1, 8.

Otherwise, the minimum

value is applied.

Stop condition setup time tSU;STO (1 + nm*2 / 2)

MCLK*1 − 20 (1 + nm*2 / 2)

MCLK*1 + 20 ns Master mode

Start condition setup time tSU;STA (1 + nm*2 / 2)

MCLK*1 − 20 (1 + nm*2 / 2)

MCLK*1 + 20 ns Master mode

Bus free time between stop

condition and start condition tBUF (2 nm*2 + 4)

MCLK*1 − 20 ⎯ns

Data hold time tHD;DAT 3 MCLK*1 − 20 ⎯ns Master mode

Data setup time tSU;DAT (−2 + nm*2 / 2)

MCLK*1 − 20 (−1 + nm*2 / 2)

MCLK*1 + 20 ns

Master mode

When assuming that “L” of SCL

is not extended,

the minimum value is applied to

first bit of continuous data. Oth-

erwise, the maximum

value is applied.

Setup time between clearing

interrupt and SCL rising tSU;INT (nm*2 / 2)

MCLK*1 − 20 (1 + nm*2 / 2)

MCLK*1 + 20 ns

Minimum value is applied to in-

terrupt at 9th SCL↓. Maximum

value is applied to interrupt at

8th SCL↓.

SCL clock “L” width tLOW 4 MCLK*1 − 20 ⎯ns At reception

SCL clock “H” width tHIGH 4 MCLK*1 − 20 ⎯ns At reception

Start condition detection tHD;STA 2 MCLK*1 − 20 ⎯ns Undetected when 1 MCLK is

used at reception

Stop condition detection tSU;STO 2 MCLK*1 − 20 ⎯ns Undetected when 1 MCLK is

used at reception

Restart condition detection

condition tSU;STA 2 MCLK*1 − 20 ⎯ns Undetected when 1 MCLK is

used at reception

Bus free time tBUF 2 MCLK*1 − 20 ⎯ns At reception

Data hold time tHD;DAT 2 MCLK*1 − 20 ⎯ns At slave transmission mode

Data setup time tSU;DAT tLOW − 3 MCLK*1 −

20 ⎯ns At slave transmission mode

Data hold time tHD;DAT 0⎯ns At reception

Data setup time tSU;DAT MCLK*1 − 20 ⎯ns At reception

MB95110A Series

(Continued)

*1 : Refer to “ (2) Source Clock/Machine Clock” for MCLK.

*2 : •m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) .

•n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) .

•Actual timing of I2C is determined by m and n values set by the machine clock (MCLK) and ICCR [4 : 0].

•Standard-mode :

m and n can be set at the range : 0.9 MHz < MCLK (machine clock) < 10 MHz.

Setting of m and n determines the machine clock that can be used below.

(m, n) = (1, 8) : 0.9 MHz < MCLK ≤ 1 MHz

(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < MCLK ≤ 2 MHz

(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < MCLK ≤ 4 MHz

(m, n) = (1, 98) : 0.9 MHz < MCLK ≤ 10 MHz

•Fast-mode :

m and n can be set at the range : 3.3 MHz < MCLK (machine clock) < 10 MHz.

Setting of m and n determines the machine clock that can be used below.

(m, n) = (1, 8) : 3.3 MHz < MCLK ≤ 4 MHz

(m, n) = (1, 22) , (5, 4) : 3.3 MHz < MCLK ≤ 8 MHz

(m, n) = (6, 4) : 3.3 MHz < MCLK ≤ 10 MHz

Parameter Sym-

bol I/O Timing Unit Remarks

Min Max

SDA↓→SCL↑

(at wakeup function ) tWAKE-

Oscillation stabi-

lization wait time

+ 2 MCLK*1 − 20 ⎯ns

MB95110A Series

5. A/D Converter

(1) A/D Converter Electrical Characteristics

(AVcc = Vcc = 1.8 V to 3.3 V [FLASH product], AVcc = Vcc = 1.8 V to 3.6 V [MASK product], AVss = Vss = 0.0 V,

TA = − 40 °C to + 85 °C)

Parameter Symbol Value Unit Remarks

Min Typ Max

Resolution

⎯

⎯⎯10 bit

Total error − 3.0 ⎯ + 3.0 LSB

Linearity error − 2.5 ⎯ + 2.5 LSB

Differential linear error − 1.9 ⎯ + 1.9 LSB

Zero transition voltage VOT

AVss − 1.5

LSB AVss + 0.5

LSB AVss + 2.5

LSB V

FLASH product :

2.7 V ≤ AVcc ≤ 3.3 V

MASK product :

2.7 V ≤ AVcc ≤ 3.6 V

AVss − 0.5

LSB AVss + 1.5

LSB AVss + 3.5

LSB V 1.8 V ≤ AVcc < 2.7 V

Full-scale transition

voltage VFST

AVcc − 3.5

LSB AVcc − 1.5

LSB AVcc + 0.5

LSB V

FLASH product :

2.7 V ≤ AVcc ≤ 3.3 V

MASK product :

2.7 V ≤ AVcc ≤ 3.6 V

AVcc − 2.5

LSB AVcc − 0.5

LSB AVcc + 1.5

LSB V 1.8 V ≤ AVcc < 2.7 V

Compare time ⎯0.6 ⎯16,500 µs

FLASH product :

2.7 V ≤ AVcc ≤ 3.3 V

MASK product :

2.7 V ≤ AVcc ≤ 3.6 V

20 ⎯16,500 µs 1.8 V ≤ AVcc < 2.7 V

Sampling time ⎯

0.4 ⎯∞µs

FLASH product :

2.7 V ≤ AVcc ≤ 3.3 V

MASK product :

2.7 V ≤ AVcc ≤ 3.6 V

external impedance <

at 1.8 kΩ

30 ⎯∞µs1.8 V ≤ AVcc < 2.7 V

external impedance <

at 14.8 kΩ

Analog input current IAIN −0.3 ⎯0.3 µA

Analog input voltage

range VAIN AVss ⎯AVcc V

Reference voltage ⎯AVss + 1.8 ⎯AVcc V AVcc pin

Reference voltage

supply current

IR⎯400 600 µAAVcc pin,

During A/D operation

IRH ⎯⎯ 5µAAVcc pin,

at stop mode

MB95110A Series

(2) Notes on Using A/D Converter

• About the external impedance of analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the inter nal sanple and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

• To satisfy the A/D conversion precision standard, consider the relationship between the exter nal impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• About errors

As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.

During sampling : ON

Analog input pin Comparator

Note : The values are reference values.

• Analog input circuit model

2.7 V ≤ AVcc ≤ 3.6 V 1.7 kΩ (Max) 14.5 pF (Max)

1.8 V ≤ AVcc < 2.7 V 84 kΩ (Max) 25.2 pF (Max)

0 5 10 15 20 25 30 35 4

0123

(External impedance = 0 kΩ to 100 kΩ) (External impedance = 0 kΩ to 20 kΩ)

Minimum sampling time [µs]

External impedance [kΩ]

Minimum sampling time [µs]

External impedance [kΩ]

• The relationship between external impedance and minimum sampling time

AVcc ≥ 2.7 V

AVcc ≥ 1.8 V

AVcc ≥ 2.7 V

MB95110A Series

(3) Definition of A/D Converter Terms

• Resolution

The level of analog variation that can be distinguished by the A/D converter.

When the number of bits is 10, analog voltage can be divided into 210 = 1024.

• Linearity error (unit : LSB)

The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000” ←

→ “00 0000 0001”) of a device and the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”)

compared with the actual conversion values obtained.

• Differential linear error (Unit : LSB)

Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.

• Total error (unit: LSB)

Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,

linearity error, quantum error, and noise.

(Continued)

VFST

1.5 LSB

FFH

FEH

FDH

004H

003H

002H

001H

1 LSB

0.5 LSB

VOT

AVSS AVC

FFH

FEH

FDH

004H

003H

002H

001H

AVSS

VNT

AVC

{1 LSB × (N − 1) + 0.5 LSB}

1 LSB =AVCC − AVSS

1024

[LSB]

Total error of digital output N =VNT − {1 LSB × (N − 1) + 0.5 LSB}

1 LSB

Ideal I/O characteristics Total error

Digital output

Analog input Analog input

VNT : A voltage at which digital output transits from (N − 1) to N.

(V)

Actual conversion

characteristic

Actual conversion

characteristic

Ideal characteristics

MB95110A Series

(Continued)

AVSS AVC

01H

02H

03H

04H

AVSS AVC

FCH

FDH

FEH

3FFH

AVSS AVC

001H

002H

003H

004H

FDH

FEH

FFH

{1 LSB × N + VOT}

VNT

AVSS AVCC

VNT

− 2

− 1

+ 1

V (N + 1)

Full-scale transition error

Digital output

Analog input

Zero transition error

Digital output

Analog input

Differential linear error

Linearity error

Digital output

Analog input

Linear error in digital output N =VNT − {1 LSB × N + VOT}

1 LSB

VNT : A voltage at which digital output transits from (N − 1) to N.

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVCC − 1.5 LSB [V]

Differential linear error in digital output N =V (N + 1) T − VNT

1 LSB − 1

Actual conversion

characteristic

Actual conversion

characteristic

VOT (measurement value)

Ideal

characteristics

Actual conversion

characteristic

Actual conversion

characteristic

Ideal

characteristics

VFST

(measurement

value)

Actual conversion

characteristic

Actual conversion

characteristic

Ideal characteristics

VFST

(measurement

value)

VOT (measurement value)

Actual conversion

characteristic

Actual conversion

characteristic

Ideal characteristics

MB95110A Series

6. Flash Memory Program/Erase Characteristics

*1 : TA = +25 °C, Vcc = 3.0 V, 10,000 cycles

*2 : TA = +85 °C, Vcc = 2.7 V, 10,000 cycles

*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85 °C) .

Parameter Value Unit Remarks

Min Typ Max

Sector erase time

(4 Kbytes sector) ⎯0.2*13*2s Excludes 00H programming prior erasure

Sector erase time

(16 Kbytes sector) ⎯0.5*112*2s Excludes 00H programming prior erasure

Byte programming time ⎯32 3600 µs Excludes system-level overhead

Erase/program cycle 10,000 ⎯⎯cycle

Power supply voltage at

erase/program 2.7 ⎯3.3 V

Flash data retension time 20*3⎯⎯year Average TA = +85 °C

MB95110A Series

■MASK OPTIONS

■ORDERING INFORMATION

No Part number MB95116A MB95F118AS MB95F118AW MB95FV100A-101

Specifying procedure Specify when

or dering MASK Setting disabled Setting disabled Setting disabled

1Clock mode select

• Single-system clock mode

• Dual-system clock mode Selectable Single-system

clock mode Dual-system

clock mode

Changing by the

switch on MCU

board

Selection of oscillation

stabilization wait time

• Selectable the initial value

of main clock oscillation

stabilization wait time

Selectable

1 : ( 22 − 2) /FCH

2 : ( 212 − 2) /FCH

3 : ( 213 − 2) /FCH

4 : ( 214 − 2) /FCH

Fixed to oscillation

stabilization wait

time of

(214-2) /FCH

Fixed to oscillation

stabilization wait

time of

(214-2) /FCH

Fixed to oscillation

stabilization wait

time of

(214-2) /FCH

Part number Package Remarks

MB95116APV

MB95F118ASPV

MB95F118AWPV

48-pin plastic BCC

(LCC-48P-M09)

MB95116APMT

MB95F118ASPMT

MB95F118AWPMT

48-pin plastic LQFP

(FPT-48P-M26)

MB2146-301

(MB95FV100A-101PBT)

MCU board

244-pin plastic PFBGA

(BGA-244P-M08)

()

MB95110A Series

■PACKAGE DIMENSIONS

(Continued)

48-pin plastic BCC

(LCC-48P-M09)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

2004 FUJITSU LIMITED C48062S-c-1-1

3725

5.00(.197)

REF

6.25(.246)

REF

"C" "B"

"A"

6.25(.246)REF

6.20(.244)

TYP

0.50±0.10

(.020±.004)

0.50(.020)

TYP

5.00(.197)REF

6.20(.244)TYP

0.075±0.025

(.003±.001)

2537

7.00±0.10(.276±.004)

(Stand off)

7.00±0.10

(.276±.004)

0.05(.002)

Details of "C" part

0.55±0.06

(.022±.002)

0.55±0.06

(.022±.002)

INDEX AREA

Details of "A" part

(.026±.002)

0.65±0.06

(.012±.002)

0.30±0.06

C0.2(.008)

Details of "B" part

0.14(.006)

MIN

(Mount height)

(.030±.002)

0.75±0.05

TYP

0.50(.020)

0.50±0.10

(.020±.004)

0.55±0.06

(.022±.002)

0.55±0.06

(.022±.002)

(8-.024±.002)

8-0.60±0.06

6.15(.242)TYP

6.15(.242)

TYP

MB95110A Series

(Continued)

48-pin plastic LQFP

(FPT-48P-M26)

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

2003 FUJITSU LIMITED F48040S-c-2-2

36 25

INDEX

9.00±0.20(.354±.008)SQ

0.145±0.055

(.006±.002)

0.08(.003)

"A" 0˚~8˚

.059 –.004

+.008

–0.10

+0.20

1.50

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

(Stand off)

0.25(.010)

Details of "A" part

112

0.08(.003) M

(.008±.002)

0.20±0.05

0.50(.020)

LEAD No.

(Mounting height)

.276 –.004

+.016

–0.10

+0.40

7.00

MB95110A Series

FUJITSU LIMITED

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F0502