EL7158ISZ-T7A - Intersil - Datasheet.Directory

FN7349.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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EL7158

Ultra-High Current Pin Driver

The EL7158 high performance pin

driver with three-state is suited to

many ATE and level-shifting

applications. The 12A peak drive capability makes this part

an excellent choice when driving high ca pacitance loads.

The output pin OUT is connected to input pins VH or VL

respectively , depending on the status of the IN pin. When the

OE pin is active low, the output is placed in the three-state

mode. The isolation of the output FETs from the power

supplies enables VH and VL to be set independently,

enabling level-sh ifting to be implemented. Related to the

EL7155, the EL7158 adds a lower supply pin VS- and makes

VL an isolated and independent input. This feature adds

applications flexibility and improves switching response due

to the increased enhancement of the output FETs.

This pin driver has improved performance over existing pin

drivers. It is specifically designed to operate at voltages

down to 0V across the switch elements while maintaining

good speed and ON-resistance characteristics.

Available in the 8 Ld SOIC package, the EL7158 is specified

for operation over the full -40°C to +85°C temperature range.

Pinout EL7158

(8 LD SOIC)

TOP VIEW

Features

• Clocking speeds up to 40MHz

• 12ns tR/tF at 2000pF CLOAD

• 0.2ns rise and fall times mismatch

• 0.5ns tON-tOFF prop delay mismatch

• 3.5pF typical input capacitance

• 12A peak drive

• Low ON-resistance of 0.5Ω

• High capacitive drive capability

• Operates from 4.5V to 12V

• Pb-free plus anneal available (RoHS compliant)

Applications

• ATE/burn-in testers

• Level shifting

•IGBT drivers

• CCD drivers

VS+

GND

OUT

VS-

Ordering Information

PART

NUMBER PART

MARKING PACKAGE TAPE &

REEL PKG.

DWG. #

EL7158IS 7158IS 8 Ld SOIC - MDP0027

EL7158IS-T7 7158IS 8 Ld SOIC 7” MDP0027

EL7158IS-T13 7158IS 8 Ld SOIC 13” MDP0027

EL7158ISZ

(Note) 7158ISZ 8 Ld SOIC

(Pb-free) - MDP0027

EL7158ISZ-T7

(Note) 7158ISZ 8 Ld SOIC

(Pb-free) 7” MDP0027

EL7158ISZ-T13

(Note) 7158ISZ 8 Ld SOIC

(Pb-free) 13” MDP0027

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which is compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J Std-020B.

Data Sheet May 14, 2007

2FN7349.2

May 14, 2007

Absolute Maximum Ratings (TA = +25°C) Thermal Information

Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .VS- -0.3V, VS +0.3V

Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests

are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Electrical Specifications VS+ = +12V, VH = +12V, VL = 0V, VS- = 0V, TA = +25°C, unless otherwise specified.

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

VIH Logic ‘1’ Input Voltage 2.4 V

IIH Logic ‘1’ Input Current VIH = VS+0.110µA

VIL Logic ‘0’ Input Voltage 0.8 V

IIL Logic ‘0’ Input Current VIL = 0V 0.1 10 µA

CIN Input Capacitance 3.5 pF

RIN Input Resistance 50 MΩ

OUTPUT

ROVH ON-Resistance VH to OUT IOUT = -500mA 0.5 1 Ω

ROVL ON-Resistance VL to OUT IOUT = +500mA 0.5 1 Ω

IOUT Output Leakage Current OE = 0V, OUT = V H/VL0.1 10 µA

IPK Peak Output Current

(linear resistive operation) Source 12 A

Sink 12 A

IDC Continuous Output Current Source/Sink 500 mA

POWER SUPPLY

ISPower Supply Current Inputs = VS+1.33mA

IVH Off Leakage at VH and VLVH, VL = 0V 4 10 µA

SWITCHING CHARACTERISTICS

tRRise Time CL = 2000pF 12.0 ns

tFFall Time CL = 2000pF 12.2 ns

tRFΔtR, tF Mismatch CL = 2000pF 0.2 ns

td-1 Turn-Off Delay Time CL = 2000pF 22.5 ns

td-2 Turn-On Delay Time CL = 2000pF 22.0 ns

tdΔtd-1-td-2 Mismatch CL = 2000pF 0.5 ns

td-3 Three-State Delay Enable 22 ns

td-4 Three-State Delay Disable 22 ns

SR+ VOUT+ Slew Rate RLOAD = 6Ω800 V/µs

SR- VOUT- Slew Rate RLOAD = 6Ω800 V/µs

EL7158

3FN7349.2

May 14, 2007

Electri ca l Specific at io ns VS+ = +12V, VH = +1.2V, VL = 0V, VS- = 0V, TA = +25°C, unless otherwise specified. (Continued)

PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT

INPUT

VIH Logic ‘1’ Input Voltage 2.0 V

IIH Logic ‘1’ Input Current VIH = VS+0.110µA

VIL Logic ‘0’ Input Voltage 0.8 V

IIL Logic ‘0’ Input Current VIL = 0V 0.1 10 µA

CIN Input Capacitance 3.5 pF

RIN Input Resistance 50 MΩ

OUTPUT

ROVH ON-Resistance VH to OUT IOUT = -500mA 0.5 1 Ω

ROVL ON-Resistance VL to OUT IOUT = +500mA 0.5 1 Ω

IOUT Output Leakage Current OE = 0V, OUT = VH/VL0.1 10 µA

IPK Peak Output Current

(linear resistive operation) Source 1.2 A

Sink 1.2 A

IDC Continuous Output Current Source/Sink 500 mA

POWER SUPPLY

ISPower Supply Current Inputs = VS+12.5mA

VH Off Leakage at VH and VLVH, VL = 0V 4 10 µA

SWITCHING CHARACTERISTICS

tRRise Time CL = 2000pF 11 ns

tFFall Time CL = 2000pF 11 ns

tRFΔtR, tF Mismatch CL = 2000pF 0 ns

td-1 Turn-Off Delay Time CL = 2000pF 20.5 ns

td-2 Turn-On Delay Time CL = 2000pF 20.0 ns

tdΔtd-1-td-2 Mismatch CL = 2000pF 0.5 ns

td-3 Three-State Delay Enable 20 ns

td-4 Three-State Delay Disable 20 ns

SR+ VOUT+ Slew Rate RLOAD = 6Ω80 V/µs

SR- VOUT- Slew Rate RLOAD = 6Ω80 V/µs

EL7158

4FN7349.2

May 14, 2007

Typical Performance Curves

FIGURE 1. INPUT THRESHOLD vs SUPPLY VOLTAGE FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

FIGURE 3. “ON”-RESISTANCE vs SUPPLY VOLTAGE (VS+) FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE

FIGURE 5. RISE/FALL TIME vs TEMPERATURE FIGURE 6. PROPAGATION DELAY vs SUPPLY VOLTAGE

T = +25°C

1.2

INPUT VOLTAGE ( V)

SUPPLY VOLTAGE (V)

1.0

1.8

1.6

1.4

12510

HIGH THRESHOLD

HYSTERESIS

LOW THRESHOLD

T = +25°C

SUPPLY CURRENT (mA)

SUPPLY VOLTAGE (V)

2.0

1.6

1.2

0.8

0.4

ALL INPUTS = VS+

ALL INPUTS = GND

IOUT = 500mA, T = +25°C, VS+ = VH, VS- = VL = 0V

“ON” RESISTANCE (Ω)

SUPPLY VOLTAGE (V)

7.5 12.5510

0.5

0.4

0.6

0.8

0.7

VOUT TO VL

VH TO VOUT

CL = 2000pF, T = +25°C, VS+ = VH, VS- = VL = 0V

RISE/FALL TIME (ns)

SUPPLY VOLTAGE (V)

71159

6 8 10 12

CL = 2000pF, VS+ = VH = 12V, VS- = VL = 0V

150

RISE/FALL TIME (ns)

TEMPERATURE (°C)

8100

-50 50

CL = 2000pF, T = +25°C, VS+ = VH = 12V,

VS- = VL = 0V

DELAY TIME (ns)

SUPPLY VOLTAGE (V)

711596 8 10 12

td1

td2

EL7158

5FN7349.2

May 14, 2007

FIGURE 7. PROPAGATION DELAY vs TEMPERATURE FIGURE 8. RISE/FALL TIME vs LOAD CAPACITANCE

FIGURE 9. SUPPLY CURRENT vs LOAD CAPACITANCE FIGURE 10. SUPPLY CURRENT vs FREQUENCY

FIGURE 1 1. PACKAGE POWER DISSIP ATION vs AMBIENT

TEMPERATURE FIGURE 12. P ACKAGE POWER DISSIPA TION vs AMBIENT

TEMPERATURE

Typical Performance Curves (Continued)

CL = 2000pF, VS+ = VH = 12V, VS- = VL = 0V

DELAY TIME (ns)

TEMPERATURE (°C)

0125-50 50

-25 25 75 100

tD1

tD2

VS+ = +12V, T = +25°C

10k

RISE/FALL TIME (ns)

LOAD CAPACITANCE (pF)

100 1k

100 1k 10k

VS+ = VH = 12V, VS- = VL = 0V, T = +25°C, f = 20kHz

SUPPLY CURRENT (mA)

LOAD CAPACITANCE (pF)

1M 10M10k 100k

0.1

1.0

100 CL = 1000pF, T = +25°C

SUPPLY CURRENT (mA)

FREQUENCY (Hz)

VS+=12V

VS+=10V

VS+=5V

625mW

= 160°C/W

SOIC8

1.0

0.9

0.8

0.6

0.4

0.1

00 255075100 150

AMBIENT TEMPERATURE (°C)

POWER DISSIPATION (W)

12585

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.2

0.7

0.3

0.5

909mW

= 110°C/W

SOIC8

1.4

1.2

1.0

0.8

0.6

0.2

00 255075100 150

AMBIENT TEMPERATURE (°C)

POWER DISSIPATION (W)

12585

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.4

EL7158

6FN7349.2

May 14, 2007

TABLE 1. TRUTH TABLE

OE IN OUT

0 0 Three-State

0 1 Three-State

10V

11V

TABLE 2. OPERATING VOLTAGE RANGE

PIN MIN MAX

VS- to GND -5 0

VS+ to VS-5 18

VH to VL012

VS+ to VH012

VS+ to GND 5 12

VL to VS-0 12

Three-State Output VLVH

FIGURE 13. TIMING DIAGRAM

90%

td1 td2

10%

INVERTED

OUTPUT

2.5V

INPUT

EL7158

CVL

VS-

VS+

GND

VS+0.1µF4.7µF

10kΩ

0.1µF 4.7µF

OUT

0.1µF 4.7µF

FIGURE 14. STANDARD TEST CONFIGURATION

2000pF

EL7158

7FN7349.2

May 14, 2007

Pin Descriptions

PIN NAME FUNCTION EQUIVALENT CIRCUIT

1 VS+ Positive Supply Voltage

2 OE Output Enable

Circuit 1

3 IN Input Reference Circuit 1

4 GND Ground

5 VS- Negative Supply Voltage

6 VL Lower Output Voltage

7 OUT Output

Circuit 2

8 VH High Output Voltage

VS+

INPUT

VS-

VOUT

VS-

VS+

VS-

VS+

VS-

THREE-

STATE

CONTROL

LEVEL

SHIFTER

GND

OUT

FIGURE 15. BLOCK DIAGRAM

EL7158

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7349.2

May 14, 2007

Applications Information

Product Descr iption

The EL7158 is a high performan c e 40MHz pin driver. It

contains two analog switches connecting VH and VL to OUT.

Depending on the value of the IN pin, one of the two

switches will be closed and the other switch open. An output

enable (OE) is also supplied which opens both switches

simultaneously.

Due to th e to pol ogy of t he EL7158, both the VH and VL pins

can be connected to any voltage between the VS+ and VS-

pins, but VH must be greater than VL in order to prevent

turning on the body diode at the output stage.

Three-State Operation

When the OE pin is low, the output is three-state (floating).

The output voltage is the parasitic capacitance’s voltage. It

can be any voltage between VH and VL, depending on the

previous state. At three-state, the output voltage can be

pushed to any voltage between VH and VL. The output

voltage can’t be pushed higher than VH or lower than VL

since the body diode at the output stage will turn on.

Supply Voltage Range and Input Compatibility

The EL7158 is designed for operation on supplies from 5V to

18V (4.5V to 18V maximum). Table 2 shows the

specifications for the relationship between the VS+, VS-, VH,

VL, and GND pins.

All input pins are compatible with both 3V and 5V CMOS

signals. With a positive supply (VS+) of 5V, the EL7158 is

also compatible with TTL inputs.

Power Supply Bypassing

When using the EL7158, it is very important to use adequate

power supply bypassing. The high switching currents

developed by the EL7158 necessitate the use of a bypass

capacitor between the supplies (VS+ and VS-) and GND

pins. It is recommended that a 2.2µF tantalum capacitor be

used in parallel with a 0.1µF low-inductance ceramic MLC

capacitor. These should be placed as close to the supply

pins as possible. It is also recommended that the VH and VL

pins have some level of bypassing, especially if the EL7158

is driving highly capacitive loads.

Power Dissipation Calculation

When switching at high speeds, or driving heavy loads, the

EL7158 drive capability is limited by the rise in die

temperature brought about by internal power dissipation. For

reliable operation die temperature must be kept below

TJMAX (+125°C). It is necessary to calculate the power

dissipation for a given application prior to selecting the

package type.

Power dissipation may be calculated:

where:

VS is the total power supply to the EL7158 (from VS+ to

GND)

VOUT is the swing on the ou tp ut (VH - VL)

CL is the load capacitance

CINT is the internal load capacitance (100pF max)

IS is the quiescent supply current (3mA max)

f is frequency

Having obtained the application’s power dissipation, a

maximum package thermal coefficient may be determined,

to maintain the internal die temperatu r e below TJMAX:

where:

TJMAX is the maximum junction temperature (+1 25°C)

TMAX is the maximum operating temperature

PD is the power dissipation calculated above

θJA thermal resistance on junction to ambient

θJA is 160°C/W for the SOIC8 package when using a

standard JEDEC JESD51-3 single-layer test board. If TJMAX

is greater than +125°C when calculated using Equation 2 ,

then one of the following actions must be taken:

Reduce θJA the system by designing more heat-sinking

into the PCB (as compared to the standard JEDEC

JESD51-3)

De-rate the application either by reducing the switching

frequency, the capacitive load, or the maximum operating

(ambient) temperature (TMAX)

PD VS

(IS)CINT

(VS2f)CL

(VOUT2f)××+××+×=

(EQ. 1)

θJA TJMAX TMAX

–

-----------------------------------------

=(EQ. 2)

EL7158

9FN7349.2

May 14, 2007

EL7158

Small Outline Package Family (SO)

GAUGE

PLANE

A1 L

DETAIL X 4° ±4°

SEATING

PLANE

0.010 BMCA

0.004 C

0.010 BMCA

(N/2)

NN (N/2)+1

PIN #1

I.D. MARK

h X 45°

SEE DETAIL “X”

0.010

MDP0027

SMALL OUTLINE PACKAGE FAMILY (SO)

SYMBOL

INCHES

TOLERANCE NOTESSO-8 SO-14

SO16

(0.150”)

SO16 (0.300”)

(SOL-16)

SO20

(SOL-20)

SO24

(SOL-24)

SO28

(SOL-28)

A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -

A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -

A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -

b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -

c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -

D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3

E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -

E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3

e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -

L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -

L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -

h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -

N 8 14 16 16 20 24 28 Reference -

Rev. M 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994