DP83846A
DP83846A DsPHYTER - Single 10/100 Ethernet Transceiver
Literature Number: SNLS063E
DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver
©2002 National Semiconductor Corporationwww.national.com
May 2002
DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver
General Description
The DP83846A is a full feature single Physical Layer
device with integrated PMD sublayers to support both
10BASE-T and 100BASE-TX Ethernet protocols over Cat-
egory 3 (10 Mb/s) or Category 5 Unsheilded twisted pair
cables.
The DP83846A is designed for easy implementation of
10/100 Mb/s Ethernet home or offic e s olutions. It interfaces
to Twisted Pair media via an external transformer. This
device interfaces directly to MAC devices through the IEEE
802.3u standard Media Independent Interface (MII) ensur-
ing interoperability between products from different ven-
dors.
The DP83846A utilizes on chip Digital Signal Processing
(DSP) technology and digital Phase Lock Loops (PLLs) for
robust performance under all operating conditions,
enhanced noise immunity, and lower external component
count when compared to analog solutions.
System Diagram
Status
10BASE-T
or
100BASE-TX
MII
25 MHz
Typical DsPHYTER application
Ethernet MAC
Magnetics
RJ-45
Clock LEDs
DP83846A
10/100 Mb/s
DsPHYTER
Features
■IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
■IEEE 802.3u PCS, 100BASE-TX transceivers and filters
■IEEE 802.3 compliant Auto-Negotiation
■Output edge rate control eliminates external filtering for
Transmit outputs
■BaseLine Wander compensation
■5V/3.3V MAC interface
■IEEE 802.3u MII (16 pins/port)
■LED support (Link, Rx, Tx, Duplex, Speed, Collision)
■Single register access for complete PHY status
■10/100 Mb/s packet loopback BIST (Built in Self Test)
■Low-power 3.3V, 0.35um CMOS technology
■Power consumption < 495mW (typical)
■5V tolerant I/Os
■80-pin LQFP package (12w) x (12l) x (1.4h) mm
Applications
■Network Interface Cards
■PCMCIA Cards
Obsolete
2 www.national.com
DP83846A
Figure 1. Block Diagram of the 10/100 DSP based core.
SERIAL
MANAGEMENT
MII
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDIO
MDC
COL
CRS
RX_ER
RX_DV
RXD[3:0]
RX_CLK
TRANSMIT CHANNELS &
100 Mb/s 10 Mb/s
NRZ TO
MANCHESTER
ENCODER
STATE MACHINES
TRANSMIT
FILTER
LINK PULSE
GENERATOR
4B/5B
ENCODER
PARALLEL TO
SCRAMBLER
NRZ TO NRZI
ENCODER
BINARY TO
MLT-3
ENCODER
10/100 COMMON
RECEIVE CHANNELS &
100 Mb/s 10 Mb/s
MANCHESTER
TO NRZ
DECODER
S TATE MACHINES
RECEIVE
FILTER
LINK PULSE
DETECTOR
4B/5B
DECODER
DESCRAMBLER
SERIAL TO
PARALLEL
NRZI TO NRZ
DECODER
MLT-3 TO
10/100 COMMON
AUTO-NEGOTIATION
STATE MACHINE
REGISTERS
AUTO
100BASE-TX
10BASE-T
MII
BASIC MODE
PCS CONTROL
PHY ADDRESS
NEGOTIATION
CLOCK
CLOCK
RECOVERY
CLOCK
RECOVERY
CODE GROUP
ALIGNMENT
SMART
SQUELCH
RX_DATA
RX_CLK
RX_DATARX_CLK
TX_DATA TX_DATA TX_CLK
SYSTEM CLOCK
REFERENCE
OUTPUT DRIVER
TD±
INPUT BUFFER
BINARY
DECODER
ADAPTIVE
RD±
LED
DRIVERS
LEDS
HARDWARE
CONFIGURATION
PINS
GENERATION
(AN_EN, AN0, AN1)
CONTROL
MII INTERFACE/CONTROL
(PAUSE_EN)
(LED_CFG, PHYAD)
SERIAL
BLW
AND EQ
COMP
Obsolete
3 www.national.com
DP83846A
Table of Contents
1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1 MII In terface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . .6
1.3 Clo ck Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.4 Spe c i a l Co nnec ti o n s . . . . . . . . . . . . . . . . . . . . . . .6
1.5 LED In terfa ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.6 Stra pping O p ti o n s/Dua l Pu rp o se Pi ns . . . . . . . . . . 7
1.7 Res e t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.8 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . .9
1.9 Package Pin Assignments . . . . . . . . . . . . . . . . . .10
2.0 C onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 PHY Address and LEDs . . . . . . . . . . . . . . . . . . .12
2.3 LED INTERFACES . . . . . . . . . . . . . . . . . . . . . . .13
2.4 Hal f Du p l e x vs. F u ll D u p l e x . . . . . . . . . . . . . . . . .13
2.5 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . .14
2.6 Loopb ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.7 BIS T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . .15
3.1 802.3u MI I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2 100B AS E-T X TRANSMI T TER . . . . . . . . . . . . . . .16
3.3 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . .20
3.4 10BASE-T TR ANSCEIVER MODU L E . . . . . . . . . 23
3.5 TPI N e tw o rk Circuit . . . . . . . . . . . . . . . . . . . . . . . 2 4
3.6 ESD Pr otect i o n . . . . . . . . . . . . . . . . . . . . . . . . . .2 5
3.7 Crystal Oscillator Cir cuit . . . . . . . . . . . . . . . . . . .26
4.0 R e s et Op e r a t i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Hardwa re Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Softwar e R e se t . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.0 R e gist e r B lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . .29
5.2 Ext ended Registers . . . . . . . . . . . . . . . . . . . . . . .37
6.0 Electric a l Spec i f i c a t ions . . . . . . . . . . . . . . . . . . . . . . . 4 4
6.1 Res e t Timi n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2 PGM Clock Timing . . . . . . . . . . . . . . . . . . . . . . .47
6.3 MII Serial Manageme nt Timing . . . . . . . . . . . . . .47
6.4 100 Mb /s Timing . . . . . . . . . . . . . . . . . . . . . . . . .48
6.5 10 Mb / s T iming . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2
6.6 Loopb ack Timi ng . . . . . . . . . . . . . . . . . . . . . . . . .57
6.7 Isol a tion T iming . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.0 Physical Dimen s ions . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Obsolete
4 www.national.com
DP83846A
Connection Diagram
COL
TXD_3
TXD_2
IO_VDD
IO_GND
TXD_1
TXD_0
IO_GND
TX_EN
TX_CLK
TX_ER
CORE_VDD
CORE_GND
RESERVED
RX_ER/PAUSE_EN
RX_CLK
RX_DV
IO_VDD
IO_GND
RXD_0
RESERVED
ANA_GND
RBIAS
ANA_VDD
RESERVED
ANA_GND
ANA_VDD
RESERVED
ANA_GND
RD-
RD+
ANA_VDD
ANA_GND
ANA_VDD
ANA_GND
TD+
TD-
ANA_GND
SUB_GND
RESERVED
DP83846A
DSPHYTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CRS/LED_CFG
RESET
RESERVED
IO_GND
IO_VDD
X2
X1
RESERVED
RESERVED
RESERVED
RESERVED
CORE_VDD
CORE_GND
RESERVED
RESERVED
SUB_GND
RESERVED
RESERVED
SUB_GND
RESERVED
RXD_1
RXD_2
RXD_3
MDC
MDIO
IO_VDD
IO_GND
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
CORE_VDD
CORE_GND
RESERVED
RESERVED
Plastic Quad Flat Pack (LQFP)
Order Number DP83846AVHG
NS Package Number VHG-80A
Obsolete
5 www.national.com
DP83846A
1.0 Pin Descriptions
The DP83846A pins are classified into the following inter-
face categories (each interface is described in the sections
that follow):
— MII Interface
— 10/100 Mb/s PMD Interface
— Clock Interface
— Special Connect Pins
— LED Interface
— Strapping Options/Dual Function pins
—Reset
— Power and Ground pins
Note: Strapping pin option (BOLD) Please see Section 1.6
for strap definitions.
Note: All DP83846A signal pins are I/O cells regardless of
the particular use. Below definitions define the functionality
of the I/O cells for each pin.
1.1 MII Interface
Type: I Inputs
Type: O Outputs
Type: I/O Input/Output
Type OD Open Drain
Type: PD,PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins except PHY-
AD[0:4] have internal pull-ups or pull-
downs. If the default strap value is needed
to be changed then an external 5 kΩ resi stor
should be used. Please see Table 1.6 on
page 7 for details.)
Signal Name Type LQFP Pin # Description
MDC I 37 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be asyn-
chronous to transmit an d receive clock s. The maximum clock rate is
25 MHz with no minimum clock rate.
MDIO I/O, OD 36 MANAGEMENT DATA I/O: Bi-directional management instruc-
tion/data signal th at may be sourced by the sta tion man agement e n-
tity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
CRS/LED_CFG O, S 61 CARRIER SENSE: Asserted high to indicat e the presence of carrier
due to receive or transmit activity in 10 BASE-T or 100BASE-TX Half
Duplex Modes, whi le in full d uplex mode carrier sens e is asserted to
indicate the presence of carrier due only to receive activity.
COL O 60 COLLISION DETECT: Asserted hig h to indic ate dete ction of a c olli-
sion condition (simultaneous transmit and receive activity) in 10
Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with Heartbeat enabled this
pin are also asserte d for a duratio n of approx imate ly 1µs at the end
of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal
is always logic 0. There is no heartbeat function during 10 Mb/s full
duplex operation.
TX_CLK O 51 TRANSMIT CLOCK: 25 MHz Transmit clock outputs in 100BASE-
TX mode or 2.5 MHz in 10BASE-T mode derived from the 25 MHz
reference cl ock.
TXD[3]
TXD[2]
TXD[1]
TXD[0]]
I 59, 58, 55, 54 TRANSMIT DATA: Transmit data MII input pins that accept nibble
data synchronous to the TX_CLK (2.5 MHz in 10BASE-T Mode or
25 MHz in 100BASE-TX mode.
TX_EN I 52 TRANSMIT ENABLE: Active high input indicates the presence of
valid nibble data on data inputs, TXD[3:0] for both 100 Mb/s or 10
Mb/s nibble mode.
TX_ER I 50 TRANSMIT ERROR: In 100MB/s mode , when this signal is h igh and
the c orre spo ndi ng T X_EN is ac tiv e th e HA LT sy mbol is su bst itu ted
for data.
In 10 Mb/s this input is ignored.
RX_CLK O, PU 45 RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks
for 100BASE-TX mode and 2.5 MHz for 10BASE-T nibble mode.
Obsolete
6 www.national.com
DP83846A
1.2 10 Mb/s and 100 Mb/s PMD Interface
1.3 Clock Interface
1.4 Special Connections
RXD[3]
RXD[2]
RXD[1]
RXD[0]
O, PU/PD 38, 39, 40, 41 RECEIVE DATA: Nibble wide receive data (synchronous to corre-
sponding RX_CLK, 25 MHz for 100BASE-TX mode, 2.5 MHz for
10BASE-T nibble mode). Data is driven on the falling edge of
RX_CLK. RXD[2] has an internal pulldown resistor. The remaining
RXD pins have pullups.
RX_ER/PAUSE_EN S, O, PU 46 RECEIVE ERROR: Asserted high to indicate that an invalid symbol
has been detected within a received packet in 100BASE-TX mode.
RX_DV O 44 RECEIVE DATA VALID: Asserted high to indicate that valid data is
present on the correspond ing RXD[3:0] for nibble mode. Da ta is driv-
en on the falling edge of the corres pon ding RX_CLK .
Signal Name Type LQFP Pin # Description
Signal Name Type LQFP Pin # Description
TD+, TD- O 16, 17 Differential common driver transmit output. These differential out-
puts are configur able to either 10BASE- T or 100BASE-TX signaling.
The DP83846A will automatically configure the common driver out-
puts f or th e prop er signal ty pe a s a re su lt o f e ith er f orc ed co nfi gura -
tion or Auto-Negotiation.
RD-, RD+ I 10, 11 Differential rec eive input. These differential inputs can be configured
to accept either 100BASE-TX or 10BASE-T signaling.
The DP83 846A will automatic ally conf igure the rece ive inputs to ac-
cept the proper signal type as a result of either forced configuration
or Auto-Negotiation.
Signal Name Type LQFP Pin # Description
X1 I 67 REFERENCE CLOCK INPUT 25 MHz: This pin is the primary
clock reference input for the DP83846A and must be connected to
a 25 MHz 0.005% (±50 ppm) clock source. The DP83846A sup-
ports CMOS-level oscillator sources.
X2 O 66 REFERENCE CLOCK OUTPUT 25 MHz: This pin is the primary
cloc k reference output.
Signal Name Type LQFP Pin # Description
RBIAS I 3 Bias Re sistor Connect ion. A 9.31 kΩ 1% resi stor shoul d be connect-
ed from RBIAS to ANA_GND.
RESERVED I/O 1, 5, 8, 20,
21, 22, 47,
63, 68, 69,
70, 71, 74,
75, 77, 78,
80
RESER VED: These pins must be left unconnected.
Obsolete
7 www.national.com
DP83846A
1.5 LED Interface
1.6 Strapping Options/Dual Purpose Pins
A 5 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is
required, then there is no need for external pull-up or pull
down res istor s, since th e int ernal pu ll-up or p ull down re sis-
tors will set the default value. Please note that the
PHYAD[0:4] pins have no internal pull-ups or pull-downs
and they must be strapped. Since these pins may have
alternate functions after reset is deasserted, they should
not be connected directly to Vcc or GND.
Signal Name Ty pe LQFP Pin # Descrip tion
LED_DPLX/PHYAD0 S, O 33 FULL DUPLEX LED STATUS: Indicates Full -Duplex status.
LED_COL/PHYAD1 S, O 32 COLLISION LED STATUS: Indicat es Collision activity in Half Duplex
mode.
LED_GDLNK/PHYAD2 S, O 31 GOOD LINK LED STATUS: Indicates Good Lin k Status fo r 10BASE-
T and 100BASE-TX.
LED_TX/PHYAD3 S, O 30 TRANSMIT LED STATUS: Indicates transmit activity. LED is on for
activity, off for no activity.
LED_RX/PHYAD4 S, O 29 RECEIVE LED STATUS: Indicates rece ive a ctivi ty. L ED is o n for ac-
tivity, off for no activity.
LED_SPEED O 28 SPEED LED STATUS: Indicates link speed; high for 100 Mb/s, low
for 10 Mb/s.
Signal Name Type LQFP Pin # Description
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
LED_RX/PHYAD4
S, O 33
32
31
30
29
PHY ADDRESS [4:0]: The DP83846A provides five PHY address
pins, the state of which are latched into the PHYCTRL register at
system Hardware-Reset.
The DP83846A supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). PHY Address 0 puts the part
into the MII Isolate Mode. The MII is olat e mode must be sele cted
by strapping Phy Address 0; changing to Address 0 by register
write will not put the Phy in the MII isolate mode.
The status of these pins are latched into the PHY Control Register
during Hardware-Reset. (Please note these pins have no internal
pull-up or pull-dow n resistors and they m ust be strappe d high or lo w
using 5 kΩ resistors.)
Obsolete
8 www.national.com
DP83846A
AN_EN
AN_1
AN_0
S, O, PU 27
26
25
Auto-Negotiation Enable: When high enables Auto-Negotiation
with the capability set by ANO and AN1 pins. When low, puts the
part into Fo rced M ode w ith the cap abili ty se t by AN0 a nd AN1 pi ns.
AN0 / AN1: These input pins control the forced or advertised oper-
ating mode of the DP83846A according to the following table. The
value on th ese pins is s et by co nnect ing th e inpu t pins t o GND (0)
or VCC (1) through 5 kΩ resistors. These pins should NEVER be
connected directly to GND or VCC.
The value set at this input is latched into the DP83846A at Hard-
ware-Reset.
The float/pull-down status of these pins are latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset. After reset is deasserted, these
pins may switch to outputs so if pull-ups or pull-downs are imple-
mented, they should be pulled through a 5kΩ resistor.
The default is 111 since these pins have pull-ups.
RX_ER/PAUSE_EN S, O, PU 46 PAUSE ENABLE: This strapping option allows advertisement of
whether or not the DTE(MAC) has implemented both the optional
MAC c on trol su blayer an d the paus e func tion as spe ci fie d in clau se
31 and annex 31B of the IEEE 802.3x specification (Full Duplex
Flow Contro l).
When left floating the Auto-Negotiation Advertisement Register will
be set to 0, indicat ing that Fu ll Duplex Flo w Control is not supported .
When tied low through a 5 kΩ, the Auto-Negotiation Advertisement
Register will be set to 1, indicating that Full Duplex Flow Control is
supported.
The float/pull-down status of this pin is latched into the Auto-Nego-
tiation Advertisement Register during Hardware-Reset.
CRS/LED_CFG S, O,
PU
61 LED CONFIGURATION: This strapping option defines the polarity
and function of the FDPLX LED pin.
See Section 2.3 for further descriptions of this strapping option.
Signal Name Type LQFP Pin # Description
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half /Full-Duplex
1 1 0 10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
Obsolete
9 www.national.com
DP83846A
1.7 Reset
1.8 Power and Ground Pins
Signal Name Type LQFP
Pin # LLP
Pin # Description
RESET I6246RESET: Active Low input that initializes or re-initializes the
DP83846A. Asserting this pin low for at least 160 µs will
force a reset p roc es s to o cc ur whi ch wi ll re sul t in all i nte rnal
registers re-initializing to their default states as specified for
each bit in the Register Block section and all strapping op-
tions are re-in iti ali ze d.
Signal Name LQFP Pin # Description
TTL/CMOS INPUT/OUTPUT SUPPLY
IO_VDD 35, 43, 57, 65 I/O Supply
IO_GND 34, 42, 53, 56, 64 I/O Ground
INTERNAL SUPPLY PAIRS
CORE_VDD 24, 49, 72 Digi tal Core S upp ly
CORE_GND 23, 48, 73 Digi tal Core Gro und
ANALOG SUPPLY PINS
ANA_VDD 4, 7, 12, 14 Analog Supply
ANA_GND 2, 6, 9, 13, 15, 18, Analog Ground
SUBSTRATE GROUND
SUB_GND 19, 76, 79 Bandgap Substrate connection
Obsolete
10 www.national.com
DP83846A
1.9 Package Pin Assignments
LQFP Pin # Pin Name LQFP Pin # Pin Na me
1 RESERVED 41 RXD_0
2 ANA_GND 42 IO_GND
3 RBIAS 43 IO_VDD
4 ANA_VDD 44 RX_DV
5 RESERVED 45 RX_CLK
6 ANA_GND 46 RX_ER/PAUSE_EN
7 ANA_VDD 47 RESERVED
8 RESERVED 48 CORE_GND
9 ANA_GND 49 CORE_VDD
10 RD- 50 TX_ER
11 RD+ 51 TX_CLK
12 ANA_VDD 52 TX_EN
13 ANA_GND 53 IO_GND
14 ANA_VDD 54 TXD_0
15 ANA_GND 55 TXD_1
16 TD+ 56 IO_GND
17 TD- 57 IO_VDD
18 ANA_GND 58 TXD_2
19 SUB_GND 59 TXD_3
20 RESERVED 60 COL
21 RESERVED 61 CRS/LED_CFG
22 RESERVED 62 RESET
23 CORE_GND 63 RESERVED
24 CORE_VDD 64 IO_GND
25 AN_0 65 IO_VDD
26 AN_1 66 X2
27 AN_EN 67 X1
28 LED_SPEED 68 RESERVED
29 LED_RX /PHYAD4 69 RESERVED
30 LED_TX /PHYAD3 70 RESERVED
31 LED_GDLNK/PHYAD2 71 RESERVED
32 LED_COL /PHYAD1 72 CORE_VDD
33 LED_FDPLX /PHYAD0 73 CORE_GND
34 IO_GND 74 RESERVED
35 IO_VDD 75 RESERVED
36 MDIO 76 SUB_GND
37 MDC 77 RESERVED
38 RXD_3 78 RESERVED
39 RXD_2 79 SUB_GND
40 RXD_1 80 RESERVED
Obsolete
11 www.national.com
DP83846A
2.0 Configuration
This se ction in clude s inform atio n on the var ious con figura -
tion options available with the DP83846A. The configura-
tion options described below include:
— Device Co nfi gura tio n
— Auto-Negotiation
— PHY Address and LEDs
— Half Dup lex vs. Full Duplex
— Isolate mode
— Loop bac k mo de
—BIST
2.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest per-
formance mode of operation supported by both devices.
Fast Link Pulse (FLP) Bursts provide the signalling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to Clause 28 of the IEEE
802.3u specification. The DP83846A supports four differ-
ent Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the high-
est performance protocol will be selected based on the
advertised ability of the Link Partner. The Auto-Negotiation
function within the DP83846A can be controlled either by
internal register access or by the use of the AN_EN, AN1
and AN0 pins.
2.1.1 Auto-Negotiation Pin Control
The st ate o f AN_EN, AN0 an d AN1 det ermine s wheth er the
DP83846A is forced into a specific mode or Auto-Negotia-
tion will advertise a specific ability (or set of abilities) as
given in Table 1. These pins allow configuration options to
be selected without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power-up/reset,
determines the state of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or
reset can be changed at any time by writing to the Basic
Mode Control Register (BMCR) at address 00h.
2.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83846A trans-
mits the abilities programmed into the Auto-Negotiation
Advertisement register (ANAR) at address 04h via FLP
Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-
Duplex, and Full Duplex modes may be selected. The
BMCR provides software with a mechanism to control the
operation of the DP83846A. The AN0 and AN1 pins do not
affect the contents of the BMCR and cannot be used by
software to obtain status of the mode selected. Bits 1 & 2 of
the PHYSTS register are only valid if Auto-Negotiation is
disabled or after Auto-Negotiation is complete. The Auto-
Negotiation protocol compares the contents of the
ANLPAR and ANAR registers and uses the results to auto-
matically configure to the highest performance protocol
between the local and far-end port. The results of Auto-
Negotiation (Auto-Neg Complete, Duplex Status and
Speed) may be accessed in the PHYSTS register.
Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Dupl ex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is dis-
abled the Speed Selec tio n bi t in th e BM C R con trol s s witc h-
ing between 10 Mb/s or 100 Mb/s operation, and the
Duplex Mode bit controls switching between full duplex
operation and half duplex operation. The Speed Selection
and Duplex Mode bits have no effect on the mode of oper-
ation when the Auto-Negotiation Enable bit is set.
The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotiation
ability, and Extended Register Capability. These bits are
permanently set to indicate the full functionality of the
DP83846A (only the 100BASE-T4 bit is not set since the
DP83846A does not support that function).
Table 1. Auto-Negotiation Modes
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Dup lex
1 1 0 10BASE-T Half-Duplex
100BASE-TX, Half-Duple x
1 1 1 10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Fu ll-Du ple x
Obsolete
12 www.national.com
DP83846A
The BMSR also provides status on:
— Whether Auto-Negotiation is complete
— Whether the Link Partner is advertising that a remote
fault has occurred
— Whether valid link has been established
— Support for Management Frame Preamble suppression
The Auto-Negotiation Adve rtis ement Register (ANAR) indi-
cates the Auto-Negotiation abilities to be advertised by the
DP8384 6A. All ava ilable abilit ies are tra nsmit ted by de fault,
but any ability can be suppressed by writing to the ANAR.
Updating the ANAR to suppress an ability is one way for a
manage ment age nt to chang e (force) the technol ogy tha t is
used.
The Auto-Negotiation Link Partner Ability Register
(ANLPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER) indi-
cates additional Auto-Negotiation status. The ANER pro-
vides sta tus on:
— Whether a Parallel Detect Fault has occurred
— Whether the Link Partner supports the Next Page func-
tion
— Whether th e DP83846A s upports the Next Pa ge function
— Wheth er the curr ent page being ex chang ed by Auto -Ne-
gotiation has been received
— Whether the Link Partner supports Auto-Negotiation
2.1.3 Auto-Negotiation Parallel Detecti on
The DP83846A supports the Parallel Detection function as
defined in the IEEE 802.3u spec ifi ca tio n. Para lle l De tec tio n
requires both the 10 Mb/s and 100 Mb/s receivers to moni-
tor the receive signal and report link status to the Auto-
Negotiation function. Auto-Negotiation uses this informa-
tion to c onfigu re the c orrect t echno logy i n the even t that th e
Link Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASE-
T PMAs recogniz e as va lid link si gnals.
If the DP83846A completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may deter-
mine that negotiation completed via Parallel Detection by
reading a ze ro in the Link Partn er Au to-Neg oti ati on Ab le b it
once the Auto -Nego tia tio n Com pl ete b it i s s et. I f co nfi gure d
for parallel detect mode and any condition other than a sin-
gle good link oc curs th en the p arall el dete ct fault bit wil l set.
2.1.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted
at any ti me by s etting bit 9 (Res tart Auto-Ne gotiat ion) of th e
BMCR to o ne. If th e mode confi gured b y a su cces sful Au to-
Negotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configu-
ration for the link. This function ensures that a valid config-
uration is maintained if the cable becomes disconnected.
A rene got iati on requ es t fro m any en tity, such as a manage-
ment agent, will cause the DP83846A to halt any transmit
data and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83846A will resume Auto-Negotiation after the
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.
2.1.5 Enabling Auto-Negotiation via Software
It is impor tant t o note that if the D P83 846 A has bee n ini t ia l-
ized upon power-up as a non-auto-negotiating device
(force d technology), and it is then requ ired that Auto-Neg o-
tiation or re-Auto-Negotiation be initiated via software,
bit 12 (Auto-Negotiation Enable) of the Basic Mode Control
Register must first be cleared and then set for any Auto-
Negotiation function to take effect.
2.1.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 s eco nd s to co mp lete. In ad dition, Auto-Neg otia tio n w i th
next page should take approximately 2-3 seconds to com-
plete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full
description of the individual timers related to Auto-Negotia-
tion.
2.2 PHY Address and LEDs
The 5 PHY address inputs pins are shared with the LED
pins as shown below.
The DP8 384 6A c an be set to respon d to any o f 32 poss ibl e
PHY addresses. Each DP83846A or port sharing an MDIO
bus in a system must have a unique physical address.
Refer to Section 3.1.4, PHY Address Sensing section for
more details.
The state of each of the PHYAD inputs latched into the
PHYCTRL register bits [4:0] at system power-up/reset
depends on whether a pull-up or pull-down resistor has
been installed for each pin. For further detail relating to the
latch-in timing requirements of the PHY Address pins, as
well as the other hardware configuration pins, refer to the
Reset summary in Section 4.0.
Sinc e t he PH YAD st r a p opt i on s sh a re t he LED out p ut pi ns ,
the external components required for strapping and LED
usage must be considered in order to avoid contention.
Specifically, when the LED outputs are used to drive LEDs
directly, the active state of each output driver is dependent
on the logic level sampled by the corresponding PHYAD
input upon power-up/reset. For example, if a given PHYAD
input is res is tiv ely pu lle d lo w the n th e co rres pon di ng o utput
will be configured as an active high driver. Conversely, if a
given PHYAD input is resistively pulled high, then the cor-
responding output will be configured as an active low
Table 2. PHY Address Mapping
Pin # PHYAD Function LED Function
33 PHYAD0 Duplex
32 PHYAD1 COL
31 PHYAD2 Good Link
30 PHYAD3 TX Activity
29 PHYAD4 RX Activity
28 n/a Speed
Obsolete
13 www.national.com
DP83846A
driver. Refer to Figure 2 for an example of a PHYAD con-
nection to external components. In this example, the
PHYAD strapping results in address 00011 (03h).
The adaptive nature of the LED outputs helps to simplify
potential implementation issues of these dual purpose pins.
2.3 LED INTERFACES
The DP83846A has 6 Light Emitting Diode (LED) outputs,
eac h capable to drive a maximum of 10 mA, to indic ate t he
status of Link, Transmit, Receive, Collision, Speed, and
Full/Half Duplex operation. The LED_CFG strap option is
used to configure the LED_FDPLX output for use as an
LED driver or more general purpose control pin. See the
table below:
The LED_FDPLX pin indicates the Half or Full Duplex con-
figuration of the port in both 10 Mb/s and 100 Mb/s opera-
tion. Since this pin is also us ed as the PHY address strap
option, the polarity of this indicator may be adjusted so that
in the “active” (FULL DUPLEX selected) state it drives
against the pullup/pulldown strap. In this configuration it is
suitable for use as an LED. When LED_CFG is high this
mode is selected and DsPHYTER automatically adjusts the
polarity of the output. If LED_CFG is low, the output drives
high to indicate the “active” state. In this configuration the
output is suitable for use as a control pin. The
LED_SPEED pin indicates 10 or 100 Mb/s data rate of the
port . The s tan da rd C M OS dr i ve r go es hi g h wh en op e rat i ng
in 100 Mb/s operation. Since this pin is not utilized as a
strap option, it is not affected by polarity adjustment.
The LED_GDLNK pin indicates the link status of the port.
Since this pin is also used as the PHY address strap
option, the polarity of this indicator is adjusted to be the
inverse of the strap value.
In 100BASE-T mode, link is established as a result of input
receive amplitude compliant with TP-PMD specifications
which will result in internal generation of signal detect.
10 Mb/s Li nk is es tab lishe d as a resu lt of the rec eption of at
least seven consecutive normal Link Pulses or the recep-
tion of a valid 10BASE-T packet. This will cause the asser-
tion of GD_LINK. GD_LINK will deassert in accordance
with the Link Loss Timer as specified in IEEE 802.3.
The Collision LED indicates the presence of collision activ-
ity for 10 Mb/s or 100 Mb/s Half Duplex operation. This bit
has no meaning in Full Duplex operation and will be deas-
serted when the port is operating in Full Duplex. Since this
pin is also used as the PHY address strap option, the
polarity of this indicator is adjusted to be the inverse of the
strap value. In 10 Mb/s half duplex mode, the collision LED
is based on the COL signal. When in this mode, the user
should disable the Heartbeat (SQE) to avoid asserting the
COL LED during transmission. See Section 3.4.2 for more
information about the Heartbeat signal.
The LED_RX and LED_TX pins indicate the presence of
transmit and/or receive activity. Since these pins are also
used in PHY address strap options, the polarity is adjusted
to be the inverse of the respective strap values.
2.4 Half Duplex vs. Full Duplex
The DP83 846A su pport s both half an d full du plex o peratio n
at both 10 Mb/s and 100 Mb/s speeds. Half-duplex is the
standard, traditional mode of operation which relies on the
CSMA/CD protocol to handle collisions and network
access. In Half-Duplex mode, CRS responds to both trans-
mit and receive activity in order to maintain compliance
with IEEE 802.3 specification.
Since the DP83846A is designed to support simultaneous
transmit and receive activity it is capable of supporting full-
duplex switched applications with a throughput of up to
Figure 2. PHYAD Strapping and LED Loading Example
LED_FDPLX
LED_COL
LED_GDLNK
LED_TX
LED_RX
VCC
10kΩ
1kΩ
1kΩ
10kΩ
1kΩ
10kΩ
1kΩ
10kΩ
1kΩ
PHYAD0 = 1
PHYAD1 = 1
PHYAD2 = 0PHYAD3 = 0
PHYAD4= 0
10kΩ
Table 3. LED Mode Select
LED_CFG Mode Description
1 LED polarity adjusted
0 Duplex active-high
Obsolete
14 www.national.com
DP83846A
200 Mb/s per port when operating in 100BASE-TX mode.
Because the CSMA/CD protocol does not apply to full-
duplex operation, the DP83846A disables its own internal
collision sensing and reporting functions and modifies the
behavior of Carrier Sense (CRS) such that it indicates only
receive activity. This allows a full-duplex capable MAC to
operate properly.
All modes of operation (100BASE-TX and 10BASE-T) can
run either half-duplex or full-duplex. Additionally, other than
CRS and Collision reporting, all remaining MII signaling
remains the same regardless of the selected duplex mode.
It is important to understand that while Auto-Negotiation
with the use of Fast Link Pulse code words can interpret
and configure to full-duplex operation, parallel detection
can not recognize the difference between full and half-
duplex from a fixed 10 Mb/s or 100 Mb/s link partner over
twisted pair. As specified in 802.3u, if a far-end link partner
is transmitting forced full duplex 100BASE-TX for example,
the parallel detection state machine in the receiving station
would be unable to detect the full duplex capability of the
far-end link partner and would negotiate to a half duplex
100BASE-TX configuration (same scenario for 10 Mb/s).
2.5 MII Iso late Mode
The DP83846A can be put into MII Isolate mode by writing
to bit 10 of the BMCR register. In addition, the MII isolate
mode can be selected by strapping in Physical Address 0.
It shou ld be not ed tha t sel ectin g Phy sica l Addr ess 0 vi a an
MDIO write to PHYCTRL will not put the device in the MII
isolate mode.
When in the MII isolate mode, the DP83846A does not
respond to packet data present at TXD[3:0], TX_EN, and
TX_ER inputs and presents a high impedance on the
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and
CRS o utp ut s . Th e D P8 384 6A w i ll co nti nue to res pon d to all
management transactions.
While in Isolate mode, the TD± outputs will not transmit
packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
2.6 Loopback
The DP83846A includes a Loopback Test mode for facili-
tating system diagnostics. The Loopback mode is selected
through bit 14 (Loopback) of the Basic Mode Control Reg-
ister (BMCR). Writing 1 to this bit enables MII transmit data
to be routed to the MII receive outputs. Loopback status
may be checked in bit 3 of the PHY Status Register
(PHYSTS). While in Loopback mode the data will not be
transmitted onto the media in 100 Mb/s mode. To ensure
that the desired operating mode is maintained, Auto-Nego-
tiation should be disabled before selecting the Loopback
mode.
During 10BASE-T operation, in order to be standard com-
pliant, the loopbac k mode loop s MII transm it dat a to the MII
receive data, however, Link Pulses are not looped back. In
100BASE-TX Loopback mode the data is routed through
the PCS and PMA layers into the PMD sublayer before it is
looped back. In addition to serving as a board diagnostic,
this mode serves as a functional verification of the device.
2.7 BIST
The DsPHYTER incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diagnos-
tics. The BIST circuit can be utilized to test the integrity of
the transmit and receive data paths. BIST testing can be
performed with the part in the internal loopback mode or
externally looped back using a loopback cable fixture.
The BIST is implemented with independent transmit and
receive pa ths , wi th the tran sm it bl ock gene rati ng a con tin u-
ous stream of a pseudo random sequence. The user can
select a 9 bit or 15 bit pseudo random sequence from the
PSR_15 bit in the PHY Control Register (PHYCTRL). The
looped ba ck data is com p a red to the data generate d by the
BIST Linear Feedback Shift Register (LFSR, which gener-
ates a pseudo random sequence) to determine the BIST
pa ss/fail st a tus .
The pass/fail status of the BIST is stored in the BIST status
bit in the PHYCTRL register. The status bit defaults to 0
(BIST fail ) and will tra ns iti on on a succes sfu l co mparison. If
an error (mis -compare) occurs, the statu s bit is la tched an d
is cleared upon a subsequent write to the Start/Stop bit.
Obsolete
15 www.national.com
DP83846A
3.0 Functional Description
3.1 802.3u MII
The DP83846A incorporates the Media Independent Inter-
face (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describ es both the seri al MI I man age ment interfac e as well
as the nibble wide MII data interface.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gather-
ing of s tat us, erro r inform ation, and th e determ inati on of th e
type and capabilities of the attached PHY(s).
The nib ble wi de MII da ta interface c ons is t s of a rec eive bu s
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC).
3.1.1 Serial Management Register Access
The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are acces-
sible through the management interface pins MDC and
MDIO. The DP83846A implements all the required MII reg-
isters as well as several optional registers. These registers
are fully described in Section 5. A description of the serial
management access protocol follows.
3.1.2 Serial Management Access Protocol
The serial control interface consists of two pins, Manage-
ment Data Clock (MDC) and Management Data Input/Out-
put (MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame for-
mat is shown below in Table 4: Typical MDIO Frame For-
mat.
The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during ID LE and turnaro und, w ill pu ll MDIO high. In order to
initial ize the MDIO int erface , the st atio n ma nagem ent entit y
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83846A with a sequence that can be used
to estab lis h sync hro nizat ion . This prea mble ma y be ge ner-
ated either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pull-up resis-
tor to pull the MDIO pin high during which time 32 MDC
clock cycles are provided. In addition 32 MDC clock cycles
should be used to re-sync the device if an invalid start,
opcode, or turnaround bit is detected.
The DP83846A waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83846A serial management port has been ini-
tialized no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.
The Start code is in dic ate d by a <01> p atte rn. Th is assure s
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid con-
tention during a read transaction, no device shall actively
drive the MDIO signal during the first bit of Turnaround.
The addressed DP83846A drives the MDIO with a zero for
the second bit of turnaround and follows this with the
required data. Figure 3 shows the timing relationship
betwee n MDC and th e MDIO as dr iven/re ceiv ed by the Sta-
tion (STA) and the DP83846A (PHY) for a typical register
read access.
For write transactions, the station management entity
writes data to the addressed DP83846A thus eliminating
the requirement for MDIO Turnaround. The Turnaround
time is filled by the management entity by inserting <10>.
Figure 4 shows the timing relationship for a typical MII reg-
ister write access.
3.1.3 Serial Management Preamble Suppression
The DP83846A supports a Preamble Suppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, address 01h.) If the station management
entity (i.e. MAC or other management controller) deter-
mines that all PHYs in the system support Preamble Sup-
Table 4. Typical MDIO Frame Format
MII Management
Serial Protocol <idle><start><op code><device addr><reg addr><turnaround><data><idle>
Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA><RRRRR>< 10>< xxxx xxxx xxxx xxxx><idle>
Figure 3. Typical MDC/MDIO Read Operation
MDC
MDIO
00011 110000000
(STA)
Idle Start Opcode
(Read) PHY Address
(PHYAD = 0Ch) Register Address
(00h = BMCR) TA Registe r Da ta
Z
MDIO
(PHY)
Z
Z
Z0 0 011000100000000Z
Idle
Z
Z
Obsolete
16 www.national.com
DP83846A
pression by returning a one in this bit, then the station
management entity need not generate preamble for each
management transaction.
The DP83846A requires a single initialization sequence of
32 bit s o f preamble foll ow in g ha rdwa re/s oftw a re res et . Thi s
requirement is generally met by the mandatory pull-up
resis t or on MDI O in co nj un c tio n w i th a cont i nu o us MDC , or
the management access made to determine whether Pre-
amble Suppression is supported.
Whil e the DP8384 6A require s an init ial preambl e sequ ence
of 32 bits for management initialization, it does not require
a full 32-bit sequence between each subsequent transac-
tion. A minimum of one idle bit between management
transac tio ns is require d as specified in IEEE 802.3u.
3.1.4 PHY Address Sensing
The DP83846A provides five PHY address pins, the infor-
mation is latched into the PHYCTRL register (address 19h,
bits [4:0]) at device power-up/Hardware reset.
The DP83846A supports PHY Address strapping values 0
( < 0 0 0 00 > ) th r o u g h 3 1 ( < 11111> ) . St r a pp i n g PHY Address
0 puts th e part i nt o Is ola t e Mod e . It should also be noted
that selecting PHY Address 0 via an MDIO write to PHYC-
TRL will not put th e devi ce in Is olate M ode; Add ress 0 must
be strapped in.
3.1.5 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface includes a
dedica ted recei ve bu s and a d edicated transmi t b us . These
two dat a bus es , alo ng w i th va rio us c on t rol a nd in di cat e sig-
nals, allow for the simultaneous exchange of data between
the DP83846A and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus
RXD[3:0], a receive error signal RX_ER, a receive data
valid flag RX_DV, and a receive clock RX_CLK for syn-
chronous transfer of the data. The receive clock can oper-
ate at either 2.5 MHz to support 10 Mb/s operation modes
or at 25 MHz to support 100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus
TXD[3:0], a transmit enable control signal TX_EN, and a
tran smit cloc k TX_CL K which runs at ei ther 2. 5 MHz or 25
MHz.
Additionally, the MII includes the carrier sense signal CRS,
as well as a collision detect signal COL. The CRS signal
asserts to indicate the reception of data from the network
or as a function of transmit data in Half Duplex mode. The
COL signal as se rts as an indic atio n o f a c ol lis io n which ca n
occur during half-duplex operation when both a transmit
and receive operation occur simultaneously.
3.1.6 Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is
detected when the receive and transmit channels are
active simultaneously. Collisions are reported by the COL
signal on the MII.
If the DP83846A is transmitting in 10 Mb/s mode when a
collis ion i s d ete cted, the collisi on is n ot reported until seven
bits have been received while in the collision state. This
prevents a collision being reported incorrectly due to noise
on the network. The COL signal remains set for the dura-
tion of the collision.
If a col lis io n o cc urs du ring a receiv e o pera t io n, i t i s i mm ed i-
ately reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1µs after the transmission of
each p acket, a Si gn al Q u ali ty Error (SQE) signal of ap prox -
imately 10 bit times is generated (internally) to indicate
succe ssful t rans m ission. SQE is repo rted as a pul se on th e
COL signal of the MII.
3.1.7 Carrier Sense
Carrier Se ns e (CR S) ma y be ass erted due to rece iv e ac tiv -
ity, onc e va lid data is de tec ted v ia the squ elc h fun ct ion dur-
ing 10 Mb/s operation. During 100 Mb/s operation CRS is
asserted when a valid link (SD) and two non-contiguous
zeros are detected on the line.
For 10 or 100 Mb/s H alf Duplex opera tio n, C RS is a sserte d
during either packet transmiss ion or rece ption .
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
3.2 100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several functional
blocks which c onvert sync hronous 4-bit ni bble da t a, as p ro-
vided by the MII, to a scrambled MLT-3 125 Mb/s serial
data stream. Because the 100BASE-TX TP-PMD is inte-
grated, the differential output pins, TD±, can be directly
routed to the magnetics.
The block diagram in Figure 5 provides an overview of
each functional block within the 100BASE-TX transmit sec-
tion.
The Transmitter section consists of the following functional
blocks:
— Code-group Encoder and I njection block (bypass option)
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
Figure 4. Typical MDC/MDIO Write Operation
MDC
MDIO
00011110000000
(STA)
Idle Start Opcode
(Write) PHY Address
(PHYAD = 0Ch) Register Address
(00h = BMCR) TA Register Data
Z000 000 00000000Z
Idle
1000
ZZ
Obsolete
17 www.national.com
DP83846A
The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The
DP83846A implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Stan-
dard, Clau se 24.
3.2.1 Code-group Encoding and Injection
The code-group encoder converts 4-bit (4B) nibble data
generated by the MAC into 5-bit (5B) code-groups for
transmission. This conversion is required to allow control
data to be combined with packet data code-groups. Refer
to Table 5: 4B5B Code-Group Encoding/Decoding for 4B to
5B code-group mapping details.
The code-group encoder substitutes the first 8-bits of the
MAC preamble with a J/K code-group pair (11000 10001)
upon transmission. The code-group encoder continues to
replace subsequent 4B preamble and data nibbles with
corresponding 5B code-groups. At the end of the transmit
packet, upon the deassertion of Transmit Enable signal
from the MAC, the code-group encoder injects the T/R
code-gro up p ai r (0 1101 00111) indicat ing the en d o f fra me .
After the T/R code-group pair, the code-group encoder
continuously injects IDLEs into the transmit data stream
until the next transmit packet is detected (reassertion of
Transmit E nable).
3.2.2 Scrambler
The scrambler is required to control the radiated emissions
at the media connector and on the twisted pair cable (for
100BASE-TX applications). By scrambling the data, the
total energy launched onto the cable is randomly distrib-
uted over a wide frequency range. Without the scrambler,
energy levels at the PMD and on the cable could peak
beyond FCC limitations at frequencies related to repeating
5B sequences (i.e., continuous transmission of IDLEs).
The scrambler is configured as a closed loop linear feed-
back shift register (LFSR) with an 11-bit polynomial. The
output of the closed loop LFSR is X-ORd with the serial
Figure 5. 100BASE-TX Transmit Block Diagram
4B5B Code-grou p
encoder & injector
scrambler
nrz to nrzi
encoder
5B parallel
to serial
TD±
TX_CLK
TXD[3:0] /
tx_er
100BASE-TX
Loopback
mux
binary to mlt-3 /
Common Driver
FROM PGM
BP_4B5B
BP_SCR mux
DIV BY 5
Obsolete
18 www.national.com
DP83846A
NRZ data from the code-group encoder. The result is a
scrambled data stream with sufficient randomization to
decrease radiated emissions at certain frequencies by as
much as 20 dB. The DP83846A uses the PHY_ID (pins
PHYAD [4:0]) to set a unique seed value.
3.2.3 NRZ to NRZI Encoder
After the transmit data stream has been serialized and
scrambled, the data must be NRZI encoded in order to
comply with the TP-PMD standard for 100BASE-TX trans-
mission over Category-5 Unsheilded twisted pair cable.
3.2.4 Binary to MLT-3 Convertor / Common Driver
The Binary to MLT-3 conversion is accomplished by con-
verting the serial binary data stream output from the NRZI
encoder into two binary data streams with alternately
phased logic one events. These two binary streams are
then fed to the twiste d p a ir outp ut dri ver which con ve rt s the
voltage to current and alternately drives either side of the
transmi t transfor mer primary winding, res ultin g in a mini mal
current (20 mA max) MLT-3 signal. Refer to Figure 6.
Figure 6. Binary to MLT-3 conversion
DQ
Q
binary_in binary_plus
binary_minus
binary_in
binary_plus
binary_minus
COMMON
DRIVER MLT-3
dif fere nti al MLT -3
Obsolete
19 www.national.com
DP83846A
Table 5. 4B5B Code-Group Encoding/Deco ding
Name PCS 5B Code-group MII 4B Nibble Code
DATA CODES
0 11110 0000
1 01001 0001
2 10100 0010
3 10101 0011
4 01010 0100
5 01011 0101
6 01110 0110
7 01111 0111
8 10010 1000
9 10011 1001
A 10110 1010
B 10111 1011
C 11010 1100
D 11011 1101
E 11100 1110
F 11101 1111
IDLE AND CONTROL CODES
H 00100 HALT code-group - Error code
I 11111 Inter-Packet IDLE - 0000 (Note 1)
J 11000 First Start of Packet - 0101 (Note 1)
K 10001 Second Start of Packet - 0101 (Note 1)
T 01101 First End of Packet - 0000 (Note 1)
R 00111 Second End of Packet - 0000 (Note 1)
INVALID CODES
V 00000
V 00001
V 00010
V 00011
V 00101
V 00110
V 01000
V 01100
V 10000
V 11001
Note 1: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.
Obsolete
20 www.national.com
DP83846A
The 100BASE-TX MLT-3 signal sourced by the TD± com-
mon driver output pins is slew rate controlled. This should
be considered when selecting AC coupling magnetics to
ensure TP-PMD Standard compliant transition times (3 ns
< Tr < 5 ns).
The 100BASE-TX transmit TP-PMD function within the
DP83846A is capable of sourcing only MLT-3 encoded
data. Binary output from the TD± outputs is not possible in
100 Mb/s mo de.
3.3 100BASE-TX RECEIVER
The 100BASE-TX receiver consists of several functional
blocks which convert the scrambled MLT-3 125 Mb/s serial
data stream to synchronous 4-bit nibble data that is pro-
vided to the MII. Because the 100BASE-TX TP-PMD is
integrated, the differential input pins, RD±, can be directly
routed from the AC coupling magnetics.
See Figure 8 for a block diagram of the 100BASE-TX
receive function. This provides an overview of each func-
tional block within the 100BASE-TX receive section.
The Receive section consists of the following functional
blocks:
—ADC
— Input and BLW Compensation
— Signal Detect
— Digital Adaptive Equalization
— MLT-3 to Binary De co der
— Cloc k Recovery Module
— NRZI to NRZ Decoder
— Serial to Parallel
— DESCRAMBLER (bypass option)
— Code Group Alignment
— 4B/5B Decoder (bypass option)
— Link Integrity Monitor
— Bad SSD Detection
The bypass option for the functional blocks within the
100BASE-TX receiver provides flexibility for applications
where data conversion is not always required.
3.3.1 Input and Base Line Wander Compensation
Unlike the DP83223V Twister, the DP83846A requires no
external attenuation circuitry at its receive inputs, RD±. It
accepts TP-PMD compliant waveforms directly, requiring
only a 100Ω termination plus a simple 1:1 transformer.
The DP8 384 6A is c omple tel y AN SI TP-PMD c om pl ian t an d
includes Base Line Wander (BLW) compensation. The
BLW co mp ensa t io n bl o ck c an su cc e ssf ul ly re cov er th e T P-
PMD defined “killer” pattern and pass it to the digital adap-
tive equalization block.
BLW can generally be defined as the change in the aver-
age DC content, over time, of an AC coupled digital trans-
mission over a given transmission medium. (i.e., copper
wire).
BLW results from the interaction between the low fre-
quency c om pon ents of a transm itt ed bit stre am an d the f re-
quency response of the AC coupling component(s) within
the transmission system. If the low frequency content of
the digital bit stream goes below the low frequency pole of
the AC coupling transformers then the droop characteris-
tics of th e tra ns form ers will dom in ate result ing in p otentiall y
serious BLW.
The digital oscilloscope plot provided in Figure 7 illustrates
the seve rity of the BLW e vent that can theo retically be ge n-
erated during 100BASE-TX packet transmission. This
event consists of approximately 800 mV of DC offset for a
Figure 7. 100BASE-TX BLW Event
Obsolete
21 www.national.com
DP83846A
Figure 8. Receive Block Diagram
4b/5b Deco der
DEscrambler
Digital
adaptive
Equalization
MLT-3 to
Binary decod er
rd±
RX_CLK RXD[3:0] / RX_ER
InPUT BLW
Compensation
BP_4B5B
BP_SCR
Signal Detect
nrzi to nrz
decoder
Code group
alignment
Serial to
parallel
mux
mux
LINK STATUS
Clock
Recovery
Module
CLOCK
LINK
Monitor
÷5
ADC
AGC
Obsolete
22 www.national.com
DP83846A
period of 120 µs. Left uncompensated, events such as this
can cause p a ck et los s.
3.3.2 Signal Detect
The sign al dete ct func ti on of the D P838 46A is i nc orpo r ate d
to meet th e specifi cat ion s m an date d by the AN SI FDDI TP-
PMD Standard as well as the IEEE 802.3 100BASE-TX
Standard for both voltage thresholds and timing parame-
ters.
Note that the reception of normal 10BASE-T link pulses
and fast link pulses per IEEE 802.3u Auto-Negotiation by
the 100BASE-TX receiver do not cause the DP83846A to
assert signal detect.
3.3.3 Digital Adaptive Equalization
When transmitting data at high speeds over copper twisted
pair cable, frequency dependent attenuation becomes a
concern. In high-speed twisted pair signalling, the fre-
quency content of the transmitted signal can vary greatly
during normal operation based primarily on the random-
ness of the scrambled data stream. This variation in signal
attenuation caused by frequency variations must be com-
pensated for to ensure the integrity of the transmission.
In order to ensure quality transmission when employing
MLT-3 encoding, the compensation must be able to adapt
to various cable lengths and cable types depending on the
installed environment. The selection of long cable lengths
for a given implementation, requires significant compensa-
tion which will over-compensate for shorter, less attenuat-
ing lengths. Conversely, the selection of short or
intermediate cable lengths requiring less compensation will
cause serious under-compensation for longer length
cables. The compensation or equalization must be adap-
tive to ensure proper conditioning of the received signal
independent of the cable length.
The DP83846A utilizes a extremely robust equalization
scheme referred as ‘Digital Adaptive Equalization’. Tradi-
tional designs use a pseudo adaptive equalization scheme
that determines the approximate cable length by monitor-
ing signal attenuation at certain frequencies. This attenua-
tion value was compared to the internal receive input
reference voltage. This comparison would indicate the
amount of equalization to use. Although this scheme is
used successfully on the DP83223V twister, it is sensitive
to transformer mismatch, resistor variation and process
induced offset. The DP83223V also required an external
attenuation network to help match the incoming signal
amplitude to the internal reference.
The Digital Equalizer removes ISI (inter symbol interfer-
ence) from the receive data stream by continuously adapt-
ing to provide a filter with the inverse frequency response
of the channel. When used in conjunction with a gain
stage, this enables the receive 'eye pattern' to be opened
sufficiently to allow very reliable data recovery.
Traditionally 'adaptive' equalizers selected 1 of N filters in
an attempt to match the cables characteristics. This
approach will typically leave holes at certain cable lengths,
where the performance of the equalizer is not optimized.
The DP83846A equalizer is truly adaptive to any length of
cable up to 150m.
3.3.4 Clock Recovery Module
The Clock Recovery Module (CRM) accepts 125 Mb/s
MLT3 data from the equalizer. The DPLL locks onto the
125 Mb/s data stream and extracts a 125 MHz recovered
clock. The extracted and synchronized clock and data are
used as required by the synchronous receive operations as
generally depicted in Figure 8.
The CRM is implemented using an advanced all digital
Phase Locked Loop (PLL) architecture that replaces sensi-
tive analog circuitry. Using digital PLL circuitry allows the
DP83846A to be manufactured and specified to tighter tol-
erances.
3.3.5 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is
required in order to present NRZ formatted data to the
descrambler (or to the code-group alignment block, if the
descrambler is bypassed, or directly to the PCS, if the
receiver is bypassed).
3.3.6 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel
converter which supplies 5-bit wide data symbols to the
PCS Rx state machine.
3.3.7 Descrambler
A serial descrambler is used to de-scramble the received
NRZ data. The descrambler has to generate an identical
data scrambling sequence (N) in order to recover the origi-
nal unscrambled data (UD) from the scrambled data (SD)
as represented in the equations:
Synchronization of the descrambler to the original scram-
bling sequence (N) is achieved based on the knowledge
that the incoming scrambled data stream consists of
scrambled IDLE data. After the descrambler has recog-
nized 12 consecutive IDLE code-groups, where an
unscrambled IDLE code-group in 5B NRZ is equal to five
consecutive ones (11111), it will synchronize to the receive
data stream and generate unscrambled data in the form of
unalign ed 5B code -gro ups.
In order to maintain synchronization, the descrambler must
continuously monitor the validity of the unscrambled data
that it generates. To ensure this, a line state monitor and a
hold timer are used to constantly monitor the synchroniza-
tion status. Upon synchronization of the descrambler the
hold timer starts a 722 µs countdown. Upon detection of
suf fic ien t ID LE c ode -grou p s (58 b it tim es) with in th e 72 2 µs
period, the hold timer will reset and begin a new count-
down. This monitoring operation will continue indefinitely
given a properly operating network connection with good
signal integrity. If the line state monitor does not recognize
sufficient unscr ambled IDLE code-groups within th e 722 µs
period, the entire descrambler will be forced out of the cur-
rent state of synchronization and reset in order to re-
acquire synchronization.
3.3.8 Code-group Alignment
The code-group alignment module operates on unaligned
5-bit data from the descrambler (or, if the descrambler is
bypassed, directly from the NRZI/NRZ decoder) and con-
verts it into 5B code-group data (5 bits). Code-group align-
ment occurs after the J/K code-group pair is detected.
Once the J/K code-group pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
UD SD N⊕()=
SD UD N⊕()=
Obsolete
23 www.national.com
DP83846A
3.3.9 4B/5B Decode r
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Specifically, the J/K 10-bit code-group pair
is replaced by the nibble pair (0101 0101). All subsequent
5B code-groups are converted to the corresponding 4B
nibbles for the duration of the entire packet. This conver-
sion ceases upon the detection of the T/R code-group pair
denoting the End of Stream Delimiter (ESD) or with the
reception of a minimum of two IDLE code-groups.
3.3.10 100BASE-TX Link Integrity Monitor
The 100 Base TX Link m onito r ensu res tha t a val id and st a-
ble link is established before enabling both the Transmit
and Receive PCS layer.
Signal detect must be valid for 395us to allow the link mon-
itor to ent er th e ' Lin k Up' st ate, and enable the tr ans m it an d
receive functions.
3.3.11 Bad SSD Detection
A Bad S t art of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83846A will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the
cycles that correspond to received 5B code-groups until at
least two IDLE code groups are detected. In addition, the
False Carrier Sense Counter register (FCSCR) will be
incremented by one.
Once at least tw o IDLE code groups a re detec ted, RX_ ER
and CRS become de-asserted.
3.4 10BASE-T TRANSCEIVER MODULE
The 10BASE-T Transceiver Module is IEEE 802.3 compli-
ant. It includes the receiver, transmitter, collision, heart-
beat, loopback, jabber, and link integrity functions, as
defined in the standard. An external filter is not required on
the 10BASE-T interface since this is integrated inside the
DP83846A. T his se ct ion foc uses on the gen eral 10 BASE-T
system level operation.
3.4.1 Operational Modes
The DP83846A has two basic 10BASE-T operational
modes:
— Half Duplex mode
— Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83846A functions as a stan-
dard IEEE 802.3 10BASE-T transceiver supporting the
CSMA/CD protocol.
Full Duplex Mode
In Full Duplex mode the DP83846A is capable of simulta-
neously transmitting and receiving without asserting the
collision signal. The DP83846A's 10 Mb/s ENDEC is
designed to encode and decode simultaneously.
3.4.2 Collision Detection and SQE
When in Half Duplex, a 10BASE-T collision is detected
when the receive and transmit channels are active simulta-
neously. Collisions are reported by the COL signal on the
MII. Collisions are also reported when a jabber condition is
detected.
The COL s ignal remain s set for the d uration of the c ollisio n.
If the ENDEC is receiving when a collision is detected it is
reported immediately (through the COL pin).
When heartbeat is enabled, approximately 1 µs after the
transmission of each packet, a Signal Quality Error (SQE)
signal of approximately 10-bit times is generated to indi-
cate successful transmission. SQE is reported as a pulse
on the COL signal of the MII.
The SQE test is in hib ite d when the PH Y is set in ful l dup le x
mode. SQE can also be inhibited by setting the
HEARTBEAT_DIS bit in the 10BTSCR register.
3.4.3 Carrier Sense
Carrier Se ns e (CR S) ma y be ass erted due to rece iv e ac tiv -
ity once valid data is detected via the squelch function.
For 10 Mb/s Half Duplex operation, CRS is asserted during
either packet transmis sion or recepti on.
For 10 Mb/s Full Duplex operation, CRS is asserted only
during receive activity.
CRS is deasserted following an end of packet.
3.4.4 Normal Link Pulse Detection/Generation
The link pulse generator produces pulses as defined in the
IEEE 802.3 10BASE-T standard. Each link pulse is nomi-
nally 100 ns in duration and transmitted every 16 ms in the
absence of transmit data.
Link pulses are used to check the integrity of the connec-
tion with the remote end. If valid link pulses are not
received, the link detector disables the 10BASE-T twisted
pair transmitter, receiver and collision detection functions.
When the link integrity function is disabled
(FORCE_LINK_10 of the 10BTSCR register), good link is
forced and the 10BASE-T transceiver will operate regard-
less of the presence of link pulses.
3.4.5 Jabber Function
The jabber function monitors the DP83846A's output and
disabl es th e trans m itte r if it atte mpts to tr ansmit a pac ke t of
longer than le gal s iz e. A ja bber time r m oni tors th e transmi t-
ter and disables the transmission if the transmitter is active
beyond the Jab time (20-150 ms).
Once disabled by the Jabber function, the transmitter stays
disabled for the entire time that the ENDEC module's inter-
nal transmit enable is asserted. This signal has to be de-
asserted for approximately 250-750 ms (the “unjab” time)
before the Jabber function re-enables the transmit outputs.
The Jabber function is only relevant in 10BASE-T mode.
3.4.6 Automatic Link Polarity D etection and C orrection
The DP83846A's 10BASE-T transceiver module incorpo-
rates an automatic link polarity detection circuit. When
seven consecutive inverted link pulses are received,
inverted polarity is reported.
Obsolete
24 www.national.com
DP83846A
A polar ity reversal ca n be cau sed by a wi ring error a t eith er
end of the cable, usually at the Main Distribution Frame
(MDF) or pat ch panel in t he wiring closet.
The inverse polarity condition is latched in the 10BTSCR
register. The DP83846A's 10BASE-T transceiver module
corrects for this error internally and will continue to decode
received data correctly. This eliminates the need to correct
the wiring error immediately.
The user is cautioned that if Auto Polarity Detection and
Correction is disabled and inverted Polarity is detected but
not corrected, the DsPHYTER may falsely report Good
Link status and allow Transmission and Reception of
inverted data. It is recommended that Auto Polarity Detec-
tion and Correction not be disabled during normal opera-
tion.
3.4.7 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83846A, as the required signal conditioning is inte-
grate d into the devic e.
Only isolation/step-up transformers and impedance match-
ing resistors are required for the 10BASE-T transmit and
receive interface. The internal transmit filtering ensures
that all the harmonics in the transmit signal are attenuated
by at least 30 dB.
3.4.8 Transmitter
The encoder begins operation when the Transmit Enable
input (TX_EN) goes high and converts NRZ data to pre-
emphasized Manchester data for the transceiver. For the
duration of TX_EN, the serialized Transmit Data (TXD) is
encoded for the transmit-driver pair (TD±). TXD must be
valid on the rising edge of Transmit Clock (TX_CLK).
Transmission ends when TX_EN deasserts. The last tran-
sition i s alway s pos itive ; it oc cur s at the cente r of the b it cel l
if the last bit is a one, or at the end of the bit cell if the last
bit is a zero.
3.4.9 Receiver
The decod er co nsi sts of a different ial receiver and a PLL to
separate a Manchester encoded data stream into internal
clock sign al s and dat a. The differential input must be exter-
nally terminated with a differential 100Ω termination net-
work to accommodate UTP cable. The impedance of RD±
(typically 1.1KΩ) is in parallel with the two 54.9Ω resistors
as is shown in Figure 9 below to approximate the 100Ω
termination.
The decod er detect s the en d of a fra me wh en n o add iti ona l
mid-bit transitions are detected. Within one and a half bit
times after the last bit, carrier sense is de-asserted.
3.5 TPI Network Circuit
Figure 9 shows the recommended circuit for a 10/100 Mb/s
twisted pair interface. Below is a partial list of recom-
mended transformers. Is is important that the user realize
that variations with PCB and component characteristics
requires that the application be tested to ensure that the
circuit meets the requirements of the intended application.
Pulse H1012B, PE-68515L
Halo TG22-S052ND
Valor PT4171
BELFUSE S558-5999-K2
BELFUSE S558-5999-46
Figure 9. 10/100 Mb/s Twisted Pair Interface
RJ45
RD-
RD+
TD-
TD+
RD-
RD+
TD-
TD+
1:1
49.9Ω49.9 Ω
0.1µF*
T1
1:1
Common Mode Ch okes may
be requi red.
54.9Ω54.9Ω
0.1µF
0.1µF*
Vdd
* Place capacitors close to
the transformer cen ter tap s
Obsolete
25 www.national.com
DP83846A
3.6 ESD Protection
Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a syst em . In th os e ca ses, st ri ct ha ndl in g p roc ed u res can
be implemented during the manufacturing process to
greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal compo-
nents are usually relatively immune from ESD events.
In the case of an installed Ethernet system however, the
network interface pins are still susceptible to external ESD
events. For example, a category 5 cable being dragged
across a carpet has the potential of developing a charge
well above the typical ESD rating of a semiconductor
device.
For applications where high reliability is required, it is rec-
ommend ed that ad dition al ESD pro tectio n diode s be added
as shown below. There are numerous dual series con-
nected diode pairs that are available specifically for ESD
protection. The l ev el o f pro tec tio n w il l vary dep endent upon
the diode ratings. The primary parameter that affects the
level of ES D prote cti on i s p eak forwa rd surge curre nt. Typi-
cal specifications for diodes intended for ESD protection
range from 50 0m A (M oto rola BAV9 9LT1 single p air diodes )
to 12A (STM DA108S1 Quad pair array). The user should
also select diodes with low input capacitance to minimize
the effect on system performance.
Since performance is dependent upon components used,
board impedance characteristics, and layout, the circuit
should be completely tested to ensure performance to the
required lev el s.
Figure 10. Typical DP83846A Network Interface with additional ESD protection
RJ-45
DP83846A 10/100
TX±
RX±
Vcc
Pin 1
Pin 2
Pin 3
Pin 6
Diodes placed on
the device side of
the isolati o n
transformer
3.3 V Vcc
Vcc
Obsolete
26 www.national.com
DP83846A
3.7 Crystal Oscillator Circuit
The DsPHYTER supports an external CMOS level oscilla-
tor sourc e o r a c rys t a l re son ator devi ce. If an ex ternal cl oc k
source is used, X1 should be tied to the clock source and
X2 should be left floating. In either case, the clock source
must be a 25 MHz 0.005% (50 PPM) CMOS oscillator, or a
25 MHz (50 PPM), parallel, 20 pF load crystal resonator.
Figure 11 below shows a typical connection for a crystal
resonator circuit. The load capacitor values will vary with
the crystal vendors; check with the vendor for the recom-
mended loads.
The oscillator circuit was designed to drive a parallel reso-
nance AT cut crystal with a maximum drive level of 500µW.
If a crystal is specified for a lower drive level, a current lim-
iting resistor should be placed in series between X2 and
the crystal.
As a star ting p oint for evaluat ing an o scillator circui t, if the
requirements for the crystal are not known, CL1 and CL2
should be set at 22 pF, and R1 should be set at 0Ω.
4.0 Re se t Opera ti o n
The DP83846A can be reset either by hardware or soft-
ware. A hardware reset may be accomplished by asserting
the RESET pin after powering up the device (this is
required) or during normal operation when a reset is
needed. A software reset is accomplished by setting the
reset bit in the Basic Mode Control Register.
While either the hardware or software reset can be imple-
mented at any time after device initialization, a hardware
reset, as described in Section 4.1 must be provided upon
device power-up/initialization. Omitting the hardware reset
operation during the device power-up/initialization
sequence can result in improper device operation.
4.1 Hardware Reset
A hardware reset is accomplished by applying a low pulse
(TTL level), with a duration of at least 160 µs, to the
RESET pin during normal operation. This will reset the
device such that all registers will be reset to default values
and the hardware configuration values will be re-latched
into the device (similar to the power-up/reset operation).
4.2 Sof tware Reset
A software reset is accomplished by setting the reset bit
(bit 15) of the Basic Mode Control Register (BMCR). The
period from the point in time when the reset bit is set to the
point in time when software reset has concluded is approx-
imately 160 µs.
The software reset will reset the device such that all regis-
ters wil l be rese t to d efau lt v alu es and the hardwa re co nfi g-
uration values will be re-latched into the device (similar to
the powe r-up/ res et ope rati on). Software dr iver code shoul d
wait 500 µs following a software reset before allowing fur-
ther serial MII operations with the DP83846A.
Figure 11. Crystal Oscillator Circuit
X1 X2
CL2
CL1
R1
Obsolete
27 www.national.com
DP83846A
5.0 Re gist er Block
Table 6. Register Map
Offset Access Tag Description
Hex Decimal
00h 0 RW BMCR Basic Mode Control Register
01h 1 RO BMSR Basic Mode Status Register
02h 2 RO PHYIDR1 PHY Identifier Register #1
03h 3 RO PHYIDR2 PHY Identifier Register #2
04h 4 RW ANAR Auto-Negotiation Advertisement Register
05h 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page)
05h 5 RW ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page)
06h 6 RW ANER Auto-Negotiation Expansion Register
07h 7 RW ANNPTR Auto-Negotiation Next Page TX
08h-Fh 8-15 RESERVED RESERVED
Extended Registers
10h 16 RO PHYSTS PHY Status Registe r
11h-13h 17-19 RESERVED RESERVED
14h 20 RW FCSCR False Carrier Sense Counter Register
15h 21 RW RECR Receive Error Counter Register
16h 22 RW PCSR PCS Sub-Layer Configuration and Status Register
17h 23 RW RESERVED RESERVED
18h 24 RW RESERVED RESERVED
19h 25 RW PHYCTRL PHY Control Register
1Ah 26 RW 10BTSCR 10Base-T Status/Control Register
1Bh 27 RW CDCTRL CD Test Control Register
1Ch-1Fh 28 RW RESERVED RESERVED
Obsolete
28 www.national.com
DP83846A
Reg is ter Na me Add r Ta g Bit 15 Bit 14 Bit 1 3 Bit 12 Bit 1 1 Bit 1 0 Bit 9 Bit 8 Bit 7 Bit 6 Bi t 5 Bit 4 Bit 3 Bi t 2 Bit 1 Bit 0
Basic Mode Control Register 00h BMCR Reset Loopb ack Speed Se-
lect Auto-Neg
Enable Power
down Isolate Restart
Auto-Neg Duplex Collision
Test Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Basic Mode Status Register 01h BMSR 100Base-
T4 100Base-
TX FDX 100Base-
TX HDX 10Base-
T
FDXx
10Base-
T
HDX
Reserved Reserved Reserved Reserved MF Pre-
amble
Suppress
Auto-Neg
Complete Remote
Fault Auto-Neg
Ability Link
Status Jabber
Detect Extended
Capability
PHY Identifier Register 1 02h PHYIDR1 OUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSBOUI MSB
PHY Identifier Register 2 03h PHY IDR2 OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB VNDR_
MDL VNDR_
MDL VNDR_
MDL VNDR_
MDL VNDR_
MDL VNDR_
MDL MDL_
REV MDL_
REV MDL_
REV MDL_
REV
Auto-Negotiation Advertisement Register 04h ANAR Next Page
Ind Reserved Remote
Fault Reserved Reserved PAUSE T4 TX_FD TX 10_FD 10 Protocol
Selection Protocol
Selection Protocol
Selection Protocol
Selection Protocol
Selection
Auto-Negotiation Link Partner Ability Regis-
ter (Base Page) 05h ANLPAR Next Page
Ind ACK Remote
Fault Reserved Reserved Reserved T4 TX_FD TX 10_FD 10 Protocol
Selection Protocol
Selection Protocol
Selection Protocol
Selection Protocol
Selection
Auto-Negotiation Link Partner Ability Regis-
ter Next Page 05h ANLPARNP Next Page
Ind ACK Message
Page ACK2 Toggle Code Code Code Code Code Code Code Code Code Code Code
Auto-Negotiation Expansion Register 06h ANER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PDF LP_NP_
ABLE NP_
ABLE PAGE_
RX LP_AN_
ABLE
Auto-Negotiation Next Page TX Register 07h ANNPTR Next Page
Ind Reserved Message
Page ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE
RESERVED 08-0fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
EXTENDED REGISTERS
PHY Status Register 10h PHY STS Reserve d Reserv ed Rx Err
Latch Polarity
Status False Car-
rier Sense Signal De-
tect Descram
Lock Page
Receive Reserved Remote
Fault Jabber
Detect Auto-Neg
Complete Loopback
Status Duplex
Status Speed
Status Link
Status
RESERVED 11-13h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
False Carrier Sense Counter Register 14h FCSCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT
Receive Error Counter Register 15h RECR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RXER-
CNT RXER-
CNT RXER-
CNT RXER-
CNT RXER-
CNT RXER-
CNT RXER-
CNT RXER-
CNT
PCS Sub-Layer Configura tion and Status
Register 16h PCSR Reserved Reserved Reserved BYP_
4B5B FREE_
CLK TQ_EN SD_FOR
CE_PMA SD_
OPTION Unused Reserved FORCE_
100_OK Reserved Reserved NRZI_
BYPASS SCRAM_
BYPASS DE
SCRAM_
BYPASS
RESERVED 17-18h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PHY Control Register 19h PHYCTRL Unused Unused Unused Unused PSR_15 BIST_
STATUS BIST_
START BP_
STRETC
H
PAUSE_
STS LED_
CNFG LED_
CNFG PHY
ADDR PHY
ADDR PHY
ADDR PHY
ADDR PHY
ADDR
10Base-T Status/Control Register 1Ah 10BTSCR Unused Unused Unused Unused Unused Unused Unused Loopback
_10_dis LP_DIS Force_
Link_10 Force_
Pol_Cor Polarity Autopol
_Dis Reserved Hrtbeat
_Dis Jabber
_Dis
CD Test Control Register 1Bh CDCTRL CD_Enabl
eDCD_
Comp FIL_TTL rise-
Time[1] rise-
Time[0] fallTime[1] fallTime[0] cdTestEn Reserved Reserved Reserved cdPattEn_
10 cdPatEn_
100 10meg_
patt_gap cdPatt-
Sel[1] cdPatt-
Sel[0]
RESERVED 1C-1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Obsolete
29 www.national.com
DP83846A
5.1 Reg ister Definition
In the register definitions under the ‘Default’ heading, the following definitions hold true:
—RW=Read Write access
—SC=Register sets on event occurrence and Self-Clears when event ends
—RW/SC =Read Write access/Self Clearing bit
—RO=Read Only access
—COR = Clear on Read
—RO/COR=Read Only, Clear on Read
—RO/P=Read Only, Permanent ly se t to a default val ue
—LL=Latched Low and held until read, based upon the occurrence of the corresponding event
—LH=Latched High and held until read, based upon the occurrence of the corresponding event
Obsolete
30 www.national.com
DP83846A
Table 7. Basic Mode Control Register (BMCR), Address 0x00
Bit Bit Name Default Description
15 Reset 0, RW/SC Reset:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit, which is self-clearing, returns a value of one until the reset process is
complete. The configuration is re-strapped.
14 Loopback 0, R W Loopback:
1 = Loopback enabled.
0 = Normal operation.
The loopback function enables MII transmit data to be routed to the MII receive
data path.
Setting this bi t may cau se the descramble r to lose synchron ization and prod uce a
500 µs “dead time” before any valid data will appear at the MII receive outputs.
13 Speed Selection Strap, RW Speed Select:
When auto-n egotiatio n is disabled writing to th is bit allows th e port speed to be se-
lected.
1 = 100 Mb/s.
0 = 10 Mb/s.
12 Auto-Negotiation
Enable Strap, RW Auto-Negotiation Enable:
Strap controls initial value at reset.
1 = Auto-Negoti ation Enabled - bits 8 and 13 of this regi ster are ignored when this
bit is set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex
mode.
11 Po wer Down 0, RW Power Down:
1 = Power down.
0 = Normal operation.
Setting this bit powers down the PH Y. Only the regis ter block is enable d during a
power down condition.
10 Isolate 0, RW Isolate:
1 = Isolates the Port from the MII with the exception of the serial management.
0 = Normal operation.
9 Restart Auto-
Negotiation 0, RW/SC Restart Auto-Negotiation:
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-
Negotiat ion is di sa ble d (bit 12 = 0), this bit is ig nore d. This b it i s sel f-c lea r ing an d
will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-
clear. Operation of the Auto-Negotiation process is not affected by the manage-
me nt ent ity clearing this b it.
0 = Normal operation.
8 Du plex Mode St rap, RW Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port Duplex capa-
bility to be selec ted .
1 = Full Duplex operation.
0 = Half Duplex operation.
7 Collisi on Tes t 0, RW Collision Test:
1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL signal to be asserted in response to the as-
sertion of TX_EN within 512-bit times. The COL signal will be de-asserted within
4-bit times in response to the de-assertion of TX_EN.
6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.
Obsolete
31 www.national.com
DP83846A
Table 8. Basic Mode Status Register (BMSR), address 0x01
Bit Bit Name Default Description
15 100BASE-T4 0, RO/P 100BASE-T4 Capable:
0 = Device not able to perform 100BASE-T4 mode.
14 100BASE-TX
Full Duplex 1, RO/P 100BASE-TX Full Duplex Capable:
1 = Device able to perform 100BASE-TX in full duplex mode.
13 100BASE-TX
Half Duplex 1, RO/P 1 00BASE-TX Half Duplex Capa ble:
1 = Device able to perform 100BASE-TX in half duplex mode.
12 10BASE-T
Full Duplex 1, RO/P 10BASE-T Full Duplex Capable:
1 = Device able to perform 10BASE-T in full duplex mode.
11 10BASE-T
Half Duplex 1, RO/P 10BASE-T Half Duplex Capable:
1 = Device able to perform 10BASE-T in half duplex mode.
10:7 RESERVED 0, RO RESERVED: Write as 0, read as 0.
6MF Preamble
Suppression 1, RO/P Preamble suppression Capable:
1 = Device able to perform management transaction with preamble
suppressed, 32-bits of preamble needed only once after reset, invalid
opcode or inval id turna rou nd.
0 = Normal management operation.
5 Auto-Negotiation
Complete 0, RO Auto-Negotiation Complete:
1 = Auto-Negotiation process complete.
0 = Auto-Negotiation process not complete.
4 Remote Fault 0, RO/LH Remote Fault:
1 = Remote Fault condition detected (cleared on read or by reset).
Fault criteria: Far End Fault Indication or notification from Link Part-
ner of Remote Fault.
0 = No remote fault condition detected.
3 Auto-Negotiation
Ability 1, RO/P Auto Negotiation Ability:
1 = Device is able to perform Auto-Negotiation.
0 = Device is not able to perform Auto-Negotiation.
2 Link Status 0, RO/LL Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not establishe d.
The criteria for link validity is implementation specific. The occurrence
of a link fai lure conditio n will causes the Link Status bit to clear. Once
cleared, this bit m ay o nly be s et by esta blishing a g ood l ink condi tion
and a read via the management interface.
1 Jabber Detect 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode.
1 = Jabber condition detected.
0 = No Jabber.
This bit is implemented with a latching function, such that the occur-
rence of a jabb er condition ca uses it to se t until it is cleare d by a read
to this register by the management interface or by a reset.
0 Extended Capa bil i-
ty 1, RO/P Extended Capability:
1 = Extended register capabilities.
0 = Basic register set capabilities only.
Obsolete
32 www.national.com
DP83846A
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83846A. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num-
ber. A PHY may r etur n a val ue of z ero in eac h of th e 32 bi ts of the PHY Ide ntifier if desired . The PHY I den tifier i s intende d
to support network management. National's IEEE assigned OUI is 080017h.
Table 9. PHY Identifier Register #1 (PHYIDR1), address 0x02
Bit Bit Name Default Description
15:0 OUI_MSB <0010 0000 0000
0000>, RO/P OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are
stored in bits 15 to 0 of this register. The most significant two bits
of the OUI are ig nored (th e IEEE standar d refe rs to these as bit s 1
and 2).
Table 10. PHY Identifier Register #2 (PHYIDR2), address 0x03
Bit Bit Name Default Description
15:10 OUI_LSB <01 0111>, RO/P OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080017h) are mapped to bits 15 to 10 of
this register respectively.
9:4 VNDR_MDL < 00 0010>, RO/P Vendor Model Number:
The six bits of vendor model number are mapped to bits 9 to 4
(most significant bit to bit 9).
3:0 MDL_REV <0011>, RO/P Model Revision Number:
Four bits of the vendor model revision number are mapped to bits
3 to 0 (m ost signifi cant bit to bit 3). This field will b e increment ed for
all major device changes.
Obsolete
33 www.national.com
DP83846A
This reg ister c ont ains the ad vertis ed abi lities of thi s dev ice a s they w ill b e trans mitted to it s link pa rtne r during Auto-N ego-
tiation.
Table 11. Auto-Negotiation Advertisement Register (ANAR), address 0x04
Bit Bit Name Default Description
15 NP 0, RW Next Page Indication:
0 = Next Page Tr ansfer not desired.
1 = Ne xt Page Transfer desired.
14 RESERVED 0, RO/P RESERVED by IEEE: Writes ignored, Read as 0.
13 RF 0, RW Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
12:11 RESERVED 0, RW RESERVED for Future IEEE use: Write as 0, Read as 0
10 PAUSE Strap, RW PAUSE: The default is set by the strap option for PAUSE_EN pin.
1 = Advertise that the DTE (MAC) has implemented both the op-
tional MAC con trol su blaye r an d the p ause fu nctio n as spec if ied in
clause 31 and annex 31B of 802.3u.
0= No MAC based full duplex flow control.
9 T4 0 , RO/P 100BASE-T4 Support:
1= 100BASE-T4 is supported by the local device.
0 = 100BASE-T4 not supported.
8 TX_FD Strap, RW 100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the local device.
0 = 100BASE-TX Full Duplex not supported.
7 TX Strap, RW 100BASE-TX Support:
1 = 100BASE-TX is supported by the local device.
0 = 100BASE-TX not supported.
6 10_FD Strap, RW 10BASE-T Full Duplex Support:
1 = 10BASE-T Full Duplex is supported by the local device.
0 = 10BASE-T Full Duplex not supported .
5 10 Strap, RW 10BASE-T Support:
1 = 10BASE-T is supported by the local device.
0 = 10BASE-T not supported.
4:0 Selector <00001>, RW Protocol Selection Bits:
These bi ts c ontain the binary enc oded protoco l se lector supp orted
by this port. <00001> indicates that this device supports IEEE
802.3u.
Obsolete
34 www.national.com
DP83846A
This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content
changes after the successful auto negotiation if Next-pages are supported.
Table 12. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05
Bit Bit Name Default Description
15 NP 0, RO Next Page Indication:
0 = Link Partner does not desire Next Page Transfer.
1 = Link Partner desires Next Page Transfer.
14 ACK 0, RO Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Device's Auto-Negotiation state machine will automatically
control the this bit based on the incoming FLP bursts.
13 RF 0, RO Remote Fault:
1 = Remote Fault indicated by Link Partner.
0 = No Remote Fault indicated by Link Partner.
12:10 RESERVED 0, RO RESERVED for Future IEEE use:
Write as 0, read as 0.
9T4 0, RO100BASE-T4 Support:
1 = 100BASE-T4 is supported by the Link Partner.
0 = 100BASE-T4 not supported by the Link Partner.
8TX_FD 0, RO100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the Link Partner.
0 = 100BASE-TX Full Duplex not supported by the Link Partner.
7TX 0, RO100BASE-TX Support:
1 = 100BASE-TX is supported by the Link Partner.
0 = 100BASE-TX not supported by the Link Partner.
6 10_FD 0, RO 10BASE-T Full Duplex Support:
1 = 10BASE-T Full Duplex is supported by the Link Partner.
0 = 10BASE-T Full Duplex not supported by the Link Partner.
510 0, RO10BASE-T Support:
1 = 10BASE-T is supported by the Link Partner.
0 = 10BASE-T not supported by the Link Partner.
4:0 Selector <0 0000>, RO Protocol Selection Bits:
Link Partner’s binary encoded protocol selector.
Obsolete
35 www.national.com
DP83846A
This register contains additional Local Device and Link Partner status information.
Table 13. Auto-Negotiation Link Partner Ability Register (ANLPAR) Next Page, address 0x05
Bit Bit Name Default Description
15 NP 0, RO Next Page Indication:
1 = Link Partner desires Next Page Transfer.
0 = Link Partner does not desire Next Page Transfer.
14 ACK 0, RO Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Device's Auto-Negotiation state machine will automatically
control the this bit based on the incoming FLP bursts. Software
should not attempt to write to this bit.
13 MP 0, RO Message Page:
1 = Message Page.
0 = Unformatted Page.
12 ACK2 0, RO Acknowledge 2:
1 = Link Part ner d oes hav e the abi lity to c omp ly to nex t pa ge m es -
sage.
0 = Link Partner does not have the ability to comply to next page
message.
11 Toggle 0, RO Toggle:
1 = Previous value of the transmitted Link Code word equalled 0.
0 = Previous value of the transmitted Link Code word equalled 1.
10:0 CODE <000 0000 0000>,
RO Code:
This field represents the code field of the next page transmission.
If the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a “Message Page”, as defined in annex 28C of
Clause 28. Otherwise, the code shall be interpreted as an “Unfor-
matted Page”, and the interpretation is application specific.
Table 14. Auto-Negotiate Expansion Register (ANER), address 0x06
Bit Bit Name Default Description
15:5 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.
4 PDF 0, RO/LH/COR Parallel Detection Fault:
1 = A fault has been detected via the Parallel Detection function.
0 = A fault has not been detected.
3 LP_NP_ABLE 0, RO Link Partner Next Page Able:
1 = Link Partner does support Next Page.
0 = Link Partner does not support Next Page.
2 NP_ABLE 1, RO/P Next Page Able:
1 = Indicates local device is able to send additional “Next Pages”.
1 PAGE_RX 0, RO/LH/COR Link Code Word Page Received:
1 = Link Code Word has been received, cleared on a read.
0 = Link Code Word has not been received.
0 LP_AN_ABLE 0, RO Link Partner Auto-Negotiation Able:
1 = indicates that the Link Partner supports Auto-Negotiation.
0 = indicates that the Link Partner does not support Auto-Negotia-
tion.
Obsolete
36 www.national.com
DP83846A
This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.
Table 15. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07
Bit Bit Name Default Description
15 NP 0, RW Next Page Indication:
0 = No other Next Page Transfer desired.
1 = Another Next Page desired.
14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
13 MP 1, RW Message Page:
1 = Message Page.
0 = Unformatted Page.
12 ACK2 0, RW Acknowledge2:
1 = Will comply with message.
0 = Cannot comply with message.
Acknowledge2 is used by the next page function to indicate tha t Lo-
cal Device has the ability to comply with the message received.
11 TOG_TX 0, RO Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word
was 0.
0 = Value of toggle bit in previously transmitted Link Code Word
was 1.
Toggle is used by the Arbitration function within Auto-Negotiation
to ensure synchronization with the Link Partner during Next Page
exchang e. This bi t shall alwa ys tak e the oppo si te valu e of the Tog -
gle bit in the previously exchanged Link Code Word.
10:0 CODE <000 0000 0001>,
RW This field represents the code field of the next page transmission.
If the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a "Messag e Page”, as defin ed in annex 28C of IEEE
802.3u. Otherwise, the code shall be interpreted as an "Unformat-
ted Page”, and the interpretation is application specific.
The default value of the CODE represents a Null Page as defined
in Annex 28C of IEEE 802.3u.
Obsolete
37 www.national.com
DP83846A
5.2 Extended Registers
This register provides a single location within the register set for quick access to commonly accessed information.
Table 16. PHY Status Register (PHYSTS), address 0x10
Bit Bit Name Default Description
15:14 RESERVED 0, RO RESERVED: Write ignored, read as 0.
13 Receive Error Latch 0, RO/LH Receive Error Latch:
This bit will be cleared upon a read of the RECR register.
1 = Rec eive error eve nt has oc curred si nce last read of RXER CNT
(address 0x15, Page 0).
0 = No receive error event has occurred.
12 Polarity Status 0, RO Polarity Status:
This bit is a duplication of bit 4 in the 10BTSCR register. This bit will
be cleared upon a read of the 10BTSCR register, but not upon a
read of the PHY STS regis ter.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
11 False C arrier Sense
Latch 0, RO/LH False Carri er Sense Latc h:
This bit will be cleared upon a read of the FCSR register.
1 = False Carrier event h as occurred since last read of FCSCR (ad -
dress 0x14).
0 = No False Carrier event has occurred.
10 Signal Detect 0, RO/LL 100Base-TX unconditional Signal Detect from PMD.
9 Descrambler Lock 0, RO/LL 100Base-TX Descrambler Lock from PMD.
8 Page Receiv ed 0, RO Link Code Word Page Received:
This is a duplicate of the Page Received bit in the ANER register,
but this bit w ill no t be cl ea red u po n a read of the PH YSTS re gis te r.
1 = A new Link Code Word Page has been received. Cleared on
read of the ANER (address 0x06, bit 1).
0 = Link Code Word Page has not been received.
Obsolete
38 www.national.com
DP83846A
7 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.
6 Remote Fault 0, RO Remote Fault:
1 = Remot e Fault condition detected (cl eared on read of BMSR (ad-
dress 01h) reg ister or by reset). Fault c riteria: notifica tion from Link
Partner of Remote Fault via Auto-Negotiation.
0 = No remote fault condition detected.
5 Jabber Detect 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode
This bit is a dupl icate of the Jabber De tect bit in the BMSR register,
except that it is not cleared upon a read of the PHYSTS register.
1 = Jabber condition detected.
0 = No Jabber.
4 Auto-Neg Comp lete 0, RO Auto-Negotiation Complete:
1 = Auto-Negotiation complete.
0 = Auto-Negotiation not complete.
3 Loopback Status 0, RO Loopback:
1 = Loopback enabled.
0 = Normal operation.
2 Duplex Status 0, RO Duplex:
This bit indi cates dupl ex status and is determined fro m Auto-Nego-
tiation or Forced Modes.
1 = Full duplex mode.
0 = Half duplex mode.
Note: This bit is only valid if Auto-Negotiation is enabled and com-
plete and th ere is a v alid li nk or if Au to-Negoti ation i s disa bled an d
there is a valid link.
1 Speed Status 0, RO Speed10:
This bit indicates the status of the speed and is determined from
Auto-Negotiation or Forced Modes.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
Note: This bit is only valid if Auto-Negotiation is enabled and com-
plete and th ere is a v alid li nk or if Au to-Negoti ation i s disa bled an d
there is a valid link.
0 Link Status 0, RO Link Status:
This bit is a duplicate of the Link Status bit in the BMSR register,
except that it will no be cleared upon a read of the PHYSTS regis-
ter.
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
Table 16. PHY Status Register (PHYSTS), address 0x10 (Continued)
Bit Bit Name Default Description
Obsolete
39 www.national.com
DP83846A
This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object
class of Clause 30 of the IEEE 802.3u specification.
This counter provides information required to implement the “SymbolErrorDuringCarrier” attribute within the PHY man-
aged object class of Clause 30 of the IEEE 802.3u specification.
Table 17. False Carrier Sense Counter Register (FCSCR), address 0x14
Bit Bit Name Default Description
15:8 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.
7:0 FCSCNT[7:0] 0, RW / COR False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This
counter sticks when it reaches its max count (FFh).
Table 18. Receiver Error Counter Register (RECR), address 0x15
Bit Bit Name Default Description
15:8 RESERVED 0, RO RESERVED: Writes ignored, Read as 0
7:0 RXERCNT[7:0] 0, RW / COR RX_ER Counter:
This 8-bit counter increments for each receive error detected.
When a v alid carr ier is present and there is at least o ne occurrenc e
of an invalid data symbo l. Thi s event can incre me nt on ly on ce per
valid carrier event. If a collision is present, the attribute will not in-
crement. The counter sticks wh en it reache s its max count.
Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16
Bit Bit Name Default Description
15:13 RESERVED <00>, RO RESERVED: Writes i gnor ed, Read as 0.
12 BYP_4B5B 0, RW Bypass 4B/5B Encoding:
1 = 4B5B encoder functio ns by pas se d.
0 = Normal 4B5B operation.
11 FREE_CLK 0, RW Receive Clock:
1 = RX_CK is free-running.
0 = RX_CK phase adjusted based on alignment.
10 TQ_EN 0, RW 100Mbs True Quiet Mode Enable:
1 = Transmit True Quiet Mode.
0 = Normal Transmit Mod e.
9 SD FORCE PMA 0,RW Signal Detect Force PMA:
1 = Forces Signal Detection in PMA.
0 = Normal SD operation.
8 SD_OPTION 1, RW Signal Detect Option:
1 = Enhanced signal detect algorithm.
0 = Reduced signal detect algorithm.
Obsolete
40 www.national.com
DP83846A
7Unused 0,RO
6 RESERVED 0 RESERVED:
Must be zero.
5 FORCE_100_OK 0, RW Force 100Mb/s Good Link:
1 = Forces 100Mb/s Good Link.
0 = Normal 100Mb /s ope ratio n.
4 RESERVED 0 RESERVED:
Must be zero.
3 RESERVED 0 RESERVED:
Must be zero.
2 NRZI_BYPASS 0, RW NRZI Bypass Enable:
1 = NRZI Bypass Enabled.
0 = NRZI Bypass Disabled.
1 SCRAM_BYPASS 0, RW Scrambler Bypass Enable :
1 = Scrambler Byp as s Enabl ed.
0 = Scrambler Bypass Disabled.
0 DESCRAM_BYPA
SS 0, RW Descrambler Bypass Enable:
1 = De scra mbler Bypass Enabled.
0 = De scra mbler Bypass Disabled.
Table 20. Reserved Registers, addresses 0x17, 0x18
Bit Bit Name Default Description
15:0 RESERVED none, RW RESERVED: Must not be written to during normal operation.
Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (Continued)
Bit Bit Name Default Description
Obsolete
41 www.national.com
DP83846A
Table 21. PHY Control Register (PHYCTRL), address 0x19
Bit Bit Name Default Description
15:12 Unused 0, RO
11 PSR_15 0, RW BIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
10 BIST_STATUS 0, RO/LL BIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared by write to BIST_ START bit.
9 BIST_START 0, RW BIST Start:
1 = BIST start.
0 = BIST stop.
8 BP_STRETCH 0, RW Bypass LED Stretching:
This will bypass the LED stretching for the Receive, Transmit and
Collision LEDs.
1 = Bypass LED stretchi ng.
0 = Normal operation.
7 PAUSE_STS 0, RO Pause Compare Status:
0 = Local Device and the Link Partner are not Pause capable.
1 = Local Device and the Link Partner are both Pause capable.
6 RESERVED 1, RO/P Reserved: Must be 1.
5 LED_CNFG Strap, RW This bit is used to b ypass the sel ective inv ersion on t he LED output
for DPLX - this enables its use in non-LED applications.
Mode Description
1 = Led polarity adjusted - DPLX selected.
0 = DPLX active HIGH.
4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port.
Obsolete
42 www.national.com
DP83846A
Table 22. 10Base-T Status/Control Register (10BTSCR), Address 0x1A
Bit Bit Name Default Description
15:9 Unused 0, RO
8 LOOPBACK_10_DIS 0, RW 10BASE-T Loopback Disable:
If bit 14 (Loopback) in the BMCR is 0:
1 = 10 Mb/s Loopback is disabled.
If bit 14 (Loopback) in the BMCR is 1:
1 = 10 Mb/s Loopback is enabled.
7 LP_DIS 0, RW Normal Link Pulse Disable:
1 = Transmission of NLPs is disabled.
0 = Transmission of NLPs is enabled.
6 FORCE_LINK_10 0, RW Force 10Mb Good Link:
1 = Forced Good 10Mb Link.
0 = Normal Link Status.
5 F ORCE_POL_COR 0, RW Force 10Mb Polarity Correction:
1 = Force inverted polarity.
0 = Normal polarity.
4POLARITYRO/LH10Mb Polarity Status:
This bit is a duplication of bit 12 in the PHYSTS register. Both bits
will be cleared upon a read of 10BTSCR register, but not upon a
read of the PHYSIS register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
3 AUTOPOL_DIS 0, RW Auto Polarity Detection & Correction Disable:
1 = Polarity Sense & Correction disabled.
0 = Polarity Sense & Correction enabled.
2 RESERVED 1, RW RESERVED:
Must be set to one.
1 HEARTBEAT_DIS 0, RW Heartbeat Disable: This bit only has influence in half-duplex 10Mb
mode.
1 = Heartbeat function disabled.
0 = Heartbeat function enabled.
When the device is operating at 100Mb or configured for full
duplex operation, this bit will be ignored - the heartbeat func-
tion is disabled.
0 JABBER_DIS 0, RW Jabber Disable:
Applicable only in 10BASE-T.
1 = Jabber function disabled.
0 = Jabber function enabled.
Obsolete
43 www.national.com
DP83846A
Table 23. CD Test Register (CDCTRL), Address 0x1B
Bit Bit Name Default Description
15 CD_ENABLE 1, RW CD Enable:
1 = CD Enabled - power-down mode, outputs high impedance.
0 = CD Disabled.
14 DCDCOMP 0, RW Duty Cycle Distortion Compensation:
1 = Increases the amount of DCD compensation.
13 FIL_TTL 0, RW Wavesh ape r Current Sour ce Tes t:
To check ability of waveshaper current sources to switch on/off.
1 = Test mode; waveshaping is done, but the output is a square
wave. All sources are either on or off.
0 = Normal mode; sin usoidal.
12 RESERVED none, RW Reserved: This bit should be written with a 0 if write access is re-
quired on this register.
11 RISETIME Strap, RW CD Rise Time Control:
10 RESERVED none, RW Reserved: This bit should be written with a 0 if write access is re-
quired on this register.
9 FALLTIME Strap, RW CD Fall Time Control:
8 CDTESTEN 0, RW CD Test Mode Enable:
1 = Enable CD test mode - differs based on speed of operation
(10/100Mb).
0 = Normal operation.
7:5 RESERVED[2:0] 000, RW RESERVED:
Must be zero.
4 CDPATTEN_10 0, RW CD Pattern Enable for 10meg:
1 = Enabled.
0 = Disabled.
3 CDPATTEN_100 0, RW CD Pattern Enable for 100meg:
1 = Enabled.
0 = Disabled.
2 10MEG_PATT_GAP 0, RW Defines gap between data or NLP test sequences:
1 = 15 µs.
0 = 10 µs.
1:0 CDPATTSEL[1:0] 00, RW CD Pattern Select[1:0]:
If CDPATTEN_100 = 1:
00 = All 0’s (True quiet)
01 = All 1’s
10 = 2 1’s, 2 0’s repeating pattern
11 = 14 1’s, 6 0’s repeating pattern
If CDPATTEN_10 = 1:
00 = Data, EOP0 sequence
01 = Data, EOP1 sequence
10 = NLPs
11 = Con stant Manch ester 1s (1 0mhz si ne wave) fo r harmonic dis-
tortion testing.
Obsolete
44 www.national.com
DP83846A
6.0 Elect rica l Speci fications
Absolute Maximum Ratings Recommended Operating Conditions
Absolute maximum ratings are those values beyond which
the safety of the device cannot be guaranteed. They are
not meant to imply that the device should be operated at
these limits.
Note:0 DC Electrical Specification
Supply Voltage (VCC) -0.5 V to 4.2 V
DC Input Voltage (VIN) -0.5V to 5.5V
DC Output Voltage (VOUT) -0.5V to 5.5V
Storage Temperature (TSTG)-65oC to 150°C
Lead Temp. (TL)
(Soldering, 10 sec) 260°C
ESD Rating
(RZAP = 1.5k, CZAP = 120 pF) 1.0 kV
Supply voltage (VCC) 3.3 Volts + 0.3V
Ambient Temperature (TA)0 to 70 °C
Max. die temperature (Tj) 107°C
Max case temp 96°C
Thermal Characteristic Max Units
Theta Junction to Case (Tjc)15 °C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - No Airflow @ 1.0W 51 °C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - 225 LFPM Airflow @ 1.0W 42 °C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - 500 LFPM Airflow @ 1.0W 37 °C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - 900 LFPM Airflow @ 1.0W 33 °C / W
Symbol Pin Types Parameter Conditions Min Typ Max Units
VIH I
I/O Input High Voltage Nominal VCC 2.0 V
VIL I
I/O Input Low V oltage 0.8 V
IIH I
I/O Input High Cur rent VIN = VCC 10 µA
IIL I
I/O Input Low Current VIN = GND 10 µA
VOL O,
I/O Output Low
Voltage IOL = 4 mA 0.4 V
VOH O,
I/O Output H igh
Voltage IOH = -4 mA VCC - 0.5 V
VledOL LED Output Low
Voltage * IOL = 2.5 mA 0.4 V
VledOH LED Output High
Voltage IOH = -2.5 mA VCC - 0.5 V
IOZH I/O,
OTRI-STATE
Leakage VOUT = VCC 10 µA
I5IH I/O,
O5 Volt Tolerant
MII Leakage VIN = 5.25 V 10 µA
I5OZH I/O,
O5 Volt Tolerant
MII Leakage VOUT = 5.25 V 10 µA
RINdiff RD+/− Differential Input
Resistance 1.1 kΩ
VTPTD_100 TD+/− 100M Transmit
Voltage .95 1 1.05 V
Obsolete
45 www.national.com
DP83846A
Note: For Idd Measurements, outputs are not loaded.
VTPTDsym TD+/− 100M Transmit
Voltage Sym metry ±2%
VTPTD_10 TD+/− 10M Transmit
Voltage 2.2 2.5 2.8 V
CIN1 I CMOS Input
Capacitance Parameter is not
100% tested 8pF
SDTHon RD+/− 100BASE-TX
Signal detect turn-
on threshold
1000 mV diff pk-pk
SDTHoff RD+/− 100BASE-TX
Signal detect turn-
off threshold
200 mV diff pk-pk
VTH1 RD+/− 10BASE-T Re-
ceive Threshold 300 585 mV
Idd100 Supply 100BASE-TX
(Full Duplex) IOUT = 0 mA
See Note
150 200 mA
Idd10 Supply 10BASE-T
(Full Duplex) IOUT = 0 mA
See Note
100 130 mA
Symbol Pin Types Parameter Conditions Min Typ Max Units
Obsolete
46 www.national.com
DP83846A
6.1 Reset Timing
Note1: Software Reset should be initiated no sooner then 500 µs after power-up or the deassertion of hardware reset.
Note2: It is im portan t to choo se pull-u p and/or pull-dow n resisto rs for each of the hardware confi guration pins that prov ide
fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
Parameter Description Notes Min Typ Max Units
T1.0.1 Post RESET Stabilization time
prior to MDC preamble for regis-
ter accesses
MDIO is pulled high for 32-bit se-
rial management initialization 3µs
T1.0.2 Hardware Configuration Latch-in
Time from the De asser tion of R E-
SET (either soft or hard)
Hardware Co nfig ura t ion Pins are
describ ed in the Pin De sc rip tio n
section
3µs
T1.0.3 Hardware Configuration pins
transit ion to output driv ers 3.5 µs
T1.0.4 RESET pulse width X1 Clock must be stable for a
minimum of 160us during RESET
pulse low time.
160 µs
VCC
HARDWARE
RSTN
MDC
32 CLOCKS
Latch-In of Hardware
Configuration Pins
Dual Function Pins
Become Enabled As Outputs
INPUT OUTPUT
T1.0.3
T1.0.2
T1.0.1
T1.0.4
X1 Clock
Obsolete
47 www.national.com
DP83846A
6.2 PGM Clock Timing
6.3 MII Serial Management Timing
Parameter Description Notes Min Typ Max Units
T2.0.1 TX_CLK Duty Cycle 35 65 %
Parameter Description Notes Min Typ Max Units
T3.0.1 MDC to MDIO (Output) Delay Time 0 300 ns
T3.0.2 MDIO (Input) to MDC Setup Time 10 ns
T3.0.3 MDIO (Input) to MDC Hold Time 10 ns
T3.0.4 MDC Frequency 2.5 MHz
TX_CLK
X1
T2.0.1
MDC
MDC
MDIO (output)
MDIO (input) Valid Data
T3.0.1
T3.0.2 T3.0.3
T3.0.4
Obsolete
48 www.national.com
DP83846A
6.4 100 Mb/s Timing
6.4.1 100 Mb/s MII Transmit Timing
6.4.2 100 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T4.1.1 TXD[3:0], TX_EN, TX_ER Data Setup to
TX_CLK 10 ns
T4.1.2 TXD[3:0], TX_EN, TX_ER Data Hold from
TX_CLK 5ns
Parameter Description Notes Min Typ Max Units
T4.2.1 RX_CLK Duty Cycle 35 65 %
T4.2.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 10 30 ns
TX_CLK
TXD[3:0]
TX_EN
TX_ER Valid Data
T4.1.1 T4.1.2
RX_CLK
RXD[3:0]
RX_DV
RX_ER Valid Data
T4.2.2
T4.2.1
Obsolete
49 www.national.com
DP83846A
6.4.3 100BASE-TX Transmit Packet Latency Timing
Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the TD± pins.
6.4.4 100BASE-TX Transmit Packet Deassertion Timing
Note: Deassertio n i s d ete rmi ned by m eas uri ng the tim e from the firs t ri si ng e dg e of TX_CL K oc cu rrin g after the deass er-
tion of TX_EN to the first bit of the “T” code group as output from the TD± pins.
Parameter Description Notes Min Typ Max Units
T4.3.1 TX_CLK to TD± Latenc y 6.0 bit ti mes
Parameter Description Notes Min Typ Max Units
T4.4.1 TX_CLK to TD± Deassertio n 6.0 bit times
TX_CLK
TX_EN
TXD
TD±(J /K) IDLE DATA
T4.3.1
TX_CLK
TXD
TX_EN
TD±(T/R) DATA IDLE
T4.4.1
(T/R) DATA IDLE
Obsolete
50 www.national.com
DP83846A
6.4.5 100BASE-TX Transmit Timing (tR/F & Jitter)
Note1: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
Note2: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude.
Parameter Description Notes Min Typ Max Units
T4.5.1 100 Mb/s TD± tR and tF 345ns
100 Mb/s tR and tF Mismatch 500 ps
T4.5.2 100 Mb/s TD± Transmit Jitter 1.4 ns
TD±
T4.5.1
T4.5.1
T4.5.1
T4.5.1
+1 rise
+1 fall
-1 fall -1 rise
TD±
eye patt ern
T4.5.2
T4.5.2
90%
10% 10%
90%
Obsolete
51 www.national.com
DP83846A
6.4.6 100BASE-TX Receive Packet Latency Timing
Note: Carrier Se nse On Delay is de termin ed by meas uring the ti me fro m the first b it of the “J” code group to the asse rtion
of Carrier Sense.
Note: RD± voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
6.4.7 100BASE-TX Receive Packet Deassertion Timing
Note: Carrier Sense Of f Delay is de termined by measurin g the ti me from the fir st bit o f the “T” c ode gr oup to t he deas ser-
tion of Carrier Sense.
Parameter Description Notes Min Typ Max Units
T4.6.1 Carrier Sense ON Delay 17.5 bit times
T4.6.2 Receive Data Latenc y 21 bit times
Parameter Description Notes Min Typ Max Units
T4.7.1 Carrier Sense OFF Delay 21.5 bit times
CRS
RXD[3:0]
RD±
RX_DV
RX_ER/RXD[4]
IDLE Data
T4.6.1
T4.6.2
(J/K)
CRS
T4.7.1
RXD[3:0]
RX_DV
RX_ER/RXD[4]
RD±DATA IDLE
(T/R)
Obsolete
52 www.national.com
DP83846A
6.5 10 Mb/s Timing
6.5.1 10 Mb/s MII Transmit Timing
6.5.2 10 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T5.1.1 TXD[3:0], TX_EN Data Setup to TX_CLK 25 ns
T5.1.2 TXD[3:0], TX_EN Data Hold from TX_CLK 5 ns
Parameter Description Notes Min Typ Max Units
T5.2.1 RX_CLK Duty Cycle 35 65 %
T5.2.2 RX_CLK to RXD[3:0], RX_DV 190 210 ns
TX_CLK
TXD[3:0]
TX_EN Valid Data
T5.1.1 T5.1.2
RX_CLK
RXD[3:0]
Valid Data
T5.2.2
T5.2.1
RX_DV
Obsolete
53 www.national.com
DP83846A
6.5.3 10BASE-T Transmit Timing (Start of Packet)
6.5.4 10BASE-T Transmit Timing (End of Packet)
Parameter Description Notes Min Typ Max Units
T5.3.1 Transmit Enable Setup Time from the
Falling Edge of TX_CLK 25 ns
T5.3.2 Transmit Data Setup Time from the
Falling Edge of TX_CLK 25 ns
T5.3.3 Transmit Data Hold Time from the
Falling Edge of TX_CLK 5ns
T5.3. 4 Transmit Output Delay from the
Falling Edge of TX_CLK 6.8 bit times
Parameter Description Notes Min Typ Max Units
T5.4.1 Transmit Enable Hold Time from the
Fal ling Edge of TX_CLK 5ns
T5.4.2 End of Packet High Time
(with ‘0’ ending bit) 250 ns
T5.4.3 End of Packet High Time
(with ‘1’ ending bit) 250 ns
TX_CLK
TX_EN
TXD[0]
TPTD±
T5.3.1
T5.3.2
T5.3.3
T5.3.4
TX_CLK
TX_EN
TPTD±00
11
TPTD±
T5.4.2
T5.4.3
T5.4.1
Obsolete
54 www.national.com
DP83846A
6.5.5 10BASE-T Receive Timing (Start of Packet)
Note: 10BASE-T receive Data Latency is measured from first bit of preamble on the wire to the assertion of RX_DV.
6.5.6 10BASE-T Receive Timing (End of Packet)
Parameter Description Notes Min Typ Max Units
T5.5.1 Carrier Sense Turn On Delay
(TPRD± to CRS) 1µs
T5.5.2 Decoder Acquisition Time 3.6 µs
T5.5.3 Receive Data Late ncy 17.3 bit times
T5.5.4 SFD Propagation Delay 10 bit times
Parameter Description Notes Min Typ Max Units
T5.6.1 Carrier Sense Turn Off Delay 1.1 µs
101
TPRD±
CRS
RX_CLK
RXD[0]
1st SFD bit decoded
RX_DV
T5.5.1
T5.5.2
T5.5.3
T5.5.4
101
TPRD±
RX_CLK
CRS
IDLE
T5.6.1
Obsolete
55 www.national.com
DP83846A
6.5.7 10 Mb/s Heartbeat Timing
6.5.8 10 Mb/s Jabber Timing
6.5.9 10BASE-T Normal Link Pulse Timing
Parameter Description Notes Min Typ Max Units
T5.7.1 CD Heartbeat Delay 600 1600 ns
T5.7.2 CD Heartbeat Duration 500 1500 ns
Parameter Description Notes Min Typ Max Units
T5.8.1 Jabber Activa tio n Time 20 150 ms
T5.8.2 Jabber Deactiv ati on Tim e 250 750 ms
Parameter Description Notes Min Typ Max Units
T5.9.1 Pulse Width 100 ns
T5.9.2 Pulse Period 8 16 24 ms
TXC
TXE
COL T5.7.1
T5.7.2
TXE
TPTD±
COL
T5.8.2
T5.8.1
T5.9.2
T5.9.1
Normal Link Puls e(s)
Obsolete
56 www.national.com
DP83846A
6.5.10 Auto-Negotiation Fast Link Pulse (FLP) Timing
6.5.11 100BASE-TX Signal Detect Timing
Note: The signal amplitude at RD± is TP-PMD compliant.
Parameter Description Notes Min Typ Max Units
T5.10.1 Clock, Data Pulse Width 100 ns
T5.10.2 Clock Pulse to Clock Pulse
Period 111 125 139 µs
T5.10.3 Clock Pulse to Data Pulse
Period Data = 1 55.5 69.5 µs
T5.10.4 Number of Pulses in a Burst 17 33 #
T5.10.5 Burst Width 2ms
T5.10.6 FLP Burst to FLP Burst Period 8 24 ms
Parameter Description Notes Min Typ Max Units
T5.11.1 SD Internal Turn-on Time 1 ms
T5.11.2 SD Internal Turn-off Time 300 µs
clock
pulse data
pulse clock
pulse
FLP Burst FLP Burst
Fast Link Pulse(s)
T5.10.1 T5.10.1
T5.10.2
T5.10.3
T5.10.4 T5.10.5
T5.10.6
T5.11.1
SD+ internal
T5.11.2
RD±
Obsolete
57 www.national.com
DP83846A
6.6 Loopback Timing
6.6.1 100 Mb/s Internal Loopback Mode
Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”
of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is
based on device delays after the initial 550µs “dead-time”.
Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
Parameter Description Notes Min Typ Max Units
T6.1.1 TX_EN to RX_DV Loopback 240 ns
TX_CLK
TX_EN
TXD[3:0]
CRS
RX_CLK
RXD[3:0]
RX_DV
T6.1.1
Obsolete
59 www.national.com
DP83846A
6.7 Isolation Timing
Parameter Description Notes Min Typ Max Units
T7.0.1 From software clear of bit 10 in
the BMCR register to the transi-
tion from Isol ate to Normal Mode
100 µs
T7.0.2 From Deassertion of S/W or H/W
Reset to transition from Isolate to
Normal mode
500 µs
Clear bit 10 of BMCR
(return to normal operation
from Isolate mode)
H/W or S/W Reset
(with PHYAD = 00000)
MODE ISOLATE NORMAL
T7.0.2
T7.0.1
Obsolete
DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver
National does not assume any responsibility for use of any cir cuitry describe d, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the us er.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Corporation
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Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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Tel: 65-25444 66
Fax: 65-2504466
Email: ap.support@nsc.com
www.national.com
7.0 Physical Dimensions
Plastic Quad Flat Pack (LQFP)
Order Number DP83846AVHG
NS Package Number VHG-80A
Obsolete
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