General Description
The MAX5258/MAX5259 are +3V/+5V single-supply,
digital serial-input, voltage-output, 8-bit octal digital-to-
analog converters (DACs). Internal precision buffers
swing Rail-to-Rail®, and the reference input range
extends from ground to the positive supply. The +5V
(MAX5258) and the +3V (MAX5259) feature a 10µA
(max) shutdown mode.
The serial interface is double-buffered. A 16-bit input
shift register is followed by eight 8-bit input registers
and eight 8-bit DAC registers. The 16-bit serial word
consists of two “don’t care” bits, three address bits,
three control bits, and eight data bits. The input and
DAC registers can both be updated independently or
simultaneously with a single software command. The
asynchronous control input (LDAC) provides simultane-
ous updating of all eight DAC registers.
The interface is compatible with SPI™, QSPI™ (CPOL =
CPHA = 0 or CPOL = CPHA = 1), and MICROWIRE™.
A buffered digital data output allows daisy-chaining of
serial devices.
The MAX5258/MAX5259 are available in a 16-pin QSOP
package.
________________________Applications
Digital Gain and Offset Adjustment
Programmable Attenuators
Programmable Current Sources
Portable Instruments
Features
♦+2.7V to +5.5V Single-Supply Operation
♦Low Supply Current: 1.3mA
♦Low-Power Shutdown Mode
0.24µA (MAX5259)
0.45µA (MAX5258)
♦±1LSB DNL (max)
♦±1LSB INL (max)
♦Ground to VDD Reference Input Range
♦Output Buffer Amplifiers Swing Rail-to-Rail
♦10MHz Serial Interface, SPI, QSPI (CPOL = CPHA
= 0 or CPOL = CPHA = 1), and MICROWIRE-
Compatible
♦Double-Buffered Registers for Synchronous
Updating
♦Serial Data Output for Daisy-Chaining
♦Ultra-Small 16-Pin QSOP Package
+3V/+5V, Low-Power, 8-Bit Octal DACs
with Rail-to-Rail Output Buffers
________________________________________________________________ Maxim Integrated Products 1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OUTB OUTC
OUTD
DOUT
DIN
CS
SCLK
OUTH
OUTG
TOP VIEW
MAX5258
MAX5259
QSOP
OUTA
OUTE
OUTF
GND
VDD
REF
LDAC
Pin Configuration
19-1844; Rev 1; 4/01
EVALUATION KIT
AVAILABLE
Ordering Information
PART
TEMP. RANGE
PIN- PACK AGE
SU PPL Y
VO LT A G E
( V)
MAX5258EEE
-40oC to +85oC
16 QSOP +5.0
MAX5259EEE
-40oC to +85oC
16 QSOP +3.0
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
MAX5258/MAX5259
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (MAX5258)
(VDD = +4.5V to +5.5V, VREF = +4.096V, GND = 0, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical
values are at VDD = +5V and TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
DIN, DOUT, CS, SCLK, LDAC to GND.....................-0.3V to +6V
REF to GND................................................-0.3V to (VDD + 0.3V)
OUT_ to GND ...........................................................-0.3V to VDD
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin Plastic QSOP (derate 8.3mW/°C about +70°C)...667mW
Operating Temperature Range ..........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
STATIC ACCURACY
Resolution 8 Bits
Integral Nonlinearity (Note 1) INL
±0.1
±1
LSB
Differential Nonlinearity (Note 1) DNL Guaranteed monotonic (all codes)
±0.05
±1
LSB
Zero-Code Error ZCE Code = 0A hex
±2.5 ±20
mV
Zero-Code Error Supply
Rejection Code = 0A hex
0.02
1
LSB
Zero-Code Temperature
Coefficient Code = 0A hex
±10
µV/oC
Full-Scale Error Code = FF hex ±1
±30
mV
Code = FF hex
0.25
1
LSB
Full-Scale Temperature
Coefficient Code = FF hex
±10
µV/oC
REFERENCE INPUTS
Input Voltage Range 0
VDD
V
Input Resistance
161 230 300
kΩ
Input Capacitance 20 pF
DAC OUTPUTS
Output Voltage Swing RL = 10kΩ to GND 0 VDD -
0.3 V
Output Voltage Range RL = 10kΩ to GND 0
VREF
V
DIGITAL INPUTS
Input High Voltage VIH
0.7 ✕
VDD
V
Input Low Voltage VIL
0.3 ✕
VDD
V
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (MAX5258) (continued)
(VDD = +4.5V to +5.5V, VREF = +4.096V, GND = 0, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical
values are at VDD = +5V and TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Current IIN VIN = 0 to VDD
±1.0
µA
Input Capacitance CIN (Note 3) 10 pF
DIGITAL OUTPUTS
Output High Voltage VOH ISOURCE = 0.2mA VDD -
0.5 V
Output Low Voltage VOL ISINK = 1.6mA 0.4 V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate Code = FF hex
0.55
V/µs
Output Settling Time To 1/2 LSB, from code 0A to code FF hex
(Note 2) 10 µs
Digital Feedthrough Code = 00 hex
0.15
nV-s
Digital-to-Analog Glitch Impulse Code = 80 to code = 7F hex 30
nV-s
VREF = 4Vp-p at 1kHz centered at 2.5V
code = FF hex 68
Signal-to-Noise Plus Distortion
Ratio
SINAD
VREF = 4Vp-p at 10kHz centered at 2.5V
code = FF hex 55
dB
Multiplying Bandwidth VREF = 0.1Vp-p centered at VDD/2, -3dB
bandwidth
700
kHz
Wideband Amplifier Noise 16 µV
POWER REQUIREMENTS
Power-Supply Voltage VDD 4.5 5.5 V
Supply Current IDD 1.4 2.6 mA
Shutdown Supply Current
ISHDN 0.45
10 µA
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (MAX5259)
(VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values
are at VDD = +3V, and TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY
Resolution 8 Bits
Integral Non Linearity (Note 1) INL
±0.1
±1
LSB
Differential Non Linearity (Note 1)
DNL Guaranteed monotonic (all codes)
±0.1
±1
LSB
Zero-Code Error ZCE Code = 0A hex
±2.5 ±20
mV
Zero-Code Error Supply
Rejection Code = 0A hex.
0.15
1
LSB
Zero-Code Temperature
Coefficient Code = 0A hex
±10
µV/oC
Full-Scale Error Code = FF hex
±0.7 ±30
mV
Full-Scale Error Supply Rejection
Code = FF hex 0.2 1
LSB
Full-Scale Temperature
Coefficient Code = FF hex
±10
µV/oC
REFERENCE INPUTS
Input Voltage Range 0
VDD
V
Input Resistance
161 218 300
kΩ
Input Capacitance 20 pF
DAC OUTPUTS
Output Voltage Swing RL = 10kΩto GND 0 VDD –
0.3 V
Output Voltage Range RL = 10kΩ to GND 0
VREF
V
DIGITAL INPUTS
Input High Voltage VIH
0.7 x
VDD
V
Input Low Voltage VIL
0.3 x
VDD
V
Input Current IIN VIN = 0 to VDD
±1.0
µA
Input Capacitance CIN (Note 3) 10 pF
DIGITAL OUTPUTS
Output High Voltage VOH ISOURCE = 0.2mA VDD –
0.5 V
Output Low Voltage VOL ISINK = 1.6mA 0.4 V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate Code = FF hex
0.55
V/µs
Output Settling Time To 1/2 LSB, from code 0A to code FF hex
(Note 2) 7µs
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (MAX5259) (continued)
(VDD = +2.7V to +3.3V, VREF = +2.5V, GND = 0, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values
are at VDD = +3V, and TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Digital Feedthrough Code = 00 hex 0.1
nV-s
Digital-to-Analog Glitch Impulse Code = 80 to code = 7F hex 20
nV-S
VREF = 2.5Vp-p at 1kHz centered at 1.5V
code = FF hex 65
Signal-to-Noise Plus Distortion
Ratio
SINAD
VREF = 2.5Vp-pat 10kHz centered at 1.5V
code = FF hex 54
dB
Multiplying Bandwidth VREF = 0.1Vp-p centered at VDD/2, -3dB
bandwidth
700
kHz
Wideband Amplifier Noise 60 µV
POWER REQUIREMENTS
Power-Supply Voltage VDD 2.7 3.6 V
Supply Current IDD 1.3 2.6 mA
Shutdown Supply Current
ISHDN 0.24
10 µA
TIMING CHARACTERISTICS (MAX5258)
(VREF = +4.096V, GND = 0, CDOUT = 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V and
TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD Rise-to-CS Fall-Setup Time tVDCS 5µs
LDAC Pulse Width Low tLDAC 40 20 ns
CS Rise-to-LDAC Fall-Setup Time
(Note 4) tCLL 40 ns
CS Pulse Width High tCSW 90 ns
SCLK Clock Frequency (Note 5)
fCLK 10
MHz
SCLK Pulse Width High tCH 40 ns
SCLK Pulse Width Low tCL 40 ns
CS Fall-to-SCLK Rise-Setup Time
tCSS 40 ns
SCLK Rise-to-CS Rise-Hold Time
tCSH 0ns
DIN to SCLK Rise-to-Setup Time
tDS 40 ns
DIN to SCLK Rise-to-Hold Time tDH 0ns
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6) tDO1
200
ns
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7) tDO2
210
ns
CS Rise-to-SCLK Rise-Setup
Time tCS1 40 ns
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS (MAX5259)
(VREF = +2.5V, GND = 0, CDOUT = 100pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +3V and
TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD Rise-to-CS Fall-Setup Time tVDCS 5µs
LDAC Pulse Width Low tLDAC 40 20 ns
CS Rise-to-LDAC Fall-Setup Time
(Note 4) tCLL 40 ns
CS Pulse Width High tCSW 90 ns
SCLK Clock Frequency (Note 5)
fCLK 10
MHz
SCLK Pulse Width High tCH 40 ns
SCLK Pulse Width Low tCL 40 ns
CS Fall-to-SCLK Rise-Setup Time
tCSS 40 ns
SCLK Rise-to-CS Rise-Hold Time
tCSH 0ns
DIN to SCLK Rise-to-Setup Time
tDS 40 ns
DIN to SCLK Rise-to-Hold Time tDH 0ns
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6) tDO1
200
ns
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7) tDO2
210
ns
CS Rise-to-SCLK Rise-Setup
Time tCS1 40 ns
Note 1: INL and DNL are measured with RLreferenced to ground. Nonlinearity is measured from the first code that is greater than or
equal to the maximum offset specification to code FF hex (full scale). (See DAC Linearity and Voltage Offset section.)
Note 2: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of the final value of VOUT.
Note 3: Guaranteed by design, not production tested.
Note 4: If LDAC is activated prior to the rising edge of CS, it must remain low for tLDAC or longer after CS goes high.
Note 5: When DOUT is not used. If DOUT is used, fCLK (max) is 4MHz due to SCLK to DOUT propagation delay.
Note 6: Serial data is clocked-out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of VDD).
Note 7: Serial data is clocked-out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of VDD).
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
_______________________________________________________________________________________ 7
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
0
100
200
300
400
500
600
700
800
021345
DAC ZERO-CODE OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX5258/9 toc01
DAC OUTPUT SINK CURRENT (mA)
DAC ZERO-CODE OUTPUT VOLTAGE (mV)
VDD = +3V
0
0.25
0.50
0.75
1.00
1.25
1.50
021 345678
DAC ZERO-CODE OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX5258/9 toc02
DAC OUTPUT SINK CURRENT (mA)
DAC ZERO-CODE OUTPUT VOLTAGE (mV)
VDD = +5V
1.0
1.5
2.5
2.0
3.0
3.5
0231 45678
DAC FULL-SCALE OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX5258/9 toc03
DAC OUTPUT SOURCE CURRENT (mA)
DAC FULL-SCALE OUTPUT VOLTAGE (mV)
VDD = +3V
2.0
2.5
3.5
3.0
4.5
5.0
4.0
5.5
0231 45678
DAC FULL-SCALE OUTPUT VOLTAGE vs.
OUTPUT SOURCE CURRENT
MAX5258/9 toc04
DAC OUTPUT SOURCE CURRENT (mA)
DAC FULL-SCALE OUTPUT VOLTAGE (V)
VDD = +5V
0.4
0.6
0.8
1.0
1.2
1.4
1.6
-40 10-15 356085
SUPPLY CURRENT vs. TEMPERATURE
MAX5258/9 toc05
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
ALL DAC CODES = OO HEX
ALL DAC CODES = FF HEX
VREF = +2.5V
VDD = +3.0V
0.4
0.8
0.6
1.2
1.0
1.6
1.4
1.8
-40 10-15 356085
SUPPLY CURRENT vs. TEMPERATURE
MAX5258/9 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
ALL DAC CODES = FF HEX
ALL DAC CODES = OO HEX
VDD = +5.0V
VREF = +4.5V
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
-40 10-15 356085
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5258/9 toc07
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
VDD = +3V
VREF = +2.5V
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-40 10-15 356085
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5258/9 toc08
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
VDD = +5V
VREF = +4.5V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 1.00.5 1.5 2.0 2.5 3.0
SUPPLY CURRENT vs. REFERENCE
VOLTAGE (VDD = +3V)
MAX5258/9 toc09
REFERENCE VOLTAGE (V)
SUPPLY CURRENT (mA)
ALL DAC CODES = FF HEX
ALL DAC CODES = OO HEX
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
021 345
SUPPLY CURRENT vs. REFERENCE
VOLTAGE (VDD = +5V)
MAX5258/9 toc10
REFERENCE VOLTAGE (V)
SUPPLY CURRENT (mA)
ALL DAC CODES = FF HEX
ALL DAC CODES = OO HEX
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.5 1.0 1.5 2.0
THD + NOISE AT DAC OUTPUT vs.
REFERENCE AMPLITUDE
MAX5258/9 toc11
REFERENCE AMPLITUDE (Vp-p)
THD + NOISE (dB)
VREF = 20kHz
VREF = 1kHz
VREF = SINE-WAVE
VDD = +3V
CENTERED AT +1.5V
DAC CODE = FF HEX
80kHz LOWPASS FILTER
-70
-55
-60
-65
-50
-45
-40
-35
-30
-25
-20
10 1k100 10k 100k
THD + NOISE AT DAC OUTPUT vs.
REFERENCE FREQUENCY
MAX5258/9 toc12
FREQUENCY (Hz)
THD + NOISE (dB)
VREF = SINE-WAVE
VDD = +3V
CENTERED AT +1.5V
DAC CODE = FF HEX
500kHz LOWPASS FILTER
VREF = 0.5Vp-p
VREF = 1Vp-p
VREF = 2Vp-p
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
1 100 1k10 10k 100k 1M 10M
REFERENCE INPUT FREQUENCY
RESPONSE
MAX5258/9 toc13
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)
VREF = 0.1Vp-p SINE-WAVE
CENTERED AT 2.5V
DAC CODE = FF HEX
VDD = +3V
-90
-85
-55
-75
-80
-70
-65
-60
-50
100 1k 10k 100k 1M 10M
REFERENCE FEEDTHROUGH
vs. FREQUENCY
MAX5258/9 toc14
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)
VREF = 3Vp-p SINE-WAVE
DAC CODE = OO HEX
VDD = +3V
OUTA
WORST-CASE 1LSB DIGITAL STEP CHANGE
(POSITIVE)
MAX5258/9 toc15
1µs/div
3V
0
50mV/div
CS
VDD = +3V
VREF = +2.5V
DAC CODE = 7F TO 80 HEX
NO-LOAD
OUTA
WORST-CASE 1LSB DIGITAL STEP CHANGE
(NEGATIVE)
MAX5258/9 toc16
1µs/div
3V
0
50mV/div
CS
VDD = +3V
VREF = +2.5V
DAC CODE = 80 TO 7F HEX
NO-LOAD
OUTA
WORST-CASE 1LSB DIGITAL STEP CHANGE
(POSITIVE)
MAX5258/9 toc17
1µs/div
3V
0
50mV/div
CS
VDD = +5V
VREF = +4.5V
DAC CODE = 7F TO 80 HEX
NO-LOAD
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
OUTA
CLOCK FEEDTHROUGH
MAX5258/9 toc19
1µs/div
3V
0
1mV/div
SCLK
VDD = +3V
VREF = +2.5V
SCLK = 333 kHz
DAC CODE = 00 HEX
NO-LOAD
OUTA
POSITIVE SETTLING TIME
MAX5258/9 toc20
2µs/div
3V
0
1.0V/div
CS
VDD = +3V
VREF = +2.5V
DAC CODE = 00 TO FF HEX
NO-LOAD
OUTA
POSITIVE SETTLING TIME
MAX5258/9 toc21
4µs/div
3V
0
2.0V/div
CS
VDD = +5V
VREF = +4.5V
DAC CODE = 00 TO FF HEX
NO-LOAD
OUTA
NEGATIVE SETTLING TIME
MAX5258/9 toc22
4µs/div
3V
0
1.0V/div
CS
VDD = +3V
VREF = +2.5V
DAC CODE = FF TO 00 HEX
NO-LOAD
OUTA
CS
NEGATIVE SETTLING TIME
MAX5258/9 toc23
4µs/div
3V
0
2.0V/div
VDD = +5V
VREF = +4.5V
DAC CODE = FF TO 00 HEX
NO-LOAD
OUTA
WORST-CASE 1LSB DIGITAL STEP CHANGE
(NEGATIVE)
MAX5258/9 toc18
1µs/div
3V
0
50mV/div
CS
VDD = +5V
VREF = +4.5V
DAC CODE = 80 TO 7F HEX
NO-LOAD
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
10 ______________________________________________________________________________________
Detailed Description
Serial Interface
At power-on, the serial interface and all DACs are
cleared and set to code zero. The serial data output
(DOUT) is set to transition on SCLK’s falling edge.
The MAX5258/MAX5259 communicate with micro-
processors (µPs) through a synchronous, 3-wire inter-
face (Figure 1). Data is sent MSB first and can be
transmitted in two 4-bit and one 8-bit (byte) packets, or
one 16-bit word. The first two bits are ignored. A 4-wire
interface adds a line for LDAC, allowing asynchronous
updating. Data is transmitted and received simultane-
ously.
Figure 2 shows the detailed serial-interface timing. Note
that the clock should be low if it is stopped between
updates. DOUT does not go into a high-impedance state
if the clock idles or CS is high.
Serial data is clocked into the data registers in MSB-first
format, with the address and configuration information
preceding the actual DAC data. Data is clocked in on
SCLK’s rising edge while CS is low. Data at DOUT is
clocked out 16 clock cycles later, either at SCLK’s falling
edge (default or mode 0) or rising edge (mode 1).
CS must be low to enable the device. If CS is high, the
interface is disabled and DOUT remains unchanged.
CS must go low at least 40ns before the first rising edge
of the clock pulse to properly clock in the first bit. With
CS low, data is clocked into the MAX5258/MAX5259’s
internal shift register on the rising edge of the external
serial clock. Always clock in the full 16 bits.
Serial Input Data Format and Control Codes
The 16-bit serial input format, shown in Figure 3, com-
prises two “don’t care” bits, three DAC address bits (A2,
A1, A0), three control bits (C2, C1, C0), and eight data
bits (D7…D0). The 6-bit address/control code configures
the DAC as shown in Table 1.
Pin Description
PIN NAME FUNCTION
1 OUTB DAC B Voltage Output
2 OUTA DAC A Voltage Output
3 GND Ground
4V
DD Power Supply
5 REF Reference Voltage Input
6LDAC Load DAC Input. Driving this asynchronous input low transfers the contents of each input register
to its respective DAC registers.
7 OUTE DAC E Voltage Output
8 OUTF DAC F Voltage Output
9 OUTG DAC G Voltage Output
10 OUTH DAC H Voltage Output
11 CS Chip Select Input. Data is shifted in and out when CS is low. Programming commands are executed
when CS returns high.
12 SCLK Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling edge
(default) or rising edge (A2 = 1; see Table 1).
13 DIN Serial Data Input. Data is clocked in on the rising edge of SCLK.
14 DOUT Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the falling
edge (mode 0) or rising edge (mode 1) of SCLK (Table 1).
15 OUTD DAC D Voltage Output
16 OUTC DAC C Voltage Output
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
______________________________________________________________________________________ 11
CS
SCLK
INSTRUCTION
EXECUTED
DIN
DACA
X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
DATA FROM PREVIOUS DATA INPUT
X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
DACA
X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
DATA FROM PREVIOUS DATA INPUT
X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
X X A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
MODE 1
DOUT
MODE 0
(DEFAULT)
Figure 1. 3-Wire Interface Timing
SCLK
tCSS
tCL
tCH tCP
tCSW
tCS1
tD02
tCLL
tLDAC
tD01
tCSH
tDS
tDH
CS
DIN
DOUT
LDAC
Figure 2. Detailed Serial-Interface Timing Diagram
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
12 ______________________________________________________________________________________
16-BIT SERIAL WORD* LDAC FUNCTION
A2
A1 A0 C2 C1 C0
D7……D0
X X X 0 0 0 XXXXXXXX X No operation (NOP); shift data in shift registers.
X X X 0 0 1 XXXXXXXX X Clears all input and DAC registers and sets all DAC
outputs to zero.
X X X 0 1 0 XXXXXXXX X Software shutdown. Output buffers can be individually
shut down with zeros in the corresponding data bits.
0 X X 0 1 1 XXXXXXXX X DOUT Phase Mode 0. DOUT transitions on the falling
edge of SCLK.
1 X X 0 1 1 XXXXXXXX X DOUT Phase Mode 1. DOUT transitions on the rising
edge of SCLK.
XXX100
8-bit DAC data
X Loads all DACs with the same data
000101
8-bit DAC data
H Load input register A. All DAC outputs unchanged.
001101
8-bit DAC data
H Load input register B. All DAC outputs unchanged.
010101
8-bit DAC data
H Load input register C. All DAC outputs unchanged.
011101
8-bit DAC data
H Load input register D. All DAC outputs unchanged.
100101
8-bit DAC data
H Load input register E. All DAC outputs unchanged.
101101
8-bit DAC data
H Load input register F. All DAC outputs unchanged.
110101
8-bit DAC data
H Load input register G. All DAC outputs unchanged.
111101
8-bit DAC data
H Load input register H. All DAC outputs unchanged.
000110
8-bit DAC data
HLoad input register A. Update OUTA. All other DAC
outputs unchanged.
001110
8-bit DAC data
HLoad input register B. Update OUTB. All other DAC
outputs unchanged.
010110
8-bit DAC data
HLoad input register C. Update OUTC. All other DAC
outputs unchanged.
011110
8-bit DAC data
HLoad input register D. Update OUTD. All other DAC
outputs unchanged.
100110
8-bit DAC data
HLoad input register E. Update OUTE. All other DAC
outputs unchanged.
101110
8-bit DAC data
HLoad input register F. Update OUTF. All other DAC
outputs unchanged.
110110
8-bit DAC data
HLoad input register G. Update OUTG. All other DAC
outputs unchanged.
111110
8-bit DAC data
HLoad input register H. Update OUTH. All other DAC
outputs unchanged.
X X X 1 1 1 XXXXXXXX H Software LDAC command. Updates all DACs from their
respective input registers.
Table 1. Serial-Interface Programming Commands
*The first two bits are “don’t care.”
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
______________________________________________________________________________________ 13
The clear command clears all input and DAC registers and sets all DAC outputs to zero. This command brings the
DAC out of shutdown.
Shuts down all output buffer amplifiers and voltage references. Output buffers can be individually disabled with the cor-
responding zeros in the data bits (D7-D0). If all data bits are zero, only the power-on reset circuit is active, and the
device draws 10µA (max). There are four ways to bring the device out of shutdown: POR, CLEAR, LOAD SAME DATA,
LOAD INPUT, AND DAC REGISTERS.
This command sets DOUT to transition at the falling edge of SCLK. The same command also updates all DAC regis-
ters with the contents of their respective input registers, identical to the LDAC command. This is the default mode on
power-up.
A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Don’t Care 0 0 1 Don’t Care
Clear
(LDAC = X)
A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Don’t Care 0 1 0 8-Bit Data
Software Shutdown
(LDAC = X)
A2
A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
0 X X 0 1 1 8-Bit Data
Set DOUT Phase—SCLK Falling (Mode 0, Default)
(LDAC = X)
A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
1 X X 0 1 1 8-Bit Data
Set DOUT Phase—SCLK Rising (Mode 1)
(LDAC = X)
A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Don’t Care 0 0 0 Don’t Care
No Operation (NOP)
(LDAC = X)
The no-operation (NOP) command allows data to be shifted through the MAX5258/MAX5259 shift register without
affecting the input or DAC registers. This is useful in daisy-chaining (see the Daisy-Chaining Devices section). For
this command, the data bits are "Don’t Cares." As an example, three MAX5258s are daisy-chained (A, B, and C), and
devices A and C need to be updated. The 48-bit-wide command would consist of one 16-bit word for device C, fol-
lowed by an NOP instruction for device B and a third 16-bit word with data for device A. At the rising edge of CS,
device B will not change state.
Mode 1 sets the serial output DOUT to transition at the rising edge of SCLK. Once this command is issued, DOUT’s
phase is latched and will not change except on power-up or if the specific command to set the phase to falling edge
is issued.
This command also loads all DAC registers with the contents of their respective input registers, and is identical to the
LDAC command.
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
14 ______________________________________________________________________________________
A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Don’t Care 1 0 0 8-Bit Data
Load All DACs with Shift-Register Data
(LDAC = X)
All eight DAC registers are updated with shift-register data. This command allows all DACs to be set to any analog
value within the reference range. This command can be used to substitute CLEAR if code 00 (hex) is programmed,
which clears all DACs. This command brings the device out of shutdown.
A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Address 1 0 1 8-Bit Data
Load Input Register, DAC Registers Unchanged (Single Update Operation)
(LDAC = X)
When performing a single update operation, A2-A0 selects the respective input register. At the rising edge of CS, the
selected input register is loaded with the current shift-register data. All DAC outputs remain unchanged. This pre-
loads individual data in the input register without changing the DAC outputs.
A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Address 1 1 0 8-Bit Data
Load Input and DAC Registers
(LDAC = X)
This command directly loads current shift-register data in the selected input and DAC registers at the rising edge of
CS. A2-A0 set the DAC address.
For example, to load all eight DAC registers simultaneously with individual settings, eight commands are required.
First perform seven single input register update operations (C2 = 1, C1 = 0, C0 = 1) for DACs A, B, C, D, E, F, and G
(C2 = 1, C1 = 0, C0 = 1). The final command loads input register H and updates all eight DAC registers from their
respective input registers. This command brings the device out of shutdown.
A2 A1 A0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
Address 1 1 1 8-Bit Data
Software “
LDAC
” Command
(LDAC = X)
All DAC registers are updated with the contents of their respective input registers at the rising edge of CS. This is a
synchronous software command that performs the same function as the asynchronous LDAC.
LDAC Operation (Hardware)
LDAC is typically used in 4-wire interfaces (Figure 4).
This command is level sensitive, and it allows asyn-
chronous hardware control of the DAC outputs. With
LDAC low, all eight DAC registers are transparent, and
any time an input register is updated, the DAC output
immediately follows.
Serial Data Output
DOUT is the internal shift-register’s output. DOUT can
be programmed to clock out data on the falling edge of
SCLK (mode 0) or the rising edge (mode 1). In mode 0,
output data lags input data by 16.5 clock cycles, main-
taining compatibility with MICROWIRE and SPI. In
mode 1, output data lags input data by 16 clock cycles.
On power-up, DOUT defaults to mode 0 timing. DOUT
never three-states; it always actively drives either high
or low and remains unchanged when CS is high.
Interfacing to the Microprocessor
The MAX5258/MAX5259 are MICROWIRE (Figure 5)
and SPI/QSPI (Figure 6) compatible. For SPI and QSPI,
clear the CPOL and CPHA configuration bits (CPOL =
CPHA = 0). The SPI/QSPI CPOL = CPHA = 1 configura-
tion can also be used if the DOUT output is ignored.
The MAX5258/MAX5259 can interface with Intel’s
80C5X/80C3X family in mode 0 if the SCLK clock polar-
ity is inverted. Universally, if a serial port is not avail-
able, three lines from one of the parallel ports can be
used for bit manipulation.
Digital feedthrough at the voltage outputs is greatly
minimized by operating the serial clock only to update
the registers. See the Clock Feedthrough photo in the
Typical Operating Characteristics section. The clock
idle state is low.
Daisy-Chaining Devices
Any number of MAX5258/MAX5259s can be daisy-
chained by connecting DOUT of one device to DIN of
the following device in the chain with all devices in
mode zero. The NOP instruction (Table 1) allows data
to be passed from DIN to DOUT without changing the
input or DAC registers of the passing device. A 3-wire
interface updates daisy-chained or individual
MAX5258/MAX5259s simultaneously by bringing CS
high (Figure 7).
Analog Section
DAC Operation
The MAX5258/MAX5259 use a matrix decoding archi-
tecture for the DACs, which saves power in the overall
system. The external reference voltage is divided down
by a resistor string placed in a matrix fashion. Row and
column decoders select the appropriate tab from the
resistor string to provide the needed analog voltages.
The resistor string presents a code-independent input
impedance to the reference and guarantees a monoto-
nic output. Figure 8 shows a simplified diagram of one
of the eight DACs.
Reference Input
The voltage at REF sets the full-scale output voltage for
all eight DACs. The 230kΩtypical input impedance at
REF is code independent. The output voltage for any
DAC can be represented by a digitally programmable
voltage source as follows:
VOUT = (NB ✕VREF) / 256,
where NB is the numerical value of the DAC’s binary
input code.
Output Buffer Amplifiers
All MAX5258/MAX5259 voltage outputs are internally
buffered by precision unity-gain followers that slew at
about 0.55V/µs. The outputs can swing from GND to
VDD. With a 0 to VREF (or VREF to 0) output transition,
the amplifier outputs will typically settle to 1/2LSB in
10µs when loaded with 10kΩin parallel with 100pF.
The buffer amplifiers are stable with any combination of
resistive (≥10kΩ) or capacitive (≤100pF) loads.
Applications Information
DAC Linearity and Voltage Offset
The output buffer can have a negative input offset volt-
age that would normally drive the output negative, but
since there is no negative supply, the output remains at
GND (Figure 9). When linearity is determined using the
endpoint method, it is measured between code 10 (0A
hex) and full-scale code (FF hex) after offset and gain
error are calibrated out. With a single-supply, negative
offset causes the output not to change with an input
code transition near zero (Figure 9). Thus, the lowest
code that produces a positive output is the lower end-
point.
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
______________________________________________________________________________________ 15
THIS IS THE FIRST BIT SHIFTED IN
DOUT X X A2 A1 A0 C2 C1 C0 D7 D6 . . . D1 D0 DIN
MSB LSB
8-BIT DAC DATACONTROL AND
ADDRESS BITS
Figure 3. Serial Input Format
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
16 ______________________________________________________________________________________
MAX5258/
MAX5259
SCLK
LDAC
DIN
CS
TO OTHER
SERIAL
DEVICES
MAX5258/
MAX5259
SCLK
LDAC
DIN
CS
MAX5258/
MAX5259
SCLK
LDAC
DIN
CS
CS1
CS2
CS3
DIN
SCLK
LDAC
Figure 4. Multiple MAX5258’s Sharing One DIN Line. (Simultaneously Update by Strobing
LDAC
, or Specifically Update by Enabling
an Individual
CS
)
MAX5258/
MAX5259
MICROWIRE
PORT
SCLK
DIN
CS
SK
SO
I/O
MAX5258/
MAX5259
SPI/QSPI
PORT
SCLK
DIN
CS
SCK
MOSI
I/O
CPOL = 0, CPHA = 0
Figure 5. Connections for MICROWIRE Figure 6. Connections for SPI/QSPI
MAX5258/
MAX5259
MAX5258/
MAX5259
SCLK
DIN
CS
DOUT
DEVICE A DEVICE B DEVICE C
TO OTHER
SERIAL DEVICES
DOUT DOUT
SCLK
DIN
CS
MAX5258/
MAX5259
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
DIN
CS
MAX5258/
MAX5259
SCLK
DIN
CS
Figure 7. Daisy-Chained or Individual MAX5258s Simultaneously Updated by Bringing
CS
High (Only Three Wires Are Required)
Power Sequencing
The voltage applied to REF should not exceed VDD at
any time. If proper power sequencing is not possible,
connect an external Schottky diode between REF and
VDD to ensure compliance with the absolute maximum
ratings. Do not apply signals to the digital inputs before
the device is fully powered-up.
Power-Supply Bypassing and
Ground Management
Bypass VDD with a 0.1µF capacitor, located as close to
VDD and GND as possible. Careful PC board layout
minimizes crosstalk among DAC outputs and digital
inputs. Figure 10 shows suggested circuit board layout
to minimize crosstalk.
Unipolar-Output, Two-Quadrant
Multiplication
In unipolar operation, the output voltages and the refer-
ence input are the same polarity. Figure 11 shows the
MAX5258/MAX5259 unipolar configuration, and Table 2
shows the unipolar code.
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
______________________________________________________________________________________ 17
REF
R1 R15
R16
R255
R0
D7
D6
D5
D4
DAC A
MSB DECODER
D3 D0
D2 D1
LSB DECODER
Figure 8. DAC Simplified Circuit Diagram
OUTC
OUTD
DOUT
DIN
SYSTEM GND
OUTB
OUTA
GND
VDD
REF
LDAC
Figure 10. Suggested PC Board Layout for Minimizing
Crosstalk (Bottom View)
ODAC CODE
NEGATIVE
OFFSET
OUTPUT
VOLTAGE
Figure 9. Effect of Negative Offset (Single Supply)
MAX5258/MAX5259
Note:1LSB = (VREF) ✕(28) = +VREF (1 / 256)
____________________Chip Information
TRANSISTOR COUNT: 13625
PROCESS: BiCMOS
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
18 ______________________________________________________________________________________
DAC A
REFERENCE INPUT +3V
REF VDD
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
OUT A
OUT B
OUT C
OUT D
OUT E
OUT F
OUT G
OUT H
MAX5258/
MAX5259
Figure 11. Unipolar Output Circuit
DAC CONTENTS
MSB LSB
ANALOG OUTPUT
1111 1111 +VREF(255/256)
1000 0001 +VREF(129/256)
1000 0000
+VREF(128/256) = +VREF/2
0111 1111 +VREF(127/256)
0000 0001 +VREF(1/256)
0000 0000 0
Table 2. Unipolar Code Table
MAX5258/MAX5259
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
______________________________________________________________________________________ 19
DAC A
DOUT LDAC
DAC
REGISTER
A
REF
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
OUT A
OUT B
OUT C
OUT D
OUT E
OUT F
OUT G
OUT H
MAX5258/
MAX5259
DECODE
CONTROL
DAC
REGISTER
B
DAC
REGISTER
C
DAC
REGISTER
D
DAC
REGISTER
E
DAC
REGISTER
F
DAC
REGISTER
G
DAC
REGISTER
H
INPUT
REGISTER
A
SR
CONTROL
CS DIN SCLK GND
INPUT
REGISTER
B
INPUT
REGISTER
C
16-BIT
SHIFT
REGISTER
INPUT
REGISTER
D
INPUT
REGISTER
E
INPUT
REGISTER
F
INPUT
REGISTER
G
INPUT
REGISTER
H
VDD
Functional Diagram
MAX5258/MAX5259
+5V/+3V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
QSOP.EPS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)