SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DDual Versions of Highly Stable SN54121
and SN74121 One Shots
DSN54221 and SN74221 Demonstrate
Electrical and Switching Characteristics
That Are Virtually Identical to the SN54121
and SN74121 One Shots
DPinout Is Identical to the SN54123,
SN74123, SN54LS123, and SN74LS123
DOverriding Clear Terminates Output Pulse
TYPE
MAXIMUM
OUTPUT
PULSE
LENGTH(S)
SN54221 21
SN74221 28
SN54LS221 49
SN74LS221 70
description/ordering information
The ’221 and ’LS221 devices are dual
multivibrators with performance characteristics
virtually identical to those of the ’121 devices.
Each multivibrator features a negative-transition-
triggered input and a positive-transition-triggered
input, either of which can be used as an inhibit
input.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N
Tube
SN74221N SN74221N
PDIP − N Tube SN74LS221N SN74LS221N
0°C to 70°C
SOIC − D
Tube SN74LS221D
LS221
0°C to 70°CSOIC − D Tape and reel SN74LS221DR LS221
SOP − NS Tape and reel SN74LS221NSR 74LS221
SSOP − DB Tape and reel SN74LS221DBR LS221
CDIP − J
Tube
SNJ54221J SNJ54221J
−55°C to 125°CCDIP − J Tube SNJ54LS221J SNJ54LS221J
−55 C to 125 C
LCCC − FK Tube SNJ54LS221FK SNJ54LS221FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
3212019
910 11 12 13
4
5
6
7
8
18
17
16
15
14
1Cext
1Q
NC
2Q
2CLR
1CLR
1Q
NC
2Q
2Cext
1B
1A
NC
2A
2B V
1R
extGND
NC
1A
1B
1CLR
1Q
2Q
2Cext
2Rext/Cext
GND
VCC
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
2A
SN54221, SN54LS221 ...J PACKAGE
SN74221 ...N PACKAGE
SN74LS221 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
SN54LS221 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
ext/Cext
2R /Cext
NC − No internal connection
(+&%#$ %!(*"# # 2343 "** (""!'#'$ "' #'$#'+
&*'$$ #-'/$' #'+, "** #-' (+&%#$ (+&%#
(%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1 "** (""!'#'$,
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing
appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of 30 ns is achieved
that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent
of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics
waveforms.
Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and
temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing
capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221,
2 kΩ to 40 kΩ for the SN74221, 2 kΩ to 70 kΩ for the SN54LS221, and 2 kΩ to 100 kΩ for the SN74LS221).
Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 ≈ 0.7 CextRext. In
circuits where pulse cutof f is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 kΩ
can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air
temperature i s 2 5 °C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher
duty cycles are available if a certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device typically is less than ±0.5% for given external timing
components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width
versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123
so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by
merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.
FUNCTION TABLE
(each monostable multivibrator)
INPUTS OUTPUTS
CLR A B Q Q
L X X L H
XHXLH
XXLLH
H L ↑††
H↓H††
↑‡L H † †
†Pulsed-output patterns are tested during
AC switching at 25 °C with Rext = 2 kΩ, and
Cext = 80 pF.
‡This condition is true only if the output of
the latch formed by the two NAND gates
has been conditioned to the logic 1 state
prior to CLR going high. This latch is
conditioned by taking either A high or
B low while CLR is inactive (high).
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing component connections
VCC
Rext
To Cext
Terminal To Rext/Cext
Terminal
NOTE: Due to the internal circuit, the Rext/Cext terminal never is more positive than the Cext terminal.
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
VCC
Req
Input
VCC
100 Ω NOM
Output
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
SN54/74221
SN54/74LS221
EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS
VCC
Req
Input
VCC
Output
120 Ω NOM
A Input: Req = 4 kΩ NOM
B, CLR Input: Req = 2 kΩ NOM
A Input: Req = 25 kΩ NOM
B Input: Req = 15.4 kΩ NOM
CLR: Req = 12.5 kΩ NOM
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): ’LS221 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
’221 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54221 SN74221
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current −800 −800 µA
IOL Low-level output current 16 16 mA
∆v/∆t
Rise or fall of input pulse rate
B input 1* 1 V/s
∆v/∆tRise or fall of input pulse rate A input 1* 1 V/µs
TAOperating free-air temperature −55 125 0 70 °C
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54221 SN74221
UNIT
PARAMETER
TEST CONDITIONS
†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VT+ Positive-going threshold voltage,
B input VCC = MIN 1.55 2* 1.55 2 V
VT− Negative-going threshold voltage,
B input VCC = MIN 0.8* 1.35 0.8 1.35 V
VIK VCC = MIN, II = −12 mA −1.5 −1.5 V
VOH VCC = MIN, IOH = −800 µA 2.4 3.4 2.4 3.4 V
VOL VCC = MIN, IOL = 16 mA 0.2 0.4 0.2 0.4 V
IIVCC = MAX, VI = 5.5 V 1 1 mA
IIH
A input
VCC = MAX,
VI = 2.4 V
40 40
A
I
IH CLR, B input VCC = MAX, VI = 2.4 V 80 80 µA
IIL
A input
VCC = MAX,
VI = 0.4 V
−1.6 −1.6
mA
IIL CLR, B input VCC = MAX, VI = 0.4 V −3.2 −3.2 mA
IOS§VCC = MAX −20 −55 −18 −55 mA
ICC
Quiescent
VCC = MAX
26 50* 26 50
mA
I
CC Triggered
V
CC
= MAX
46 80* 46 80
mA
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SN54221 SN74221
UNIT
MIN MAX MIN MAX
UNIT
tw
Pulse duration
A or B input 50 50
ns
twPulse duration CLR 20 20 ns
tsu Setup time, inactive-state¶ CLR 15 15 ns
Rext External timing resistance 1.4* 30* 1.4 40 kΩ
Cext External timing capacitance 0* 1000* 0 1000 µF
Output duty cycle
Rext = 2 kΩ67% 67%
Output duty cycle
Rext = MAX Rext 90% 90%
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶Inactive-state setup time also is referred to as recovery time.
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics VCC = 5 V, RL = 400 Ω, TA = 25_C (see Figures 1 and 2)
PARAMETER
FROM
TO
TEST CONDITIONS
SN54221 SN74221
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
tPLH
A
Q
45 70 45 70
tPLH B
Q
Cext = 80 pF,
Rext = 2 kΩ
35 55 35 55
ns
tPHL
A
Q
C
ext
= 80 pF,
R
ext
= 2 k
Ω50 80 50 80 ns
tPHL B
Q
40 65 40 65
tPHL
CLR
Q
Cext = 80 pF,
Rext = 2 kΩ
27 27
ns
tPLH
CLR
Q
C
ext
= 80 pF,
R
ext
= 2 k
Ω40 40 ns
Cext = 80 pF, Rext = 2 kΩ70 110 150 70 110 150
tw
A or B
Q or Q
Cext = 0, Rext = 2 kΩ17 30 50 17 30 50 ns
t
w
A or B
Q or Q
Cext = 100 pF, Rext = 10 kΩ650 700 750 650 700 750
ns
Cext = 1 µF, Rext = 10 kΩ6.5* 7 7.5* 6.5 7 7.5 ms
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
recommended operating conditions (see Note 4)
SN54LS221 SN74LS221
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current −400 −400 µA
IOL Low-level output current 4 8 mA
∆v/∆t
Rise or fall of input pulse rate
B input 1*1 V/s
∆v/∆tRise or fall of input pulse rate A input 1*1 V/µs
TAOperating free-air temperature −55 125 0 70 °C
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS†
SN54LS221 SN74LS221
UNIT
PARAMETER
TEST CONDITIONS
†
MIN TYP‡MAX MIN TYP‡MAX
UNIT
VT+ Positive-going threshold voltage,
B input VCC = MIN 1 2* 1 2 V
VT− Negative-going threshold voltage,
B input VCC = MIN 0.7* 0.9 0.8 0.9 V
VIK VCC = MIN, II = −18 mA −1.5 −1.5 V
VOH VCC = MIN, IOH = −400 µA 2.5 3.4 2.7 3.4 V
VOL
VCC = MIN
IOL = 4 mA 0.25 0.4 0.25 0.4
V
VOL VCC = MIN IOL = 8 mA 0.35 0.5 V
IIVCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VI = 2.7 V 20 20 µA
IIL
A input
VCC = MAX,
VI = 0.4 V
−0.4 −0.4
mA
IIL CLR, B input VCC = MAX, VI = 0.4 V −0.8 −0.8 mA
IOS§VCC = MAX −20 −100 −20 −100 mA
ICC
Quiescent
VCC = MAX
4.7 11 4.7 11
mA
I
CC Triggered
V
CC
= MAX
19 27* 19 27
mA
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡All typical values are at VCC = 5 V, TA = 25°C.
§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SN54LS221 SN74LS221
UNIT
MIN MAX MIN MAX
UNIT
tw
Pulse duration
A or B 50 50
ns
twPulse duration CLR 40 40 ns
tsu Setup time, inactive state¶CLR 15 15 ns
Rext External timing resistance 1.4* 70* 1.4 100 kΩ
Cext External timing capacitance 0* 1000* 0 1000 µF
Output duty cycle
RT = 2 kΩ50% 50%
Output duty cycle
RT = MAX Rext 90% 90%
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶Inactive-state setup time also is referred to as recovery time.
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics VCC = 5 V, RL = 2 kΩ, TA = 25_C (see Figures 1 and 2)
PARAMETER
FROM
TO
TEST CONDITIONS
SN54LS221 SN74LS221
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
MIN TYP MAX MIN TYP MAX
UNIT
tPLH
A
Q
45 70 45 70
tPLH B
Q
Cext = 80 pF,
Rext = 2 kΩ
35 55 35 55
ns
tPHL
A
Q
C
ext
= 80 pF,
R
ext
= 2 k
Ω50 80 50 80 ns
tPHL B
Q
40 65 40 65
tPHL
CLR
Q
Cext = 80 pF,
Rext = 2 kΩ
35 55 35 55
ns
tPLH
CLR
Q
C
ext
= 80 pF,
R
ext
= 2 k
Ω44 65 44 65 ns
Cext = 80 pF, Rext = 2 kΩ70 120 150 70 120 150
tw
A or B
Q or Q
Cext = 0, Rext = 2 kΩ20 47 70 20 47 70 ns
t
w
A or B
Q or Q
Cext = 100 pF, Rext = 10 kΩ670 740 810 670 740 810
ns
Cext = 1 µF, Rext = 10 kΩ6* 6.9 7.5* 6 6.9 7.5 ms
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
B†
CLR
Q
Q
3 V
3 V
0 V
0 V
VOH
VOH
VOL
VOL
tw
≥ 60 ns
tPLH tPHL
tPHL tPLH
CONDITION 1: TRIGGER FROM B, THEN CLR
B†
CLR
Q
3 V
3 V
0 V
0 V
VOH
VOL
≥ 60 ns
CONDITION 2: TRIGGER FROM B, THEN CLR
B†
CLR
Q
3 V
3 V
0 V
0 V
VOH
VOL
≥ 50 ns
CONDITION 3: CLR OVERRIDING B, THEN TRIGGER FROM B
tsu
≥ 0
tw
Triggered
Not Triggered
†A is low.
Figure 1. Switching Characteristics
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
B†
CLR
Q
3 V
3 V
0 V
0 V
VOH
VOL
≥ 50 ns
CONDITION 4: TRIGGERING FROM POSITIVE TRANSITION OF CLR
≥ 50 ns
A‡
CLR
Q
Q
3 V
3 V
0 V
0 V
VOH
VOH
VOL
VOL
tw
≥ 60 ns
tPLH tPHL
tPHL tPLH
CONDITION 5: TRIGGER FROM A, THEN CLR
A‡
Q
Q
3 V
0 V
VOH
VOH
VOL
VOL
tw
CONDITION 6: TRIGGER FROM A
tw
†A is low.
‡B and CLR are high.
NOTES: A. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50Ω; for SN54/74221, tr ≤ 7 ns,
tf ≤ 7 ns, for SN54/74LS221, tr ≤ 15 ns, tf ≤ 6 ns.
B. All measurements are made between the 1.5-V points of the indicated transitions for the SN54/74221 or between the 1.3-V points
for the SN54/74LS221.
Figure 1. Switching Characteristics (Continued)
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tPHL tPLH
tPLH tPHL
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
High-Level
Pulse
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test CL = 15 pF
(see Note A)
Test
Point
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω and, for SN54/74221,
tr ≤ 7 ns, tf ≤ 7 ns, for SN54/74LS221, tr ≤ 15 ns, tf ≤ 6 ns.
E. All measurements are made between the 1.5-V points of the indicated transitions for the SN54/74221 or between the 1.3-V points
for the SN54/74LS221.
Figure 2. Load Circuits and Voltage Waveforms
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS (SN54/74221 ONLY)†
Figure 3
Median
Relative Frequency of Occurrence
DISTRIBUTION OF UNITS
FOR
OUTPUT PULSE
tw − Output Pulse
VCC = 5 V
TA = 25°C
Median
+0.5%
Median
+0.5%
Figure 4
0
− 0.5
−14.5 4.75 5
0.5
VARIATION IN OUTPUT PULSE
vs
SUPPLY VOLTAGE
1
5.25 5.5
− Variation in Output Pulse − %∆tw
VCC − Supply Voltage − V
Cext = 60 pF
Rext = 10 kΩ
TA = 25°C
tw ≈ 420 ns
at VCC = 5 V
Figure 5
−25−50−75
0
− 0.5
−1 02550
− Variation in Output Pulse − %
0.5
VARIATION IN OUTPUT PULSE
vs
FREE-AIR TEMPERATURE
1
75 100 125
TA − Free-Air Temperature − °C
∆tw
VCC = 5 V
Cext = 60 pF
Rext = 10 kΩ
tw ≈ 420 ns
at TA = 25°C
OUTPUT PULSE
vs
TIMING RESISTOR VALUE
Figure 6
100 ns
10 ns12 4710
10 ms
1 ms
20 40 70 100
− Output Pulsetw
100 µs
10 µs
1 µs
VCC = 5 V
TA = 25°C
FµCext = 1
FµCext= 0.1
FµCext = 0.01
Cext = 1000 pF
Cext = 100 pF
Cext = 10 pF
See Note A
Rext − Timing Resistor Value − kΩ
†Data for temperatures below 0°C and above 70°C, and for supply voltages below 4.75 V and above 5.25 V are applicable for the SN54221 only.
NOTE A: These values of resistance exceed the maximum recommended for use over the full military temperature range of the SN54221.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8771101EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8771101EA
SNJ54221J
76042012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 76042012A
SNJ54LS
221FK
7604201EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7604201EA
SNJ54LS221J
7604201FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 7604201FA
SNJ54LS221W
JM38510/31402B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
31402B2A
JM38510/31402BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
31402BEA
JM38510/31402BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
31402BFA
M38510/31402B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
31402B2A
M38510/31402BEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
31402BEA
M38510/31402BFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
31402BFA
SN54221J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54221J
SN54LS221J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 SN54LS221J
SN74221N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74221N
SN74221NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74221N
SN74LS221D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS221
SN74LS221DBR ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS221
SN74LS221DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS221
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LS221DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS221
SN74LS221DE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS221
SN74LS221DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS221
SN74LS221DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS221
SN74LS221DRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS221
SN74LS221DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 LS221
SN74LS221N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS221N
SN74LS221N3 OBSOLETE PDIP N 16 TBD Call TI Call TI 0 to 70
SN74LS221NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN74LS221N
SN74LS221NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS221
SN74LS221NSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS221
SN74LS221NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 74LS221
SNJ54221J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8771101EA
SNJ54221J
SNJ54LS221FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 76042012A
SNJ54LS
221FK
SNJ54LS221J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 7604201EA
SNJ54LS221J
SNJ54LS221W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 7604201FA
SNJ54LS221W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54221, SN54LS221, SN74221, SN74LS221 :
•Catalog: SN74221, SN74LS221
•Military: SN54221, SN54LS221
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LS221DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74LS221DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74LS221NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LS221DBR SSOP DB 16 2000 367.0 367.0 38.0
SN74LS221DR SOIC D 16 2500 333.2 345.9 28.6
SN74LS221NSR SO NS 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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