© Semiconductor Components Industries, LLC, 2017
December, 2018 − Rev. 1
1Publication Order Number:
NVMFD5C478N/D
NVMFD5C478N
Power MOSFET
40 V, 17.0 mW, 27 A, Dual N−Channel
Features
•Small Footprint (5 x 6 mm) for Compact Design
•Low RDS(on) to Minimize Conduction Losses
•Low Capacitance to Minimize Driver Losses
•NVMFD5C478NWF − Wettable Flanks Product
•AEC−Q101 Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS 40 V
Gate−to−Source Voltage VGS ±20 V
Continuous Drain
Current RqJC
(Notes 1, 2, 3, 4) Steady
State
TC = 25°CID27 A
TC = 100°C 19
Power Dissipation
RqJC (Notes 1, 2, 3)
TC = 25°CPD23 W
TC = 100°C 12
Continuous Drain
Current RqJA
(Notes 1 & 3, 4) Steady
State
TA = 25°CID9.8 A
TA = 100°C 6.9
Power Dissipation
RqJA (Notes 1, 3)
TA = 25°CPD3.1 W
TA = 100°C 1.5
Pulsed Drain Current TA = 25°C, tp = 10 msIDM 90 A
Operating Junction and Storage Temperature TJ, Tstg −55 to
+175
°C
Source Current (Body Diode) IS19 A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 1.4 A)
EAS 48 mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter Symbol Value Unit
Junction−to−Case − Steady State (Note 3) RqJC 6.5 °C/W
Junction−to−Ambient − Steady State (Note 3) RqJA 48.8
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
www.onsemi.com
V(BR)DSS RDS(on) MAX ID MAX
40 V 17.0 mW @ 10 V 27 A
DFN8, 5x6
(S08FL)
CASE 506BT
PIN CONNECTION &
MARKING DIAGRAM
(Note: Microdot may be in either location)
XXXXXX = 5C478N (NVMFD5C478N) or
478NWF (NVMFD5C478NWF)
A = Assembly Location
Y = Year
ZZ = Lot Traceability
WW = Work Week
G= Pb−Free Package
Dual−Channel
D1
S1
G1
See detailed ordering, marking and shipping information on
page 5 of this data sheet.
ORDERING INFORMATION
D2
S2
G2
1XXXXXX
AYWZZ
1D1 D1
D1
D1
D2
D2
S1
G1
S2
G2
D2 D2
NVMFD5C478N
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2
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA40 V
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = 40 V
TJ = 25°C 10 mA
TJ = 125°C 250
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = 20 V 100 nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 20 mA2.5 3.5 V
Drain−to−Source On Resistance RDS(on) VGS = 10 V, ID = 7.5 A 14 17 mW
Forward Transconductance gFS VDS = 3 V, ID = 7.5 A 2 S
CHARGES AND CAPACITANCES
Input Capacitance Ciss
VGS = 0 V, f = 1.0 MHz,
VDS = 25 V
325 pF
Output Capacitance Coss 165
Reverse Transfer Capacitance Crss 10
Total Gate Charge QG(TOT)
VGS = 10 V, VDS = 32 V, ID = 7.5 A
6.3 nC
Threshold Gate Charge QG(TH) 1.3 nC
Gate−to−Source Charge QGS 2.0
Gate−to−Drain Charge QGD 1.2
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time td(on)
VGS = 10 V, VDS = 32 V,
ID = 7.5 A, RG = 1 W
7ns
Rise Time tr13
Turn−Off Delay Time td(off) 14
Fall Time tf4.5
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = 7.5 A
TJ = 25°C 0.84 1.2 V
TJ = 125°C 0.72
Reverse Recovery Time tRR
VGS = 0 V, dlS/dt = 100 A/ms,
IS = 7.5 A
18 ns
Charge Time ta7.0
Discharge Time tb11
Reverse Recovery Charge QRR 6 nC
5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
NVMFD5C478N
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3
TYPICAL CHARACTERISTICS
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
IDSS, LEAKAGE (nA)
TJ = 125°C
TJ = 25°C
TJ = −55°C
TJ = 25°C
ID = 7.5 A TJ = 25°C
VGS = 10 V
VGS = 10 V
ID = 7.5 A
TJ = 125°C
TJ = 85°C
VDS = 10 V
TJ = 150°C
7 V to 10 V
0
5
10
15
20
25
30
012
4 V
0
10
20
30
40
50
60
4 5 6 7 9 10 5 10 25 30
16
0
15
0.7
0.9
1.3
−50 −25 0 25 50 75 100 125 150 175
10
100
1K
10K
51525
80
90
100
14
10
6
2
0
10 20 30
8
5 V
6 V
70
20
3
0
5
10
15
20
25
30
3456
1.5
1.1
1.7
1.9
35 40
20
4
8
12
18
NVMFD5C478N
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4
TYPICAL CHARACTERISTICS
Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total
Charge
VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
RG, GATE RESISTANCE (W)VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
VDS, DRAIN−TO−SOURCE VOLTAGE(V) TIME IN AVALANCHE (s)
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
t, TIME (ns)
IS, SOURCE CURRENT (A)
ID, DRAIN CURRENT (A)
IPEAK, (A)
VGS = 0 V
TJ = 25°C
f = 1 MHz
CISS
COSS
CRSS VDS = 32 V
ID = 7.5 A
TJ = 25°C
QGS QGD
VGS = 10 V
VDS = 32 V
td(off)
td(on)
tf
tr
TJ = 25°C
TJ = −55°C
TJ (initial) = 100°C
TJ (initial) = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
10 ms
1 ms
10 ms
TC = 25°C
VGS ≤ 10 V
Single Pulse
1
100
1000
02030
0
2
4
10
0357
1
10
110
6.2
0.5 0.6 0.8 0.9 1.0
1000
1 10 1000.1
100
10
1
0.1 0.1
10
100
0.00001 0.001 0.01
510 25 1 4
1
3
5
TJ = 125°C
VGS = 0 V
26
100
0.2
10
15
1000
0.5 ms 1
0.0001
0.7
2.2
8.2
4035
6
7
8
9
4.2
10,000
NVMFD5C478N
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5
TYPICAL CHARACTERISTICS
0.01
0.1
1
10
100
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Figure 13. Thermal Characteristics
PULSE TIME (sec)
RqJA (°C/W)
Single Pulse
50% Duty Cycle
20%
10%
5%
2%
1%
DEVICE ORDERING INFORMATION
Device Marking Package Shipping†
NVMFD5C478NT1G 5C478N DFN8
(Pb−Free)
1500 / Tape & Reel
NVMFD5C478NWFT1G 478NWF DFN8
(Pb−Free)
1500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
M3.25
h−−−
3.50
−−−
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
DATE 26 FEB 2013
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
XXXXXX= Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
ZZ = Lot Traceability
1234
56
TOP VIEW
SIDE VIEW
BOTTOM VIEW
D1
E1
h
D
E
B
A
0.20 C
0.20 C
2X
2X
DIM MIN
MILLIMETERS
A0.90
A1 −−−
b0.33
c0.20
D5.15 BSC
D1 4.70
D2 3.90
E6.15 BSC
E1 5.70
E2 3.90
e1.27 BSC
G0.45
K0.51
L0.48
A
0.10 C
0.10 C
14
8
e
8X
D2
b1 E2
b
A0.10 BC
0.05 C
L
DETAIL A
A1
c
4X
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer
to device data sheet for actual part
marking.
1
XXXXXX
AYWZZ
1
5
MAX
−−−
−−−
0.42
−−−
4.90
4.10
5.90
4.15
0.55
−−−
0.61
M
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.27
0.75
1.40
3.70
4.56
8X
N1.80 2.00
78
N
PITCH
6.59
4.84
1.00
DIMENSION: MILLIMETERS
PIN ONE
IDENTIFIER
NOTE 7
NOTE 4 CSEATING
PLANE
DETAIL A NOTE 6
4X
K
NOTE 3
2.30
4X
0.70
5.55
4X
0.56
2X
D3 1.50 1.70
b1 0.33 0.42
ÏÏ
ÏÏ
4X
D3
G
4X
DETAIL B
DETAIL B
ALTERNATE
CONSTRUCTION
2.08
2X
K1 0.56 −−−
K1
3.75
12
_
MAX
1.10
0.05
0.51
0.33
5.10
4.30
6.10
4.40
0.65
−−−
0.71
2.20
1.90
0.51
−−−
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
NEW STANDARD:
DESCRIPTION:
98AON50417E
ON SEMICONDUCTOR STANDARD
DFN8 5X6, 1.27P DUAL FLAG (SO8FL−DUAL)
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2
DOCUMENT NUMBER:
98AON50417E
PAGE 2 OF 2
ISSUE REVISION DATE
ORELEASED FOR PRODUCTION. REQ. BY M. RAMOS. 16 APR 2010
ACORRECTED SOLDER FOOTPRINT. REQ. BY I. CAMBALIZA. 16 FEB 2011
BCORRECTED ERROR IN SOLDER FOOTPRINT SHAPE. REQ. BY I. CAMBALIZA. 29 JUN 2011
CCORRECTED MARKING DIAGRAM TO ADD LOT TRACEABILITY. REQ. BY J.
CARTER.
12 APR 2012
DADDED DIMENSION K1 TO BOTTOM VIEW AND TABLE. REQ. BY D. TRUHITTE. 11 JAN 2013
EMODIFED DIMENSIONS D1 & E1 AND ADDED NOMINAL VALUES. REQ. BY I.
MARIANO.
26 FEB 2013
© Semiconductor Components Industries, LLC, 2013
February, 2013 − Rev. E
Case Outline Number:
506BT
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