This is information on a product in full production.
July 2018 DS11484 Rev 3 1/43
VNHD7012AY
H-bridge motor driver for automotive DC motor driving
Datasheet - production data
Features
AEC-Q100 qualified
Output current: 38 A
Dual fully protected HSD with MultiSense
feedback
Two integrated drivers for the external LSDs
3 V CMOS compatible inputs
Protections:
– Undervoltage shutdown
– Overvoltage clamp
– Thermal shutdown
– Load current limitation
– Self-limiting of fast thermal transients
(Power Limitation)
– Cross current protection
– Shoot through protection
– Loss of ground and loss of VCC
– Electrostatic discharge protection
– Drain and source voltage monitoring of the
external power MOSFETs, configurable via
an external resistance (short-to-battery
protection)
PWM operation up to 20 kHz for external LSDs
MultiSense monitoring functions
– Analog motor current feedback
– Chip temperature monitoring
– Battery voltage monitoring
MultiSense diagnostic functions
– Output short to ground detection
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
Standby mode
Half bridge operation
Charge pump output for reverse battery
protection
Package: ECOPACK®
Description
The device is a DC motor driver for automotive
applications. It integrates a full protected dual
high-side driver and the drivers and protections
for the two external power MOSFETs in low-side
configuration.
The device is designed using STMicroelectronics’
well known and proven proprietary VIPower®
technology that allows to efficiently integrate on
the same die a true PowerMOSFET with an
intelligent signal/ protection circuitry. The device
is housed in a PowerSSO-36 exposed pad
package to optimize the dissipation
performances.
The input signals INA and INB can directly
interface the microcontroller to select the motor
direction and the brake conditions. Two selection
pins (SEL0 and SEL1) are available to address to
the microcontroller the information available on
the MultiSense. The MultiSense pin allows to
monitor the motor current, provides a voltage
proportional to the battery value and the
information on the temperature of the chip. The
integrated protections are: load current limitation,
overload active power limitation (with latch-off),
overtemperature shutdown (with latch-off) and
cross current protection.
Type RDS(on) Iout VCCmax
VNHD7012AY 12 mΩtyp
per channel) 38 A 38 V
*$3*&)7
1PXFS440
www.st.com
Contents VNHD7012AY
2/43 DS11484 Rev 3
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 Power limitation (high-side driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3 High-side current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 External PowerMOS low side VDS monitoring . . . . . . . . . . . . . . . . . . . . . 27
4 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 MultiSense operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1 MultiSense analog monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 Multisense diagnostics flag in fault conditions . . . . . . . . . . . . . . . . . . . . . 29
6 VREG and Driver_LS Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9 Immunity against transient electrical disturbances . . . . . . . . . . . . . . . 31
10 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11.1 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11.2 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DS11484 Rev 3 3/43
VNHD7012AY Contents
3
11.3 PowerSSO-36 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
List of tables VNHD7012AY
4/43 DS11484 Rev 3
List of tables
Table 1. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Suggested connection for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Logic inputs (INA, INB) (Vcc = 7 V up to 28 V; -40 °C < Tj < 150 °C) . . . . . . . . . . . . . . . . . 12
Table 8. HSD switching (VCC = 13 V; RLOAD = 1.6 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Gate driver for external MOS parameters (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10. Protections and diagnostics (7 V < VCC < 18 V; -40 °C < Tj < 150 °C). . . . . . . . . . . . . . . . 13
Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Operative condition - truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. On-state fault conditions- truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Off-state — truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. IISO 7637-2 - electrical transient conduction along supply line . . . . . . . . . . . . . . . . . . . . . 31
Table 16. PCB properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. PowerSSO-36 (exposed pad) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 19. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DS11484 Rev 3 5/43
VNHD7012AY List of figures
5
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Low-side turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Input reset time for HSD-fault unlatch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Input reset time for LSD-fault unlatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL) . . . . . . . . . . . . . . . . 21
Figure 11. Normal operative conditions (resistive load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Out shorted to ground and short clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. OUT shorted to Vcc and short clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Gate driver low side rise time normalized vs Cg = 4.7nF . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Gate driver low side fall time normalized vs Cg = 4.7nF . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. MultiSense block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. PowerSSO-36 PCB board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Rthj-amb vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. Thermal fitting model of a double-channel HSD in PowerSSO-36 . . . . . . . . . . . . . . . . . . . 34
Figure 21. Thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 24. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 25. PowerSSO-36 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Block diagram and pin description VNHD7012AY
6/43 DS11484 Rev 3
1 Block diagram and pin description
Figure 1. Block diagram
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Table 1. Block description
Name Description
Logic control Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the truth table.
Undervoltage (US) Shuts down the device for battery voltage below (4 V).
High-side and low-side clamp voltage Protect the high-side and the low-side switches from the high
voltage on the battery line.
High-side and low-side driver Drive the gate of the concerned switch to allow a proper Ron
for the leg of the bridge.
Current limitation Limits the motor current in case of short circuit.
High-side overtemperature protection
In case of short-circuit with the increase of the junction
temperature, it shuts down the concerned driver to prevent
degradation and to protect the die.
VDS_MONITORING Protection of LSD powers against short to battery failure
VREG Internal voltage regulator that provides the supply for the
gates of the external low-side switches
Fault detection
Signalizes an abnormal condition of the power stage (output
shorted to ground or output shorted to battery) by a feedback
on the MultiSense
DS11484 Rev 3 7/43
VNHD7012AY Block diagram and pin description
42
Figure 2. Configuration diagram (top view)
Power limitation Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
Open-load in OFF-state
Signalize, in combination with an external resistor, an open-
load when the switches are off by a feedback on the
MultiSense
Tchip monitoring Provides a signal linked to the Chip temperature by a
feedback on the MultiSense
VCC monitoring Provides a signal linked to the Chip temperature by a
feedback on the MultiSense
Reverse driver Drives an external PowerMOSFET to provide the reverse
battery protection
CP
Charge pump to drive the external N-MOSFET used on the
battery track for the reverse battery protection.
The N-MOSFET source must be connected to the Vbatt pin.
Table 1. Block description (continued)
Name Description
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Block diagram and pin description VNHD7012AY
8/43 DS11484 Rev 3
Table 2. Pin definitions and functions
Pin N° Symbol Function
20 PWM PWM input.
25 VREG Internal supply output
16 INAClockwise input.
18 Vbatt
Battery supply, connection to the source of the external
PowerMOS used for the reverse battery protection
19 MultiSense Output of current sense and diagnostic feedback
12 MultiSense_EN Enables the MultiSense diagnostic pin
11 SEL0 Address the MultiSense multiplexer (refer to Table 12)
26 SEL1 Address the MultiSense multiplexer (refer to Table 12)
21 INBCounter clockwise input.
1, 2, 3, 4, 5, 6, 7,
8, 9, 10 OUTASource of high-side switch A
27, 28, 29, 30, 31,
32, 33, 34, 35, 36 OUTBSource of high-side switch B
17 CP Drives the gate of external P-MOSFET for the reverse
battery protection
15 VREF_OVL_LSA Sets the threshold for VDS_MONITORING feature for LSA
22 VREF_OVL_LSB Sets the threshold for VDS_MONITORING feature for LSB
13 GATE_LSA Gate driver of the external PowerMOS LSA
24 GATE_LSB Gate driver of the external PowerMOS LSB
14 KSOURCE_LSA Source of external LSA. Ground connection
23 KSOURCE_LSB Source of external LSB. Ground connection
TAB VCC
Supply voltage. Drain of the high-side switches and
connection to the drain of the external PowerMOS used for
the reverse battery protection
Table 3. Suggested connection for unused and not connected pins
Connection / pin OUTA, OUTB Inx, PWM, SELx,
Multisense_EN Multisense
GATE_LSA,
GATE_LSB, CP,
VREG
VREF_OVL_LSA,
VREF_OVL_LSB
Floating X X X X X
To ground Not allowed Through 10 kΩ resistor Not allowed X
DS11484 Rev 3 9/43
VNHD7012AY Electrical specifications
42
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
Stressing the device above the rating listed in Table 4 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.
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Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
VCC Bridge supply voltage 38 V
VBAT Maximum battery voltage(1) -16 to 38 V
Imax DC output current Internally
limited A
IR Reverse output current (continuous)(2) 30 A
IIN Input current (INA and INB pins) -1 to 10 mA
ISEL SEL0,1 DC input current -1 to 10 mA
IPWM PWM Input current -1 to 10 mA
IMultiSense_EN SenseEnable DC input current -1 to 1.5 mA
IMultiSense
MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 mA
MultiSense pin DC output current in reverse (VCC < 0 V) -20 mA
VREG VREG DC voltage 12 V
Electrical specifications VNHD7012AY
10/43 DS11484 Rev 3
2.2 Thermal data
VCP VCP DC voltage VBATT -6 to
VBAT+14 V
VGATE_LSx GATE_LAS, GATE_LSB DC voltage 12 V
VREF_OVL_LSx VREF_OVL_LSA, VREF_OVL_LSB input current -1 to 10 V
VESD
Electrostatic discharge (Human body model: R = 1.5 kΩ; C = 100 pF)
– MultiSenseVREG, VREF_OVL_LSx
–IN
A, INB, OUTA, OUTB, PWM, SEL0, SEL1, SENSE_EN
–GATE_LSx
2
4
4
kV
TcJunction operating temperature -40 to 150 °C
TSTG Storage temperature -55 to 150 °C
IK_SOURCE_LSx DC reverse ground pin current (per leg) 100 mA
1. This applies with the n-channel MOSFET used for the reverse battery protection. Otherwise VBAT has to be shorted to
VCC.
2. Based on the internal wires capability.
Note: All logic pins cannot be left floating but they must be connected to GND if unused.
Table 4. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Table 5. Thermal data
Symbol Parameter Max. value Unit
Rthj-case
Thermal resistance junction-case (per leg channel)
(JEDEC JESD 51-8) 2.4 °C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)
1. Device mounted on two-layers 2s0p PCB with 2 cm2.heatsink copper trace.
50.6 °C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7) 16.6 °C/W
DS11484 Rev 3 11/43
VNHD7012AY Electrical specifications
42
2.3 Electrical characteristics
VCC = 7 V up to 28 V; -40 °C < Tj < 150 °C, unless otherwise specified.
Table 6. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC
Operating supply
voltage 428V
ISSupply current
Off-state standby
INA = INB = PWM = Multisense_EN= 0;
SEL0,1 = 0; Tj = 25 °C; VCC = 13 V
1µA
Off-state standby;
INA = INB = PWM = Multisense_EN= 0;
SEL0,1 = 0; VCC = 13 V; Tj = 85 °C
1µA
Off-state standby;
INA = INB = PWM = Multisense_EN= 0;
SEL0,1 = 0; VCC = 13 V; Tj = 125 °C
10 µA
Off-state (no standby)
INA = INB = PWM = Multisense_EN= 0;
SEL0,1 = 5 V
48mA
On-state: INA or INB = 5V;
PWM = 0 V or PWM = 5 V;
SEL0 = 0 or SEL0 = 5 V;
SEL1 = 0 or SEL1 = 5 V
612mA
On-state: INA = INB = 5V;
PWM = 0 V or PWM = 5 V;
SEL0 = 0 or SEL0 = 5 V;
SEL1 = 0 or SEL1 = 5 V
918mA
tD_STBY
Standby mode
blanking time
VCC = 13 V; INA = INB = SEL1 =
MultiSense_EN = PWM = 0 V;
VSEL0 from 5 V to 0 V.
60 300 550 µs
RONHS
Static high-side
resistance
IOUT = 8 A; Tj = 25 °C,
VCC = 13 V 12 mΩ
IOUT = 8 A;
Tj = - 40 °C to 150 °C 24 mΩ
VCC = 4 V, IOUT = 8 A, Tj=25 °C 12
Vf
High-side free-
wheeling diode forward
voltage
IOUT = -8 A; Tj = 150 °C 0.6 0.7 V
IL(off)
Off-State Output
current of one output
INA = INB = PWM = 0; VOUT = 0 V;
VCC = 13 V; Tj = 25 °C 00.5µA
INA = INB = PWM = 0; VOUT = 0 V;
VCC = 13 V; Tj = 125°C 05µA
IL(off_h)
Off-state output current
of one output with
other HSD on
INA = PWM = 0; INB = 5 V; VCC = 13 V 20 60 µA
Electrical specifications VNHD7012AY
12/43 DS11484 Rev 3
Table 7. Logic inputs (INA, INB) (Vcc = 7 V up to 28 V; -40 °C < Tj < 150 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level voltage 0.9 V
VIH Input high level voltage 2.1 V
VIHYST Input hysteresis voltage 0.2 V
VICL Input clamp voltage
IIN = 1 mA 5.3 7.2 V
IIN = -1 mA -0.7 V
IINL Input current VIN = 0.9 V 1 µA
IINH Input current VIN = 2.1 V 10 µA
SEL0, SEL1 (VCC = 7 V up to 18 V; -40 °C < Tj < 150 °C)
VSELL Input low level voltage 0.9 V
ISELL Low level input current VSEL = 0.9 V 1 µA
VSELH Input high level voltage 2.1 V
ISELH High level input current VSEL = 2.1 V 10 µA
VSEL(hyst) Input hysteresis voltage 0.2 V
VSELCL Input clamp voltage
ISEL = 1 mA 5.3 7.2 V
ISEL = -1 mA -0.7 V
PWM (VCC = 7 V up to 28 V; -40 °C < Tj < 150 °C)
VPWM Input low level voltage 0.9 V
IPWM Low level input current VPWM = 0.9 V 1 µA
VPWM Input high level voltage 2.1 V
IPWMH High level input current VPWM = 2.1 V 10 µA
VPWM(hyst) Input hysteresis voltage 0.2 V
VPMWCL Input clamp voltage
IPWM = 1 mA 5.3 7.2 V
IPWM = -1 mA -0.7 V
MultiSense_EN (VCC = 7 V up to 18 V; -40 °C < Tj < 150 °C)
VSEnL Input low level voltage 0.9 V
ISEnL Low level input current VSEn = 0.9 V 1 µA
VSEnH Input high level voltage 2.1 V
ISEnH High level input current VSEn = 2.1 V 10 µA
VSEn(hyst) Input hysteresis voltage 0.2 V
VSEnCL Input clump voltage
ISEn = 1 mA 5.3 7.5 V
ISEn = -1 mA -0.7 V
DS11484 Rev 3 13/43
VNHD7012AY Electrical specifications
42
Table 8. HSD switching (VCC = 13 V; RLOAD = 1.6 Ω)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time
Input rise time < 1 µs;
MultiSense_EN = 5 V (no
standby); SEL0,1 = 0; PWM = 0
(see Figure 6)
50 µs
td(off) Turn-off delay time
Input rise time < 1 µs;
MultiSense_EN = 5 V (no
standby); SEL0,1 = 0; PWM = 0
(see Figure 6)
18 µs
Table 9. Gate driver for external MOS parameters (VCC = 13 V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
f(1)
1. Parameter guaranteed by design.
PWM frequency 0 20 kHz
Vgs_lsd Gate_LSD voltage
PWM = 5 V; INx = 0 V 10 V
VCC = 4 V, PWM = 5 V,
INx = 0 V, Tj=25 °C 4V
tcross Low-side turn-on delay time Input rise time < 1 µs
(see Figure 7)40 160 300 µs
tgr_ls Rise time
VCC = 13.5 V; Rg = 0 Ω;
Cg = 4.7 nF
(see Figure 5)
0.25 0.5 µs
tgf_ls Fall time
VCC = 13.5 V; Rg = 0 Ω;
Cg = 4.7 nF
(see Figure 5)
0.35 0.5 µs
Table 10. Protections and diagnostics (7 V < VCC < 18 V; -40 °C < Tj < 150 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VUSD Undervoltage shutdown VCC falling 4 V
VUSDreset Undervoltage shutdown reset VCC rising 5 V
VUSDhyst
Undervoltage shutdown
hysteresis 0.3 V
ILIM_HSD High-side current limitation
38 56 78 A
VCC = 4 V, Tj=25 °C (1) 50 A
VCL_HSD
High-side driver clamp
voltage (VCC to OUTA = 0 or
OUTB = 0)
IOUT = 100 mA;
tclamp = 1 ms;
Iclamp = 100 mA
38 46 V
VCL_LSD(1)
Low-side clamp voltage
(OUTA = VCC or OUTB = VCC
to GND)
IOUT = 100 mA;
tclamp = 1 ms;
Iclamp = 100 mA
38 46 52 V
tDEL_OVL_LSD
Low-side drain-current
overload blanking time 15µs
Electrical specifications VNHD7012AY
14/43 DS11484 Rev 3
IREF_OVL_LSD
Low-side drain-current
overload reference current 40 50 60 µA
VREF_OVL_LSD_MIN
Low-side drain-current
overload threshold voltage
minimum
0.32 0.4 0.48 V
VREF_OVL_LSD_MAX
Low-side drain-current
overload threshold voltage
maximum
1.6 2 2.4 V
TTSD_HSD
High-side thermal shutdown
temperature INx = 2.1 V 150 175 200 °C
TTR_HSD
High-side thermal reset
temperature 135 °C
THYST_HSD
High-side thermal hysteresis
(TSD_HSD - TR_HSD)7°C
∆Tj_SD(1) Dynamic temperature 60 °C
IL(off3)
OFF-state output sink current
with VOUT = VCC
INA = INB = 0; PWM = 0;
VOUT = VCC
01.12.5mA
VCL
Clamp signal
(VCC to GND)
IOUT = 100 mA;
tclamp = 1 ms;
Iclamp = 100 mA
38 46 52 V
VOL
OFF-state open-load voltage
detection threshold
INA = INB = 0; PWM = 0;
VSEL0 = 5 V for CHA;
VSEL0 = 0 V and within
tD_STBY for CHB
234V
IL(off2) OFF-state output sink current
INA = INB = 0; VOUT = 2 V;
PWM = 0 V;
VSEL0 = 5 V for CHA;
VSEL0 = 0 V
-150 -5 µA
tDSTKON
OFF-state diagnostic delay
time from falling edge of
INPUT (see Figure 4)
INA = 5 V to 0 V; INB = 0;
PWM = 0; VSEL0 = 5 V;
IOUT = 0 A; VOUTA = 4 V
40 160 300 µs
VGS_CP CP output voltage
VCP - VBAT = VGS_CP 81215V
VBAT = -16 V;
VCP - VBAT = VGS_CP
0.6 V
tD_VOL
OFF-state diagnostic delay
time from rising edge of VOUT
(see Figure 10)
INA = INB = 0 V; PWM = 0;
VOUTx = 0 V to 4 V;
VSEL0 = 5 V for CHA;
VSEL0 = 0 V for CHB;
VSEL0,1 = 0 V;
SENSE_EN = 5 V
530µs
tLATCH_RST_HS
Input reset time for high-side
fault unlatch
VINx = 5 V to 0 V; HSDx
faulting (see Figure 8)31020µs
Table 10. Protections and diagnostics (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DS11484 Rev 3 15/43
VNHD7012AY Electrical specifications
42
tLATCH_RST_LS
Input reset time for low-side
fault unlatch
VINx = 0 V to 5 V; LSDx
faulting (see Figure 9)31020µs
tstby_ovl_lsd
Low-side drain current
overload delay time form stby
exit
50% of VSENSEH 20 µs
1. Parameter guaranteed by design and characterization; not subject to production test.
Table 10. Protections and diagnostics (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSENSE_CL
MultiSense clamp
voltage
VSEn = 0 V; ISENSE = -1 mA 7 V
VSEn = 0 V; ISENSE = 1 mA -17 -12 V
KOL IOUT/ISENSE
IOUT = 0.3 A; VSENSE = 0.5 V
Tj = -40 °C to 150 °C 6000 8000 10000
K0IOUT/ISENSE
IOUT = 4 A; VSENSE = 0.5 V;
Tj = -40 °C to 150 °C 6800 8000 9200
K1IOUT/ISENSE
IOUT = 8 A; VSENSE = 0.5
Tj = -40 °C to 150 °C 7200 8000 8800
K2IOUT/ISENSE
IOUT = 16 A; VSENSE = 4 V;
Tj = -40 °C to 150 °C 7200 8000 8800
dKOL/KOL(1) Analog sense
current drift
IOUT = 0.3 A; VSENSE = 0.5 V;
Tj = -40 °C to 150 °C -12 12 %
dK0/K0(1) Analog sense
current drift
IOUT = 4 A; VSENSE = 0.5 V;
VSENSE_EN = 0 V;
Tj = -40 °C to 150 °C
-5 5 %
dK1/K1(1) Analog sense
current drift
IOUT = 8 A; VSENSE = 0.5 V;
VSENSE_EN = 0 V;
Tj = -40 °C to 150 °C
-5 5 %
dK2/K2(1) Analog sense
current drift
IOUT = 16 A; VSENSE = 4 V;
Tj = -40 °C to 150°C -5 5 %
VSENSE_SAT
Max analog sense
output voltage
VCC = 7 V; RSENSE = 10 kΩ;
IOUT = 16 A; VSEL0 = 5 V;
Tj = 150 °C
5V
ISENSE_SAT(2) MultiSense
saturation current
VCC = 7 V; VINA = 5 V; VINB = 0 V;
VSEL0 = 5 V; Tj = 150°C 3.8 mA
IOUT_SAT(2) Output saturation
current
VCC = 7 V; VSENSE = 4 V;
VINA = 5 V; VINB = 0 V; VSEL0 = 5 V;
Tj = 150°C
33 A
VOUT_MSD(2)
Output Voltage for
MultiSense
shutdown
VINA = 5 V; VINB = 0 V; VSEL0 = 5 V;
VSEL1 = 0 V; RSENSE = 2.7 kΩ
IOUT = 24 A
5V
Electrical specifications VNHD7012AY
16/43 DS11484 Rev 3
ISENSE0
MultiSense leakage
current
VMultiSense = VSENSE_EN = PWM = 0
V; INA = INB =0 V; SEL0 = SEL1 = 0;
Tj = -40 °C to 150°C (standby)
00.5µA
SEn = 5 V; INA = INB = 5 V;
PWM = 0 V; SideX diagnostic
selected; IOUTx = 0 A
E.g.
– SideA: SEL0 = 5 V; SEL1 = 0 V;
IOUTA = 0 A; IOUTB = 12 A
– SideB: SEL0 = 0 V; SEL1 = 0 V;
IOUTA = 12 A; IOUTB = 0 V
014µA
SEn = 5 V; PWM = 0 V; SideX
diagnostic selected; HSx OFF
E.g.
– SideA: SEL0 = 5 V; SEL1 = 0 V;
INA = 0 V; INB = 5 V; IOUTB = 12 A
– SideB: SEL0 = 0 V; SEL1 = 0 V;
INA = 5 V; INB = 0 V; IOUTA = 12 A
010µA
VSENSEH
MultiSense output
voltage in fault
condition
VCC = 13 V; RSENSE = 1 kΩ;
– E.g: Ch0 in open-load; VIN = 0 V;
IOUT = 0 A; VOUT = 4 V
57V
ISENSEH
MultiSense current
in fault condition
9 V < VCC < 18 V;
VSENSE = 5 V; MultiSense in fault
condition
10 20 30 mA
Chip temperature analog feedback
VSENSE_TC
MultiSense output
voltage proportional
to chip temperature
VSENSE_EN = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN = 0 V;
RSENSE = 1 kΩ; Tj = -40 °C
2.325 2.41 2.495 V
VSENSE_EN = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN = 0 V;
RSENSE = 1 kΩ; Tj = 25 °C
1.985 2.07 2.155 V
VSENSE_EN = 5 V; VSEL0 = 0 V;
VSEL1 = 5 V; VIN = 5 V;
RSENSE = 1 kΩ; Tj = 125 °C
1.435 1.52 1.605 V
dVSENSE_TC/dT
(2)
Temperature
coefficient Tj = -40 °C to 150 °C -5.5 mV/K
Transfer function VSENSE_TC(T) = VSENSE_TC(T0) + dVSENSE_TC/dT * (T - T0)
VCC supply voltage analog feedback
VSENSE_VCC
MultiSense output
voltage proportional
to VCC supply
voltage
VCC = 13 V; VSENSE_EN = 5 V;
VSEL0 = VSEL1 = 5 V; RSENSE = 1 kΩ3.16 3.23 3.3 V
Transfer function VSENSE_VCC = VCC/4
Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DS11484 Rev 3 17/43
VNHD7012AY Electrical specifications
42
MultiSense timings (Multiplexer transition times)(2)
tD_CStoTC
MultiSense
transition delay from
current sense to TC
sense
VINA = 5 V; VSENSE_EN = 5 V;
VSEL0 = 5 V to 0 V;
VSEL1 = 0 V to 5 V; IOUTA = 2.5 A;
RSENSE = 1 kΩ; VSENSE_TC = 90% of
VSENSE_TC_FINAL
60 µs
tD_TCtoCS
MultiSense
transition delay from
TC sense to current
sense
VINA = 5 V; VSENSE_EN = 5 V;
VSEL0 = 0 V to 5 V;
VSEL1 = 5 V to 0 V; IOUTA = 2.5 A;
RSENSE = 1 kΩ; ISENSE = 90% of
ISENSE_MAX
20 µs
tD_CStoVCC
MultiSense
transition delay from
current sense to VCC
sense
VINA = 5 V; VSENSE_EN = 5 V;
VSEL0 = 5 V; VSEL1 = 0 V to 5 V;
IOUTA = 2.5 A; RSENSE = 1 kΩ;
VSENSE_VCC = 90% of
VSENSE_VCC_FINAL
60 µs
tD_VCCtoCS
MultiSense
transition delay from
VCC sense to current
sense
VINA = 5 V; VSENSE_EN = 5 V;
VSEL0 = 5 V; VSEL1 = 5 V to 0 V;
IOUTA = 2.5 A; RSENSE = 1 kΩ;
ISENSE = 90% of ISENSE_MAX
20 µs
tD_TCtoVCC
MultiSense
transition delay from
TC sense to VCC
sense
VCC = 13 V; Tj = 125 °C;
VSENSE_EN = 5 V;
VSEL0 = 0 V to 5 V;
VSEL1 = 5 V; RSENSE = 1 kΩ;
VSENSE_VCC = 90% of
VSENSE_VCC_FINAL
20 µs
tD_VCCtoTC
MultiSense
transition delay from
VCC sense to TC
sense
VCC = 13 V; Tj = 125 °C;
VSENSE_EN = 5 V;
VSEL0 = 5 V to 0 V;
VSEL1 = 5 V; RSENSE = 1 kΩ;
VSENSE_TC = 90% of
VSENSE_TC_FINAL
20 µs
MultiSense timings (CurrentSense mode)
tDSENSE1H
Current sense
settling time from
rising edge of
VSENSE_EN
VINA = 5 V; VINB = 0 V;
VSENSE_EN = 0 V to 5 V;
RSENSE = 1 k; RL = 2.6 Ω
VPWM = 5 V; VSEL0 = 5 V;
VSEL1 = 0 V
60 µs
tDSENSE1L
Current sense
disable delay time
from falling edge of
VSENSE_EN
VINA = 5 V; VINB = 0 V;
VSENSE_EN = 5 V to 0 V;
RSENSE = 1 k; RL = 2.6 Ω
VPWM = 5 V; VSEL0 = 5 V;
VSEL1 = 0 V
20 µs
tDSENSE2H
VSENSE_TC settling
time from rising
edge of VSENSE_EN
VSENSE_EN = 0 V to 5 V;
VSEL0 = 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
60 µs
Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical specifications VNHD7012AY
18/43 DS11484 Rev 3
Figure 4. TDSTKON
tDSENSE2L
VSENSE_TC settling
time from rising
edge of VSENSE_EN
VSENSE_EN = 5 V to 0 V;
VSEL0 = 0 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20 µs
MultiSense timings (VCC voltage sensor mode)
tDSENSE3H
VSENSE_VCC settling
time from rising
edge of VSENSE_EN
VSENSE_EN = 0 V to 5 V;
VSEL0 = 5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
60 µs
tDSENSE3L
VSENSE_VCC settling
time from rising
edge of VSENSE_EN
VSENSE_EN = 5 V to 0 V;
VSEL0 = 5 V; VSEL1 = 5 V;
RSENSE = 1 kΩ
20 µs
1. Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and 9 V < VCC < 18 V) with
respect to its value measured at Tj = 25 °C, VCC = 13 V.
2. Parameter guaranteed by design and characterization; not subject to production test.
Table 11. MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
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DS11484 Rev 3 19/43
VNHD7012AY Electrical specifications
42
Figure 5. Definition of the low-side switching times
Figure 6. Definition of the high-side switching times
t
gf_Is
PWM
t
t
V
GATE_LSA,LSB
20%
80% 80%
20%
t
gr_Is
t
t
V
OUTA
V
INA
90%
10%
t
D(on)
t
D(off)
Electrical specifications VNHD7012AY
20/43 DS11484 Rev 3
Figure 7. Low-side turn-on delay time
Figure 8. Input reset time for HSD-fault unlatch
Note: Multisense_EN=1
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DS11484 Rev 3 21/43
VNHD7012AY Electrical specifications
42
Figure 9. Input reset time for LSD-fault unlatch
Note: Multisense_EN=1
Figure 10. OFF-state diagnostic delay time from rising edge of VOUT (tD_VOL)
Note: Multisense_EN=1.
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Electrical specifications VNHD7012AY
22/43 DS11484 Rev 3
Table 12. Operative condition - truth table
INA INB PWM SEL0 SEL1 MultiSense_EN MultiSense HSA LSA HSB LSB
00
1 0 0 1 High-Z OFF ON OFF ON
1 1 0 1 High-Z OFF ON OFF ON
01
0 0 0 1 Current Monitoring HSB OFF OFF ON OFF
1 0 0 1 Current Monitoring HSB OFF ON ON OFF
01
0 1 0 1 High-Z OFF OFF ON OFF
1 1 0 1 High-Z OFF ON ON OFF
10
0 0 0 1 High-Z ON OFF OFF OFF
1 0 0 1 High-Z ON OFF OFF ON
10
0 1 0 1 Current Monitoring HSA ON OFF OFF OFF
1 1 0 1 Current Monitoring HSA ON OFF OFF ON
11X
(1) 0 0 1 Current Monitoring HSB ON OFF ON OFF
1 0 1 Current Monitoring HSA ON OFF ON OFF
0 0 0 1 0 1 Off-state diagnostic OUTA OFF OFF OFF OFF
0 0 0 0 0 1 Off-state diagnostic OUTB OFF OFF OFF OFF
XX X 0 1 1 T
CHIP Monitoring — ———
XX X 1 1 1 V
CC Monitoring — — — —
X X X X X 0 High-Z(2) — ———
1. X: the level of the pin can be 0 or 1.
2. When INA = INB = PWM = SEL0 = SEL1 = MultiSense_EN = 0 device enters standby after TDSTBY
.
Table 13. On-state fault conditions- truth table
Digital input pins(1)
MultiSense Comment
INA INB PWM SEL0
0010V
SENSE_H VDS LSB protection triggered; LSB latched off
0011V
SENSE_H VDS LSA protection triggered; LSA latched off
01 X 0 V
SENSE_H HSB protection triggered; HSB latched off
0111V
SENSE_H VDS LSA protection triggered; LSA latched off
1010V
SENSE_H VDS LSB protection triggered; LSB latched off
10 X 1 V
SENSE_H HSA protection triggered; HSA latched off
11 X 0 V
SENSE_H HSB protection triggered; HSB latched off
11 X 1 V
SENSE_H HSA protection triggered; HSA latched off
1. MultiSense_EN = 1 and SEL1 = 0 are mandatory for fault detection. Other logic combinations on digital input pins not
reported on the above table do not allow to detect a latched-off channel.
DS11484 Rev 3 23/43
VNHD7012AY Electrical specifications
42
Note: To power on the device from standby, it is recommended to: toggle INA or INB or SEL0 or
SEL1 from 0 to 1 first to come out from STBY mode; toggle PWM from 0 to 1 with a delay of
20 microsecond th is avoid s an y overstr ess on the device in case of existing short-to-battery.
Table 14. Off-state — truth table
INA
INB
SEL0
SEL1
PWM
OUTA
OUTB
MultiSense_EN
MultiSense
Description
Off-state diagnostic
00
10
0
VOUTA > VOL
X 1V
SENSEH
Case 1: OUTA shorted to VCC if no pull-up is applied.
Case 2: NO open-load in full bridge configuration with
an external pull-up on OUTB
Case 3: open-load in half bridge configuration with an
external pull-up on OUTA (motor connected between
Out and Ground)
VOUTA < VOL
X1 Hi-Z
Case 1: open-load in full Bridge configuration with an
external pull-up on OUTB
Case 2: NO open-load in half Bridge configuration
with external pull-up on OUTA (motor connected
between Out and Ground)
00
X
VOUTB > VOL
1V
SENSEH
Case 1: OUTB shorted to VCC if no pull-up is applied
Case 2: NO open-load in full bridge configuration with
external pull-up on OUTA
Case 3: open-load in half bridge configuration with
external pull-up on OUTB (motor connected between
Out and Ground)
X
VOUTB < VOL
1Hi-Z
Case1: open-load in full Bridge configuration with an
external pull-up on OUTA
Case 2. NO open-load in half Bridge configuration
with external pull-up on OUTB (motor connected
between Out and Ground)
Electrical specifications VNHD7012AY
24/43 DS11484 Rev 3
2.4 Waveforms
Figure 11. Normal operative conditions (resistive load)
Note: MultiSense_EN=1
DS11484 Rev 3 25/43
VNHD7012AY Electrical specifications
42
Figure 12. Out shorted to ground and short clearing
Note: MultiSense_EN=1
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Electrical specifications VNHD7012AY
26/43 DS11484 Rev 3
Figure 13. OUT shorted to Vcc and short clearing
Note: MultiSense_EN=1
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Figure 14. Gate driver low side rise time
normalized vs Cg = 4.7nF
Figure 15. Gate driver low side fall time
normalized vs Cg = 4.7nF
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DS11484 Rev 3 27/43
VNHD7012AY Protections
42
3 Protections
3.1 Power limitation (high-side driver)
The basic working principle of this protection consists of an indirect measurement of the
junction temperature swing Δ Tj through the direct measurement of the spatial temperature
gradient on the device surface in order to automatically shut off the output MOSFET as soon
as Δ Tj exceeds the safety level of Δ Tj_SD. The protection prevents fast thermal transient
effects and, consequently, reduces thermo-mechanical fatigue. When Power Limitation is
reached, The device enters in latch mode and generates the Fault Flag on Multisense =
VsenseH when the faulty leg diagnostic is selected (please refer to Table 13).
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold
(typically 175°C), the device enters in latch mode and generates the Fault Flag on
Multisense = VsenseH (please refer to Table 13). The concerned high side can be switched
ON again as soon as: Tj drops below TTR_HSD, INX is set low for a duration >
TLATCH_RST_HS and set high again.
3.3 High-side current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as
the other components of the system (e.g. bonding wires, wiring harness, connectors, loads,
etc.) from excessive current flow. In case of short circuit, overload or during load power-up,
the output current is clamped to a safety level, ILIMH, by operating the output power
MOSFET in the active region
3.4 External PowerMOS low side VDS monitoring
The VDS_monitoring function has the ability to sense the OUTPUT Mosfet source voltage
and compare it to a predetermined threshold. This threshold is programmable, using an
internal reference current IREF_OVL_LSD = 50 µA (typ.) and an external resistor connected
at VREF_OVL_LS external pin.
This protection will be activated when the low side Power Mos is switched ON and its gate is
fully charged: to guarantee this condition the function will detect a short to battery event only
when PWM = H and after a blanking time tfil_OVL_LS= 2.2 µs (typ.) starting from PWM
rising edge. This feature is present for each LSD leg.
In case of fault conditions caused by Power Limitation or overtemperature or open
load/short to VCC in OFF state, the fault is indicated by the MultiSense pin being internally
switched to a "current limited" voltage source pulled to level VSENSEH.
Typical application schematic VNHD7012AY
28/43 DS11484 Rev 3
4 Typical application schematic
Figure 16. Typical application schematic
Note: To protect the device against Battery disconnection with energized inductive load when the
bridge driver goes into 3-state, suggested C(Vcc) is:
where:
Emotor = 33.5 mJ;
DVcc,max = Vcc_AMR - Vcc_max;
Vcc_AMR = 38 V;
Vcc_max = 26 V (Vcc at jump start);
C(Vcc) = 470 µF
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DS11484 Rev 3 29/43
VNHD7012AY MultiSense operation
42
5 MultiSense operation
5.1 MultiSense analog monitoring
Diagnostic information on device and load status are provided by an analog output pin
(MultiSense) delivering the following signals:
Current monitor: current mirror of HSDx output current
VCC monitor: voltage propotional to VCC
TCASE: voltage propotional to chip temperature
Those signals are routed through an analog multiplexer which is configured and controlled
by means of SELx and SEn pins, according to the address map in Table 12.
Figure 17. MultiSense block diagram
5.2 Multisense diagnostics flag in fault conditions
Multisense pin delivers fixed voltage (VSENSEH) with a certain current capability in case of:
fault condition on activated high-side triggered by Power Limitation
fault condition on activated high-side triggered by overtemperature protection
fault condition on VDS of Low side exceeded threshold
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VREG and Driver_LS Block VNHD7012AY
30/43 DS11484 Rev 3
6 VREG and Driver_LS Block
VREG pin is the output of an internal low drop voltage regulator. VREG block is designed to
power the driver of external power Mosfet (Driver_LS) and it allows a proper MOS transition.
VREG out voltage will be VREG=10V if Vbattery > 10V, while VREG = Vbattery if
Vbattery < 10V.
An external capacitor CREG = 100 nF connected to the pin VREG is needed to proper
polarize the circuit (see Figure 16).
7 Reverse battery protection
CP pin provides the necessary gate drive for an external n-channel PowerMOS used for
reverse polarity protection. The external N-channel Power MOSFET used for the reverse
battery protection should have the following characteristics:
BVdss > 20 V (for a reverse battery of -16 V);
RDS(on) < 1/3 of H-bridge total RDS(on)
Standard Logic Gate Driving
8 Open-load detection in off-state
The Open Load (OL) detection in off-state operates when output is deactivated (means INA
= INB = PWM=0, or INB together with PWM=0). Open load detection is performed by
reading the MultiSense output. External (switched) pull-up resistor has to be used and
dimensioned to pull output voltage above the maximum open load detection voltage (VOL
MAX) when load is not connected and as well stays below the minimum level (VOL MIN)
when load is connected.
When the open load is detected, VsenseH is indicated on Multisense pin, possible
conditions are specified in Table 14.
If pull up resistor is applied over switched circuitry, it allows to detect short to VCC from
open-load (see Figure 16).
The RPU value has to be:
Rpull_up
VBATTmin VOLmax
–
2I
L(off2)min [@VOLmax]
-----------------------------------------------------------
DS11484 Rev 3 31/43
VNHD7012AY Immunity against transient electrical disturbances
42
9 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the
supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)
and ISO 16750-2:2010.
The related function performance status classification is shown in Table 15.
Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and
in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device
only, without components and accessed through VCC and GND terminals.
Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as
follows: "The function does not perform as designed during the test but returns automatically
to normal operation after the test".
Table 15. IISO 7637-2 - electrical transient conduction along supply line
Test pulse
2011(E)
Test pulse severity level
with status II functional
performance status
Minimum
number of
pulses or
test time
Burst cycle/pulse
repetition time
Pulse duration
and pulse
generator
internal
impedance
Level US(1)
1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E)
min. max.
1 III -112 V 500 pulses 0.5 s 2 ms, 10 Ω
2a III +55 500 pulses 0.2 s 5 s 50 µs, 2 Ω
3a IV -220 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b IV +150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4(2)
2. Test pulse from ISO 7637-2:2004(E)
IV -7 V 1 pulse 100 ms, 0.01 Ω
Load dump according to ISO 16750-2:2010
Test B(3)
3. With 40 V external suppressor referred to ground (-40 °C < TJ < 150 °C)
40 V 5 pulse 1 min 400 ms, 2 Ω
Package and PCB thermal data VNHD7012AY
32/43 DS11484 Rev 3
10 Package and PCB thermal data
10.1 PowerSSO-36 thermal data
Figure 18. PowerSSO-36 PCB board
DS11484 Rev 3 33/43
VNHD7012AY Package and PCB thermal data
42
Figure 19. Rthj-amb vs PCB copper area in open box free air condition
Equation 1: pulse calculation formula
ZTHδ = RTH · δ + ZTHtp (1 - δ)
where δ = tP/T
Table 16. PCB properties
Dimension Value
Board finish thickness 1.6 mm +/- 10%
Board dimension 129 mm x 60 mm
Board material FR4
Cu thickness (outer layers) 0.070 mm
Cu thickness (inner layers) 0.035 mm
Thermal via separation 1.2 mm
Thermal via diameter 0.3 mm +/- 0.08 mm
Cu thickness on vias 0.025 mm
Footprint dimension 4.1 mm x 6.5 mm
Package and PCB thermal data VNHD7012AY
34/43 DS11484 Rev 3
Figure 20. Thermal fitting model of a double-channel HSD in PowerSSO-36
Note: The fitting model is a simplified thermal tool and is valid for transient evolutions where the
embedded protections (power limit ation or thermal cycling during thermal shutdown) ar e not
triggered.
Figure 21. Thermal impedance junction ambient single pulse
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Table 17. Thermal parameters
Area / island FP 2 8 4L
R1 (°C/W) 0.95
R2 (°C/W) 1.3
R3 (°C/W) 2 2 2 1
R4 (°C/W) 7 6 6 4
R5 (°C/W) 20 14 10 2
R6 (°C/W) 30 26 15 7
DS11484 Rev 3 35/43
VNHD7012AY Package and PCB thermal data
42
R7 (°C/W) 0.95
R8 (°C/W) 1.3
C1 (W•s/°C) 0.002
C2 (W•s/°C) 0.005
C3 (W•s/°C) 0.05 0.05 0.05 0.05
C4 (W•s/°C) 0.15 0.2 0.2 0.2
C5 (W•s/°C) 1 2 3 10
C6 (W•s/°C) 3 5 9 18
C7 (W•s/°C) 0.002
C8 (W•s/°C) 0.005
Table 17. Thermal parameters (continued)
Area / island FP 2 8 4L
Package and packing information VNHD7012AY
36/43 DS11484 Rev 3
11 Package and packing information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
11.1 PowerSSO-36 package information
Figure 22. PowerSSO-36 package dimensions
Table 18. PowerSSO-36 (exposed pad) package mechanical data
Ref
Millimeters
Min. Typ. Max.
Ө0° - 8°
Ө1 5° - 10°
Ө20° - -
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DS11484 Rev 3 37/43
VNHD7012AY Package and packing information
42
A 2.15 - 2.45
A1 0.0 - 0.1
A2 2.15 - 2.35
b 0.18 - 0.32
b1 0.13 0.25 0.3
c 0.23 - 0.32
c1 0.2 0.2 0.3
D(1) 10.30 BSC
D1 6.9 - 7.5
D2 - 3.65 -
D3 - 4.3 -
e 0.50 BSC
E 10.30 BSC
E1(1) 7.50 BSC
E2 4.3 - 5.2
E3 - 2.3 -
E4 - 2.9 -
G1 - 1.2 -
G2 - 1 -
G3 - 0.8 -
h0.3-0.4
L 0.55 0.7 0.85
L1 1.40 REF
L2 0.25 BSC
N36
R0.3 - -
R1 0.2 - -
S0.25 - -
Tolerance of form and position
aaa 0.2
bbb 0.2
ccc 0.1
ddd 0.2
Table 18. PowerSSO-36 (exposed pad) package mechanical data (continued)
Ref
Millimeters
Min. Typ. Max.
Package and packing information VNHD7012AY
38/43 DS11484 Rev 3
11.2 PowerSSO-36 packing information
Figure 23. PowerSSO-36 tube shipment (no suffix)
eee 0.1
ffff 0.2
ggg 0.15
1. Dimensions D and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is ‘0.25
mm’ per side D and ‘0.15 mm’ per side E1. D and E1 are Maximum plastic body size dimensions including
mold mismatch.
Table 18. PowerSSO-36 (exposed pad) package mechanical data (continued)
Ref
Millimeters
Min. Typ. Max.
All dimensions are in mm.
Base Qty 49
Bulk Qty 1225
Tube length (±0.5) 532
A3.5
B13.8
C (±0.1) 0.6
A
C
B
DS11484 Rev 3 39/43
VNHD7012AY Package and packing information
42
Figure 24. PowerSSO-36 tape and reel shipment (suffix “TR”)
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (±0.2) 13
F20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
Reel dimensions
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 12
Hole Diameter D (±0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (±0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (±0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min 500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Package and packing information VNHD7012AY
40/43 DS11484 Rev 3
11.3 PowerSSO-36 marking information
Figure 25. PowerSSO-36 marking information
Note: Engineering Samples: these samples can be clearly identified by a dedicated special
symbol in the marking of each unit. These samples are intended to be used for electrical
compatibility evaluation only; usage for any other purpose may be agreed only upon written
authorization by ST. ST is not liable for any customer usage in production and/or in reliability
qualification trials.
Note: Commercial Samples: fully qualified parts from ST standard production with no usage
restrictions.
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DS11484 Rev 3 41/43
VNHD7012AY Order codes
42
12 Order codes
Table 19. Device summary
Package Order codes
Tube Tape and reel
PowerSSO-36 VNHD7012AY VNHD7012AYTR
Revision history VNHD7012AY
42/43 DS11484 Rev 3
13 Revision history
Table 20. Document revision history
Date Revision Description of changes
14-Nov-2017 1 Initial release.
11-Apr-2018 2
In Cover page:
– updated value of “Iout” from 40 A to 38 A
– updated feature “Output current = 40 A” with “Output current = 38 A”
– removed “MO” from sentence “ The device is designed using
STMicroelectronics...”
In Table 10: Protections and diagnostics (7 V < VCC < 18 V; -
40 °C < Tj < 150 °C):
– Updated min value of “ILIM_HSD” parameter from 40 A to 38 A
– Fixed typ. value “ILIM_HSD” parameter to 50 A
– Updated max value of “ILIM_HSD” parameter from 80 A to 78 A
– Updated min value of “tDEL_OVL_LSD” parameter from 0.05 µs to 1 µs
– Updated test condition of “IL(off2)” parameter from “PWM = 2 V” to
“PWM = 0 V”
– Removed “and within tD_STBY for CHB” from test condition of “IL(off2)”
parameter
– Updated test condition of “tD_VOL” parameter from “VSEL1 = 0 V for
CHA;” to “VSEL0 = 5 V for CHA; VSEL0 = 0 V for CHB;” and removed
“for CHB”
In Table 11: MultiSense (7 V < VCC < 18 V; -40 °C < Tj < 150 °C):
– Updated min value of “ISENSE_SAT” parameter from 4 mA to 3.8 mA
– Updated min value of “IOUT_SAT” parameter from 48 A to 33 A
– Updated max value of “ISENSE0” parameter from 10 µA to 14 µA
In Table 16: PCB properti es updated value of “Board dimension” from
“129 mm x 86 mm” to “129 mm x 60 mm”
Updated Figure 21: Thermal impedance junction ambient single pulse
Updated Table 17: Thermal parameters
12-Jul-2018 3
Updated from target spec to production data.
Updated Table 4: Absolute maximum ratings (add VBAT value).
Updated Table 10: Protections and diagno stics (7 V < VCC < 18 V; -
40 °C < Tj < 150 °C) (add Min. and Max. values in VGS_CP).
DS11484 Rev 3 43/43
VNHD7012AY
43
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